Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_1_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_1_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_1_req_during_sram_0_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_1_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12263

1

T1

4

T4

14

T5

20

auto[1]

869

1

T13

8

T97

4

T107

1

---

Summary for Variable sram_1_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12134

1

T1

4

T4

14

T5

20

auto[1]

998

1

T13

3

T97

2

T107

1

---

Summary for Variable sram_1_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_1_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13094

1

T1

4

T4

14

T5

20

lc_esc_on

38

1

T146

1

T101

2

T73

1

---

Summary for Variable sram_1_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12544

1

T1

4

T4

14

T5

20

auto[1]

588

1

T13

7

T97

8

T8

8

---

Summary for Variable sram_1_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1906

1

T13

9

T96

10

T97

2

auto[1]

11226

1

T1

4

T4

14

T5

20

---

Summary for Variable sram_1_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13033

1

T1

4

T4

14

T5

20

auto[1]

99

1

T101

2

T73

1

T72

1