Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49783	1			T65	421		T50	9		T56	207
access_err	57630	1			T4	111		T5	272		T13	140
write_blank_err	470	1			T6	1		T7	12		T16	8
ecc_uncorr_err	65332	1			T6	196		T7	266		T50	29
ecc_corr_err	1589	1			T50	1		T56	94		T66	62
no_err	86237	1			T1	26		T4	80		T5	235

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	810	1			T6	4		T7	17		T16	21
secret2	25928	1			T1	8		T4	23		T5	50
secret1	28389	1			T4	21		T5	55		T13	18
secret0	30944	1			T4	7		T5	45		T13	27
hw_cfg1	38922	1			T4	14		T5	28		T13	15
hw_cfg0	22071	1			T4	16		T5	60		T13	17
rot_creator_auth_state	21916	1			T1	1		T4	28		T5	39
rot_creator_auth_codesign	20522	1			T1	6		T4	27		T5	66
owner_sw_cfg	19554	1			T1	2		T4	11		T5	53
creator_sw_cfg	21710	1			T1	7		T4	27		T5	39
vendor_test	30275	1			T1	2		T4	17		T5	72

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	6573	1			T145	162		T260	55		T91	204
fsm_err	secret1	3747	1			T143	14		T337	131		T338	46
fsm_err	secret0	4069	1			T101	39		T37	86		T339	299
fsm_err	hw_cfg1	3949	1			T14	8		T16	614		T72	147
fsm_err	hw_cfg0	1888	1			T222	191		T144	155		T146	13
fsm_err	rot_creator_auth_state	4276	1			T65	421		T240	214		T193	26
fsm_err	rot_creator_auth_codesign	3693	1			T101	162		T158	15		T340	248
fsm_err	owner_sw_cfg	2918	1			T100	287		T111	123		T163	61
fsm_err	creator_sw_cfg	4777	1			T16	21		T99	1		T20	163
fsm_err	vendor_test	13893	1			T50	9		T56	207		T66	287
access_err	life_cycle	810	1			T6	4		T7	17		T16	21
access_err	secret2	10301	1			T4	17		T5	35		T13	22
access_err	secret1	5597	1			T4	13		T5	43		T13	15
access_err	secret0	4488	1			T4	6		T5	34		T13	18
access_err	hw_cfg1	1193	1			T4	3		T13	8		T97	3
access_err	hw_cfg0	2120	1			T4	10		T5	4		T13	5
access_err	rot_creator_auth_state	5414	1			T4	13		T5	28		T13	1
access_err	rot_creator_auth_codesign	7058	1			T4	13		T5	44		T13	19
access_err	owner_sw_cfg	6487	1			T4	5		T5	25		T13	14
access_err	creator_sw_cfg	7381	1			T4	20		T5	22		T13	9
access_err	vendor_test	6781	1			T4	11		T5	37		T13	29
write_blank_err	secret2	7	1			T16	1		T139	1		T341	1
write_blank_err	secret1	30	1			T7	1		T16	3		T102	1
write_blank_err	secret0	44	1			T6	1		T102	1		T72	1
write_blank_err	hw_cfg1	73	1			T162	1		T102	2		T111	1
write_blank_err	hw_cfg0	24	1			T221	1		T219	1		T91	1
write_blank_err	rot_creator_auth_state	163	1			T7	4		T16	4		T102	7
write_blank_err	rot_creator_auth_codesign	56	1			T260	1		T220	2		T91	1
write_blank_err	owner_sw_cfg	29	1			T7	7		T102	3		T95	1
write_blank_err	creator_sw_cfg	14	1			T342	1		T220	1		T91	1
write_blank_err	vendor_test	30	1			T102	3		T219	2		T343	1
ecc_uncorr_err	secret2	4014	1			T16	617		T139	208		T159	58
ecc_uncorr_err	secret1	10502	1			T7	266		T16	813		T102	258
ecc_uncorr_err	secret0	13987	1			T6	196		T50	7		T102	255
ecc_uncorr_err	hw_cfg1	23456	1			T162	770		T102	456		T111	541
ecc_uncorr_err	hw_cfg0	6148	1			T161	2		T163	121		T193	61
ecc_uncorr_err	rot_creator_auth_state	3863	1			T50	10		T163	183		T72	431
ecc_uncorr_err	rot_creator_auth_codesign	859	1			T193	31		T201	116		T213	65
ecc_uncorr_err	owner_sw_cfg	1254	1			T50	12		T163	60		T344	29
ecc_uncorr_err	creator_sw_cfg	1249	1			T193	34		T201	49		T213	199
ecc_corr_err	secret2	112	1			T56	13		T344	1		T113	6
ecc_corr_err	secret1	124	1			T56	5		T66	4		T43	3
ecc_corr_err	secret0	158	1			T56	17		T66	1		T43	1
ecc_corr_err	hw_cfg1	303	1			T56	20		T66	15		T43	5
ecc_corr_err	hw_cfg0	292	1			T50	1		T56	17		T66	14
ecc_corr_err	rot_creator_auth_state	111	1			T56	1		T66	9		T43	4
ecc_corr_err	rot_creator_auth_codesign	201	1			T56	12		T66	18		T43	6
ecc_corr_err	owner_sw_cfg	152	1			T56	8		T66	1		T43	3
ecc_corr_err	creator_sw_cfg	136	1			T56	1		T43	2		T163	1
no_err	secret2	4921	1			T1	8		T4	6		T5	15
no_err	secret1	8389	1			T4	8		T5	12		T13	3
no_err	secret0	8198	1			T4	1		T5	11		T13	9
no_err	hw_cfg1	9948	1			T4	11		T5	28		T13	7
no_err	hw_cfg0	11599	1			T4	6		T5	56		T13	12
no_err	rot_creator_auth_state	8089	1			T1	1		T4	15		T5	11
no_err	rot_creator_auth_codesign	8655	1			T1	6		T4	14		T5	22
no_err	owner_sw_cfg	8714	1			T1	2		T4	6		T5	28
no_err	creator_sw_cfg	8153	1			T1	7		T4	7		T5	17
no_err	vendor_test	9571	1			T1	2		T4	6		T5	35

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded