Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1386 |
1 |
|
|
T13 |
6 |
|
T223 |
3 |
|
T224 |
12 |
auto[1] |
913 |
1 |
|
|
T4 |
4 |
|
T13 |
15 |
|
T223 |
3 |
Summary for Variable sram_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for sram_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
51 |
1 |
|
|
T13 |
2 |
|
T260 |
1 |
|
T91 |
2 |
sram_key[0x1] |
717 |
1 |
|
|
T4 |
2 |
|
T13 |
5 |
|
T223 |
2 |
sram_key[0x2] |
760 |
1 |
|
|
T4 |
2 |
|
T13 |
7 |
|
T223 |
2 |
sram_key[0x3] |
771 |
1 |
|
|
T13 |
7 |
|
T223 |
2 |
|
T106 |
1 |
Summary for Cross sram_req_lock_cross
Samples crossed: sram_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for sram_req_lock_cross
Bins
sram_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
auto[0] |
28 |
1 |
|
|
T13 |
1 |
|
T260 |
1 |
|
T91 |
1 |
sram_key[0x0] |
auto[1] |
23 |
1 |
|
|
T13 |
1 |
|
T91 |
1 |
|
T392 |
3 |
sram_key[0x1] |
auto[0] |
447 |
1 |
|
|
T223 |
1 |
|
T224 |
4 |
|
T102 |
5 |
sram_key[0x1] |
auto[1] |
270 |
1 |
|
|
T4 |
2 |
|
T13 |
5 |
|
T223 |
1 |
sram_key[0x2] |
auto[0] |
448 |
1 |
|
|
T13 |
3 |
|
T223 |
1 |
|
T224 |
4 |
sram_key[0x2] |
auto[1] |
312 |
1 |
|
|
T4 |
2 |
|
T13 |
4 |
|
T223 |
1 |
sram_key[0x3] |
auto[0] |
463 |
1 |
|
|
T13 |
2 |
|
T223 |
1 |
|
T224 |
4 |
sram_key[0x3] |
auto[1] |
308 |
1 |
|
|
T13 |
5 |
|
T223 |
1 |
|
T106 |
1 |