Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49386	1			T12	91		T13	144		T77	34
access_err	62254	1			T1	33		T4	16		T6	23
write_blank_err	502	1			T7	6		T8	4		T15	11
ecc_uncorr_err	69895	1			T69	145		T7	724		T8	684
ecc_corr_err	1264	1			T7	3		T98	1		T142	2
no_err	90199	1			T1	44		T4	39		T6	34

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	934	1			T7	22		T15	9		T16	4
secret2	24264	1			T1	8		T4	2		T6	12
secret1	28765	1			T1	5		T4	7		T6	2
secret0	36078	1			T1	8		T4	4		T6	5
hw_cfg1	39943	1			T1	11		T4	6		T6	1
hw_cfg0	25847	1			T1	10		T4	11		T6	7
rot_creator_auth_state	20828	1			T1	7		T4	6		T10	3
rot_creator_auth_codesign	22467	1			T1	5		T4	12		T6	9
owner_sw_cfg	21504	1			T1	8		T4	2		T6	7
creator_sw_cfg	22017	1			T1	5		T4	2		T6	7
vendor_test	30853	1			T1	10		T4	3		T6	7

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2814	1			T236	658		T19	236		T189	214
fsm_err	secret1	4797	1			T113	523		T15	508		T343	332
fsm_err	secret0	3167	1			T190	286		T120	56		T269	93
fsm_err	hw_cfg1	2487	1			T20	224		T262	38		T344	241
fsm_err	hw_cfg0	5570	1			T8	57		T256	269		T226	349
fsm_err	rot_creator_auth_state	3231	1			T260	414		T270	54		T337	457
fsm_err	rot_creator_auth_codesign	5070	1			T285	188		T345	178		T257	112
fsm_err	owner_sw_cfg	4516	1			T153	454		T346	569		T347	205
fsm_err	creator_sw_cfg	4451	1			T185	484		T120	27		T146	14
fsm_err	vendor_test	13283	1			T12	91		T13	144		T77	34
access_err	life_cycle	934	1			T7	22		T15	9		T16	4
access_err	secret2	11096	1			T1	4		T4	2		T6	12
access_err	secret1	5874	1			T1	4		T4	1		T10	5
access_err	secret0	4666	1			T1	3		T4	4		T6	1
access_err	hw_cfg1	1318	1			T1	4		T11	5		T17	19
access_err	hw_cfg0	2229	1			T1	6		T4	3		T11	4
access_err	rot_creator_auth_state	5658	1			T4	2		T10	1		T11	14
access_err	rot_creator_auth_codesign	7924	1			T4	3		T6	2		T10	6
access_err	owner_sw_cfg	7126	1			T1	5		T4	1		T6	2
access_err	creator_sw_cfg	7984	1			T1	3		T6	3		T11	20
access_err	vendor_test	7445	1			T1	4		T6	3		T11	14
write_blank_err	secret2	11	1			T7	1		T231	1		T348	1
write_blank_err	secret1	26	1			T242	1		T216	1		T121	1
write_blank_err	secret0	56	1			T15	1		T16	2		T269	1
write_blank_err	hw_cfg1	84	1			T7	1		T8	1		T72	1
write_blank_err	hw_cfg0	16	1			T7	1		T15	1		T16	1
write_blank_err	rot_creator_auth_state	149	1			T7	1		T15	6		T16	1
write_blank_err	rot_creator_auth_codesign	62	1			T8	3		T15	2		T20	1
write_blank_err	owner_sw_cfg	49	1			T114	1		T349	2		T231	4
write_blank_err	creator_sw_cfg	21	1			T7	1		T127	1		T339	3
write_blank_err	vendor_test	28	1			T7	1		T15	1		T242	1
ecc_uncorr_err	secret2	4941	1			T7	409		T142	28		T146	34
ecc_uncorr_err	secret1	9131	1			T142	24		T149	142		T242	436
ecc_uncorr_err	secret0	19551	1			T15	635		T16	1198		T238	19
ecc_uncorr_err	hw_cfg1	25193	1			T7	315		T8	684		T98	2
ecc_uncorr_err	hw_cfg0	5514	1			T15	111		T16	524		T149	137
ecc_uncorr_err	rot_creator_auth_state	3226	1			T69	145		T215	368		T146	9
ecc_uncorr_err	rot_creator_auth_codesign	662	1			T149	198		T327	51		T151	18
ecc_uncorr_err	owner_sw_cfg	705	1			T146	22		T350	90		T152	5
ecc_uncorr_err	creator_sw_cfg	972	1			T149	64		T146	23		T350	88
ecc_corr_err	secret2	101	1			T149	1		T58	2		T75	3
ecc_corr_err	secret1	144	1			T58	1		T146	1		T198	1
ecc_corr_err	secret0	163	1			T58	3		T74	2		T75	2
ecc_corr_err	hw_cfg1	224	1			T20	3		T242	2		T89	4
ecc_corr_err	hw_cfg0	220	1			T7	3		T149	1		T89	1
ecc_corr_err	rot_creator_auth_state	99	1			T142	1		T149	1		T58	1
ecc_corr_err	rot_creator_auth_codesign	101	1			T98	1		T74	1		T75	8
ecc_corr_err	owner_sw_cfg	75	1			T89	3		T74	9		T146	1
ecc_corr_err	creator_sw_cfg	137	1			T142	1		T351	1		T89	1
no_err	secret2	5301	1			T1	4		T10	2		T11	12
no_err	secret1	8793	1			T1	1		T4	6		T6	2
no_err	secret0	8475	1			T1	5		T6	4		T10	4
no_err	hw_cfg1	10637	1			T1	7		T4	6		T6	1
no_err	hw_cfg0	12298	1			T1	4		T4	8		T6	7
no_err	rot_creator_auth_state	8465	1			T1	7		T4	4		T10	2
no_err	rot_creator_auth_codesign	8648	1			T1	5		T4	9		T6	7
no_err	owner_sw_cfg	9033	1			T1	3		T4	1		T6	5
no_err	creator_sw_cfg	8452	1			T1	2		T4	2		T6	4
no_err	vendor_test	10097	1			T1	6		T4	3		T6	4

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded