Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.99 93.81 96.70 95.93 91.65 97.19 96.34 93.28


Total test records in report: 1318
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T1259 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1622054651 Jun 22 04:54:33 PM PDT 24 Jun 22 04:54:35 PM PDT 24 545914224 ps
T1260 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.693928628 Jun 22 04:54:20 PM PDT 24 Jun 22 04:54:25 PM PDT 24 223956081 ps
T1261 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3699761706 Jun 22 04:54:45 PM PDT 24 Jun 22 04:54:47 PM PDT 24 39766713 ps
T1262 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.726595820 Jun 22 04:54:09 PM PDT 24 Jun 22 04:54:13 PM PDT 24 76813170 ps
T1263 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1303650179 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:12 PM PDT 24 65722993 ps
T1264 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.797807761 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:17 PM PDT 24 1779877545 ps
T1265 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.4034796670 Jun 22 04:54:20 PM PDT 24 Jun 22 04:54:23 PM PDT 24 580738971 ps
T1266 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3038203913 Jun 22 04:54:24 PM PDT 24 Jun 22 04:54:27 PM PDT 24 92219700 ps
T354 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1449687513 Jun 22 04:54:24 PM PDT 24 Jun 22 04:54:36 PM PDT 24 705025979 ps
T356 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4057608063 Jun 22 04:54:30 PM PDT 24 Jun 22 04:54:49 PM PDT 24 1294651078 ps
T1267 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3462505665 Jun 22 04:54:13 PM PDT 24 Jun 22 04:54:20 PM PDT 24 1689320312 ps
T1268 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3773996264 Jun 22 04:54:36 PM PDT 24 Jun 22 04:55:00 PM PDT 24 4835150678 ps
T1269 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1989128445 Jun 22 04:54:12 PM PDT 24 Jun 22 04:54:16 PM PDT 24 140052647 ps
T1270 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3615315780 Jun 22 04:54:17 PM PDT 24 Jun 22 04:54:23 PM PDT 24 947118388 ps
T1271 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.466407506 Jun 22 04:54:31 PM PDT 24 Jun 22 04:54:35 PM PDT 24 266379490 ps
T1272 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.215900569 Jun 22 04:54:12 PM PDT 24 Jun 22 04:54:16 PM PDT 24 624071806 ps
T1273 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1529083435 Jun 22 04:54:37 PM PDT 24 Jun 22 04:54:40 PM PDT 24 137371792 ps
T1274 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1800151530 Jun 22 04:54:31 PM PDT 24 Jun 22 04:54:34 PM PDT 24 968244811 ps
T1275 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2509860668 Jun 22 04:54:17 PM PDT 24 Jun 22 04:54:19 PM PDT 24 69067609 ps
T1276 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3081216833 Jun 22 04:54:18 PM PDT 24 Jun 22 04:54:20 PM PDT 24 43378625 ps
T1277 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1499098698 Jun 22 04:54:15 PM PDT 24 Jun 22 04:54:18 PM PDT 24 93307135 ps
T1278 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.553884359 Jun 22 04:54:24 PM PDT 24 Jun 22 04:54:30 PM PDT 24 271940250 ps
T1279 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3539366350 Jun 22 04:54:30 PM PDT 24 Jun 22 04:54:32 PM PDT 24 105175254 ps
T1280 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3760919423 Jun 22 04:54:35 PM PDT 24 Jun 22 04:54:39 PM PDT 24 108363551 ps
T1281 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.625297603 Jun 22 04:54:35 PM PDT 24 Jun 22 04:54:37 PM PDT 24 50735187 ps
T319 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.68331746 Jun 22 04:54:12 PM PDT 24 Jun 22 04:54:16 PM PDT 24 395394404 ps
T357 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.586582712 Jun 22 04:54:19 PM PDT 24 Jun 22 04:54:30 PM PDT 24 2478270687 ps
T1282 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.952814845 Jun 22 04:54:34 PM PDT 24 Jun 22 04:54:38 PM PDT 24 312753221 ps
T1283 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1644023231 Jun 22 04:54:16 PM PDT 24 Jun 22 04:54:19 PM PDT 24 93692652 ps
T320 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2096648329 Jun 22 04:54:17 PM PDT 24 Jun 22 04:54:20 PM PDT 24 322787542 ps
T1284 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1171306200 Jun 22 04:54:36 PM PDT 24 Jun 22 04:54:42 PM PDT 24 1647267881 ps
T1285 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3459590412 Jun 22 04:54:31 PM PDT 24 Jun 22 04:54:33 PM PDT 24 164627019 ps
T1286 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.994541536 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:14 PM PDT 24 39491943 ps
T1287 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1256251855 Jun 22 04:54:19 PM PDT 24 Jun 22 04:54:23 PM PDT 24 74776739 ps
T1288 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3879242291 Jun 22 04:54:17 PM PDT 24 Jun 22 04:54:20 PM PDT 24 141603913 ps
T1289 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1824024053 Jun 22 04:54:36 PM PDT 24 Jun 22 04:54:41 PM PDT 24 225195778 ps
T1290 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3506198614 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:26 PM PDT 24 9886636502 ps
T1291 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3392889566 Jun 22 04:54:47 PM PDT 24 Jun 22 04:54:49 PM PDT 24 41619478 ps
T359 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.239665970 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:28 PM PDT 24 1221960018 ps
T1292 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1088875871 Jun 22 04:54:36 PM PDT 24 Jun 22 04:54:38 PM PDT 24 142019533 ps
T1293 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3437067564 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:14 PM PDT 24 38379114 ps
T1294 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.540160945 Jun 22 04:54:37 PM PDT 24 Jun 22 04:54:43 PM PDT 24 68361920 ps
T1295 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3990788667 Jun 22 04:54:24 PM PDT 24 Jun 22 04:54:28 PM PDT 24 101145051 ps
T1296 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3229314984 Jun 22 04:54:50 PM PDT 24 Jun 22 04:54:52 PM PDT 24 581612823 ps
T1297 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.61832804 Jun 22 04:54:23 PM PDT 24 Jun 22 04:54:55 PM PDT 24 19951366939 ps
T1298 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3624656138 Jun 22 04:55:03 PM PDT 24 Jun 22 04:55:05 PM PDT 24 89052583 ps
T1299 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.4267312737 Jun 22 04:54:44 PM PDT 24 Jun 22 04:54:46 PM PDT 24 46379054 ps
T1300 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1182652499 Jun 22 04:54:12 PM PDT 24 Jun 22 04:54:16 PM PDT 24 506627933 ps
T1301 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1620816174 Jun 22 04:54:19 PM PDT 24 Jun 22 04:54:23 PM PDT 24 232572397 ps
T1302 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1963748583 Jun 22 04:54:38 PM PDT 24 Jun 22 04:54:44 PM PDT 24 75532594 ps
T1303 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2921887796 Jun 22 04:54:35 PM PDT 24 Jun 22 04:54:38 PM PDT 24 39221216 ps
T1304 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3295452096 Jun 22 04:54:45 PM PDT 24 Jun 22 04:54:47 PM PDT 24 107081724 ps
T1305 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.569592647 Jun 22 04:54:13 PM PDT 24 Jun 22 04:54:16 PM PDT 24 162243750 ps
T1306 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.732643633 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:16 PM PDT 24 276062427 ps
T1307 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.294456772 Jun 22 04:54:34 PM PDT 24 Jun 22 04:54:58 PM PDT 24 4662195844 ps
T1308 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3953034714 Jun 22 04:54:23 PM PDT 24 Jun 22 04:54:28 PM PDT 24 178146282 ps
T1309 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.135306501 Jun 22 04:54:11 PM PDT 24 Jun 22 04:54:17 PM PDT 24 220015999 ps
T1310 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3528346530 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:13 PM PDT 24 39206833 ps
T360 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.183564004 Jun 22 04:54:20 PM PDT 24 Jun 22 04:54:41 PM PDT 24 2523079322 ps
T1311 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2431948022 Jun 22 04:54:19 PM PDT 24 Jun 22 04:54:21 PM PDT 24 71879518 ps
T1312 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3900477597 Jun 22 04:54:37 PM PDT 24 Jun 22 04:54:41 PM PDT 24 201685271 ps
T283 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.25550557 Jun 22 04:54:36 PM PDT 24 Jun 22 04:55:02 PM PDT 24 20073107868 ps
T1313 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.458218395 Jun 22 04:54:35 PM PDT 24 Jun 22 04:54:37 PM PDT 24 617516155 ps
T1314 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.357890995 Jun 22 04:54:10 PM PDT 24 Jun 22 04:54:23 PM PDT 24 2050285359 ps
T1315 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1962547306 Jun 22 04:54:20 PM PDT 24 Jun 22 04:54:31 PM PDT 24 1477445235 ps
T1316 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.515218953 Jun 22 04:54:20 PM PDT 24 Jun 22 04:54:23 PM PDT 24 613928926 ps
T1317 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1777997076 Jun 22 04:54:13 PM PDT 24 Jun 22 04:54:17 PM PDT 24 139912977 ps
T1318 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4045542326 Jun 22 04:55:06 PM PDT 24 Jun 22 04:55:09 PM PDT 24 553607120 ps

Test location /workspace/coverage/default/38.otp_ctrl_test_access.2547503596
Short name T11
Test name
Test status
Simulation time 10439672683 ps
CPU time 21.28 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:33 PM PDT 24
Peak memory 242784 kb
Host smart-d8447656-dd9b-479d-a88f-6c562f846144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547503596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.2547503596
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.1263120151
Short name T17
Test name
Test status
Simulation time 75044326653 ps
CPU time 164.16 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 07:01:25 PM PDT 24
Peak memory 257364 kb
Host smart-0f6b97ae-ba7c-4d85-8070-3eca5f677bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263120151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.1263120151
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.1344751925
Short name T7
Test name
Test status
Simulation time 238870379825 ps
CPU time 1490.28 seconds
Started Jun 22 07:00:39 PM PDT 24
Finished Jun 22 07:25:31 PM PDT 24
Peak memory 263600 kb
Host smart-84b6a924-f05c-45d5-984f-55d6b678dfba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344751925 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.1344751925
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1948097120
Short name T189
Test name
Test status
Simulation time 165293984319 ps
CPU time 452.55 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 07:05:17 PM PDT 24
Peak memory 260756 kb
Host smart-a61332df-94da-4c76-bdf9-2e739373df23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948097120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1948097120
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.632601196
Short name T16
Test name
Test status
Simulation time 11886876018 ps
CPU time 217.18 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 07:03:20 PM PDT 24
Peak memory 257444 kb
Host smart-5145e44b-7262-453c-ad0f-0fb51d315dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632601196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.
632601196
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.88602236
Short name T78
Test name
Test status
Simulation time 1566987182 ps
CPU time 4.4 seconds
Started Jun 22 07:00:48 PM PDT 24
Finished Jun 22 07:00:59 PM PDT 24
Peak memory 242120 kb
Host smart-40175f65-60e3-47ec-b0a2-53127fa478ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88602236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.88602236
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1427768814
Short name T24
Test name
Test status
Simulation time 19009250625 ps
CPU time 180.4 seconds
Started Jun 22 06:57:28 PM PDT 24
Finished Jun 22 07:00:30 PM PDT 24
Peak memory 270760 kb
Host smart-4f678130-4051-4a20-b45c-f19fc7a9a76f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427768814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1427768814
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2051896975
Short name T74
Test name
Test status
Simulation time 1235193003 ps
CPU time 29.94 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:01:15 PM PDT 24
Peak memory 244988 kb
Host smart-f99e99c9-857b-4983-b5e1-366791ec6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051896975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2051896975
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1875935874
Short name T13
Test name
Test status
Simulation time 3015139469 ps
CPU time 13.59 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:56 PM PDT 24
Peak memory 242196 kb
Host smart-15bbd3c1-c58d-4bdd-84e6-3af12642c10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875935874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1875935874
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.4022351877
Short name T35
Test name
Test status
Simulation time 167962298 ps
CPU time 4.33 seconds
Started Jun 22 07:02:39 PM PDT 24
Finished Jun 22 07:02:46 PM PDT 24
Peak memory 242620 kb
Host smart-f785e492-dbac-4bfe-a71c-643bedd6610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022351877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.4022351877
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1415237810
Short name T15
Test name
Test status
Simulation time 228591755016 ps
CPU time 1294.21 seconds
Started Jun 22 07:00:51 PM PDT 24
Finished Jun 22 07:22:32 PM PDT 24
Peak memory 297844 kb
Host smart-a34b5779-bdc7-4c49-80b3-fa1bb5f1e718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415237810 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.1415237810
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.4242405670
Short name T146
Test name
Test status
Simulation time 1406365060 ps
CPU time 23.08 seconds
Started Jun 22 06:59:33 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 243844 kb
Host smart-f2c2c25b-257d-413a-8eb1-2f872c5931c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242405670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.4242405670
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2854930394
Short name T284
Test name
Test status
Simulation time 2649217544 ps
CPU time 18.48 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 243968 kb
Host smart-2b46426d-02ed-499a-890e-42e021019bda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854930394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2854930394
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.3731793326
Short name T114
Test name
Test status
Simulation time 16346447081 ps
CPU time 302.86 seconds
Started Jun 22 06:59:07 PM PDT 24
Finished Jun 22 07:04:15 PM PDT 24
Peak memory 266288 kb
Host smart-a17e9110-7410-4ff4-9d9f-e0a0eb05c99c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731793326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.3731793326
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.2520539850
Short name T293
Test name
Test status
Simulation time 915737084494 ps
CPU time 1485.33 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:26:19 PM PDT 24
Peak memory 283996 kb
Host smart-6f6363e1-dd22-4091-9b00-f3d3a8f861ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520539850 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.2520539850
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2790709363
Short name T26
Test name
Test status
Simulation time 1614124515 ps
CPU time 4.82 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:48 PM PDT 24
Peak memory 242624 kb
Host smart-c543bcf5-ec87-44a4-bb85-f1b4c07567bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790709363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2790709363
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.1558538578
Short name T5
Test name
Test status
Simulation time 34142973493 ps
CPU time 951.64 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 07:15:04 PM PDT 24
Peak memory 304844 kb
Host smart-24eea0a7-9c14-457f-b8eb-bc08b52b4da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558538578 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.1558538578
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.2550658350
Short name T50
Test name
Test status
Simulation time 3205086919 ps
CPU time 36.14 seconds
Started Jun 22 06:58:01 PM PDT 24
Finished Jun 22 06:58:39 PM PDT 24
Peak memory 249156 kb
Host smart-61926ae5-e264-4b3d-a3b2-000ed4179fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550658350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2550658350
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3528178724
Short name T121
Test name
Test status
Simulation time 15941121040 ps
CPU time 181.29 seconds
Started Jun 22 06:59:00 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 249840 kb
Host smart-504d0f11-a0c8-4196-bf6a-487fb092d142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528178724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3528178724
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.3376653858
Short name T57
Test name
Test status
Simulation time 270126327 ps
CPU time 3.57 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:37 PM PDT 24
Peak memory 242144 kb
Host smart-75d05964-4ab2-4bcd-babe-116b02969dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376653858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3376653858
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.1811024849
Short name T231
Test name
Test status
Simulation time 310167320779 ps
CPU time 2542.5 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 07:41:46 PM PDT 24
Peak memory 312608 kb
Host smart-2075dcc3-d08e-4e26-af75-6a83c56573bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811024849 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.1811024849
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1253861292
Short name T2
Test name
Test status
Simulation time 199820774 ps
CPU time 1.89 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:30 PM PDT 24
Peak memory 240524 kb
Host smart-0d755092-e18f-467f-b034-ad341e2c6a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253861292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1253861292
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3114714795
Short name T3
Test name
Test status
Simulation time 95132209 ps
CPU time 3.61 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242408 kb
Host smart-3fec103f-54da-448d-9f49-1ca31fbc94c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114714795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3114714795
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1614662708
Short name T65
Test name
Test status
Simulation time 272898654 ps
CPU time 4.27 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 242492 kb
Host smart-7d54992f-6d30-436d-9651-ba259adc3ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614662708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1614662708
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.194394591
Short name T22
Test name
Test status
Simulation time 87263195041 ps
CPU time 1117.52 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:19:27 PM PDT 24
Peak memory 336472 kb
Host smart-03150ef0-bb0b-4ee8-a2ab-da068bdb1db4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194394591 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.194394591
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.2672437074
Short name T144
Test name
Test status
Simulation time 111210436 ps
CPU time 4.05 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242220 kb
Host smart-179379dc-602b-407e-96cf-599d8b7725da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672437074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.2672437074
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1747719033
Short name T32
Test name
Test status
Simulation time 297911182 ps
CPU time 4.94 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 242616 kb
Host smart-c3333621-e23f-4803-b67a-42c83d68689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747719033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1747719033
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.3848106452
Short name T14
Test name
Test status
Simulation time 616446234 ps
CPU time 4.95 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242720 kb
Host smart-f057f005-1abb-49a5-8085-81ee87b7e62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848106452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3848106452
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.548671334
Short name T262
Test name
Test status
Simulation time 764032921523 ps
CPU time 2425.34 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 07:37:54 PM PDT 24
Peak memory 450908 kb
Host smart-a92e33e1-a7ad-458b-baf3-9c58a78fb4c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548671334 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.548671334
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.1338634435
Short name T52
Test name
Test status
Simulation time 2018596561 ps
CPU time 5.41 seconds
Started Jun 22 06:57:52 PM PDT 24
Finished Jun 22 06:57:59 PM PDT 24
Peak memory 241952 kb
Host smart-6dc7f17b-cbc0-4516-a807-b4644da4a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338634435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1338634435
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.2655459042
Short name T83
Test name
Test status
Simulation time 199113694 ps
CPU time 4.91 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242628 kb
Host smart-221db072-0b51-446c-9341-3a116b49f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655459042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2655459042
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.2935895273
Short name T49
Test name
Test status
Simulation time 160382311 ps
CPU time 4.15 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:23 PM PDT 24
Peak memory 242096 kb
Host smart-e3583d4c-6007-4aed-9bb4-56fe126b8c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935895273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.2935895273
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3565971843
Short name T658
Test name
Test status
Simulation time 16636304652 ps
CPU time 46.34 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 249112 kb
Host smart-e61f4ddb-979d-4773-820b-c7ce438c52b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565971843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3565971843
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1983536002
Short name T42
Test name
Test status
Simulation time 250586260 ps
CPU time 4.69 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:33 PM PDT 24
Peak memory 242608 kb
Host smart-61875bbc-862e-405d-a331-801d9a00e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983536002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1983536002
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.716134483
Short name T220
Test name
Test status
Simulation time 56592091677 ps
CPU time 84.14 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 251488 kb
Host smart-32b99a73-4c7d-4252-b5c5-6e625dfd9e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716134483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.
716134483
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3378336881
Short name T307
Test name
Test status
Simulation time 150926595 ps
CPU time 4.7 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 238364 kb
Host smart-d8b45605-3610-4b3d-9077-0c100a273434
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378336881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.3378336881
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1484385982
Short name T29
Test name
Test status
Simulation time 716099078 ps
CPU time 26.02 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 243484 kb
Host smart-7b680b50-4d6b-4fe7-8434-8f20b14f6390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484385982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1484385982
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.822661066
Short name T96
Test name
Test status
Simulation time 1975044094 ps
CPU time 4.65 seconds
Started Jun 22 07:02:43 PM PDT 24
Finished Jun 22 07:02:50 PM PDT 24
Peak memory 242312 kb
Host smart-a137c574-694b-47b1-a266-0ce7957ce146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822661066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.822661066
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.840409303
Short name T258
Test name
Test status
Simulation time 23942475470 ps
CPU time 128.98 seconds
Started Jun 22 06:59:04 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 249668 kb
Host smart-9b0a6de5-689d-43fc-9c32-80ac2b6bef79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840409303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
840409303
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.67724101
Short name T366
Test name
Test status
Simulation time 4578593778 ps
CPU time 13.5 seconds
Started Jun 22 07:00:51 PM PDT 24
Finished Jun 22 07:01:11 PM PDT 24
Peak memory 242268 kb
Host smart-90aa6bd8-e388-408b-8215-81b3553fba90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=67724101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.67724101
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.2833837899
Short name T55
Test name
Test status
Simulation time 412935900 ps
CPU time 4.55 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:35 PM PDT 24
Peak memory 242284 kb
Host smart-02a4d208-91b9-4fd8-b2bb-a0cad9c0bfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833837899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2833837899
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2631005033
Short name T90
Test name
Test status
Simulation time 464966333 ps
CPU time 3.63 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:01:58 PM PDT 24
Peak memory 242640 kb
Host smart-5a9fe563-f017-4f0f-ac4a-501285010158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631005033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2631005033
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3633299502
Short name T353
Test name
Test status
Simulation time 4992723884 ps
CPU time 23.24 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 238532 kb
Host smart-e04cd15a-6e4b-41a6-bf14-3e98b2d1d788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633299502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.3633299502
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1182806905
Short name T216
Test name
Test status
Simulation time 24446076543 ps
CPU time 242.54 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 07:03:30 PM PDT 24
Peak memory 273708 kb
Host smart-ad6f4c13-643b-493c-a997-e00e9852b727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182806905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1182806905
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.3751862665
Short name T72
Test name
Test status
Simulation time 119997570432 ps
CPU time 1199.43 seconds
Started Jun 22 07:01:00 PM PDT 24
Finished Jun 22 07:21:04 PM PDT 24
Peak memory 356092 kb
Host smart-a4a83e22-2239-448b-a3ee-63eee14a1a25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751862665 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.3751862665
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.2240835350
Short name T19
Test name
Test status
Simulation time 136042123265 ps
CPU time 1212.26 seconds
Started Jun 22 07:01:12 PM PDT 24
Finished Jun 22 07:21:29 PM PDT 24
Peak memory 276080 kb
Host smart-ae508b44-527e-4d10-a37f-0b1e3c043a56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240835350 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.2240835350
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3443551741
Short name T237
Test name
Test status
Simulation time 832692947 ps
CPU time 12.82 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:34 PM PDT 24
Peak memory 242376 kb
Host smart-eb9bb42f-841e-4fab-af72-932793e08611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443551741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3443551741
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.32418480
Short name T193
Test name
Test status
Simulation time 9344649807 ps
CPU time 112.59 seconds
Started Jun 22 06:58:08 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 261968 kb
Host smart-94a2f8d2-a87e-43c1-954d-a32f62cc8949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32418480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.32418480
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.1228167207
Short name T254
Test name
Test status
Simulation time 147101196639 ps
CPU time 1124.45 seconds
Started Jun 22 06:58:13 PM PDT 24
Finished Jun 22 07:16:58 PM PDT 24
Peak memory 351492 kb
Host smart-0c9f9983-78cc-431c-b459-7f57fd68d488
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228167207 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1228167207
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3302846867
Short name T36
Test name
Test status
Simulation time 759299180 ps
CPU time 5.12 seconds
Started Jun 22 07:02:31 PM PDT 24
Finished Jun 22 07:02:38 PM PDT 24
Peak memory 242288 kb
Host smart-e8390f69-d01b-48f3-b129-a67b7bf61556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302846867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3302846867
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.3894033106
Short name T41
Test name
Test status
Simulation time 9305211568 ps
CPU time 19.51 seconds
Started Jun 22 07:00:06 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 243012 kb
Host smart-f1ecfd17-fd9f-466c-be03-7e01389d0a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894033106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3894033106
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.4014793707
Short name T190
Test name
Test status
Simulation time 821311920 ps
CPU time 11.65 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:00:58 PM PDT 24
Peak memory 242052 kb
Host smart-e99c10fb-101d-46df-95eb-3a8dc815627f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014793707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.4014793707
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.3389986295
Short name T225
Test name
Test status
Simulation time 40930691382 ps
CPU time 352.05 seconds
Started Jun 22 06:58:02 PM PDT 24
Finished Jun 22 07:03:55 PM PDT 24
Peak memory 290108 kb
Host smart-86259056-a69c-47d5-aa59-8cbddbb787c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389986295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
3389986295
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.433523126
Short name T223
Test name
Test status
Simulation time 288404043 ps
CPU time 16.24 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242128 kb
Host smart-25e96db3-e1a1-4490-a9e6-77330539f62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433523126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.433523126
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.188290551
Short name T138
Test name
Test status
Simulation time 541347990 ps
CPU time 15.74 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:12 PM PDT 24
Peak memory 242100 kb
Host smart-7f20739d-276b-4031-aa4f-16c4a9901add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188290551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.188290551
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.526520637
Short name T73
Test name
Test status
Simulation time 50880162365 ps
CPU time 1181.68 seconds
Started Jun 22 06:59:10 PM PDT 24
Finished Jun 22 07:18:57 PM PDT 24
Peak memory 348212 kb
Host smart-432b6263-be63-4f0b-baec-4c8000ce880a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526520637 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.526520637
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.776515588
Short name T119
Test name
Test status
Simulation time 158893135 ps
CPU time 4.52 seconds
Started Jun 22 07:02:31 PM PDT 24
Finished Jun 22 07:02:37 PM PDT 24
Peak memory 242568 kb
Host smart-b12777a5-59f1-4bbf-a1e2-44f75ad83e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776515588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.776515588
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2357528497
Short name T79
Test name
Test status
Simulation time 440571457 ps
CPU time 5.91 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:43 PM PDT 24
Peak memory 242212 kb
Host smart-5208ea5a-aced-4a37-83f4-cf52b0849c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357528497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2357528497
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.3968115706
Short name T228
Test name
Test status
Simulation time 277510771 ps
CPU time 8.74 seconds
Started Jun 22 07:01:03 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242088 kb
Host smart-47efe68e-57e8-49ce-8cf4-269f71b1af51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968115706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.3968115706
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3561221610
Short name T94
Test name
Test status
Simulation time 509095247 ps
CPU time 4.62 seconds
Started Jun 22 07:01:41 PM PDT 24
Finished Jun 22 07:01:49 PM PDT 24
Peak memory 242260 kb
Host smart-446b343a-d9e7-4b4b-a68b-9d9fd950e1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561221610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3561221610
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1583724055
Short name T362
Test name
Test status
Simulation time 414419919 ps
CPU time 8.33 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:29 PM PDT 24
Peak memory 242348 kb
Host smart-ad728db0-8c63-45c0-a537-1658249f7437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1583724055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1583724055
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3774948339
Short name T63
Test name
Test status
Simulation time 4679133317 ps
CPU time 14.63 seconds
Started Jun 22 06:59:33 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 242744 kb
Host smart-71a716ab-9452-424c-b78b-a71b12c57515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774948339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3774948339
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.3864154532
Short name T450
Test name
Test status
Simulation time 5755134924 ps
CPU time 71.44 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 249464 kb
Host smart-5d444d4f-7397-4268-9c70-9eb4c6ec932c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864154532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.3864154532
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3145695095
Short name T44
Test name
Test status
Simulation time 13093793719 ps
CPU time 34.28 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:46 PM PDT 24
Peak memory 244580 kb
Host smart-8e4ee512-21a2-4bae-aa71-cacd2db86f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145695095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3145695095
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1071263053
Short name T282
Test name
Test status
Simulation time 100395219 ps
CPU time 1.59 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 239996 kb
Host smart-1c2e311d-a3e1-4817-8706-a35bc57ebd25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071263053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1071263053
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.724771829
Short name T221
Test name
Test status
Simulation time 186423489465 ps
CPU time 1175.85 seconds
Started Jun 22 06:58:00 PM PDT 24
Finished Jun 22 07:17:37 PM PDT 24
Peak memory 325408 kb
Host smart-71d30aee-62ab-4847-9d40-0276f5fa9ec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724771829 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.724771829
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.939146313
Short name T696
Test name
Test status
Simulation time 3108480938 ps
CPU time 46.48 seconds
Started Jun 22 07:00:26 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 250904 kb
Host smart-6a2dbf64-5323-4221-860f-182dd92745f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939146313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.939146313
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.4287196294
Short name T47
Test name
Test status
Simulation time 153348358 ps
CPU time 4.2 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242404 kb
Host smart-4faf14fd-e29c-487b-a074-33fa9d40a40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287196294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.4287196294
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.836029275
Short name T84
Test name
Test status
Simulation time 1060108262 ps
CPU time 26.32 seconds
Started Jun 22 06:57:19 PM PDT 24
Finished Jun 22 06:57:46 PM PDT 24
Peak memory 244676 kb
Host smart-fc04833a-2a80-4abe-bdaf-072f03f94ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836029275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.836029275
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.713212310
Short name T82
Test name
Test status
Simulation time 1358014790 ps
CPU time 19.42 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242544 kb
Host smart-95eb76ba-2d64-41df-b031-875d9e3105a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713212310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.713212310
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.495347607
Short name T59
Test name
Test status
Simulation time 285247157 ps
CPU time 7.3 seconds
Started Jun 22 06:58:25 PM PDT 24
Finished Jun 22 06:58:34 PM PDT 24
Peak memory 242628 kb
Host smart-a1850c11-bd16-496f-9350-7b6c30678441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495347607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.495347607
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.507160726
Short name T610
Test name
Test status
Simulation time 109503158 ps
CPU time 3.41 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:43 PM PDT 24
Peak memory 242480 kb
Host smart-9627fb44-a655-4056-b4ec-525a806518f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507160726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.507160726
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2449124828
Short name T129
Test name
Test status
Simulation time 276541800 ps
CPU time 4.15 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242656 kb
Host smart-b842c1f4-b124-4062-bf11-00741616237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449124828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2449124828
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.796985488
Short name T949
Test name
Test status
Simulation time 3187910145 ps
CPU time 9.94 seconds
Started Jun 22 06:58:26 PM PDT 24
Finished Jun 22 06:58:37 PM PDT 24
Peak memory 242568 kb
Host smart-a7a45207-168c-434a-b1d7-2e354484609d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=796985488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.796985488
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.3754931751
Short name T1003
Test name
Test status
Simulation time 1114754941 ps
CPU time 7.53 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:35 PM PDT 24
Peak memory 242472 kb
Host smart-46087480-6d66-4f86-9067-4fd6b519dbeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3754931751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3754931751
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2060632206
Short name T276
Test name
Test status
Simulation time 686417483 ps
CPU time 9.97 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 243384 kb
Host smart-7ca69caf-e67a-462a-aa5f-63079fe79353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060632206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2060632206
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.25550557
Short name T283
Test name
Test status
Simulation time 20073107868 ps
CPU time 24.46 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:55:02 PM PDT 24
Peak memory 245212 kb
Host smart-4ea60796-1527-4c19-8fab-a6dd51df7512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25550557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_int
g_err.25550557
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2393608536
Short name T28
Test name
Test status
Simulation time 1352438903 ps
CPU time 5.11 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:19 PM PDT 24
Peak memory 242336 kb
Host smart-be6b7167-b474-4ccd-8440-4d80aa943ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393608536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2393608536
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3424792094
Short name T266
Test name
Test status
Simulation time 503937429831 ps
CPU time 1967.08 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 07:30:32 PM PDT 24
Peak memory 282384 kb
Host smart-b57db77c-4fe5-4dfd-8dab-6953d53a67f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424792094 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.3424792094
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3727661545
Short name T105
Test name
Test status
Simulation time 589510521 ps
CPU time 16.94 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:46 PM PDT 24
Peak memory 242076 kb
Host smart-47544c28-364f-4436-afbb-81f9f4446ef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727661545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3727661545
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3180999720
Short name T86
Test name
Test status
Simulation time 505588539 ps
CPU time 4.74 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 07:01:18 PM PDT 24
Peak memory 242516 kb
Host smart-6b29080e-b67e-4dfa-835e-d355c7272e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180999720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3180999720
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3991514645
Short name T134
Test name
Test status
Simulation time 2578495091 ps
CPU time 15.44 seconds
Started Jun 22 06:57:57 PM PDT 24
Finished Jun 22 06:58:14 PM PDT 24
Peak memory 242716 kb
Host smart-57bf95bb-6e02-461d-9ecd-6acce80946d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991514645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3991514645
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.1391642110
Short name T91
Test name
Test status
Simulation time 221004230 ps
CPU time 3.36 seconds
Started Jun 22 07:01:38 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242476 kb
Host smart-98dea567-444d-40b7-b7df-12f777bd7280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391642110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.1391642110
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2198731647
Short name T1032
Test name
Test status
Simulation time 347804673 ps
CPU time 4.35 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242440 kb
Host smart-aa0a4ca0-2b9a-416d-aa35-79c5c3e735b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198731647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2198731647
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.2239044239
Short name T27
Test name
Test status
Simulation time 162276569 ps
CPU time 4.23 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:01:24 PM PDT 24
Peak memory 242196 kb
Host smart-4fe5950c-9794-4806-8023-8fd018dc2856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239044239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2239044239
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.4010520792
Short name T264
Test name
Test status
Simulation time 6390089422 ps
CPU time 59.08 seconds
Started Jun 22 06:57:28 PM PDT 24
Finished Jun 22 06:58:28 PM PDT 24
Peak memory 245280 kb
Host smart-c465c540-45f2-460b-9f06-84c78cc7437a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010520792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
4010520792
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.2612793996
Short name T100
Test name
Test status
Simulation time 1300718069 ps
CPU time 19.36 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:59:05 PM PDT 24
Peak memory 242256 kb
Host smart-10023a24-1de8-4113-b4f3-d19470bc4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612793996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2612793996
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3884665470
Short name T161
Test name
Test status
Simulation time 33309530953 ps
CPU time 86.13 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:58:47 PM PDT 24
Peak memory 248020 kb
Host smart-72dfc8bb-e2a3-405d-b189-b61abd7fc097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884665470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3884665470
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1739704178
Short name T1221
Test name
Test status
Simulation time 115920637 ps
CPU time 3.12 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 238404 kb
Host smart-e9b6d796-b71d-47f7-bd26-f68cecac7f9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739704178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.1739704178
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.357890995
Short name T1314
Test name
Test status
Simulation time 2050285359 ps
CPU time 11.51 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 238388 kb
Host smart-06874c29-2a73-42ed-944c-7dc74e35be54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357890995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.357890995
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.68331746
Short name T319
Test name
Test status
Simulation time 395394404 ps
CPU time 2.38 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 238424 kb
Host smart-ad6993af-eb0d-4903-9fcc-bd9382c1b7a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68331746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_res
et.68331746
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.135306501
Short name T1309
Test name
Test status
Simulation time 220015999 ps
CPU time 2.98 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 246748 kb
Host smart-0de767b5-eba2-4ac2-9b88-1c38e80eaf12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135306501 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.135306501
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.215900569
Short name T1272
Test name
Test status
Simulation time 624071806 ps
CPU time 1.97 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 240240 kb
Host smart-a17460c3-ede7-418f-94e5-d1843d4275ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215900569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.215900569
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.3437067564
Short name T1293
Test name
Test status
Simulation time 38379114 ps
CPU time 1.39 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 229476 kb
Host smart-44b820ca-de92-4685-8dd6-2852ad089008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437067564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.3437067564
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3028228781
Short name T1196
Test name
Test status
Simulation time 52220519 ps
CPU time 1.33 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 229304 kb
Host smart-7b64d284-fa51-44e9-983d-cc485837c26a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028228781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.3028228781
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1303650179
Short name T1263
Test name
Test status
Simulation time 65722993 ps
CPU time 1.34 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 230180 kb
Host smart-44cc1d45-63d6-4300-b078-cc257ef23d76
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303650179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1303650179
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3917120193
Short name T1239
Test name
Test status
Simulation time 1261999554 ps
CPU time 3.44 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 241652 kb
Host smart-3dc017fa-b6d7-4db9-9897-48673a350f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917120193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.3917120193
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3961844127
Short name T1247
Test name
Test status
Simulation time 187773432 ps
CPU time 5.56 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 245828 kb
Host smart-ceab0986-f11a-469d-94d7-f23804aaf07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961844127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3961844127
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.239665970
Short name T359
Test name
Test status
Simulation time 1221960018 ps
CPU time 16.79 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 238532 kb
Host smart-fc6b9417-fd46-48a6-a58e-38e0f1369037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239665970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_int
g_err.239665970
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.1128227682
Short name T316
Test name
Test status
Simulation time 81614985 ps
CPU time 4.77 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 238480 kb
Host smart-8118a1fd-93cf-430b-b5d6-086e40ac98f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128227682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.1128227682
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.578905899
Short name T279
Test name
Test status
Simulation time 371108909 ps
CPU time 5.17 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 238468 kb
Host smart-0cfe720e-b955-4c12-90f3-a5955ef890a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578905899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.578905899
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3241970305
Short name T318
Test name
Test status
Simulation time 66196265 ps
CPU time 1.75 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 239904 kb
Host smart-d357c575-894d-453a-a0e2-9cedd813e9f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241970305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.3241970305
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.797807761
Short name T1264
Test name
Test status
Simulation time 1779877545 ps
CPU time 3.23 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 246660 kb
Host smart-73e50990-576d-489c-b662-c2be2c3e7847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797807761 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.797807761
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1323669730
Short name T317
Test name
Test status
Simulation time 72593530 ps
CPU time 1.41 seconds
Started Jun 22 04:54:09 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 238252 kb
Host smart-7fec8b8d-d5d2-417a-85e4-7e3a9ef12107
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323669730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1323669730
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.994541536
Short name T1286
Test name
Test status
Simulation time 39491943 ps
CPU time 1.45 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:14 PM PDT 24
Peak memory 229764 kb
Host smart-f2f75957-d977-4839-8486-48be96351216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994541536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.994541536
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.989972211
Short name T1195
Test name
Test status
Simulation time 40848611 ps
CPU time 1.42 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 229328 kb
Host smart-2d031144-5763-435a-a905-bc014d250ae7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989972211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl
_mem_partial_access.989972211
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3528346530
Short name T1310
Test name
Test status
Simulation time 39206833 ps
CPU time 1.33 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 230176 kb
Host smart-140d5c6b-511c-45f7-bcac-04e7619f582f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528346530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.3528346530
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.569592647
Short name T1305
Test name
Test status
Simulation time 162243750 ps
CPU time 2.02 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 238432 kb
Host smart-74784c47-2e0a-464b-92b1-7fca7078f40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569592647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_same_csr_outstanding.569592647
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1777997076
Short name T1317
Test name
Test status
Simulation time 139912977 ps
CPU time 2.78 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 245356 kb
Host smart-8b53052b-e5d2-4b3b-bf38-1fe61ed21b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777997076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1777997076
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1824481322
Short name T355
Test name
Test status
Simulation time 19973313350 ps
CPU time 29.8 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:42 PM PDT 24
Peak memory 244296 kb
Host smart-defa0c7b-3259-4145-a02d-ad6fc4bbef83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824481322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1824481322
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.2876657061
Short name T1245
Test name
Test status
Simulation time 66884631 ps
CPU time 1.92 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 243572 kb
Host smart-57a4842b-5e06-42e0-abc0-36461f13bacf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876657061 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.2876657061
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.4004763083
Short name T315
Test name
Test status
Simulation time 43037334 ps
CPU time 1.58 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 240396 kb
Host smart-c9f9ce8f-dfe4-47b4-8e66-021004d9115d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004763083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.4004763083
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.146237707
Short name T1222
Test name
Test status
Simulation time 87173668 ps
CPU time 1.52 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 229548 kb
Host smart-119fed8e-8473-4799-89fb-3eb35d5fa827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146237707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.146237707
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1256251855
Short name T1287
Test name
Test status
Simulation time 74776739 ps
CPU time 2.27 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 241620 kb
Host smart-b9288490-f8b6-4247-97bc-6b6a078c28b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256251855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1256251855
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1667279566
Short name T1220
Test name
Test status
Simulation time 1166885032 ps
CPU time 5.93 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 245760 kb
Host smart-d654e935-c7b0-48e7-ac26-fb21b61f0f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667279566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1667279566
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1962547306
Short name T1315
Test name
Test status
Simulation time 1477445235 ps
CPU time 9.82 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:31 PM PDT 24
Peak memory 243228 kb
Host smart-5fb38ef3-971d-46b4-8449-792abe489ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962547306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1962547306
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1617492417
Short name T1256
Test name
Test status
Simulation time 110147602 ps
CPU time 2.22 seconds
Started Jun 22 04:54:25 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 245644 kb
Host smart-c546c018-1519-4327-a47f-e2b824080d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617492417 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1617492417
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1287432735
Short name T314
Test name
Test status
Simulation time 46728929 ps
CPU time 1.79 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 240644 kb
Host smart-7d98c987-55ca-4d7d-b396-364504bc2b7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287432735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1287432735
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3539366350
Short name T1279
Test name
Test status
Simulation time 105175254 ps
CPU time 1.42 seconds
Started Jun 22 04:54:30 PM PDT 24
Finished Jun 22 04:54:32 PM PDT 24
Peak memory 230252 kb
Host smart-d51be8c9-adab-40e1-9ce2-cfb663fd98a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539366350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3539366350
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3953034714
Short name T1308
Test name
Test status
Simulation time 178146282 ps
CPU time 3.13 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 241740 kb
Host smart-587e461c-1885-4a83-91be-71390c07b155
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953034714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3953034714
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.693928628
Short name T1260
Test name
Test status
Simulation time 223956081 ps
CPU time 3.74 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:25 PM PDT 24
Peak memory 245696 kb
Host smart-3b262e83-c7dd-409a-9690-85a202b8f5bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693928628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.693928628
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.4057608063
Short name T356
Test name
Test status
Simulation time 1294651078 ps
CPU time 18.69 seconds
Started Jun 22 04:54:30 PM PDT 24
Finished Jun 22 04:54:49 PM PDT 24
Peak memory 238568 kb
Host smart-833a21ee-122c-4dcb-8ef5-10052323e694
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057608063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.4057608063
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.792739477
Short name T1209
Test name
Test status
Simulation time 97195338 ps
CPU time 3.14 seconds
Started Jun 22 04:54:25 PM PDT 24
Finished Jun 22 04:54:29 PM PDT 24
Peak memory 246372 kb
Host smart-1cdfd50f-2e09-4cd7-ad53-12baf7c8a63f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792739477 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.792739477
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3904569357
Short name T1249
Test name
Test status
Simulation time 55646557 ps
CPU time 1.63 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 238464 kb
Host smart-d876361c-db16-4cca-80c3-083c0dafb63c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904569357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3904569357
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.2311237857
Short name T1250
Test name
Test status
Simulation time 130709100 ps
CPU time 1.35 seconds
Started Jun 22 04:54:28 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 229748 kb
Host smart-f9fbeee7-1193-44b2-9bab-540ef2ad9da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311237857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2311237857
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.3828325382
Short name T1236
Test name
Test status
Simulation time 72318011 ps
CPU time 2.15 seconds
Started Jun 22 04:54:25 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 238512 kb
Host smart-c7676755-fb59-449e-80a6-b7691677fbca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828325382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.3828325382
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.249367320
Short name T1187
Test name
Test status
Simulation time 196070966 ps
CPU time 3.05 seconds
Started Jun 22 04:54:27 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 245488 kb
Host smart-85f0ff74-6f06-4d09-80ef-c1849e781e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249367320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.249367320
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.1449687513
Short name T354
Test name
Test status
Simulation time 705025979 ps
CPU time 10.08 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:36 PM PDT 24
Peak memory 238480 kb
Host smart-79bb6f59-cddc-4724-8a8a-4ab358ad6f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449687513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.1449687513
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3990788667
Short name T1295
Test name
Test status
Simulation time 101145051 ps
CPU time 2.56 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 246764 kb
Host smart-1550e832-5f44-42b2-b0d7-5acdbe3fc3dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990788667 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3990788667
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1119391256
Short name T1193
Test name
Test status
Simulation time 40760621 ps
CPU time 1.4 seconds
Started Jun 22 04:54:25 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 229096 kb
Host smart-ed05c709-f584-41c5-8daf-697c7480e30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119391256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1119391256
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3459590412
Short name T1285
Test name
Test status
Simulation time 164627019 ps
CPU time 1.93 seconds
Started Jun 22 04:54:31 PM PDT 24
Finished Jun 22 04:54:33 PM PDT 24
Peak memory 238516 kb
Host smart-f795a502-dda7-4295-8127-0a71702a9ef8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459590412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3459590412
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3399498069
Short name T1258
Test name
Test status
Simulation time 306299984 ps
CPU time 5.46 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:31 PM PDT 24
Peak memory 245408 kb
Host smart-959b8a13-7593-455f-ac67-cbe0927220e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399498069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3399498069
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3431302588
Short name T358
Test name
Test status
Simulation time 726005913 ps
CPU time 10.43 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:36 PM PDT 24
Peak memory 242176 kb
Host smart-f771c708-1e51-4422-b970-fd01f77154f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431302588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.3431302588
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4071584197
Short name T280
Test name
Test status
Simulation time 102076452 ps
CPU time 2.85 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 246776 kb
Host smart-78895c09-813d-420f-82a8-b82979a2c6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071584197 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.4071584197
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1442857270
Short name T309
Test name
Test status
Simulation time 49737707 ps
CPU time 1.51 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 237476 kb
Host smart-109ce1dc-7ce8-4fc0-90ff-c31cee30e639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442857270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1442857270
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2092617025
Short name T1233
Test name
Test status
Simulation time 74145779 ps
CPU time 1.37 seconds
Started Jun 22 04:54:28 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 229476 kb
Host smart-d2b6b955-9334-46fd-96a6-2eab59838891
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092617025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2092617025
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1800151530
Short name T1274
Test name
Test status
Simulation time 968244811 ps
CPU time 2.81 seconds
Started Jun 22 04:54:31 PM PDT 24
Finished Jun 22 04:54:34 PM PDT 24
Peak memory 238568 kb
Host smart-ab2f13a4-1d5e-4982-ba4c-9e162d9e9015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800151530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.1800151530
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.4134336386
Short name T1204
Test name
Test status
Simulation time 112833558 ps
CPU time 3.85 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 245424 kb
Host smart-f7985e33-2ac9-4ae1-8c5d-c607611fe090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134336386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.4134336386
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1793817830
Short name T277
Test name
Test status
Simulation time 2718450619 ps
CPU time 20.99 seconds
Started Jun 22 04:54:26 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 243916 kb
Host smart-3644368a-5332-4fbd-9a34-70c6e18df279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793817830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1793817830
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.466407506
Short name T1271
Test name
Test status
Simulation time 266379490 ps
CPU time 3.72 seconds
Started Jun 22 04:54:31 PM PDT 24
Finished Jun 22 04:54:35 PM PDT 24
Peak memory 246740 kb
Host smart-504bed08-db6a-4754-914c-db0177ab2cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466407506 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.466407506
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.599863559
Short name T323
Test name
Test status
Simulation time 81024696 ps
CPU time 1.66 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 240616 kb
Host smart-86ae0a49-0eb4-4af0-bdd9-7c1d1d7d8dd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599863559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.599863559
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.1554575511
Short name T1219
Test name
Test status
Simulation time 86218734 ps
CPU time 1.56 seconds
Started Jun 22 04:54:27 PM PDT 24
Finished Jun 22 04:54:29 PM PDT 24
Peak memory 230092 kb
Host smart-04caa5f4-a24a-4028-9692-9517efa47d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554575511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1554575511
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3038203913
Short name T1266
Test name
Test status
Simulation time 92219700 ps
CPU time 2.03 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 238444 kb
Host smart-59643ee8-90b4-448d-aaae-058fb92fda5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038203913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.3038203913
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.553884359
Short name T1278
Test name
Test status
Simulation time 271940250 ps
CPU time 4.87 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 245688 kb
Host smart-a4bdda3a-be16-437f-adb7-dac8c8901f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553884359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.553884359
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.61832804
Short name T1297
Test name
Test status
Simulation time 19951366939 ps
CPU time 30.91 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:55 PM PDT 24
Peak memory 244196 kb
Host smart-6f233762-6e00-49e7-a538-ba56acb08b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61832804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_int
g_err.61832804
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.3760919423
Short name T1280
Test name
Test status
Simulation time 108363551 ps
CPU time 2.82 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:39 PM PDT 24
Peak memory 246116 kb
Host smart-45839244-6131-4826-be8a-dc9d9acb170a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760919423 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.3760919423
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1061853379
Short name T1248
Test name
Test status
Simulation time 48712024 ps
CPU time 1.77 seconds
Started Jun 22 04:54:34 PM PDT 24
Finished Jun 22 04:54:37 PM PDT 24
Peak memory 240708 kb
Host smart-ccff4b97-b557-47d8-83f7-aa42d9c7c4cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061853379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1061853379
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.625297603
Short name T1281
Test name
Test status
Simulation time 50735187 ps
CPU time 1.5 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:37 PM PDT 24
Peak memory 229524 kb
Host smart-223f10fe-6a2b-47dc-a927-78a9cc3115f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625297603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.625297603
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4219153715
Short name T1232
Test name
Test status
Simulation time 194916452 ps
CPU time 2.5 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 241560 kb
Host smart-99b92791-c205-43fd-8ebc-30f9ce4a3f2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219153715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.4219153715
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1397967585
Short name T1192
Test name
Test status
Simulation time 285302955 ps
CPU time 7.09 seconds
Started Jun 22 04:54:38 PM PDT 24
Finished Jun 22 04:54:46 PM PDT 24
Peak memory 246476 kb
Host smart-a6fb701f-7e1f-43b8-b3aa-3bd0b47831da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397967585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1397967585
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.294456772
Short name T1307
Test name
Test status
Simulation time 4662195844 ps
CPU time 22.44 seconds
Started Jun 22 04:54:34 PM PDT 24
Finished Jun 22 04:54:58 PM PDT 24
Peak memory 238584 kb
Host smart-eca17718-3292-4ce5-bc4f-3dd498d0a7cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294456772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.294456772
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.1171306200
Short name T1284
Test name
Test status
Simulation time 1647267881 ps
CPU time 4.64 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:42 PM PDT 24
Peak memory 246700 kb
Host smart-f7c47ba6-5fa0-41ab-a093-89b248f3e12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171306200 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.1171306200
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1850891867
Short name T321
Test name
Test status
Simulation time 157470125 ps
CPU time 1.72 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 240412 kb
Host smart-fe8a0a79-8cfd-4f30-8a09-41908ee715c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850891867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1850891867
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.1529083435
Short name T1273
Test name
Test status
Simulation time 137371792 ps
CPU time 1.47 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 229368 kb
Host smart-fb766e82-8aa9-4beb-863e-a875aaa07a59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529083435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1529083435
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.952814845
Short name T1282
Test name
Test status
Simulation time 312753221 ps
CPU time 3.06 seconds
Started Jun 22 04:54:34 PM PDT 24
Finished Jun 22 04:54:38 PM PDT 24
Peak memory 238392 kb
Host smart-25a73c27-e17f-4906-8c37-1675b1d46f7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952814845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.952814845
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1963748583
Short name T1302
Test name
Test status
Simulation time 75532594 ps
CPU time 5.12 seconds
Started Jun 22 04:54:38 PM PDT 24
Finished Jun 22 04:54:44 PM PDT 24
Peak memory 238504 kb
Host smart-071b94ee-5660-4772-b499-a67b44c79a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963748583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1963748583
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3900477597
Short name T1312
Test name
Test status
Simulation time 201685271 ps
CPU time 2.72 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 245952 kb
Host smart-0de8a6b1-f3da-43d7-84dc-9cd8d2a3636b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900477597 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3900477597
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.428499002
Short name T310
Test name
Test status
Simulation time 41924346 ps
CPU time 1.58 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 240724 kb
Host smart-f8606186-b959-4077-8daa-99216c8b7386
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428499002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.428499002
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.4026408766
Short name T1255
Test name
Test status
Simulation time 103859243 ps
CPU time 1.36 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 229668 kb
Host smart-4873e6fa-c6a1-44bb-83e8-76ec6e4bc0b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026408766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.4026408766
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1021323370
Short name T324
Test name
Test status
Simulation time 67256479 ps
CPU time 2.54 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 238524 kb
Host smart-a37c4e63-98c4-4854-8143-4f10946e4aba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021323370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1021323370
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.319266032
Short name T1191
Test name
Test status
Simulation time 66797617 ps
CPU time 3.7 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 246048 kb
Host smart-d665f544-4d40-4d8f-ae85-dac4cc67758e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319266032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.319266032
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3773996264
Short name T1268
Test name
Test status
Simulation time 4835150678 ps
CPU time 21.82 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:55:00 PM PDT 24
Peak memory 245280 kb
Host smart-037c5077-0024-4168-aa91-7132a164ed7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773996264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3773996264
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1824024053
Short name T1289
Test name
Test status
Simulation time 225195778 ps
CPU time 3.37 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 246696 kb
Host smart-47173703-838d-401b-a5f1-f4a446cbc6d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824024053 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1824024053
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.458218395
Short name T1313
Test name
Test status
Simulation time 617516155 ps
CPU time 1.56 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:37 PM PDT 24
Peak memory 238504 kb
Host smart-f5baae92-0b47-42f8-ae9b-6e78daa66402
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458218395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.458218395
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1662844231
Short name T1231
Test name
Test status
Simulation time 521207348 ps
CPU time 1.66 seconds
Started Jun 22 04:54:39 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 229524 kb
Host smart-df0cc2db-3e93-43f9-b4dc-9661e3c5de6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662844231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1662844231
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1353671505
Short name T326
Test name
Test status
Simulation time 238741837 ps
CPU time 2.33 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 238544 kb
Host smart-3db04d7c-6551-4292-8706-90a86a3da80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353671505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1353671505
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.540160945
Short name T1294
Test name
Test status
Simulation time 68361920 ps
CPU time 4.65 seconds
Started Jun 22 04:54:37 PM PDT 24
Finished Jun 22 04:54:43 PM PDT 24
Peak memory 245960 kb
Host smart-16a498e6-9b00-46fb-b065-4dbfd5cae39d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540160945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.540160945
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.732643633
Short name T1306
Test name
Test status
Simulation time 276062427 ps
CPU time 3.98 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 238388 kb
Host smart-53d7473b-ba4e-43fa-a297-460d70c86cbe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732643633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.732643633
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.1988822653
Short name T281
Test name
Test status
Simulation time 356350884 ps
CPU time 2.36 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 240440 kb
Host smart-40d87532-25bf-49e0-8296-1bb09c381f4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988822653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.1988822653
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.2956839682
Short name T1194
Test name
Test status
Simulation time 194371097 ps
CPU time 2.96 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:17 PM PDT 24
Peak memory 246676 kb
Host smart-6267b61b-7a42-4d47-b943-2523decf0b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956839682 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.2956839682
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.3647602494
Short name T308
Test name
Test status
Simulation time 134776271 ps
CPU time 1.84 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 238404 kb
Host smart-87ab32eb-9f7b-486c-8e8a-8d9668cfec2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647602494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3647602494
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3632613540
Short name T1227
Test name
Test status
Simulation time 69213976 ps
CPU time 1.36 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:15 PM PDT 24
Peak memory 229516 kb
Host smart-0e31762e-623d-4fca-b7fc-cffdbd105e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632613540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3632613540
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2652983726
Short name T1210
Test name
Test status
Simulation time 75225080 ps
CPU time 1.31 seconds
Started Jun 22 04:54:10 PM PDT 24
Finished Jun 22 04:54:12 PM PDT 24
Peak memory 229336 kb
Host smart-5edcc4e2-a2c6-48d6-8950-3e69875a3736
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652983726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.2652983726
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1899969476
Short name T1226
Test name
Test status
Simulation time 68758525 ps
CPU time 1.43 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 230168 kb
Host smart-ca425ecf-e789-4716-a891-4d82a6f0e7b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899969476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.1899969476
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1644023231
Short name T1283
Test name
Test status
Simulation time 93692652 ps
CPU time 2.32 seconds
Started Jun 22 04:54:16 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 238532 kb
Host smart-c2903cdb-2de5-4de0-b89c-32bf362eaa80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644023231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.1644023231
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3462505665
Short name T1267
Test name
Test status
Simulation time 1689320312 ps
CPU time 5.27 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 245452 kb
Host smart-e80bb9eb-a0ba-4890-bc5c-27182a6dea3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462505665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3462505665
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3506198614
Short name T1290
Test name
Test status
Simulation time 9886636502 ps
CPU time 12.48 seconds
Started Jun 22 04:54:11 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 244016 kb
Host smart-deaaf480-139b-4fc4-b8b3-2f66f3d4af31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506198614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.3506198614
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.703952103
Short name T1202
Test name
Test status
Simulation time 41340718 ps
CPU time 1.5 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:38 PM PDT 24
Peak memory 229800 kb
Host smart-c17c346f-317e-43ea-b0aa-8c176d2af329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703952103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.703952103
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2921887796
Short name T1303
Test name
Test status
Simulation time 39221216 ps
CPU time 1.47 seconds
Started Jun 22 04:54:35 PM PDT 24
Finished Jun 22 04:54:38 PM PDT 24
Peak memory 230164 kb
Host smart-88f0908c-2075-4ef4-8b51-0d5dc01279ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921887796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2921887796
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2034709377
Short name T1201
Test name
Test status
Simulation time 544378475 ps
CPU time 1.84 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 229528 kb
Host smart-fc0cb4be-8c72-424a-92ac-ba7384ace851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034709377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2034709377
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2248781426
Short name T1251
Test name
Test status
Simulation time 60578609 ps
CPU time 1.4 seconds
Started Jun 22 04:54:38 PM PDT 24
Finished Jun 22 04:54:40 PM PDT 24
Peak memory 229544 kb
Host smart-22895c72-771b-4de3-aefa-955b8adad9ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248781426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2248781426
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3951427139
Short name T1203
Test name
Test status
Simulation time 56159497 ps
CPU time 1.42 seconds
Started Jun 22 04:54:34 PM PDT 24
Finished Jun 22 04:54:36 PM PDT 24
Peak memory 230184 kb
Host smart-8d4e55c9-3229-48b8-b6e9-1a349f002cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951427139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3951427139
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1622054651
Short name T1259
Test name
Test status
Simulation time 545914224 ps
CPU time 1.59 seconds
Started Jun 22 04:54:33 PM PDT 24
Finished Jun 22 04:54:35 PM PDT 24
Peak memory 229740 kb
Host smart-93f254ec-14fb-47a2-bfe3-f80ae23d0446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622054651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1622054651
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.3889361933
Short name T1189
Test name
Test status
Simulation time 41645340 ps
CPU time 1.51 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:39 PM PDT 24
Peak memory 229532 kb
Host smart-ea0fe425-eeab-4c09-8d1a-76d2f2f0dd6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889361933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.3889361933
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2204491860
Short name T1199
Test name
Test status
Simulation time 156361718 ps
CPU time 1.46 seconds
Started Jun 22 04:54:39 PM PDT 24
Finished Jun 22 04:54:42 PM PDT 24
Peak memory 230240 kb
Host smart-d7daa3ca-9c9c-4f56-8d58-ac87ce469c5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204491860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2204491860
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2993751102
Short name T1215
Test name
Test status
Simulation time 136278100 ps
CPU time 1.54 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:39 PM PDT 24
Peak memory 229860 kb
Host smart-55c2602f-2279-49e7-b6e7-0140a2d40adf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993751102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2993751102
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.1088875871
Short name T1292
Test name
Test status
Simulation time 142019533 ps
CPU time 1.37 seconds
Started Jun 22 04:54:36 PM PDT 24
Finished Jun 22 04:54:38 PM PDT 24
Peak memory 229472 kb
Host smart-478d8a51-a467-47e5-ac54-5554614eeda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088875871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1088875871
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.2497467306
Short name T1257
Test name
Test status
Simulation time 133160488 ps
CPU time 3.67 seconds
Started Jun 22 04:54:18 PM PDT 24
Finished Jun 22 04:54:22 PM PDT 24
Peak memory 238340 kb
Host smart-00e32a5a-587a-46d2-8381-ddc2e2d45ac1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497467306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.2497467306
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3245114238
Short name T329
Test name
Test status
Simulation time 1956812779 ps
CPU time 7.46 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 230196 kb
Host smart-39509ea3-bfaf-4837-b2ca-16a6532f0cee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245114238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.3245114238
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.1499098698
Short name T1277
Test name
Test status
Simulation time 93307135 ps
CPU time 2.37 seconds
Started Jun 22 04:54:15 PM PDT 24
Finished Jun 22 04:54:18 PM PDT 24
Peak memory 240320 kb
Host smart-b331f884-2bd2-449c-b994-e70c8acbe251
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499098698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.1499098698
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2995746266
Short name T1254
Test name
Test status
Simulation time 421636576 ps
CPU time 4.05 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:25 PM PDT 24
Peak memory 246680 kb
Host smart-3d31433a-5080-4fcd-bfb2-4ab19ac5ac46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995746266 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2995746266
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3218458766
Short name T306
Test name
Test status
Simulation time 155440074 ps
CPU time 1.55 seconds
Started Jun 22 04:54:16 PM PDT 24
Finished Jun 22 04:54:18 PM PDT 24
Peak memory 239824 kb
Host smart-be26f0d0-1149-4522-8c73-a7e637fdca58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218458766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3218458766
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.895810986
Short name T1211
Test name
Test status
Simulation time 130598318 ps
CPU time 1.39 seconds
Started Jun 22 04:54:13 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 229460 kb
Host smart-3315f491-a9a5-40c7-849d-849cad729fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895810986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.895810986
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1989128445
Short name T1269
Test name
Test status
Simulation time 140052647 ps
CPU time 1.44 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 230192 kb
Host smart-32e1dfe0-d063-407e-a839-4b0b67011e46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989128445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1989128445
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1182652499
Short name T1300
Test name
Test status
Simulation time 506627933 ps
CPU time 1.63 seconds
Started Jun 22 04:54:12 PM PDT 24
Finished Jun 22 04:54:16 PM PDT 24
Peak memory 229480 kb
Host smart-51987e8a-1c6d-4973-a195-bdbd2cf7d413
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182652499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.1182652499
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.4031159747
Short name T322
Test name
Test status
Simulation time 143107461 ps
CPU time 2.37 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:57 PM PDT 24
Peak memory 238468 kb
Host smart-a265a425-d321-4ddf-9d73-7c47202993cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031159747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.4031159747
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.726595820
Short name T1262
Test name
Test status
Simulation time 76813170 ps
CPU time 3.3 seconds
Started Jun 22 04:54:09 PM PDT 24
Finished Jun 22 04:54:13 PM PDT 24
Peak memory 245528 kb
Host smart-e7302cd6-4cb0-40b7-a541-7cbba20df748
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726595820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.726595820
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.4267312737
Short name T1299
Test name
Test status
Simulation time 46379054 ps
CPU time 1.48 seconds
Started Jun 22 04:54:44 PM PDT 24
Finished Jun 22 04:54:46 PM PDT 24
Peak memory 229508 kb
Host smart-e478d3f7-1398-4b2c-9305-c0e4b7728756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267312737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.4267312737
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3350476532
Short name T1214
Test name
Test status
Simulation time 152061780 ps
CPU time 1.46 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:53 PM PDT 24
Peak memory 229448 kb
Host smart-b13656f7-c97d-4fb1-b644-6df8ae60b64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350476532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3350476532
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.670507149
Short name T1216
Test name
Test status
Simulation time 39837190 ps
CPU time 1.41 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:51 PM PDT 24
Peak memory 229560 kb
Host smart-3a892eba-387a-4433-82de-af7a04f564c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670507149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.670507149
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.3699761706
Short name T1261
Test name
Test status
Simulation time 39766713 ps
CPU time 1.43 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 229436 kb
Host smart-ed709854-e9c3-48f1-9384-2bcea382d547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699761706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3699761706
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.916724249
Short name T1188
Test name
Test status
Simulation time 580367993 ps
CPU time 1.45 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:51 PM PDT 24
Peak memory 229864 kb
Host smart-a8995373-30ca-45ac-859f-70114db27335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916724249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.916724249
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3392889566
Short name T1291
Test name
Test status
Simulation time 41619478 ps
CPU time 1.4 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:54:49 PM PDT 24
Peak memory 229488 kb
Host smart-d37d715b-138d-4c41-8256-8dfef35e6935
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392889566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3392889566
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.998578338
Short name T1186
Test name
Test status
Simulation time 45889996 ps
CPU time 1.49 seconds
Started Jun 22 04:54:44 PM PDT 24
Finished Jun 22 04:54:46 PM PDT 24
Peak memory 229572 kb
Host smart-a2c18fdc-ecf4-4fea-b9b3-d2956656004d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998578338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.998578338
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3229314984
Short name T1296
Test name
Test status
Simulation time 581612823 ps
CPU time 1.64 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:52 PM PDT 24
Peak memory 230260 kb
Host smart-f88dcecd-7f32-4e84-b55e-36afffcd3c30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229314984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3229314984
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.1914734047
Short name T1223
Test name
Test status
Simulation time 120377353 ps
CPU time 1.44 seconds
Started Jun 22 04:54:48 PM PDT 24
Finished Jun 22 04:54:51 PM PDT 24
Peak memory 229804 kb
Host smart-7365869c-d540-40aa-b8da-f2c62ae20d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914734047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1914734047
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.3222260740
Short name T1228
Test name
Test status
Simulation time 514226896 ps
CPU time 1.83 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:52 PM PDT 24
Peak memory 229500 kb
Host smart-be17d76c-97a3-457e-94e0-1cefcca0b569
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222260740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.3222260740
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1220305049
Short name T312
Test name
Test status
Simulation time 132990179 ps
CPU time 5.01 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:25 PM PDT 24
Peak memory 238488 kb
Host smart-08070e33-0a99-4fc1-8351-67f9636b2fd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220305049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.1220305049
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.3615315780
Short name T1270
Test name
Test status
Simulation time 947118388 ps
CPU time 4.98 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 238448 kb
Host smart-2649043b-0a84-4928-a32d-44aac60abd5d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615315780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.3615315780
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.2096648329
Short name T320
Test name
Test status
Simulation time 322787542 ps
CPU time 2.33 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 240880 kb
Host smart-300300ef-a6e2-47a1-9114-8ec34affeaf8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096648329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.2096648329
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2954402678
Short name T1217
Test name
Test status
Simulation time 59664520 ps
CPU time 1.63 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 240732 kb
Host smart-2e8f5ec9-5473-4fea-aff3-6ac0b6924c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954402678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2954402678
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3342206028
Short name T1213
Test name
Test status
Simulation time 36792348 ps
CPU time 1.42 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:22 PM PDT 24
Peak memory 229592 kb
Host smart-417d2615-889c-4526-a40c-cea120e15e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342206028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3342206028
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.142470504
Short name T1229
Test name
Test status
Simulation time 42713482 ps
CPU time 1.41 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 230196 kb
Host smart-5d82e49e-65e9-4c1a-9396-b12221a16af7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142470504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl
_mem_partial_access.142470504
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2431948022
Short name T1311
Test name
Test status
Simulation time 71879518 ps
CPU time 1.38 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:21 PM PDT 24
Peak memory 229428 kb
Host smart-e2d6e4f5-ff60-45fe-b118-d4ad08bc41d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431948022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2431948022
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1011135991
Short name T1246
Test name
Test status
Simulation time 88294879 ps
CPU time 1.95 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 238460 kb
Host smart-3bc88f6a-bc0d-46b7-90cc-6a49909dd152
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011135991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.1011135991
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.409486709
Short name T1198
Test name
Test status
Simulation time 126002425 ps
CPU time 5.16 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:26 PM PDT 24
Peak memory 245660 kb
Host smart-edeb5c7a-2388-4c91-9180-a42d17db813d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409486709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.409486709
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.586582712
Short name T357
Test name
Test status
Simulation time 2478270687 ps
CPU time 9.79 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:30 PM PDT 24
Peak memory 243636 kb
Host smart-d6b8d5fb-03e5-4f00-b94a-61724890b3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586582712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.586582712
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.4045542326
Short name T1318
Test name
Test status
Simulation time 553607120 ps
CPU time 1.35 seconds
Started Jun 22 04:55:06 PM PDT 24
Finished Jun 22 04:55:09 PM PDT 24
Peak memory 230216 kb
Host smart-3ee489b6-c22c-4df4-b63c-0c6a91e4c2be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045542326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.4045542326
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.2217159534
Short name T1242
Test name
Test status
Simulation time 535484594 ps
CPU time 1.9 seconds
Started Jun 22 04:54:51 PM PDT 24
Finished Jun 22 04:54:55 PM PDT 24
Peak memory 230268 kb
Host smart-f4181a87-bb29-488b-9dbc-f374a084d79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217159534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2217159534
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2236863423
Short name T1244
Test name
Test status
Simulation time 529770937 ps
CPU time 1.9 seconds
Started Jun 22 04:54:50 PM PDT 24
Finished Jun 22 04:54:53 PM PDT 24
Peak memory 229380 kb
Host smart-5ded64fa-cb93-40fd-a643-bee0f027d55e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236863423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2236863423
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.938097011
Short name T1206
Test name
Test status
Simulation time 41344111 ps
CPU time 1.46 seconds
Started Jun 22 04:54:47 PM PDT 24
Finished Jun 22 04:54:50 PM PDT 24
Peak memory 229496 kb
Host smart-534d63cd-5ab0-4d7e-80ee-6985dd1c1e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938097011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.938097011
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.4145869727
Short name T1190
Test name
Test status
Simulation time 91619150 ps
CPU time 1.41 seconds
Started Jun 22 04:54:46 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 229704 kb
Host smart-50838a51-e0be-4845-bbb0-39a1133e47e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145869727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.4145869727
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.414885176
Short name T1241
Test name
Test status
Simulation time 581076393 ps
CPU time 1.57 seconds
Started Jun 22 04:54:44 PM PDT 24
Finished Jun 22 04:54:46 PM PDT 24
Peak memory 229848 kb
Host smart-8e09c74f-23b0-436e-b617-c8376d1e1208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414885176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.414885176
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.1109565546
Short name T1205
Test name
Test status
Simulation time 74588046 ps
CPU time 1.41 seconds
Started Jun 22 04:54:52 PM PDT 24
Finished Jun 22 04:54:56 PM PDT 24
Peak memory 229516 kb
Host smart-ec4bf659-82ee-4c40-8b63-032f42b7aeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109565546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.1109565546
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.128098753
Short name T1207
Test name
Test status
Simulation time 105937533 ps
CPU time 1.42 seconds
Started Jun 22 04:54:43 PM PDT 24
Finished Jun 22 04:54:44 PM PDT 24
Peak memory 230268 kb
Host smart-573cafc9-1e4a-4fcb-a319-48597ae70d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128098753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.128098753
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.3295452096
Short name T1304
Test name
Test status
Simulation time 107081724 ps
CPU time 1.51 seconds
Started Jun 22 04:54:45 PM PDT 24
Finished Jun 22 04:54:47 PM PDT 24
Peak memory 229460 kb
Host smart-a5f215c2-be28-4d08-82b2-cdaa1a4463f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295452096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3295452096
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.3465043306
Short name T1238
Test name
Test status
Simulation time 39066527 ps
CPU time 1.41 seconds
Started Jun 22 04:54:46 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 230240 kb
Host smart-e115e619-5220-462f-bab3-458fca5391d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465043306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3465043306
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.439688249
Short name T1218
Test name
Test status
Simulation time 106722688 ps
CPU time 2.91 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:24 PM PDT 24
Peak memory 246268 kb
Host smart-aca57f03-9826-43a6-b375-3054077f95d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439688249 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.439688249
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3081216833
Short name T1276
Test name
Test status
Simulation time 43378625 ps
CPU time 1.48 seconds
Started Jun 22 04:54:18 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 240132 kb
Host smart-a67df89b-00f9-4a07-a883-d58283d3fad9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081216833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3081216833
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.2497784146
Short name T1252
Test name
Test status
Simulation time 41014262 ps
CPU time 1.44 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 229416 kb
Host smart-36887273-3403-494c-8574-0d24d07dde6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497784146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2497784146
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.605077322
Short name T1240
Test name
Test status
Simulation time 97353927 ps
CPU time 2.67 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 238444 kb
Host smart-4cab7655-1440-4dc5-a86c-ffb3409b81dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605077322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct
rl_same_csr_outstanding.605077322
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.15616377
Short name T1243
Test name
Test status
Simulation time 48447504 ps
CPU time 2.34 seconds
Started Jun 22 04:54:21 PM PDT 24
Finished Jun 22 04:54:24 PM PDT 24
Peak memory 244644 kb
Host smart-ba3ec894-58f3-40b4-9b64-ae5ca37c0b22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15616377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.15616377
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1545956358
Short name T1208
Test name
Test status
Simulation time 700139728 ps
CPU time 10.14 seconds
Started Jun 22 04:54:22 PM PDT 24
Finished Jun 22 04:54:32 PM PDT 24
Peak memory 238524 kb
Host smart-d848aedd-7f76-48d9-a1b6-d1524a0e7dff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545956358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1545956358
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2509860668
Short name T1275
Test name
Test status
Simulation time 69067609 ps
CPU time 1.9 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 243320 kb
Host smart-0ca297a8-e959-479b-9f19-9e2c14c27304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509860668 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2509860668
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.515218953
Short name T1316
Test name
Test status
Simulation time 613928926 ps
CPU time 1.82 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 238420 kb
Host smart-ed6c34fb-08c9-4506-802b-44fc9115c05c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515218953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.515218953
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3624656138
Short name T1298
Test name
Test status
Simulation time 89052583 ps
CPU time 1.39 seconds
Started Jun 22 04:55:03 PM PDT 24
Finished Jun 22 04:55:05 PM PDT 24
Peak memory 229468 kb
Host smart-8a913eb7-8fe3-4ae8-89e3-363b4e019f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624656138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3624656138
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3425380659
Short name T1234
Test name
Test status
Simulation time 435690458 ps
CPU time 3.47 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:25 PM PDT 24
Peak memory 238532 kb
Host smart-30de72ac-f610-48ff-a3be-20c935eb5020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425380659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3425380659
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1443793513
Short name T1197
Test name
Test status
Simulation time 65957664 ps
CPU time 3.4 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 245700 kb
Host smart-4c802722-6785-4972-8bdb-f3fc58102ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443793513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1443793513
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.183564004
Short name T360
Test name
Test status
Simulation time 2523079322 ps
CPU time 19.71 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:41 PM PDT 24
Peak memory 243840 kb
Host smart-abc754e0-6370-499e-9c83-8a3110f85828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183564004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_int
g_err.183564004
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.464219434
Short name T1235
Test name
Test status
Simulation time 263932780 ps
CPU time 2.87 seconds
Started Jun 22 04:54:18 PM PDT 24
Finished Jun 22 04:54:21 PM PDT 24
Peak memory 246560 kb
Host smart-6e589748-cbf6-494b-9518-a4bd8b7f3c62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464219434 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.464219434
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3879242291
Short name T1288
Test name
Test status
Simulation time 141603913 ps
CPU time 1.84 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:20 PM PDT 24
Peak memory 240508 kb
Host smart-2bc0d915-28c0-4b16-9312-925dc7a3d7b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879242291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3879242291
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2390016876
Short name T1224
Test name
Test status
Simulation time 70508376 ps
CPU time 1.41 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:21 PM PDT 24
Peak memory 230256 kb
Host smart-12c28437-e826-4983-92ac-3c381ce0e5b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390016876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2390016876
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1620816174
Short name T1301
Test name
Test status
Simulation time 232572397 ps
CPU time 2.12 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 238448 kb
Host smart-cc1ebe60-e271-4482-8ac1-ee234b5cdf56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620816174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1620816174
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.942224221
Short name T1200
Test name
Test status
Simulation time 191855360 ps
CPU time 6.15 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:24 PM PDT 24
Peak memory 245384 kb
Host smart-98854e58-ee81-4cd7-ad1a-955b4139b95f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942224221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.942224221
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.434660073
Short name T352
Test name
Test status
Simulation time 4591992460 ps
CPU time 18.96 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:37 PM PDT 24
Peak memory 244228 kb
Host smart-f93af18c-827a-40c7-8cc2-228afe651189
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434660073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.434660073
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2350328931
Short name T1230
Test name
Test status
Simulation time 107463050 ps
CPU time 2.96 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 246668 kb
Host smart-0ed73bbf-59ea-4f5f-b4f4-1c7efb291a2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350328931 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2350328931
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3373708877
Short name T311
Test name
Test status
Simulation time 564984848 ps
CPU time 1.64 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 240156 kb
Host smart-0ccd35da-1049-4f2c-a7c8-c4b9dc9b0c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373708877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3373708877
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.4034796670
Short name T1265
Test name
Test status
Simulation time 580738971 ps
CPU time 1.77 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 229552 kb
Host smart-40dd4ae8-9d63-4370-a7a8-70b220c1bbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034796670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.4034796670
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1437253662
Short name T325
Test name
Test status
Simulation time 74130906 ps
CPU time 2.28 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 238484 kb
Host smart-55a664ab-574e-4e5d-b592-4d78b98333eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437253662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.1437253662
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2528302241
Short name T1253
Test name
Test status
Simulation time 125065982 ps
CPU time 4.1 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:25 PM PDT 24
Peak memory 238620 kb
Host smart-f86f1d53-d929-4e68-8c92-0e9a9ac68013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528302241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2528302241
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.3502707232
Short name T378
Test name
Test status
Simulation time 395785011 ps
CPU time 3.08 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 244620 kb
Host smart-1a26428c-8390-4d51-afc3-7adfd353d69d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502707232 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.3502707232
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3225641563
Short name T313
Test name
Test status
Simulation time 53943155 ps
CPU time 1.58 seconds
Started Jun 22 04:54:19 PM PDT 24
Finished Jun 22 04:54:22 PM PDT 24
Peak memory 238464 kb
Host smart-ea190ca9-c8cb-4f7b-9486-b6d73f8cf643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225641563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3225641563
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3860166580
Short name T1237
Test name
Test status
Simulation time 586253297 ps
CPU time 1.37 seconds
Started Jun 22 04:54:17 PM PDT 24
Finished Jun 22 04:54:19 PM PDT 24
Peak memory 229460 kb
Host smart-ba4749b1-2e56-45c4-ac3b-963610bb4bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860166580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3860166580
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.491327197
Short name T1225
Test name
Test status
Simulation time 321170823 ps
CPU time 3.62 seconds
Started Jun 22 04:54:23 PM PDT 24
Finished Jun 22 04:54:28 PM PDT 24
Peak memory 238536 kb
Host smart-d89b12e6-3e80-4027-bb2c-f542c914e93a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491327197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.491327197
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1424645863
Short name T1212
Test name
Test status
Simulation time 1964604168 ps
CPU time 5.77 seconds
Started Jun 22 04:54:20 PM PDT 24
Finished Jun 22 04:54:27 PM PDT 24
Peak memory 245556 kb
Host smart-acd1af21-11bb-4fe5-9b6f-c5659cbbccab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424645863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1424645863
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3434944269
Short name T278
Test name
Test status
Simulation time 10400391951 ps
CPU time 22.5 seconds
Started Jun 22 04:54:24 PM PDT 24
Finished Jun 22 04:54:48 PM PDT 24
Peak memory 238516 kb
Host smart-857ee132-b11a-4884-8e84-2a3ba393888a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434944269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.3434944269
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.2898663474
Short name T902
Test name
Test status
Simulation time 700048934 ps
CPU time 1.97 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:23 PM PDT 24
Peak memory 240516 kb
Host smart-43107404-87d2-4283-b72c-638548a579c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898663474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2898663474
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3541432139
Short name T1170
Test name
Test status
Simulation time 3741544538 ps
CPU time 10.28 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:24 PM PDT 24
Peak memory 242732 kb
Host smart-0897bd0c-0fd3-4e25-85b3-576ffd76a97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541432139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3541432139
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.3675424588
Short name T348
Test name
Test status
Simulation time 2208960754 ps
CPU time 32.21 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:53 PM PDT 24
Peak memory 242628 kb
Host smart-69448827-9dae-4761-8c2d-5e630bf35eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675424588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3675424588
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3198067046
Short name T734
Test name
Test status
Simulation time 3209054800 ps
CPU time 29.51 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:43 PM PDT 24
Peak memory 242768 kb
Host smart-5b84bfa5-f234-4b9c-9248-1fea00ccc050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198067046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3198067046
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.540506490
Short name T137
Test name
Test status
Simulation time 2355591220 ps
CPU time 4.93 seconds
Started Jun 22 06:57:13 PM PDT 24
Finished Jun 22 06:57:19 PM PDT 24
Peak memory 242272 kb
Host smart-8e645ca6-7427-4d09-920b-360b2e7788e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540506490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.540506490
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.1990836952
Short name T757
Test name
Test status
Simulation time 3067339182 ps
CPU time 14.66 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:28 PM PDT 24
Peak memory 242076 kb
Host smart-9a778f0d-79e8-49cb-bd01-2ba99050ce3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990836952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.1990836952
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.730200826
Short name T151
Test name
Test status
Simulation time 1587863477 ps
CPU time 18.57 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:40 PM PDT 24
Peak memory 244108 kb
Host smart-9d084e99-07fd-4852-8246-6dfb36aaa272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730200826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.730200826
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.888411204
Short name T464
Test name
Test status
Simulation time 3615745999 ps
CPU time 28.37 seconds
Started Jun 22 06:57:19 PM PDT 24
Finished Jun 22 06:57:48 PM PDT 24
Peak memory 249156 kb
Host smart-50c2be0c-3f55-4c7d-a158-2707d074d24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888411204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.888411204
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.589748805
Short name T289
Test name
Test status
Simulation time 287023558 ps
CPU time 5.91 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:19 PM PDT 24
Peak memory 242616 kb
Host smart-c2042593-bc92-4d94-ae79-ec1e944dc1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589748805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.589748805
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2526524854
Short name T936
Test name
Test status
Simulation time 4557296055 ps
CPU time 10.89 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:24 PM PDT 24
Peak memory 242788 kb
Host smart-2238e6c4-3edc-423c-831c-2b8edca332bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2526524854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2526524854
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.298000880
Short name T401
Test name
Test status
Simulation time 1479679267 ps
CPU time 20.24 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:33 PM PDT 24
Peak memory 241844 kb
Host smart-2b55321a-1d4c-4edf-853e-d1418d2412b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298000880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.298000880
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1248299537
Short name T581
Test name
Test status
Simulation time 224915682 ps
CPU time 3.48 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:26 PM PDT 24
Peak memory 242196 kb
Host smart-ce3790c9-fa16-4c4f-9593-959177840753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248299537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1248299537
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.2766529944
Short name T23
Test name
Test status
Simulation time 22275598055 ps
CPU time 169.51 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 07:00:12 PM PDT 24
Peak memory 270764 kb
Host smart-facc6996-3d72-4de2-85a6-fe54ffdd5468
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766529944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2766529944
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.3421441559
Short name T475
Test name
Test status
Simulation time 4261024759 ps
CPU time 12.26 seconds
Started Jun 22 06:57:11 PM PDT 24
Finished Jun 22 06:57:25 PM PDT 24
Peak memory 243396 kb
Host smart-b9730e53-094d-42e8-9445-c15340d444ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421441559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3421441559
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.72852905
Short name T877
Test name
Test status
Simulation time 2629442418 ps
CPU time 23.76 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:46 PM PDT 24
Peak memory 243240 kb
Host smart-223d2a3e-10a3-455b-b91f-3bf2706e4dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72852905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.72852905
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.403025711
Short name T524
Test name
Test status
Simulation time 99211010 ps
CPU time 1.88 seconds
Started Jun 22 06:57:12 PM PDT 24
Finished Jun 22 06:57:15 PM PDT 24
Peak memory 240672 kb
Host smart-975dfdca-2dd2-4850-8be7-2fb6ad95079f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=403025711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.403025711
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.1875145029
Short name T523
Test name
Test status
Simulation time 154322781 ps
CPU time 1.69 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:30 PM PDT 24
Peak memory 240772 kb
Host smart-1112f68c-e0d8-41da-8ffe-b681d9396d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875145029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1875145029
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.742173565
Short name T122
Test name
Test status
Simulation time 4797997865 ps
CPU time 29.2 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:52 PM PDT 24
Peak memory 242608 kb
Host smart-2295fbc1-b671-4b70-a4d7-2f64fbd97a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742173565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.742173565
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1583405762
Short name T746
Test name
Test status
Simulation time 584107077 ps
CPU time 6.61 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:29 PM PDT 24
Peak memory 242340 kb
Host smart-f5d56ef1-39b5-4eac-8233-860cae19861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583405762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1583405762
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.1902173362
Short name T1105
Test name
Test status
Simulation time 3952536373 ps
CPU time 17.49 seconds
Started Jun 22 06:57:19 PM PDT 24
Finished Jun 22 06:57:37 PM PDT 24
Peak memory 242396 kb
Host smart-1c7663ef-ade6-46bf-af8e-0d84d889476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902173362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1902173362
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1196947001
Short name T1008
Test name
Test status
Simulation time 4408195853 ps
CPU time 25.58 seconds
Started Jun 22 06:57:19 PM PDT 24
Finished Jun 22 06:57:45 PM PDT 24
Peak memory 243048 kb
Host smart-ef9d877b-cc28-4cb5-8dc9-3f68dc412c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196947001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1196947001
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.4145507775
Short name T562
Test name
Test status
Simulation time 262919773 ps
CPU time 4.16 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:27 PM PDT 24
Peak memory 242220 kb
Host smart-67cd2d49-c6a1-4f0e-9656-148a9e83397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145507775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.4145507775
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.4175522389
Short name T200
Test name
Test status
Simulation time 16650992783 ps
CPU time 22.62 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:43 PM PDT 24
Peak memory 245032 kb
Host smart-042bd477-1ca5-45f8-bf62-b85f0f6981a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175522389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4175522389
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.4081693439
Short name T966
Test name
Test status
Simulation time 11779222316 ps
CPU time 27.02 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:55 PM PDT 24
Peak memory 243088 kb
Host smart-618a3498-6147-42b5-859c-29acbaffbc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081693439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4081693439
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1400420503
Short name T77
Test name
Test status
Simulation time 1786763446 ps
CPU time 6.7 seconds
Started Jun 22 06:57:21 PM PDT 24
Finished Jun 22 06:57:30 PM PDT 24
Peak memory 242264 kb
Host smart-3c7f6e93-f3ca-45f2-b95b-59cd43a32913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400420503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1400420503
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3698660767
Short name T811
Test name
Test status
Simulation time 601549828 ps
CPU time 5.94 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:27 PM PDT 24
Peak memory 242260 kb
Host smart-b7bab9f5-2da3-43b4-ba51-584451a0bf00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698660767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3698660767
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2937334969
Short name T1156
Test name
Test status
Simulation time 182733182 ps
CPU time 7.1 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:36 PM PDT 24
Peak memory 242712 kb
Host smart-afc97c56-245a-4dcd-9900-6dbe3c63f8c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937334969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2937334969
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3579447812
Short name T107
Test name
Test status
Simulation time 3615954406 ps
CPU time 6.45 seconds
Started Jun 22 06:57:20 PM PDT 24
Finished Jun 22 06:57:28 PM PDT 24
Peak memory 242364 kb
Host smart-474bb4f8-157f-47fe-baf3-82f0842ee176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579447812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3579447812
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3641527177
Short name T579
Test name
Test status
Simulation time 2765710510 ps
CPU time 18.2 seconds
Started Jun 22 06:57:28 PM PDT 24
Finished Jun 22 06:57:48 PM PDT 24
Peak memory 242800 kb
Host smart-ebd50371-c387-4fa3-a548-9cf6fc7b45eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641527177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3641527177
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.4191738472
Short name T112
Test name
Test status
Simulation time 6964578479 ps
CPU time 25.62 seconds
Started Jun 22 06:58:12 PM PDT 24
Finished Jun 22 06:58:39 PM PDT 24
Peak memory 244388 kb
Host smart-d55bb559-c0dc-465a-918f-8df59c9fc62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191738472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.4191738472
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.804395151
Short name T568
Test name
Test status
Simulation time 476781399 ps
CPU time 13.95 seconds
Started Jun 22 06:58:17 PM PDT 24
Finished Jun 22 06:58:31 PM PDT 24
Peak memory 242152 kb
Host smart-ed11293c-f5f5-4d79-ac4f-9bb13a27207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804395151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.804395151
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.3889888535
Short name T962
Test name
Test status
Simulation time 5637134866 ps
CPU time 14.54 seconds
Started Jun 22 06:58:12 PM PDT 24
Finished Jun 22 06:58:28 PM PDT 24
Peak memory 242472 kb
Host smart-482dd121-787a-46fd-ab14-f18177c10244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889888535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.3889888535
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3789316840
Short name T1097
Test name
Test status
Simulation time 123224889 ps
CPU time 4.3 seconds
Started Jun 22 06:58:17 PM PDT 24
Finished Jun 22 06:58:23 PM PDT 24
Peak memory 242308 kb
Host smart-d4ef28df-5588-44f7-bccc-ef0e51fffa7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789316840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3789316840
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.698067368
Short name T729
Test name
Test status
Simulation time 1642387682 ps
CPU time 26.45 seconds
Started Jun 22 06:58:26 PM PDT 24
Finished Jun 22 06:58:53 PM PDT 24
Peak memory 242472 kb
Host smart-365159c3-87cb-4660-a65d-fd7f7f91461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698067368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.698067368
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3715157515
Short name T786
Test name
Test status
Simulation time 410112413 ps
CPU time 20.27 seconds
Started Jun 22 06:58:26 PM PDT 24
Finished Jun 22 06:58:47 PM PDT 24
Peak memory 242552 kb
Host smart-d0fd91f4-b887-43ff-83c9-6d3829a34b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715157515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3715157515
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.1283814704
Short name T691
Test name
Test status
Simulation time 11285721974 ps
CPU time 27.83 seconds
Started Jun 22 06:58:13 PM PDT 24
Finished Jun 22 06:58:42 PM PDT 24
Peak memory 242264 kb
Host smart-9a10619a-5a64-4485-a0aa-b660266314d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283814704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1283814704
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2798360601
Short name T248
Test name
Test status
Simulation time 3749457023 ps
CPU time 7.58 seconds
Started Jun 22 06:58:14 PM PDT 24
Finished Jun 22 06:58:22 PM PDT 24
Peak memory 242260 kb
Host smart-904d27b7-ecbd-4c04-bd72-4f5f1d78bfed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798360601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2798360601
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.2767276238
Short name T409
Test name
Test status
Simulation time 2236831462 ps
CPU time 12.29 seconds
Started Jun 22 06:58:17 PM PDT 24
Finished Jun 22 06:58:31 PM PDT 24
Peak memory 242460 kb
Host smart-e8d39fbe-807d-4ec3-bd57-9b9052b3738f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767276238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2767276238
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.981341883
Short name T340
Test name
Test status
Simulation time 11274191014 ps
CPU time 51.96 seconds
Started Jun 22 06:58:25 PM PDT 24
Finished Jun 22 06:59:18 PM PDT 24
Peak memory 245756 kb
Host smart-df36f9a1-6038-44b2-8ca0-0686da8776c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981341883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
981341883
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3496245701
Short name T38
Test name
Test status
Simulation time 44893805153 ps
CPU time 911.5 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 07:13:40 PM PDT 24
Peak memory 265828 kb
Host smart-fb7415c1-286a-4b17-8509-5ef3896b6369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496245701 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3496245701
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1649484616
Short name T981
Test name
Test status
Simulation time 2619799088 ps
CPU time 17.71 seconds
Started Jun 22 06:58:25 PM PDT 24
Finished Jun 22 06:58:44 PM PDT 24
Peak memory 249156 kb
Host smart-31d65a6a-173c-487f-8794-a10acf7bfd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649484616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1649484616
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1077745711
Short name T441
Test name
Test status
Simulation time 203006712 ps
CPU time 4.39 seconds
Started Jun 22 07:01:29 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242104 kb
Host smart-be3994e9-4f87-446b-b3cc-06b4c6360440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077745711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1077745711
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2334597234
Short name T257
Test name
Test status
Simulation time 569677336 ps
CPU time 8.23 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:42 PM PDT 24
Peak memory 242584 kb
Host smart-af3a5f46-33f8-4aba-92e0-1e415d653e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334597234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2334597234
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.3518816568
Short name T847
Test name
Test status
Simulation time 942262640 ps
CPU time 12.05 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:46 PM PDT 24
Peak memory 242468 kb
Host smart-a9987378-370c-44c4-afa1-6a37fdab2e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518816568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.3518816568
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.563585132
Short name T946
Test name
Test status
Simulation time 729754314 ps
CPU time 5.06 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:40 PM PDT 24
Peak memory 242212 kb
Host smart-6eee126b-8155-4078-be6f-7438b66f47ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563585132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.563585132
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.3447776954
Short name T892
Test name
Test status
Simulation time 347943687 ps
CPU time 4.96 seconds
Started Jun 22 07:01:28 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242064 kb
Host smart-6912bb0c-e7aa-411c-bc4f-471bf370ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447776954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3447776954
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2075116222
Short name T950
Test name
Test status
Simulation time 517524888 ps
CPU time 4.48 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:38 PM PDT 24
Peak memory 242360 kb
Host smart-1cbb87af-e9bb-453c-852b-23ff80f4538e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075116222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2075116222
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.1521863729
Short name T675
Test name
Test status
Simulation time 433842290 ps
CPU time 11.71 seconds
Started Jun 22 07:01:29 PM PDT 24
Finished Jun 22 07:01:43 PM PDT 24
Peak memory 242216 kb
Host smart-16f4a7d3-c7c4-475a-81e3-f01994279185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521863729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1521863729
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.363194290
Short name T489
Test name
Test status
Simulation time 297993207 ps
CPU time 4.69 seconds
Started Jun 22 07:01:28 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242272 kb
Host smart-3ae65a73-57b5-446f-9661-821eb939a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363194290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.363194290
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.2683340849
Short name T185
Test name
Test status
Simulation time 16142394115 ps
CPU time 35.23 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242412 kb
Host smart-29e02e1d-9113-4fec-a717-f8eb154653d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683340849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.2683340849
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.833400074
Short name T970
Test name
Test status
Simulation time 465373534 ps
CPU time 3.1 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:43 PM PDT 24
Peak memory 242212 kb
Host smart-9d7e6b6c-be7e-4e88-bd6f-a9d7fec18d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833400074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.833400074
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3755385048
Short name T1108
Test name
Test status
Simulation time 182854673 ps
CPU time 3.85 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242204 kb
Host smart-fcaf2084-7052-4421-938c-8395edaf4c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755385048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3755385048
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3734813691
Short name T1143
Test name
Test status
Simulation time 1979653610 ps
CPU time 6.48 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:49 PM PDT 24
Peak memory 242632 kb
Host smart-d0462047-20a8-4452-9d12-c1c77842fa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734813691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3734813691
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.3235104391
Short name T803
Test name
Test status
Simulation time 239485100 ps
CPU time 7.97 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:51 PM PDT 24
Peak memory 242176 kb
Host smart-62de8cf9-4727-46a1-be58-61421762ca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235104391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.3235104391
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.762309261
Short name T939
Test name
Test status
Simulation time 3539754419 ps
CPU time 13.94 seconds
Started Jun 22 07:01:41 PM PDT 24
Finished Jun 22 07:01:58 PM PDT 24
Peak memory 242196 kb
Host smart-7c1e5e3e-ff15-419d-b516-833ff157d9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762309261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.762309261
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2641363892
Short name T840
Test name
Test status
Simulation time 94619937 ps
CPU time 3.51 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242080 kb
Host smart-708dcc79-3c8e-49a0-8f7f-26d6daa885b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641363892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2641363892
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.1772177993
Short name T839
Test name
Test status
Simulation time 298411854 ps
CPU time 4.33 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242212 kb
Host smart-ef001f11-bf74-4773-92ba-356158ea662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772177993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.1772177993
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.2931694879
Short name T920
Test name
Test status
Simulation time 135677888 ps
CPU time 3.92 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:43 PM PDT 24
Peak memory 242304 kb
Host smart-9695eb7a-07f8-41ec-85d8-9a43fb581b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931694879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2931694879
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.1856298207
Short name T602
Test name
Test status
Simulation time 77338901 ps
CPU time 1.66 seconds
Started Jun 22 06:58:26 PM PDT 24
Finished Jun 22 06:58:28 PM PDT 24
Peak memory 240608 kb
Host smart-9de7ba2d-ff83-4dcc-8a88-34edeeef106f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856298207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.1856298207
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1492634811
Short name T556
Test name
Test status
Simulation time 181354671 ps
CPU time 9.86 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:38 PM PDT 24
Peak memory 242328 kb
Host smart-f3b02d97-82b3-47a4-88e8-03c869197da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492634811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1492634811
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.3174001693
Short name T792
Test name
Test status
Simulation time 2487009320 ps
CPU time 16.71 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:45 PM PDT 24
Peak memory 242408 kb
Host smart-ead36c77-96c6-4df8-b95c-bea60afeb791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174001693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3174001693
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.3803919618
Short name T1149
Test name
Test status
Simulation time 6256369445 ps
CPU time 40.55 seconds
Started Jun 22 06:58:28 PM PDT 24
Finished Jun 22 06:59:10 PM PDT 24
Peak memory 257296 kb
Host smart-656477d5-1e69-42f2-8b86-cce0a2ed957b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803919618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3803919618
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.3322113868
Short name T671
Test name
Test status
Simulation time 647475674 ps
CPU time 9.02 seconds
Started Jun 22 06:58:24 PM PDT 24
Finished Jun 22 06:58:34 PM PDT 24
Peak memory 242468 kb
Host smart-855dce6a-f253-43a4-ae3f-6b50a4eed66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322113868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3322113868
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.959629248
Short name T644
Test name
Test status
Simulation time 162656806 ps
CPU time 7.65 seconds
Started Jun 22 06:58:25 PM PDT 24
Finished Jun 22 06:58:34 PM PDT 24
Peak memory 242088 kb
Host smart-465d8c3c-881d-42a2-a9de-cd69e788b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959629248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.959629248
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.533564980
Short name T552
Test name
Test status
Simulation time 211578579 ps
CPU time 6.5 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:35 PM PDT 24
Peak memory 242268 kb
Host smart-b223ad36-4d39-43c9-a328-5be95b03e5b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533564980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.533564980
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2374452073
Short name T577
Test name
Test status
Simulation time 1851806057 ps
CPU time 13.13 seconds
Started Jun 22 06:58:28 PM PDT 24
Finished Jun 22 06:58:42 PM PDT 24
Peak memory 242244 kb
Host smart-509b656a-cd6f-4f1c-bc80-946ae0a941ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374452073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2374452073
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.2958616180
Short name T349
Test name
Test status
Simulation time 653337364 ps
CPU time 15.33 seconds
Started Jun 22 06:58:27 PM PDT 24
Finished Jun 22 06:58:43 PM PDT 24
Peak memory 248896 kb
Host smart-af337a45-4c79-4a08-b744-93c8837c8fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958616180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.2958616180
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2122431412
Short name T298
Test name
Test status
Simulation time 317358109994 ps
CPU time 2571.48 seconds
Started Jun 22 06:58:25 PM PDT 24
Finished Jun 22 07:41:18 PM PDT 24
Peak memory 549772 kb
Host smart-43c9b7ea-b1ad-422a-a244-273d7b0154e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122431412 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.2122431412
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.3019553577
Short name T656
Test name
Test status
Simulation time 11447489466 ps
CPU time 45.07 seconds
Started Jun 22 06:58:26 PM PDT 24
Finished Jun 22 06:59:12 PM PDT 24
Peak memory 243824 kb
Host smart-fced13e7-649e-4867-9869-82c30d49d041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019553577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3019553577
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.325538293
Short name T451
Test name
Test status
Simulation time 166860525 ps
CPU time 4.19 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242448 kb
Host smart-af56705d-7e4d-463c-8f16-ab93490b5743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325538293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.325538293
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3171749926
Short name T1034
Test name
Test status
Simulation time 562835430 ps
CPU time 6.15 seconds
Started Jun 22 07:01:36 PM PDT 24
Finished Jun 22 07:01:45 PM PDT 24
Peak memory 242216 kb
Host smart-140a26f9-479b-419a-80fc-cac84ca89188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171749926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3171749926
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3138696830
Short name T209
Test name
Test status
Simulation time 195758993 ps
CPU time 3.76 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:46 PM PDT 24
Peak memory 242300 kb
Host smart-213915fd-2bef-450c-b40c-839487af8bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138696830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3138696830
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.2129806623
Short name T876
Test name
Test status
Simulation time 1919240532 ps
CPU time 13.53 seconds
Started Jun 22 07:01:38 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242244 kb
Host smart-95d6412b-83a6-4d90-8d49-a693e5c7dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129806623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2129806623
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.134902637
Short name T991
Test name
Test status
Simulation time 6879889337 ps
CPU time 13.97 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242204 kb
Host smart-0bf280ab-4e7b-428b-9f28-767009354a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134902637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.134902637
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2321289637
Short name T777
Test name
Test status
Simulation time 490631164 ps
CPU time 4 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242088 kb
Host smart-5cbfe7e8-7b8e-4565-a12d-07f5f600b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321289637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2321289637
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2786424628
Short name T345
Test name
Test status
Simulation time 7102014639 ps
CPU time 16.59 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:02:00 PM PDT 24
Peak memory 242332 kb
Host smart-143d7ac2-6ef0-4ebf-9959-5ad04f772289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786424628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2786424628
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.1143099332
Short name T1165
Test name
Test status
Simulation time 290844093 ps
CPU time 3.79 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242264 kb
Host smart-52ce4442-1257-4b78-900c-aa93c55c9cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143099332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1143099332
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3948770936
Short name T553
Test name
Test status
Simulation time 105722661 ps
CPU time 4.1 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242088 kb
Host smart-f5db5117-dbfe-4749-bab0-414776f0a109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948770936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3948770936
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2030832052
Short name T796
Test name
Test status
Simulation time 1406474799 ps
CPU time 3.87 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242300 kb
Host smart-9b37e2c7-51e0-47eb-a60b-b6170dd7b033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030832052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2030832052
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.438704825
Short name T478
Test name
Test status
Simulation time 1275505332 ps
CPU time 15.35 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242340 kb
Host smart-e8207a05-2b61-40f2-953e-57288eb01c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438704825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.438704825
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.1019620033
Short name T1102
Test name
Test status
Simulation time 293705067 ps
CPU time 4.01 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242184 kb
Host smart-6c3a8f6c-d931-4935-aa55-6f65db7ff630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019620033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1019620033
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.12762496
Short name T268
Test name
Test status
Simulation time 300003781 ps
CPU time 8.27 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:48 PM PDT 24
Peak memory 242272 kb
Host smart-d155c20e-3d76-4c12-b873-f36be9db3ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12762496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.12762496
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3215849903
Short name T513
Test name
Test status
Simulation time 213490057 ps
CPU time 3.99 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242172 kb
Host smart-07d8c1cb-564b-4452-9f1a-1b8eb9451de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215849903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3215849903
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.3781008662
Short name T716
Test name
Test status
Simulation time 6780494029 ps
CPU time 21.59 seconds
Started Jun 22 07:01:39 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242192 kb
Host smart-55cb93f7-c587-417c-90d9-b3ccf44447ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781008662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3781008662
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.1277791981
Short name T1144
Test name
Test status
Simulation time 158780113 ps
CPU time 4.47 seconds
Started Jun 22 07:01:40 PM PDT 24
Finished Jun 22 07:01:48 PM PDT 24
Peak memory 242084 kb
Host smart-761ee093-7dfe-4871-94fb-a92c555d421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277791981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1277791981
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.3922199507
Short name T686
Test name
Test status
Simulation time 370700876 ps
CPU time 4.77 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242156 kb
Host smart-d24261ce-077e-43af-88cd-20c4083b65cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922199507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3922199507
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.4253998132
Short name T469
Test name
Test status
Simulation time 52431084 ps
CPU time 1.77 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:58:44 PM PDT 24
Peak memory 240816 kb
Host smart-8c3fabe9-13b1-4ae9-aa90-f3fa73ead71c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253998132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.4253998132
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.1601387713
Short name T392
Test name
Test status
Simulation time 15569913763 ps
CPU time 20.32 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:59:03 PM PDT 24
Peak memory 242892 kb
Host smart-0d372b49-e139-4abd-a110-989b491c14e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601387713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1601387713
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.3136836177
Short name T242
Test name
Test status
Simulation time 1589115605 ps
CPU time 29.63 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:59:13 PM PDT 24
Peak memory 242368 kb
Host smart-7ce7f0da-5fae-4acb-b0f5-50a1b9068733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136836177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3136836177
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.4063240822
Short name T682
Test name
Test status
Simulation time 2707218707 ps
CPU time 16.48 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 06:58:57 PM PDT 24
Peak memory 242252 kb
Host smart-84e654e9-1e82-426f-a258-42d3aa802d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063240822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.4063240822
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.4152869806
Short name T80
Test name
Test status
Simulation time 2747547110 ps
CPU time 4.67 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:58:51 PM PDT 24
Peak memory 242500 kb
Host smart-b7766146-0374-4266-80f7-22b069e1d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152869806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.4152869806
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.335228847
Short name T816
Test name
Test status
Simulation time 10723795723 ps
CPU time 23.53 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:59:09 PM PDT 24
Peak memory 247384 kb
Host smart-0875365b-e776-4c58-93a8-30027ecae55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335228847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.335228847
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.672076276
Short name T593
Test name
Test status
Simulation time 1331302937 ps
CPU time 27.36 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:59:12 PM PDT 24
Peak memory 242544 kb
Host smart-81693e60-85b8-4f4d-b733-e0bc11008c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672076276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.672076276
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.2884670999
Short name T1162
Test name
Test status
Simulation time 409926318 ps
CPU time 9.43 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:58:55 PM PDT 24
Peak memory 242116 kb
Host smart-702e7e2b-1520-457e-acca-596d7f00b8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884670999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2884670999
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.4290281079
Short name T1127
Test name
Test status
Simulation time 393263887 ps
CPU time 11.32 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:58:56 PM PDT 24
Peak memory 242132 kb
Host smart-58945774-99d4-4319-975f-4d3890ce7975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290281079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.4290281079
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1519746099
Short name T376
Test name
Test status
Simulation time 870496122 ps
CPU time 8.35 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:58:50 PM PDT 24
Peak memory 242256 kb
Host smart-43fb60bb-7a2d-4976-b3c4-6326dd797697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519746099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1519746099
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.3643793389
Short name T93
Test name
Test status
Simulation time 298246380 ps
CPU time 2.86 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 06:58:44 PM PDT 24
Peak memory 247992 kb
Host smart-1ddf4650-0a66-4268-b458-8c6fdc5b9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643793389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3643793389
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3671731225
Short name T542
Test name
Test status
Simulation time 33991607503 ps
CPU time 197.11 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 07:02:01 PM PDT 24
Peak memory 278740 kb
Host smart-9d8c3961-5742-45e1-ac9f-411f2451c364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671731225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3671731225
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.909875959
Short name T219
Test name
Test status
Simulation time 1734465853 ps
CPU time 22.25 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 06:59:03 PM PDT 24
Peak memory 242516 kb
Host smart-8e608f6d-9a1d-4578-94e6-eb7d2c925486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909875959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.909875959
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.3610573175
Short name T459
Test name
Test status
Simulation time 128302812 ps
CPU time 3.87 seconds
Started Jun 22 07:01:41 PM PDT 24
Finished Jun 22 07:01:48 PM PDT 24
Peak memory 242392 kb
Host smart-ed6e6498-9a63-48a5-aba8-84a17cc3da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610573175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3610573175
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.921129064
Short name T919
Test name
Test status
Simulation time 303340486 ps
CPU time 3.3 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:53 PM PDT 24
Peak memory 242212 kb
Host smart-d700982c-584e-4485-b7a6-1463ddf7af1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921129064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.921129064
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.4032959793
Short name T805
Test name
Test status
Simulation time 198453924 ps
CPU time 3.94 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:52 PM PDT 24
Peak memory 242380 kb
Host smart-c0b66379-14be-4e3d-aa95-2e8b0c08eae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032959793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4032959793
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.1885716604
Short name T870
Test name
Test status
Simulation time 109685864 ps
CPU time 4.72 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:53 PM PDT 24
Peak memory 242156 kb
Host smart-c3d88f39-51b6-4fe4-a834-d6f8c53cdef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885716604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.1885716604
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.3121673916
Short name T181
Test name
Test status
Simulation time 390096178 ps
CPU time 3.79 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:51 PM PDT 24
Peak memory 242456 kb
Host smart-aa821810-53b0-44b3-854f-0ae3c5482293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121673916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3121673916
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.1830608123
Short name T275
Test name
Test status
Simulation time 194765001 ps
CPU time 6.95 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242076 kb
Host smart-29444380-19f2-49db-9f72-dad8e4a02b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830608123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1830608123
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3761760953
Short name T1068
Test name
Test status
Simulation time 204142983 ps
CPU time 4.75 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:53 PM PDT 24
Peak memory 242452 kb
Host smart-8ed8b3b7-9878-4975-b6a5-21a78a5e9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761760953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3761760953
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3639191571
Short name T1054
Test name
Test status
Simulation time 277170823 ps
CPU time 7.84 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:58 PM PDT 24
Peak memory 242532 kb
Host smart-3aa5e5bf-9a17-4695-bf13-238daf3f71f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639191571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3639191571
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.787668447
Short name T182
Test name
Test status
Simulation time 331029481 ps
CPU time 4.45 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242612 kb
Host smart-babceb8b-8120-40aa-985e-877915d6e6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787668447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.787668447
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.3697569914
Short name T1123
Test name
Test status
Simulation time 180239107 ps
CPU time 9.18 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:58 PM PDT 24
Peak memory 242116 kb
Host smart-afc8cb66-b0cd-4cc6-99c9-325bbbecf8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697569914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3697569914
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.2606172684
Short name T446
Test name
Test status
Simulation time 184110344 ps
CPU time 5.02 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:55 PM PDT 24
Peak memory 242492 kb
Host smart-44b7623f-07da-4356-b06b-796ab929ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606172684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2606172684
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.4246405773
Short name T945
Test name
Test status
Simulation time 4394259549 ps
CPU time 12.3 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:02:01 PM PDT 24
Peak memory 243016 kb
Host smart-c1891973-bf4d-42dc-9bab-fa05b1e5405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246405773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.4246405773
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3339736062
Short name T70
Test name
Test status
Simulation time 355948199 ps
CPU time 3.48 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:51 PM PDT 24
Peak memory 242656 kb
Host smart-f20d8505-f414-4a8a-9abf-4e3b9523f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339736062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3339736062
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.4287705313
Short name T601
Test name
Test status
Simulation time 2010465628 ps
CPU time 6.93 seconds
Started Jun 22 07:01:52 PM PDT 24
Finished Jun 22 07:02:00 PM PDT 24
Peak memory 241988 kb
Host smart-b339144f-017c-4387-92bd-3f8881ed20ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287705313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.4287705313
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.377082830
Short name T509
Test name
Test status
Simulation time 1834191621 ps
CPU time 4.84 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 242148 kb
Host smart-771688fe-0eb8-4ff0-90e3-0a30c8291469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377082830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.377082830
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.1641730977
Short name T961
Test name
Test status
Simulation time 272431541 ps
CPU time 7.83 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242084 kb
Host smart-e41e96bb-c007-4b1b-b257-5de618aea1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641730977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1641730977
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.77237143
Short name T204
Test name
Test status
Simulation time 230559795 ps
CPU time 3.51 seconds
Started Jun 22 07:01:44 PM PDT 24
Finished Jun 22 07:01:50 PM PDT 24
Peak memory 242308 kb
Host smart-5e78381b-fb01-4bc3-9878-380615dc16e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77237143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.77237143
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3931310105
Short name T806
Test name
Test status
Simulation time 371317168 ps
CPU time 4.65 seconds
Started Jun 22 07:01:47 PM PDT 24
Finished Jun 22 07:01:55 PM PDT 24
Peak memory 241836 kb
Host smart-37670daa-f0e6-424f-88be-88cc60bf51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931310105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3931310105
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.821385404
Short name T61
Test name
Test status
Simulation time 455085120 ps
CPU time 3.57 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:53 PM PDT 24
Peak memory 242608 kb
Host smart-5393f2e9-0dc5-449a-b543-34ee79a2b545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821385404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.821385404
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.2931186543
Short name T739
Test name
Test status
Simulation time 1094831252 ps
CPU time 15.47 seconds
Started Jun 22 07:01:47 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 241684 kb
Host smart-17d1065e-7629-4987-90de-50c61d2496c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931186543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.2931186543
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1934719811
Short name T1047
Test name
Test status
Simulation time 82245726 ps
CPU time 2.1 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:58:47 PM PDT 24
Peak memory 240816 kb
Host smart-3af70eda-000d-4514-94f5-6214c219f14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934719811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1934719811
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.1522828575
Short name T198
Test name
Test status
Simulation time 968408076 ps
CPU time 16.01 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:59:02 PM PDT 24
Peak memory 242576 kb
Host smart-84b3087f-7c08-4307-a6fb-6b4fb3c73e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522828575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.1522828575
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.4293987120
Short name T844
Test name
Test status
Simulation time 1351270369 ps
CPU time 14.86 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 06:58:56 PM PDT 24
Peak memory 242416 kb
Host smart-b6140fa8-f587-4b79-ab2c-3fbf56bd77ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293987120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.4293987120
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2788073124
Short name T718
Test name
Test status
Simulation time 2061095803 ps
CPU time 40.92 seconds
Started Jun 22 06:58:40 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242804 kb
Host smart-66c310b5-cf5e-46b2-a29b-d6ece4fffbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788073124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2788073124
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.751990553
Short name T455
Test name
Test status
Simulation time 475519232 ps
CPU time 4.74 seconds
Started Jun 22 06:58:44 PM PDT 24
Finished Jun 22 06:58:52 PM PDT 24
Peak memory 242340 kb
Host smart-133bb721-55cc-49fd-b98b-67e216716f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751990553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.751990553
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.127640180
Short name T498
Test name
Test status
Simulation time 631623962 ps
CPU time 15.14 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:59:00 PM PDT 24
Peak memory 242116 kb
Host smart-4490b1dd-c66e-4444-bfee-158e0e4a21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127640180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.127640180
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.234650538
Short name T285
Test name
Test status
Simulation time 621925771 ps
CPU time 9.28 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:58:54 PM PDT 24
Peak memory 242148 kb
Host smart-88e6d23e-fc05-4803-8b22-a3547a2906c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234650538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.234650538
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.2528203744
Short name T515
Test name
Test status
Simulation time 2658328024 ps
CPU time 27.33 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:59:10 PM PDT 24
Peak memory 242220 kb
Host smart-3fb3b154-778e-4cf2-ad2a-cbf0e44b91cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528203744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2528203744
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2559596884
Short name T373
Test name
Test status
Simulation time 257687856 ps
CPU time 8.49 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:58:51 PM PDT 24
Peak memory 242468 kb
Host smart-500756e9-502c-4c6b-a689-ff16baa09d66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559596884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2559596884
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1117636981
Short name T288
Test name
Test status
Simulation time 375109690 ps
CPU time 7.93 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:58:54 PM PDT 24
Peak memory 242552 kb
Host smart-082caf06-8ea9-4d8a-b3b4-71d39635198c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117636981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1117636981
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.2222846939
Short name T263
Test name
Test status
Simulation time 37219968686 ps
CPU time 910.81 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 07:13:53 PM PDT 24
Peak memory 331160 kb
Host smart-6f9fb00c-b5ef-427b-a405-8af5ad2e4dae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222846939 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.2222846939
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.661169267
Short name T843
Test name
Test status
Simulation time 4114083186 ps
CPU time 24.63 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:59:11 PM PDT 24
Peak memory 242668 kb
Host smart-ac79ab17-37c1-496e-a39e-824be9524ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661169267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.661169267
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.926384264
Short name T728
Test name
Test status
Simulation time 318919342 ps
CPU time 4.02 seconds
Started Jun 22 07:01:47 PM PDT 24
Finished Jun 22 07:01:55 PM PDT 24
Peak memory 242184 kb
Host smart-6a0f7e3f-f8d6-48ee-82e7-397186ce02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926384264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.926384264
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2257218678
Short name T439
Test name
Test status
Simulation time 531452807 ps
CPU time 6.08 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:56 PM PDT 24
Peak memory 242156 kb
Host smart-fd42e6a6-2ca6-4edd-876f-1ea9f4bd3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257218678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2257218678
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.227253469
Short name T1065
Test name
Test status
Simulation time 259655447 ps
CPU time 3.57 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:53 PM PDT 24
Peak memory 242316 kb
Host smart-c4221471-51f9-47f7-8797-f22e54726fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227253469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.227253469
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3627533258
Short name T343
Test name
Test status
Simulation time 631728131 ps
CPU time 16.84 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242212 kb
Host smart-f99db467-d580-40ce-98e0-b464cc03c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627533258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3627533258
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1241240283
Short name T1104
Test name
Test status
Simulation time 411424126 ps
CPU time 4.97 seconds
Started Jun 22 07:01:48 PM PDT 24
Finished Jun 22 07:01:56 PM PDT 24
Peak memory 242184 kb
Host smart-1fcca00b-3f24-476f-a77a-63dc8e6acdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241240283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1241240283
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.335869632
Short name T1025
Test name
Test status
Simulation time 164830934 ps
CPU time 3.34 seconds
Started Jun 22 07:01:47 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242544 kb
Host smart-8fed3564-b06a-450d-a65c-4037221c7203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335869632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.335869632
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1431127638
Short name T207
Test name
Test status
Simulation time 178779559 ps
CPU time 3.7 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242480 kb
Host smart-632c2b2f-b7ee-455a-ae8d-072a372b8376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431127638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1431127638
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.3064774163
Short name T236
Test name
Test status
Simulation time 3992623981 ps
CPU time 28.88 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:02:19 PM PDT 24
Peak memory 242632 kb
Host smart-e3501911-8e20-4ff9-98cc-75ae72a92719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064774163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3064774163
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.900346536
Short name T206
Test name
Test status
Simulation time 99511063 ps
CPU time 3.35 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242600 kb
Host smart-65822d6a-5bd1-4617-b8e2-082b19da71d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900346536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.900346536
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.1645398551
Short name T126
Test name
Test status
Simulation time 220254939 ps
CPU time 7.24 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242212 kb
Host smart-9b15548f-6d4c-451e-985d-69dd0baa8756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645398551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1645398551
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.2504873885
Short name T195
Test name
Test status
Simulation time 275229207 ps
CPU time 4.36 seconds
Started Jun 22 07:01:52 PM PDT 24
Finished Jun 22 07:01:57 PM PDT 24
Peak memory 242040 kb
Host smart-2b243078-9169-4e21-acce-5ff20844fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504873885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2504873885
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.3245202002
Short name T852
Test name
Test status
Simulation time 130038012 ps
CPU time 5.08 seconds
Started Jun 22 07:01:45 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242136 kb
Host smart-080d7b48-00f8-4f0f-a39c-929ce28b35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245202002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3245202002
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2964010210
Short name T604
Test name
Test status
Simulation time 1144226673 ps
CPU time 8.23 seconds
Started Jun 22 07:01:46 PM PDT 24
Finished Jun 22 07:01:58 PM PDT 24
Peak memory 242608 kb
Host smart-5a8b32dc-f955-4fbd-b2ef-98ed72a9a6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964010210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2964010210
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.143413261
Short name T785
Test name
Test status
Simulation time 305337146 ps
CPU time 4.08 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242408 kb
Host smart-210c8cb8-d03a-4242-9d2c-ad186ea199b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143413261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.143413261
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1565758539
Short name T765
Test name
Test status
Simulation time 336939108 ps
CPU time 9.78 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242220 kb
Host smart-240a0a79-9f65-4d1e-8900-57ac21d5600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565758539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1565758539
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2091933534
Short name T183
Test name
Test status
Simulation time 165946403 ps
CPU time 4.02 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242156 kb
Host smart-0d85ccb1-e823-4a07-849f-5b863ae833ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091933534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2091933534
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.4160749458
Short name T830
Test name
Test status
Simulation time 211231503 ps
CPU time 5.08 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242048 kb
Host smart-1a271ca1-7dc2-43d0-ba08-75b1e0b633b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160749458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.4160749458
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2811954442
Short name T432
Test name
Test status
Simulation time 140969971 ps
CPU time 3.82 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242628 kb
Host smart-34e5380d-0303-474c-9400-b1033cce1676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811954442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2811954442
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1345137162
Short name T418
Test name
Test status
Simulation time 157147920 ps
CPU time 4.47 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242228 kb
Host smart-4e7e0b8e-5bda-482a-ab8f-cb93ce3b3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345137162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1345137162
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.640799780
Short name T909
Test name
Test status
Simulation time 58361184 ps
CPU time 1.79 seconds
Started Jun 22 06:58:55 PM PDT 24
Finished Jun 22 06:58:59 PM PDT 24
Peak memory 240812 kb
Host smart-e3284b59-0118-466c-9f65-d8d2579c4723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640799780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.640799780
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.3356645857
Short name T58
Test name
Test status
Simulation time 524594708 ps
CPU time 8.77 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:04 PM PDT 24
Peak memory 242548 kb
Host smart-5ab6388e-cec5-4882-8eed-ecdca35596ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356645857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.3356645857
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3193420787
Short name T878
Test name
Test status
Simulation time 1226464411 ps
CPU time 23.45 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:19 PM PDT 24
Peak memory 242700 kb
Host smart-04ec9851-ac93-4456-a2d9-64513672b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193420787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3193420787
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.1277227908
Short name T975
Test name
Test status
Simulation time 157180097 ps
CPU time 4.09 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:58:49 PM PDT 24
Peak memory 242168 kb
Host smart-428018ea-0a8a-43ec-bd8b-97c18d18bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277227908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1277227908
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.3058668589
Short name T1011
Test name
Test status
Simulation time 1304768525 ps
CPU time 22.94 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:19 PM PDT 24
Peak memory 242792 kb
Host smart-176a2802-da66-462c-809b-1396b7a1119e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058668589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3058668589
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.2200396909
Short name T4
Test name
Test status
Simulation time 1127640633 ps
CPU time 12.95 seconds
Started Jun 22 06:58:53 PM PDT 24
Finished Jun 22 06:59:07 PM PDT 24
Peak memory 242268 kb
Host smart-6c41973c-831b-410a-b3c3-2e463c722738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200396909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2200396909
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2529077625
Short name T918
Test name
Test status
Simulation time 1331702273 ps
CPU time 3.33 seconds
Started Jun 22 06:58:42 PM PDT 24
Finished Jun 22 06:58:48 PM PDT 24
Peak memory 242204 kb
Host smart-8f4abf22-3c39-4e51-afc8-162971812d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529077625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2529077625
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1452541942
Short name T1015
Test name
Test status
Simulation time 545171572 ps
CPU time 10.05 seconds
Started Jun 22 06:58:41 PM PDT 24
Finished Jun 22 06:58:53 PM PDT 24
Peak memory 242160 kb
Host smart-a0370248-21bd-4dbe-a82c-cccdb6e2a00e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452541942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1452541942
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.3737265039
Short name T1113
Test name
Test status
Simulation time 123552338 ps
CPU time 4.13 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:02 PM PDT 24
Peak memory 241892 kb
Host smart-7302c594-bdd7-4b83-a0f1-4cae102874eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737265039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3737265039
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.902103962
Short name T922
Test name
Test status
Simulation time 241677920 ps
CPU time 3.72 seconds
Started Jun 22 06:58:43 PM PDT 24
Finished Jun 22 06:58:50 PM PDT 24
Peak memory 242408 kb
Host smart-15041c30-aa0f-4f01-bf98-74d78a78a4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902103962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.902103962
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1674668671
Short name T866
Test name
Test status
Simulation time 37739861389 ps
CPU time 233.94 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 07:02:52 PM PDT 24
Peak memory 273288 kb
Host smart-2aeda7a9-b366-4acd-896a-ba0ef9267e38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674668671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1674668671
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.382851427
Short name T294
Test name
Test status
Simulation time 488322475792 ps
CPU time 2198.35 seconds
Started Jun 22 06:58:57 PM PDT 24
Finished Jun 22 07:35:38 PM PDT 24
Peak memory 407952 kb
Host smart-28476bed-6a24-4d23-b354-d1ab4ab7cf39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382851427 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.382851427
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2855787014
Short name T291
Test name
Test status
Simulation time 1361833043 ps
CPU time 21.75 seconds
Started Jun 22 06:58:53 PM PDT 24
Finished Jun 22 06:59:17 PM PDT 24
Peak memory 242112 kb
Host smart-259271b1-9d63-47ee-a709-1c2094564ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855787014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2855787014
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1576093181
Short name T720
Test name
Test status
Simulation time 181368017 ps
CPU time 4.59 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 242112 kb
Host smart-09dfe9d0-63dd-449d-afb1-dace10d3fbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576093181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1576093181
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.1761890396
Short name T155
Test name
Test status
Simulation time 1561019364 ps
CPU time 5.2 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242256 kb
Host smart-507c5b49-b318-424f-a821-a94814302854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761890396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1761890396
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.3892931008
Short name T599
Test name
Test status
Simulation time 604399163 ps
CPU time 4.51 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:05 PM PDT 24
Peak memory 242196 kb
Host smart-bd61bb64-4a6c-4505-a2f0-d184143e4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892931008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3892931008
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.2817833441
Short name T1004
Test name
Test status
Simulation time 3252874585 ps
CPU time 23.19 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:20 PM PDT 24
Peak memory 242272 kb
Host smart-14b38668-ba55-4087-95f4-8357ec59b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817833441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2817833441
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.815182876
Short name T1106
Test name
Test status
Simulation time 181524315 ps
CPU time 3.64 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:01:59 PM PDT 24
Peak memory 242240 kb
Host smart-a5e88984-5dc1-49b7-9075-dfbc95a8cf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815182876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.815182876
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.766780788
Short name T398
Test name
Test status
Simulation time 286415183 ps
CPU time 5.05 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242204 kb
Host smart-b1efa47f-3ece-47e2-ada6-bae38f6c7a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766780788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.766780788
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2644827346
Short name T511
Test name
Test status
Simulation time 417852697 ps
CPU time 5.21 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 242556 kb
Host smart-20536720-1f8c-4c47-8483-e9f71fb1cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644827346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2644827346
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.556507751
Short name T880
Test name
Test status
Simulation time 334624718 ps
CPU time 5.49 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:05 PM PDT 24
Peak memory 242132 kb
Host smart-31dd04e5-1c71-4278-91bd-3b48d1ef1862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556507751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.556507751
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.2804238494
Short name T857
Test name
Test status
Simulation time 153984780 ps
CPU time 4.16 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:01:59 PM PDT 24
Peak memory 242300 kb
Host smart-a387c7ab-4696-4539-b43d-b428710583eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804238494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2804238494
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.246105377
Short name T347
Test name
Test status
Simulation time 224249779 ps
CPU time 11.24 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:07 PM PDT 24
Peak memory 242072 kb
Host smart-cce8925f-f74a-4260-a86d-459b1de98078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246105377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.246105377
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.3478125678
Short name T434
Test name
Test status
Simulation time 1944126047 ps
CPU time 5.74 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 242192 kb
Host smart-cad7ebe3-89b0-4dcf-84a0-688f0e349e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478125678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3478125678
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.4064286915
Short name T454
Test name
Test status
Simulation time 495942537 ps
CPU time 4.49 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:05 PM PDT 24
Peak memory 242484 kb
Host smart-2bacf753-e85a-4b22-bd28-6607aa67fc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064286915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.4064286915
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.4278667050
Short name T1080
Test name
Test status
Simulation time 266843745 ps
CPU time 4.43 seconds
Started Jun 22 07:01:57 PM PDT 24
Finished Jun 22 07:02:07 PM PDT 24
Peak memory 242288 kb
Host smart-4f2cc66c-f871-4257-91ff-00aff65ebcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278667050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.4278667050
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1717367153
Short name T422
Test name
Test status
Simulation time 444300669 ps
CPU time 5.96 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242444 kb
Host smart-93f50e06-6b7a-4c80-a63d-a64b1ca1d83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717367153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1717367153
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1230111017
Short name T554
Test name
Test status
Simulation time 1834512426 ps
CPU time 5.05 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242388 kb
Host smart-3d8adafe-f8f4-4c2b-acb7-b475a65db4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230111017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1230111017
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.4393027
Short name T456
Test name
Test status
Simulation time 218296619 ps
CPU time 5.67 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242452 kb
Host smart-feacb139-5af0-460e-9c48-f6f729416f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4393027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.4393027
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.1652675308
Short name T174
Test name
Test status
Simulation time 93420142 ps
CPU time 3.59 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:01 PM PDT 24
Peak memory 242636 kb
Host smart-61404f87-3d0d-42e5-aca0-c90c204bf718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652675308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1652675308
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2034030367
Short name T709
Test name
Test status
Simulation time 91069350 ps
CPU time 1.78 seconds
Started Jun 22 06:58:53 PM PDT 24
Finished Jun 22 06:58:56 PM PDT 24
Peak memory 240820 kb
Host smart-7662b40e-cf31-4eba-9433-424c6c9295cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034030367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2034030367
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2431144065
Short name T782
Test name
Test status
Simulation time 3924863397 ps
CPU time 11 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:09 PM PDT 24
Peak memory 242452 kb
Host smart-d3ba6dbd-a43d-46ae-9074-6e69c0f6c305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431144065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2431144065
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.4146138323
Short name T1001
Test name
Test status
Simulation time 3188685624 ps
CPU time 38.31 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:36 PM PDT 24
Peak memory 242532 kb
Host smart-5ad0a195-27a8-4ce6-964d-10e43a1f0f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146138323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.4146138323
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.2535016766
Short name T873
Test name
Test status
Simulation time 1023061644 ps
CPU time 13.62 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:10 PM PDT 24
Peak memory 249040 kb
Host smart-25deb281-98d8-48b1-87a8-446dd2f5eb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535016766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2535016766
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1833909571
Short name T986
Test name
Test status
Simulation time 238235357 ps
CPU time 3.65 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:00 PM PDT 24
Peak memory 242132 kb
Host smart-f01bdb4d-5ade-49fc-bd2e-dc43f4a45498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833909571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1833909571
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3050593583
Short name T636
Test name
Test status
Simulation time 145480532 ps
CPU time 2.89 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:01 PM PDT 24
Peak memory 242588 kb
Host smart-ab6324d6-6943-4dc7-bf60-eaa5f69a1deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050593583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3050593583
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.2548322978
Short name T381
Test name
Test status
Simulation time 1687742219 ps
CPU time 14.3 seconds
Started Jun 22 06:58:52 PM PDT 24
Finished Jun 22 06:59:07 PM PDT 24
Peak memory 242008 kb
Host smart-4bf94013-0c66-43f9-9f11-ce745486e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548322978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2548322978
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.4018031069
Short name T771
Test name
Test status
Simulation time 1925876286 ps
CPU time 4.4 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:00 PM PDT 24
Peak memory 242428 kb
Host smart-27f7d579-4046-4b1c-8387-5488cdd80a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018031069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.4018031069
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.2949255759
Short name T506
Test name
Test status
Simulation time 436262103 ps
CPU time 7.58 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:06 PM PDT 24
Peak memory 242092 kb
Host smart-60b69a42-3d55-49e4-8e02-61cd2fd6cf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949255759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2949255759
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3193353998
Short name T374
Test name
Test status
Simulation time 4484694989 ps
CPU time 15.72 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:11 PM PDT 24
Peak memory 242652 kb
Host smart-ad052dc3-2148-4f22-abde-2f41ae75a41c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193353998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3193353998
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3272987141
Short name T1160
Test name
Test status
Simulation time 261258958 ps
CPU time 4.6 seconds
Started Jun 22 06:58:55 PM PDT 24
Finished Jun 22 06:59:02 PM PDT 24
Peak memory 242592 kb
Host smart-6f099104-9424-444f-919d-99fb24e8768c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272987141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3272987141
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.213025024
Short name T384
Test name
Test status
Simulation time 36098921525 ps
CPU time 155.22 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 07:01:33 PM PDT 24
Peak memory 259724 kb
Host smart-5bc99410-141a-4848-8a8c-7953d0764edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213025024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
213025024
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3171448437
Short name T1085
Test name
Test status
Simulation time 18614462739 ps
CPU time 448.76 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 07:06:25 PM PDT 24
Peak memory 284052 kb
Host smart-511ac3e3-d04f-4347-9da4-98afae280e60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171448437 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.3171448437
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3042002257
Short name T188
Test name
Test status
Simulation time 16173902104 ps
CPU time 36.15 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:33 PM PDT 24
Peak memory 243948 kb
Host smart-4c5279ff-15a2-4f1b-a87b-c736f6210d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042002257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3042002257
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.2918966533
Short name T711
Test name
Test status
Simulation time 1691194541 ps
CPU time 4.27 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 242464 kb
Host smart-f8e050c8-a4ae-447c-a56c-850639ba0a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918966533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.2918966533
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3333979583
Short name T1180
Test name
Test status
Simulation time 900811797 ps
CPU time 5.89 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:01 PM PDT 24
Peak memory 242092 kb
Host smart-7bafd386-e777-43f1-b2bb-75d1798f5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333979583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3333979583
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.968357547
Short name T928
Test name
Test status
Simulation time 471642910 ps
CPU time 5.03 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:01 PM PDT 24
Peak memory 242568 kb
Host smart-51e7d824-8b4c-4889-a1e8-28095ee0ae40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968357547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.968357547
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2434148572
Short name T192
Test name
Test status
Simulation time 225495319 ps
CPU time 5 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242072 kb
Host smart-a1af626b-14a6-4985-a246-315db3ee1e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434148572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2434148572
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3915326579
Short name T580
Test name
Test status
Simulation time 369206028 ps
CPU time 2.72 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:00 PM PDT 24
Peak memory 242176 kb
Host smart-cb550df3-0cb6-4bed-88f6-a86d9b00d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915326579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3915326579
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.4080273100
Short name T518
Test name
Test status
Simulation time 1126761442 ps
CPU time 10.01 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:09 PM PDT 24
Peak memory 242268 kb
Host smart-9aa1256e-a003-4204-ae9a-2cae787096a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080273100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.4080273100
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1739365154
Short name T1161
Test name
Test status
Simulation time 477043640 ps
CPU time 4.67 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242116 kb
Host smart-7ab77c41-73e0-462a-9c05-6f3bbbecf2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739365154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1739365154
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.4152300035
Short name T587
Test name
Test status
Simulation time 194313133 ps
CPU time 5.51 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:05 PM PDT 24
Peak memory 242476 kb
Host smart-e0149c81-0f3e-418d-8df7-de4e0f7f6556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152300035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.4152300035
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.172680048
Short name T505
Test name
Test status
Simulation time 113558644 ps
CPU time 3.47 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:00 PM PDT 24
Peak memory 242180 kb
Host smart-e35d80d3-4332-4a81-829e-e79afa58c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172680048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.172680048
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.870210534
Short name T901
Test name
Test status
Simulation time 473635471 ps
CPU time 5.16 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242132 kb
Host smart-8106da27-fa9d-4546-9e98-20acf0743594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870210534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.870210534
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1916374793
Short name T895
Test name
Test status
Simulation time 168328949 ps
CPU time 5.05 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242412 kb
Host smart-d57cf397-b663-4e04-885b-94ba81cea301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916374793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1916374793
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1226451066
Short name T168
Test name
Test status
Simulation time 1970474040 ps
CPU time 6.25 seconds
Started Jun 22 07:01:53 PM PDT 24
Finished Jun 22 07:02:02 PM PDT 24
Peak memory 242600 kb
Host smart-fc62168e-6010-479b-b3b2-2c80693ba70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226451066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1226451066
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3800206082
Short name T988
Test name
Test status
Simulation time 511333113 ps
CPU time 5.32 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:06 PM PDT 24
Peak memory 242400 kb
Host smart-cd9c50fb-c061-4e4b-91f1-b8a83d97c67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800206082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3800206082
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2090404337
Short name T396
Test name
Test status
Simulation time 477863634 ps
CPU time 10.24 seconds
Started Jun 22 07:01:55 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242468 kb
Host smart-5fa3a390-ca85-49b2-b715-10c9dd9eb3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090404337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2090404337
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.139442728
Short name T570
Test name
Test status
Simulation time 208385362 ps
CPU time 3.34 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242436 kb
Host smart-e7a9ccfb-c5aa-45d6-b538-f468a35a15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139442728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.139442728
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3444472403
Short name T618
Test name
Test status
Simulation time 782353913 ps
CPU time 19.92 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:27 PM PDT 24
Peak memory 242108 kb
Host smart-a5b249bd-a332-471e-ba35-e32611c612cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444472403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3444472403
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2585205423
Short name T661
Test name
Test status
Simulation time 140722733 ps
CPU time 4.26 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242600 kb
Host smart-b939d35c-24b9-481a-98f4-154a647333d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585205423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2585205423
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3037433304
Short name T1117
Test name
Test status
Simulation time 315116580 ps
CPU time 17.34 seconds
Started Jun 22 07:01:54 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242156 kb
Host smart-2d293e49-495e-467f-b7c5-25f652b1b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037433304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3037433304
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.3760238215
Short name T960
Test name
Test status
Simulation time 296356588 ps
CPU time 5 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:12 PM PDT 24
Peak memory 242104 kb
Host smart-151f9ae5-9698-416c-8c24-4d07419d4a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760238215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.3760238215
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1458419893
Short name T1181
Test name
Test status
Simulation time 135947594 ps
CPU time 3.93 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242268 kb
Host smart-cbd597a6-625f-4abd-b561-0f0dbb04651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458419893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1458419893
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.700918822
Short name T978
Test name
Test status
Simulation time 552835477 ps
CPU time 1.86 seconds
Started Jun 22 06:59:03 PM PDT 24
Finished Jun 22 06:59:08 PM PDT 24
Peak memory 240636 kb
Host smart-a829fda7-b5ed-425e-9463-c53a1c23101d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700918822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.700918822
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2642216871
Short name T132
Test name
Test status
Simulation time 227678466 ps
CPU time 7.21 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:12 PM PDT 24
Peak memory 242116 kb
Host smart-f87cc0df-2bcf-4b0e-828a-7169ad754d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642216871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2642216871
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.1681437412
Short name T472
Test name
Test status
Simulation time 282676875 ps
CPU time 16.11 seconds
Started Jun 22 06:59:03 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242196 kb
Host smart-281a3831-e191-48b8-9b77-0dcf62e5009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681437412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1681437412
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3526868002
Short name T872
Test name
Test status
Simulation time 533182708 ps
CPU time 5.71 seconds
Started Jun 22 06:59:00 PM PDT 24
Finished Jun 22 06:59:07 PM PDT 24
Peak memory 242156 kb
Host smart-055074c2-df1d-4be4-b7f7-a9f6530a3092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526868002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3526868002
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.253351097
Short name T43
Test name
Test status
Simulation time 144662327 ps
CPU time 4.87 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:03 PM PDT 24
Peak memory 242632 kb
Host smart-04744e0c-ec2a-4887-8367-f16b880a3f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253351097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.253351097
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.546002692
Short name T938
Test name
Test status
Simulation time 1207774287 ps
CPU time 13.75 seconds
Started Jun 22 06:59:00 PM PDT 24
Finished Jun 22 06:59:15 PM PDT 24
Peak memory 242220 kb
Host smart-26bc1e56-aba9-43b7-998d-ef4927c84a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546002692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.546002692
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3904913582
Short name T766
Test name
Test status
Simulation time 606546242 ps
CPU time 4.82 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:09 PM PDT 24
Peak memory 242676 kb
Host smart-f34c7f8b-a9c1-4c30-81f8-30b4414696cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904913582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3904913582
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.652307215
Short name T926
Test name
Test status
Simulation time 500349760 ps
CPU time 12.62 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:17 PM PDT 24
Peak memory 242180 kb
Host smart-c20d19de-cde4-48b7-869c-fceb580f310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652307215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.652307215
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.1457901110
Short name T987
Test name
Test status
Simulation time 965953159 ps
CPU time 16.14 seconds
Started Jun 22 06:58:54 PM PDT 24
Finished Jun 22 06:59:12 PM PDT 24
Peak memory 242380 kb
Host smart-0cd5898c-7705-4a5f-b35a-547099252957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457901110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1457901110
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.653874047
Short name T808
Test name
Test status
Simulation time 314073683 ps
CPU time 9.59 seconds
Started Jun 22 06:59:02 PM PDT 24
Finished Jun 22 06:59:15 PM PDT 24
Peak memory 242192 kb
Host smart-b197a978-41c5-4973-a1ef-aacf1f0f5b86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653874047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.653874047
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2875434648
Short name T433
Test name
Test status
Simulation time 4733536140 ps
CPU time 15.99 seconds
Started Jun 22 06:58:56 PM PDT 24
Finished Jun 22 06:59:14 PM PDT 24
Peak memory 242252 kb
Host smart-18483c43-1bd2-4539-a1f2-6955dc391bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875434648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2875434648
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.1309259185
Short name T227
Test name
Test status
Simulation time 24491202083 ps
CPU time 113.05 seconds
Started Jun 22 06:59:00 PM PDT 24
Finished Jun 22 07:00:54 PM PDT 24
Peak memory 251364 kb
Host smart-056b930f-85ff-446c-ad5e-a3c4076405cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309259185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.1309259185
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1978260261
Short name T8
Test name
Test status
Simulation time 102305421668 ps
CPU time 569.52 seconds
Started Jun 22 06:59:03 PM PDT 24
Finished Jun 22 07:08:35 PM PDT 24
Peak memory 299296 kb
Host smart-4ed2b1bb-5753-40f3-90c5-b100297c678f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978260261 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1978260261
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.749589176
Short name T1030
Test name
Test status
Simulation time 2575749644 ps
CPU time 23.32 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:28 PM PDT 24
Peak memory 242520 kb
Host smart-e02de0d8-7a24-44d0-8e92-70a7ffe7a155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749589176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.749589176
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.136811451
Short name T1168
Test name
Test status
Simulation time 2456804805 ps
CPU time 6.77 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:08 PM PDT 24
Peak memory 242420 kb
Host smart-9c216483-895f-4233-9c98-2b1116626bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136811451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.136811451
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.140100134
Short name T1013
Test name
Test status
Simulation time 246232166 ps
CPU time 4.54 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:05 PM PDT 24
Peak memory 242088 kb
Host smart-8083435a-de1b-41b2-bc98-a576a8246b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140100134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.140100134
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1269855424
Short name T213
Test name
Test status
Simulation time 416836103 ps
CPU time 3.79 seconds
Started Jun 22 07:01:56 PM PDT 24
Finished Jun 22 07:02:04 PM PDT 24
Peak memory 242264 kb
Host smart-22ecafb6-c060-443b-b6a7-0598e149504a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269855424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1269855424
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.4160225648
Short name T445
Test name
Test status
Simulation time 290532066 ps
CPU time 11.79 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:15 PM PDT 24
Peak memory 242152 kb
Host smart-aec870fd-2a86-4c9d-8e28-1e8fd576b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160225648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4160225648
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2179326243
Short name T572
Test name
Test status
Simulation time 202762078 ps
CPU time 4.22 seconds
Started Jun 22 07:02:02 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242304 kb
Host smart-60e7ec90-19e3-49aa-b13f-fd761d4c1c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179326243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2179326243
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.518579049
Short name T933
Test name
Test status
Simulation time 4589828879 ps
CPU time 13.1 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:17 PM PDT 24
Peak memory 242788 kb
Host smart-62a1cfd4-2107-4499-93e8-e9e16a2c169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518579049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.518579049
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.3435326557
Short name T565
Test name
Test status
Simulation time 169990307 ps
CPU time 3.5 seconds
Started Jun 22 07:02:02 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242176 kb
Host smart-6f22ab7c-bac1-4485-a0a7-f6a7df9fcf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435326557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.3435326557
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3243261543
Short name T976
Test name
Test status
Simulation time 167556867 ps
CPU time 6.55 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:13 PM PDT 24
Peak memory 242120 kb
Host smart-1b6c4d2f-2b56-4505-af48-7df35cb0e163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243261543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3243261543
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1828688531
Short name T1176
Test name
Test status
Simulation time 2319415442 ps
CPU time 5.78 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:09 PM PDT 24
Peak memory 242628 kb
Host smart-2ebe28ef-74d6-4e3b-b194-7a79868dce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828688531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1828688531
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.3114948131
Short name T260
Test name
Test status
Simulation time 625028110 ps
CPU time 19.66 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:25 PM PDT 24
Peak memory 242196 kb
Host smart-4d4a1f8e-3208-485e-8bb7-e2cc799baaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114948131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3114948131
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2438707192
Short name T705
Test name
Test status
Simulation time 182255812 ps
CPU time 4.15 seconds
Started Jun 22 07:01:58 PM PDT 24
Finished Jun 22 07:02:08 PM PDT 24
Peak memory 242152 kb
Host smart-05c133e1-37c2-4baf-bba0-52fdfda28fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438707192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2438707192
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.739549304
Short name T680
Test name
Test status
Simulation time 786081365 ps
CPU time 6.78 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:13 PM PDT 24
Peak memory 242552 kb
Host smart-acfa36fa-4673-48ca-8857-29b2676cd977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739549304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.739549304
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3609917205
Short name T784
Test name
Test status
Simulation time 102281718 ps
CPU time 4.57 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242384 kb
Host smart-8861c579-3ae8-4b7a-aa1e-6af7f58cb2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609917205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3609917205
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2010367470
Short name T224
Test name
Test status
Simulation time 555232534 ps
CPU time 6.45 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242532 kb
Host smart-3ee28d1a-d16b-40ca-84f4-314ec7d5d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010367470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2010367470
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.2155892841
Short name T415
Test name
Test status
Simulation time 166657505 ps
CPU time 4.3 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:09 PM PDT 24
Peak memory 242240 kb
Host smart-07200b54-2fba-4a47-a583-4a732494e642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155892841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2155892841
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.4023805782
Short name T825
Test name
Test status
Simulation time 2475111438 ps
CPU time 8.89 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:13 PM PDT 24
Peak memory 242320 kb
Host smart-51d46cc9-fded-4b63-a157-5cda99b843da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023805782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.4023805782
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3961488928
Short name T156
Test name
Test status
Simulation time 363562253 ps
CPU time 4.67 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:12 PM PDT 24
Peak memory 242192 kb
Host smart-cd1bef03-f280-4862-9e9e-47d7ab70591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961488928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3961488928
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1450866360
Short name T722
Test name
Test status
Simulation time 321247397 ps
CPU time 7.92 seconds
Started Jun 22 07:02:02 PM PDT 24
Finished Jun 22 07:02:15 PM PDT 24
Peak memory 242156 kb
Host smart-121a73aa-accc-48fb-b17d-369654a82682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450866360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1450866360
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.1978014473
Short name T573
Test name
Test status
Simulation time 361283972 ps
CPU time 3.62 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242148 kb
Host smart-5aaa60ae-ade4-461b-b617-34ae662be484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978014473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1978014473
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.856465112
Short name T829
Test name
Test status
Simulation time 2139418641 ps
CPU time 20.97 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:26 PM PDT 24
Peak memory 242572 kb
Host smart-480a5a85-38b5-4967-8ec1-53211ff92ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856465112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.856465112
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.168568262
Short name T911
Test name
Test status
Simulation time 220825111 ps
CPU time 1.98 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:13 PM PDT 24
Peak memory 241036 kb
Host smart-4bf78007-7e04-456f-bf3a-9ffe9f3ce47d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168568262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.168568262
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.1814266957
Short name T85
Test name
Test status
Simulation time 10669884960 ps
CPU time 25.68 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 247432 kb
Host smart-ab2322d5-e592-45fc-be91-ccb0b6406567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814266957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.1814266957
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.4161523819
Short name T694
Test name
Test status
Simulation time 871940901 ps
CPU time 23.48 seconds
Started Jun 22 06:59:04 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 242152 kb
Host smart-2de37662-9440-4c11-ad3a-31f3cd85321f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161523819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.4161523819
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3691346280
Short name T1182
Test name
Test status
Simulation time 19385401138 ps
CPU time 31.48 seconds
Started Jun 22 06:59:03 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 243360 kb
Host smart-c541ad71-33e0-4f03-9b95-3c6d75059e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691346280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3691346280
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.3839784688
Short name T208
Test name
Test status
Simulation time 379683375 ps
CPU time 4.18 seconds
Started Jun 22 06:59:03 PM PDT 24
Finished Jun 22 06:59:10 PM PDT 24
Peak memory 242156 kb
Host smart-8b42c7eb-4fa3-4c95-9ffd-58403f401335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839784688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3839784688
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1136166291
Short name T199
Test name
Test status
Simulation time 6341460556 ps
CPU time 52.12 seconds
Started Jun 22 06:59:04 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 257400 kb
Host smart-00a3e661-648b-49f9-9394-4f0d38f236c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136166291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1136166291
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.3055672350
Short name T557
Test name
Test status
Simulation time 1079125401 ps
CPU time 7.53 seconds
Started Jun 22 06:59:02 PM PDT 24
Finished Jun 22 06:59:13 PM PDT 24
Peak memory 242352 kb
Host smart-a0731ebb-339d-43c7-a186-951d7e18ceb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055672350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3055672350
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1400329137
Short name T194
Test name
Test status
Simulation time 614055911 ps
CPU time 9.97 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:14 PM PDT 24
Peak memory 242156 kb
Host smart-9f142809-ae0a-41b4-8ec8-1c46b251c3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400329137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1400329137
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.1378311568
Short name T558
Test name
Test status
Simulation time 2859858478 ps
CPU time 24.97 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:29 PM PDT 24
Peak memory 242276 kb
Host smart-7ba54911-978b-4a09-9571-5f90e44f3e6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378311568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.1378311568
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2835083176
Short name T789
Test name
Test status
Simulation time 145605570 ps
CPU time 5.2 seconds
Started Jun 22 06:59:01 PM PDT 24
Finished Jun 22 06:59:08 PM PDT 24
Peak memory 242200 kb
Host smart-eace62a2-350f-4643-b857-1d3e201dcffe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835083176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2835083176
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3796871658
Short name T794
Test name
Test status
Simulation time 720430067 ps
CPU time 9.18 seconds
Started Jun 22 06:59:02 PM PDT 24
Finished Jun 22 06:59:14 PM PDT 24
Peak memory 242280 kb
Host smart-6d99db37-b5de-4b7e-a798-d4323f526c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796871658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3796871658
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1720422461
Short name T736
Test name
Test status
Simulation time 26551396216 ps
CPU time 547.44 seconds
Started Jun 22 06:59:09 PM PDT 24
Finished Jun 22 07:08:21 PM PDT 24
Peak memory 281992 kb
Host smart-971d7b58-b642-4d06-acbc-a7a1a0c9cbf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720422461 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.1720422461
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3122398799
Short name T1082
Test name
Test status
Simulation time 3905634838 ps
CPU time 12.77 seconds
Started Jun 22 06:59:05 PM PDT 24
Finished Jun 22 06:59:21 PM PDT 24
Peak memory 243160 kb
Host smart-2c950ba6-6b7b-49f9-94ee-057aae66ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122398799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3122398799
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3161519794
Short name T853
Test name
Test status
Simulation time 1465989472 ps
CPU time 3.7 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:09 PM PDT 24
Peak memory 242620 kb
Host smart-f055c058-4ac9-4257-bee2-bfdb1ad5dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161519794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3161519794
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.1541216528
Short name T810
Test name
Test status
Simulation time 621225479 ps
CPU time 19.36 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:26 PM PDT 24
Peak memory 242428 kb
Host smart-597c8db1-f6a8-4877-8301-82a8e4e8a20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541216528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1541216528
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.4129192842
Short name T890
Test name
Test status
Simulation time 509495610 ps
CPU time 3.82 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242292 kb
Host smart-d970ff6d-53f9-4907-a11e-ac8f199f455b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129192842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.4129192842
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.4215214356
Short name T153
Test name
Test status
Simulation time 1408380512 ps
CPU time 24.96 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:31 PM PDT 24
Peak memory 242076 kb
Host smart-b15ab44d-d030-4106-bd46-c23668a7a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215214356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.4215214356
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3947843684
Short name T87
Test name
Test status
Simulation time 647727141 ps
CPU time 4.51 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:11 PM PDT 24
Peak memory 242248 kb
Host smart-0946d2b2-57bd-4184-b523-b4396ae8fc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947843684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3947843684
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1954416985
Short name T270
Test name
Test status
Simulation time 402485094 ps
CPU time 4.41 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242748 kb
Host smart-7ea6605b-3ac1-46a8-8829-d4ef2c3a28ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954416985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1954416985
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2161541772
Short name T995
Test name
Test status
Simulation time 297618204 ps
CPU time 3.45 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242064 kb
Host smart-1ce3cb9e-0dd5-46b5-9ba1-af2a662f0106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161541772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2161541772
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.467987266
Short name T628
Test name
Test status
Simulation time 249934102 ps
CPU time 13.33 seconds
Started Jun 22 07:01:59 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242204 kb
Host smart-6f42074f-eab8-4184-a518-6016608d6dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467987266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.467987266
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1777625848
Short name T452
Test name
Test status
Simulation time 2761869246 ps
CPU time 10.91 seconds
Started Jun 22 07:02:01 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242384 kb
Host smart-9ab6b572-8469-4fb5-a093-64f5431f90d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777625848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1777625848
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.351288158
Short name T567
Test name
Test status
Simulation time 549532236 ps
CPU time 4.04 seconds
Started Jun 22 07:02:00 PM PDT 24
Finished Jun 22 07:02:10 PM PDT 24
Peak memory 242240 kb
Host smart-9977449f-5d5d-4923-99e1-59e33795123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351288158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.351288158
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2421936252
Short name T1037
Test name
Test status
Simulation time 395202321 ps
CPU time 3.27 seconds
Started Jun 22 07:02:06 PM PDT 24
Finished Jun 22 07:02:13 PM PDT 24
Peak memory 242604 kb
Host smart-983b8e49-6d56-4166-a401-3746692df0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421936252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2421936252
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.4018261301
Short name T790
Test name
Test status
Simulation time 443601488 ps
CPU time 4.29 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242588 kb
Host smart-c4b5dfb9-165a-407f-b39d-7f6b5cc48c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018261301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4018261301
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.3037341178
Short name T413
Test name
Test status
Simulation time 158276108 ps
CPU time 5.67 seconds
Started Jun 22 07:02:11 PM PDT 24
Finished Jun 22 07:02:20 PM PDT 24
Peak memory 242224 kb
Host smart-6b2936bd-2e4a-400f-a9a0-7cf5a8817e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037341178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.3037341178
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2662902521
Short name T1099
Test name
Test status
Simulation time 251479836 ps
CPU time 3.72 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242112 kb
Host smart-8aa40427-2e40-415b-9bc2-5a5574e03eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662902521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2662902521
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.3319552696
Short name T330
Test name
Test status
Simulation time 252032347 ps
CPU time 4.35 seconds
Started Jun 22 07:02:09 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242600 kb
Host smart-930fbb81-553d-497b-bf79-b8285b72566c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319552696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3319552696
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.768326338
Short name T1093
Test name
Test status
Simulation time 396025515 ps
CPU time 4.23 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242240 kb
Host smart-15bdb8c5-7561-46f3-ad79-4e8514aaafd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768326338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.768326338
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3329777578
Short name T753
Test name
Test status
Simulation time 148707605 ps
CPU time 5.63 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:18 PM PDT 24
Peak memory 242220 kb
Host smart-44cfad30-6b72-492e-ae71-14cf5627c983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329777578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3329777578
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.3085801278
Short name T66
Test name
Test status
Simulation time 354227760 ps
CPU time 4.99 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:19 PM PDT 24
Peak memory 242128 kb
Host smart-7adb72af-10d9-4533-9f61-14461f468c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085801278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3085801278
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.3145940807
Short name T769
Test name
Test status
Simulation time 11169715918 ps
CPU time 31.69 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:43 PM PDT 24
Peak memory 242252 kb
Host smart-d5fa5021-68dd-4df6-911c-baaffedbbc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145940807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3145940807
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.1594664932
Short name T481
Test name
Test status
Simulation time 261575399 ps
CPU time 1.78 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:20 PM PDT 24
Peak memory 240700 kb
Host smart-0d13e4a3-e038-4cdd-b0ca-fd141e605a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594664932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.1594664932
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.635383438
Short name T804
Test name
Test status
Simulation time 545007803 ps
CPU time 18.45 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:28 PM PDT 24
Peak memory 242216 kb
Host smart-0d080a5c-1a80-4fc8-89f1-6a63eae56aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635383438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.635383438
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.1487062257
Short name T549
Test name
Test status
Simulation time 5034710275 ps
CPU time 40 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 06:59:53 PM PDT 24
Peak memory 252624 kb
Host smart-ec9ff502-7a12-4cc3-8178-223544c42b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487062257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.1487062257
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2133749893
Short name T907
Test name
Test status
Simulation time 690888071 ps
CPU time 16.72 seconds
Started Jun 22 06:59:09 PM PDT 24
Finished Jun 22 06:59:31 PM PDT 24
Peak memory 242384 kb
Host smart-c15a6b91-117c-45f3-a045-53f4826a7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133749893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2133749893
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.3969047494
Short name T1057
Test name
Test status
Simulation time 150649120 ps
CPU time 3.93 seconds
Started Jun 22 06:59:09 PM PDT 24
Finished Jun 22 06:59:18 PM PDT 24
Peak memory 242432 kb
Host smart-f1f98787-66a8-4870-9385-7c31bc81ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969047494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.3969047494
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.526426500
Short name T253
Test name
Test status
Simulation time 410727571 ps
CPU time 13.64 seconds
Started Jun 22 06:59:05 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242280 kb
Host smart-df320959-c6d3-48d9-a5c0-d1c2515de86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526426500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.526426500
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2909987380
Short name T787
Test name
Test status
Simulation time 808660352 ps
CPU time 5.49 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:16 PM PDT 24
Peak memory 242148 kb
Host smart-7f299afb-27e1-41ce-b24c-0980c0dd8255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909987380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2909987380
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3164924260
Short name T583
Test name
Test status
Simulation time 200567562 ps
CPU time 11.26 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 242568 kb
Host smart-6de206ba-d0a7-4103-a0c4-ff103f0ce7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164924260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3164924260
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.2810091957
Short name T836
Test name
Test status
Simulation time 3081918231 ps
CPU time 29.73 seconds
Started Jun 22 06:59:07 PM PDT 24
Finished Jun 22 06:59:41 PM PDT 24
Peak memory 242384 kb
Host smart-ba33b44b-ba1b-4a9a-a552-8242f6139932
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810091957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2810091957
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1492182517
Short name T1007
Test name
Test status
Simulation time 232081565 ps
CPU time 4.45 seconds
Started Jun 22 06:59:05 PM PDT 24
Finished Jun 22 06:59:13 PM PDT 24
Peak memory 248912 kb
Host smart-0ec21b0f-4568-4d6d-9241-7785ed7520a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1492182517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1492182517
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.467596087
Short name T1175
Test name
Test status
Simulation time 835187665 ps
CPU time 6.77 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:17 PM PDT 24
Peak memory 242560 kb
Host smart-0d16a04d-c33b-469f-9fbe-353def428832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467596087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.467596087
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.3082376498
Short name T269
Test name
Test status
Simulation time 589328107467 ps
CPU time 970 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 07:15:29 PM PDT 24
Peak memory 276620 kb
Host smart-50fbe9eb-37cb-4a20-b5b1-fa767b311a5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082376498 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.3082376498
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.37238437
Short name T985
Test name
Test status
Simulation time 157055061 ps
CPU time 4.25 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242172 kb
Host smart-7d3fa0bf-bf66-4b90-a68f-29f580180b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37238437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.37238437
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1810648346
Short name T1070
Test name
Test status
Simulation time 331171080 ps
CPU time 5.18 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:19 PM PDT 24
Peak memory 242588 kb
Host smart-79a30a8c-441e-49fd-a7de-b5e2c62ef18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810648346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1810648346
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1136193283
Short name T226
Test name
Test status
Simulation time 13857276667 ps
CPU time 44.17 seconds
Started Jun 22 07:02:07 PM PDT 24
Finished Jun 22 07:02:54 PM PDT 24
Peak memory 242500 kb
Host smart-ca3b3b74-f0df-477e-a469-7e32cd1a59c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136193283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1136193283
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.739158986
Short name T527
Test name
Test status
Simulation time 128801949 ps
CPU time 3.91 seconds
Started Jun 22 07:02:07 PM PDT 24
Finished Jun 22 07:02:15 PM PDT 24
Peak memory 242484 kb
Host smart-7ee68c3f-1236-4f5e-b0aa-ced7faa0594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739158986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.739158986
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.1399737765
Short name T229
Test name
Test status
Simulation time 528020620 ps
CPU time 6.4 seconds
Started Jun 22 07:02:09 PM PDT 24
Finished Jun 22 07:02:20 PM PDT 24
Peak memory 242160 kb
Host smart-89a9f0a4-ba43-4dee-ac17-a806968ba9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399737765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.1399737765
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2002189906
Short name T403
Test name
Test status
Simulation time 136386125 ps
CPU time 3.72 seconds
Started Jun 22 07:02:09 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242572 kb
Host smart-36f6720d-ad33-4616-88df-0c7fe3de819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002189906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2002189906
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.3536041948
Short name T488
Test name
Test status
Simulation time 2651395512 ps
CPU time 13.67 seconds
Started Jun 22 07:02:11 PM PDT 24
Finished Jun 22 07:02:28 PM PDT 24
Peak memory 242332 kb
Host smart-4e4a1c76-5807-442b-933c-c418e972e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536041948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3536041948
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.2099721064
Short name T12
Test name
Test status
Simulation time 879444121 ps
CPU time 8.78 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:23 PM PDT 24
Peak memory 242544 kb
Host smart-a53bd536-93f2-4082-a7ea-28315bedb7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099721064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2099721064
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.3533052708
Short name T965
Test name
Test status
Simulation time 115428277 ps
CPU time 2.98 seconds
Started Jun 22 07:02:07 PM PDT 24
Finished Jun 22 07:02:13 PM PDT 24
Peak memory 242392 kb
Host smart-d9125957-4296-4b90-b774-40c40e890980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533052708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3533052708
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.650073599
Short name T500
Test name
Test status
Simulation time 1074086747 ps
CPU time 12.17 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242140 kb
Host smart-3fd0e3f3-c432-46f1-8564-e62d8713bff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650073599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.650073599
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3727060844
Short name T205
Test name
Test status
Simulation time 147019189 ps
CPU time 3.88 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242276 kb
Host smart-c2d63934-d3c8-4546-ae4a-544533c2ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727060844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3727060844
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2118266407
Short name T725
Test name
Test status
Simulation time 245548051 ps
CPU time 13.95 seconds
Started Jun 22 07:02:10 PM PDT 24
Finished Jun 22 07:02:28 PM PDT 24
Peak memory 242272 kb
Host smart-f72c48f8-3dc0-45bc-b73d-4a8f760ddab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118266407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2118266407
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3750406778
Short name T673
Test name
Test status
Simulation time 1670370983 ps
CPU time 4.5 seconds
Started Jun 22 07:02:07 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242188 kb
Host smart-9fe6a3d8-7f63-46cc-a960-83afb02c3d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750406778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3750406778
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1845404289
Short name T742
Test name
Test status
Simulation time 148670785 ps
CPU time 4.27 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:16 PM PDT 24
Peak memory 242272 kb
Host smart-e53854e5-002a-49c8-9710-3e0143a53b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845404289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1845404289
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.4058545239
Short name T891
Test name
Test status
Simulation time 125476903 ps
CPU time 4.68 seconds
Started Jun 22 07:02:11 PM PDT 24
Finished Jun 22 07:02:19 PM PDT 24
Peak memory 242312 kb
Host smart-144cd6c1-b9ab-4105-9bd8-cadf9e683495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058545239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.4058545239
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.633556691
Short name T166
Test name
Test status
Simulation time 530296247 ps
CPU time 12.51 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242468 kb
Host smart-9d9fc122-2c8c-41c3-8343-261953ef3c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633556691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.633556691
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.1262437793
Short name T1024
Test name
Test status
Simulation time 188321518 ps
CPU time 3.33 seconds
Started Jun 22 07:02:08 PM PDT 24
Finished Jun 22 07:02:15 PM PDT 24
Peak memory 242332 kb
Host smart-6b80f71a-2d5b-4910-9f3e-e4f1eb02b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262437793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.1262437793
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.3967616160
Short name T508
Test name
Test status
Simulation time 272585239 ps
CPU time 13.53 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:32 PM PDT 24
Peak memory 242192 kb
Host smart-26a3e9c1-7d9b-4c4a-900b-c1da93d0b677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967616160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3967616160
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.3894393510
Short name T447
Test name
Test status
Simulation time 544401135 ps
CPU time 4.42 seconds
Started Jun 22 07:02:17 PM PDT 24
Finished Jun 22 07:02:25 PM PDT 24
Peak memory 242152 kb
Host smart-3c7cd22c-c9a7-4784-b9de-7d11d7a2770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894393510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3894393510
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.574217236
Short name T250
Test name
Test status
Simulation time 332126534 ps
CPU time 10.88 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242216 kb
Host smart-c4474851-0d4a-4ada-9d38-d0b929480d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574217236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.574217236
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.965603156
Short name T336
Test name
Test status
Simulation time 189609138 ps
CPU time 1.89 seconds
Started Jun 22 06:59:07 PM PDT 24
Finished Jun 22 06:59:14 PM PDT 24
Peak memory 240624 kb
Host smart-6e71ac79-654f-4c30-a0c3-085d2f011f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965603156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.965603156
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2205769671
Short name T427
Test name
Test status
Simulation time 2141846684 ps
CPU time 36.47 seconds
Started Jun 22 06:58:53 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 244344 kb
Host smart-23f54131-e162-4dd3-946e-1072729bdbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205769671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2205769671
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.330277341
Short name T457
Test name
Test status
Simulation time 1351167210 ps
CPU time 21.96 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242276 kb
Host smart-0843cd86-f1c1-4dd9-9e56-62c93a6d9699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330277341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.330277341
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.2994297260
Short name T687
Test name
Test status
Simulation time 520205273 ps
CPU time 12.36 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 06:59:25 PM PDT 24
Peak memory 242736 kb
Host smart-05cec6b0-4404-4e0b-addb-992ed7f0f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994297260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.2994297260
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1427944402
Short name T832
Test name
Test status
Simulation time 1911248726 ps
CPU time 4.74 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 06:59:17 PM PDT 24
Peak memory 242104 kb
Host smart-2032abf1-3ead-43ff-b4bd-53af9299d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427944402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1427944402
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.502341861
Short name T708
Test name
Test status
Simulation time 1168970290 ps
CPU time 13.76 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:34 PM PDT 24
Peak memory 249208 kb
Host smart-51736b2c-4661-41e5-9c61-be87d0c40ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502341861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.502341861
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.1194243983
Short name T670
Test name
Test status
Simulation time 2391837243 ps
CPU time 20.83 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:38 PM PDT 24
Peak memory 242672 kb
Host smart-087faa69-587d-40b7-a9ed-b1c2f57245c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194243983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.1194243983
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2837376170
Short name T1084
Test name
Test status
Simulation time 1384395737 ps
CPU time 4.31 seconds
Started Jun 22 06:59:06 PM PDT 24
Finished Jun 22 06:59:14 PM PDT 24
Peak memory 242152 kb
Host smart-dd3313fb-fe3f-4e67-8054-aaf14b478cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837376170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2837376170
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.1944424113
Short name T1071
Test name
Test status
Simulation time 6240213524 ps
CPU time 15.98 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 06:59:29 PM PDT 24
Peak memory 242220 kb
Host smart-c2821e99-885c-4940-b5a1-f95f59dec6d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944424113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.1944424113
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1233105200
Short name T244
Test name
Test status
Simulation time 1044158888 ps
CPU time 10.71 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:31 PM PDT 24
Peak memory 242432 kb
Host smart-2f6b4223-bf9f-499f-8805-72ba69894e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1233105200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1233105200
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.614503300
Short name T410
Test name
Test status
Simulation time 278188355 ps
CPU time 6.88 seconds
Started Jun 22 06:59:07 PM PDT 24
Finished Jun 22 06:59:19 PM PDT 24
Peak memory 242200 kb
Host smart-a31dcad0-d159-4ba5-ba65-311a7189005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614503300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.614503300
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.822724386
Short name T479
Test name
Test status
Simulation time 2379833781 ps
CPU time 20.7 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:38 PM PDT 24
Peak memory 242876 kb
Host smart-9ed56fda-0f15-47c7-92a3-55561ff99f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822724386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
822724386
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.2687556074
Short name T386
Test name
Test status
Simulation time 2700592966 ps
CPU time 19.64 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 249144 kb
Host smart-a6091789-3bf5-462f-a9d6-516d08a2f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687556074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2687556074
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.2495629513
Short name T879
Test name
Test status
Simulation time 106087296 ps
CPU time 3.79 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242376 kb
Host smart-9fba63c9-01b6-4c7a-ad6d-ab4513d04a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495629513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2495629513
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.4104328929
Short name T1075
Test name
Test status
Simulation time 366552583 ps
CPU time 11.17 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:30 PM PDT 24
Peak memory 242508 kb
Host smart-5b5de677-8e30-4a5c-99c1-ac78c119280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104328929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.4104328929
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.3521705442
Short name T453
Test name
Test status
Simulation time 312821236 ps
CPU time 4.71 seconds
Started Jun 22 07:02:19 PM PDT 24
Finished Jun 22 07:02:26 PM PDT 24
Peak memory 242456 kb
Host smart-19e7f290-e906-459c-94e1-d8a31425de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521705442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3521705442
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.1072548876
Short name T1060
Test name
Test status
Simulation time 809891230 ps
CPU time 19.82 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:37 PM PDT 24
Peak memory 242464 kb
Host smart-850a0c33-6610-408b-a6c8-01cd749529e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072548876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1072548876
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2678406962
Short name T37
Test name
Test status
Simulation time 194958601 ps
CPU time 3.98 seconds
Started Jun 22 07:02:14 PM PDT 24
Finished Jun 22 07:02:20 PM PDT 24
Peak memory 242232 kb
Host smart-d1dfc254-b1a8-4ec4-b837-ad1534a3a12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678406962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2678406962
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.3573572798
Short name T1049
Test name
Test status
Simulation time 2679617612 ps
CPU time 6.41 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242524 kb
Host smart-d1c8755d-1994-4ef4-b9de-f75efc1bb19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573572798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3573572798
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.3736571874
Short name T461
Test name
Test status
Simulation time 457413724 ps
CPU time 4.04 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:23 PM PDT 24
Peak memory 242276 kb
Host smart-9756abae-297a-4738-a215-59adb6dbe9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736571874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3736571874
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.2069416228
Short name T157
Test name
Test status
Simulation time 187210765 ps
CPU time 4.32 seconds
Started Jun 22 07:02:18 PM PDT 24
Finished Jun 22 07:02:25 PM PDT 24
Peak memory 242596 kb
Host smart-e7e64759-7d7b-4b53-846f-554802b4d834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069416228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2069416228
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.2838123784
Short name T178
Test name
Test status
Simulation time 127001506 ps
CPU time 4.4 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:23 PM PDT 24
Peak memory 242128 kb
Host smart-8c330dd0-4602-4d6f-8ca6-0ed670845cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838123784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.2838123784
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1492124930
Short name T259
Test name
Test status
Simulation time 225376195 ps
CPU time 6.49 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242076 kb
Host smart-3db911e7-9df7-4de2-8b35-047f263db4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492124930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1492124930
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4074354075
Short name T654
Test name
Test status
Simulation time 207037297 ps
CPU time 4.93 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242184 kb
Host smart-6ea82b72-37e8-4431-876b-ba401eeecd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074354075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4074354075
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.2973905479
Short name T545
Test name
Test status
Simulation time 2379684754 ps
CPU time 5.74 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:25 PM PDT 24
Peak memory 242724 kb
Host smart-549224a3-3758-4ec6-8313-c87d8ba502e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973905479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2973905479
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.3348654362
Short name T619
Test name
Test status
Simulation time 240727284 ps
CPU time 3.72 seconds
Started Jun 22 07:02:17 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242612 kb
Host smart-5392249e-5403-4bf1-a1c7-39884f1cb982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348654362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3348654362
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.765901571
Short name T1019
Test name
Test status
Simulation time 164084209 ps
CPU time 4.14 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242220 kb
Host smart-206e4fc2-e4e8-4715-92e7-c85f613dddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765901571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.765901571
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.387282411
Short name T535
Test name
Test status
Simulation time 320029440 ps
CPU time 9.1 seconds
Started Jun 22 07:02:14 PM PDT 24
Finished Jun 22 07:02:26 PM PDT 24
Peak memory 242216 kb
Host smart-2d020f7d-1a90-43a2-b47a-c5e01fd816af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387282411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.387282411
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.4044207910
Short name T646
Test name
Test status
Simulation time 2148735230 ps
CPU time 15.62 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:35 PM PDT 24
Peak memory 242272 kb
Host smart-cfa83738-4a09-4531-8d81-060210a37425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044207910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.4044207910
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.1591110159
Short name T438
Test name
Test status
Simulation time 335195817 ps
CPU time 4.49 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242164 kb
Host smart-da1a53f9-f4c6-4c05-93f9-8568b966de8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591110159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1591110159
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1441115426
Short name T629
Test name
Test status
Simulation time 425912395 ps
CPU time 5.43 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242024 kb
Host smart-8ff2b269-6285-412a-b48a-3cf53dd44f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441115426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1441115426
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.137836013
Short name T898
Test name
Test status
Simulation time 131128635 ps
CPU time 1.85 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:38 PM PDT 24
Peak memory 240736 kb
Host smart-1274dadb-4a96-49a2-b344-f426f527c91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137836013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.137836013
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.3861363614
Short name T471
Test name
Test status
Simulation time 639507572 ps
CPU time 21.07 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:49 PM PDT 24
Peak memory 242604 kb
Host smart-4ae6770a-6adf-4f34-bb96-400b640ed2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861363614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.3861363614
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.539518393
Short name T730
Test name
Test status
Simulation time 520489110 ps
CPU time 18.77 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:56 PM PDT 24
Peak memory 249036 kb
Host smart-56df92d1-3c76-4789-b160-7716f21b200c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539518393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.539518393
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.878502097
Short name T906
Test name
Test status
Simulation time 2660770729 ps
CPU time 23.39 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:58:01 PM PDT 24
Peak memory 242740 kb
Host smart-dd0d1403-7c0c-4a3a-a8a7-951c16a60d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878502097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.878502097
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.1901642050
Short name T534
Test name
Test status
Simulation time 390713788 ps
CPU time 6.75 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:43 PM PDT 24
Peak memory 242048 kb
Host smart-29a51944-5d8c-49a1-945c-8ff69c297937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901642050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1901642050
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.1015294124
Short name T99
Test name
Test status
Simulation time 1246031081 ps
CPU time 3.94 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:33 PM PDT 24
Peak memory 242080 kb
Host smart-c625b906-8ae5-4161-b488-6b99907702e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015294124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.1015294124
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.954873765
Short name T197
Test name
Test status
Simulation time 3236347981 ps
CPU time 30.43 seconds
Started Jun 22 06:57:37 PM PDT 24
Finished Jun 22 06:58:09 PM PDT 24
Peak memory 250544 kb
Host smart-c7481cc3-436b-4a95-a11a-032339986f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954873765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.954873765
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.1107253867
Short name T517
Test name
Test status
Simulation time 4777519314 ps
CPU time 17.02 seconds
Started Jun 22 06:57:38 PM PDT 24
Finished Jun 22 06:57:56 PM PDT 24
Peak memory 242332 kb
Host smart-7a2b1e0f-a490-4529-a352-ec05852d8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107253867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.1107253867
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.2336297285
Short name T889
Test name
Test status
Simulation time 221561987 ps
CPU time 4.57 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:33 PM PDT 24
Peak memory 242144 kb
Host smart-1eb2a489-4009-40aa-bdb7-931d9631aecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336297285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.2336297285
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.668271196
Short name T798
Test name
Test status
Simulation time 2979498139 ps
CPU time 24.34 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:52 PM PDT 24
Peak memory 242516 kb
Host smart-7e97eae6-8d76-466c-b592-a24308bdf44a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=668271196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.668271196
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.2442500295
Short name T365
Test name
Test status
Simulation time 254403513 ps
CPU time 5.71 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:43 PM PDT 24
Peak memory 242212 kb
Host smart-e3fea868-4607-47f0-bc4e-53f379112ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2442500295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.2442500295
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3573489058
Short name T247
Test name
Test status
Simulation time 41544277709 ps
CPU time 162.93 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 264380 kb
Host smart-769cf482-acd7-4a8f-b9e8-8c14dfab0ef2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573489058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3573489058
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3543752618
Short name T713
Test name
Test status
Simulation time 323272219 ps
CPU time 4.16 seconds
Started Jun 22 06:57:27 PM PDT 24
Finished Jun 22 06:57:32 PM PDT 24
Peak memory 242180 kb
Host smart-3f5937e4-7a20-45bd-9c1a-91d7b8962e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543752618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3543752618
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.602532137
Short name T128
Test name
Test status
Simulation time 28700940172 ps
CPU time 148.19 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 246104 kb
Host smart-722adc3e-dac2-43bc-b1e1-7f214c6dbdfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602532137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.602532137
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.213045652
Short name T419
Test name
Test status
Simulation time 324411614 ps
CPU time 4.3 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:40 PM PDT 24
Peak memory 242556 kb
Host smart-2076a94d-b9ca-4429-b8b5-64474b1b9196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213045652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.213045652
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.901292456
Short name T395
Test name
Test status
Simulation time 71742166 ps
CPU time 2.11 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 240908 kb
Host smart-11976af4-7dd6-461e-9396-50af915ce863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901292456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.901292456
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2160575668
Short name T791
Test name
Test status
Simulation time 2578483557 ps
CPU time 24.54 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 242332 kb
Host smart-c71912f1-b3bf-41b1-b8ff-945880901640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160575668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2160575668
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.650806167
Short name T828
Test name
Test status
Simulation time 1953457188 ps
CPU time 30.68 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:51 PM PDT 24
Peak memory 244484 kb
Host smart-76f51abb-27d5-410a-941d-80b5509d8ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650806167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.650806167
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.4088069464
Short name T1017
Test name
Test status
Simulation time 1013299755 ps
CPU time 30.43 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 242924 kb
Host smart-bab3d9f4-06d6-4513-85ad-6ab9454bb685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088069464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.4088069464
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.3595419123
Short name T697
Test name
Test status
Simulation time 469443248 ps
CPU time 4.35 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242200 kb
Host smart-d8bf724a-d042-47aa-b597-18c8d2ed302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595419123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.3595419123
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3975449834
Short name T531
Test name
Test status
Simulation time 645859139 ps
CPU time 9.27 seconds
Started Jun 22 06:59:08 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242828 kb
Host smart-f849602c-5201-4fa8-b0e9-88409fa47e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975449834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3975449834
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.3813192780
Short name T672
Test name
Test status
Simulation time 2620567532 ps
CPU time 42.04 seconds
Started Jun 22 06:59:10 PM PDT 24
Finished Jun 22 06:59:57 PM PDT 24
Peak memory 242340 kb
Host smart-34ff57c2-d584-4542-8032-eba674695cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813192780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3813192780
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1808430982
Short name T136
Test name
Test status
Simulation time 180594416 ps
CPU time 6.31 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:25 PM PDT 24
Peak memory 242388 kb
Host smart-4579805e-e068-4af5-ba30-8f5efa882594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808430982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1808430982
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.2770953130
Short name T663
Test name
Test status
Simulation time 142118775 ps
CPU time 3.77 seconds
Started Jun 22 06:59:10 PM PDT 24
Finished Jun 22 06:59:19 PM PDT 24
Peak memory 242260 kb
Host smart-98126a5c-786c-4234-bf59-b378e539d9f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770953130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2770953130
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.1903671285
Short name T1128
Test name
Test status
Simulation time 204193892 ps
CPU time 5.24 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:25 PM PDT 24
Peak memory 242232 kb
Host smart-0e0f6965-6bf6-433d-b7f5-d1f6a02e9dde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903671285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1903671285
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.2208726229
Short name T431
Test name
Test status
Simulation time 1362345563 ps
CPU time 11.74 seconds
Started Jun 22 06:59:09 PM PDT 24
Finished Jun 22 06:59:25 PM PDT 24
Peak memory 242212 kb
Host smart-4920494a-c0bc-448f-b7f2-8dc890b6ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208726229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2208726229
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.380520719
Short name T967
Test name
Test status
Simulation time 1697853431 ps
CPU time 27.18 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:47 PM PDT 24
Peak memory 242472 kb
Host smart-0ef49e86-074e-4654-933b-62df23e19d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380520719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.380520719
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.3887666622
Short name T172
Test name
Test status
Simulation time 439565948 ps
CPU time 4.74 seconds
Started Jun 22 07:02:14 PM PDT 24
Finished Jun 22 07:02:22 PM PDT 24
Peak memory 242176 kb
Host smart-2640cb45-1a8a-48c7-b17c-87fdf0a12c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887666622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.3887666622
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1390131073
Short name T1058
Test name
Test status
Simulation time 495855653 ps
CPU time 3.93 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:23 PM PDT 24
Peak memory 242144 kb
Host smart-71ad7dcb-0f48-4e69-ad76-a88b870a3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390131073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1390131073
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.938916733
Short name T596
Test name
Test status
Simulation time 440249816 ps
CPU time 5.07 seconds
Started Jun 22 07:02:16 PM PDT 24
Finished Jun 22 07:02:24 PM PDT 24
Peak memory 242300 kb
Host smart-dbaa8e0a-0b5b-4b36-8d79-a9fdbded77ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938916733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.938916733
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.197767459
Short name T867
Test name
Test status
Simulation time 259039870 ps
CPU time 3.34 seconds
Started Jun 22 07:02:15 PM PDT 24
Finished Jun 22 07:02:20 PM PDT 24
Peak memory 242304 kb
Host smart-56dc3494-10a8-416e-914c-0910d4dbfbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197767459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.197767459
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2359358542
Short name T688
Test name
Test status
Simulation time 469005830 ps
CPU time 4.1 seconds
Started Jun 22 07:02:24 PM PDT 24
Finished Jun 22 07:02:31 PM PDT 24
Peak memory 242408 kb
Host smart-bdbaa6f9-e93d-402d-9e6a-11897e0ad57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359358542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2359358542
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.978260786
Short name T1062
Test name
Test status
Simulation time 134950051 ps
CPU time 3.97 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242636 kb
Host smart-13eadb95-847d-4b7f-aeb3-67b435039135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978260786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.978260786
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2088656346
Short name T856
Test name
Test status
Simulation time 2647592174 ps
CPU time 5.65 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:36 PM PDT 24
Peak memory 242376 kb
Host smart-8b79bee2-71b5-4872-ae0e-57ab8d9bc20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088656346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2088656346
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.999027796
Short name T848
Test name
Test status
Simulation time 110356281 ps
CPU time 3.46 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:28 PM PDT 24
Peak memory 242304 kb
Host smart-9e8d477e-2595-4ca7-93d2-e0693b198ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999027796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.999027796
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2891884656
Short name T846
Test name
Test status
Simulation time 1702877135 ps
CPU time 5.66 seconds
Started Jun 22 07:02:24 PM PDT 24
Finished Jun 22 07:02:31 PM PDT 24
Peak memory 242588 kb
Host smart-690555cd-c919-488a-b4dc-efa1abb31210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891884656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2891884656
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.584142863
Short name T1116
Test name
Test status
Simulation time 488263762 ps
CPU time 2.79 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:26 PM PDT 24
Peak memory 240904 kb
Host smart-26af7ac1-8014-4fbb-8ac7-3ef651d6e416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584142863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.584142863
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1514763709
Short name T111
Test name
Test status
Simulation time 1059889440 ps
CPU time 6.37 seconds
Started Jun 22 06:59:11 PM PDT 24
Finished Jun 22 06:59:22 PM PDT 24
Peak memory 242420 kb
Host smart-c25b8f39-8c59-4cfd-b4a3-e0b1cdd05608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514763709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1514763709
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.2703598315
Short name T858
Test name
Test status
Simulation time 242917087 ps
CPU time 11.22 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242832 kb
Host smart-f01e4f29-1642-400e-abad-feef8bea1cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703598315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2703598315
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1678383285
Short name T1072
Test name
Test status
Simulation time 17959321865 ps
CPU time 32.02 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:49 PM PDT 24
Peak memory 243876 kb
Host smart-84bbee24-9c9e-4d25-9abb-4c06b50383fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678383285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1678383285
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.67034842
Short name T81
Test name
Test status
Simulation time 144438852 ps
CPU time 3.95 seconds
Started Jun 22 06:59:12 PM PDT 24
Finished Jun 22 06:59:21 PM PDT 24
Peak memory 242392 kb
Host smart-4049a0ae-9ab8-4282-aeee-6d9e7fa8ecf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67034842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.67034842
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2421455581
Short name T952
Test name
Test status
Simulation time 243543683 ps
CPU time 9.83 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:31 PM PDT 24
Peak memory 242264 kb
Host smart-279e18b0-5cbe-4c5c-8516-05b1697286eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421455581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2421455581
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.413668365
Short name T586
Test name
Test status
Simulation time 943405115 ps
CPU time 24.94 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:47 PM PDT 24
Peak memory 242768 kb
Host smart-ee789a49-3fbc-49ff-b9e1-2ee4ea51dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413668365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.413668365
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.1692734686
Short name T633
Test name
Test status
Simulation time 597002221 ps
CPU time 19.19 seconds
Started Jun 22 06:59:13 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 242664 kb
Host smart-2006fdf1-46ad-4341-a6d7-7b1d3278ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692734686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1692734686
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.558498675
Short name T1152
Test name
Test status
Simulation time 1258130139 ps
CPU time 12.55 seconds
Started Jun 22 06:59:11 PM PDT 24
Finished Jun 22 06:59:28 PM PDT 24
Peak memory 242156 kb
Host smart-96027169-8e36-4f05-805c-e240d2618bdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=558498675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.558498675
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1526980964
Short name T1010
Test name
Test status
Simulation time 333015016 ps
CPU time 10.54 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242184 kb
Host smart-ada95cf2-84bb-4327-81bf-9a939e4c8e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1526980964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1526980964
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.2863466969
Short name T818
Test name
Test status
Simulation time 395194559 ps
CPU time 9.23 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:29 PM PDT 24
Peak memory 242760 kb
Host smart-69390047-7422-4c92-91e7-861d9823205c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863466969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2863466969
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2960423833
Short name T968
Test name
Test status
Simulation time 12522571967 ps
CPU time 70.04 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 07:00:32 PM PDT 24
Peak memory 249048 kb
Host smart-79ff8812-379c-46c1-8bf5-e092ce2d05d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960423833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2960423833
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2500981106
Short name T621
Test name
Test status
Simulation time 452783557683 ps
CPU time 3070.94 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 07:50:33 PM PDT 24
Peak memory 446712 kb
Host smart-b9c2908d-a37d-4976-a452-efc63164bbed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500981106 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2500981106
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3220889675
Short name T779
Test name
Test status
Simulation time 4662276923 ps
CPU time 12.22 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242668 kb
Host smart-ef2d173f-1f29-4afe-9fee-4a15ed2a0dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220889675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3220889675
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.2600413605
Short name T1096
Test name
Test status
Simulation time 176043523 ps
CPU time 5.11 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:35 PM PDT 24
Peak memory 242224 kb
Host smart-f50983d8-c6dc-42bb-b55b-b31c9773dae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600413605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.2600413605
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.563042800
Short name T141
Test name
Test status
Simulation time 256584587 ps
CPU time 4.15 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242252 kb
Host smart-fd3e2e19-a641-4be3-9a21-8824d37e4a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563042800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.563042800
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.744631748
Short name T569
Test name
Test status
Simulation time 211092877 ps
CPU time 3.48 seconds
Started Jun 22 07:02:26 PM PDT 24
Finished Jun 22 07:02:32 PM PDT 24
Peak memory 242312 kb
Host smart-67869303-baae-4714-8c4b-8268006574af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744631748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.744631748
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.1509594207
Short name T477
Test name
Test status
Simulation time 121111998 ps
CPU time 3.98 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:34 PM PDT 24
Peak memory 242192 kb
Host smart-1ceb0a54-b685-42b8-8367-c7a6eca5306d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509594207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1509594207
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.4254572322
Short name T408
Test name
Test status
Simulation time 92439063 ps
CPU time 3.93 seconds
Started Jun 22 07:02:25 PM PDT 24
Finished Jun 22 07:02:31 PM PDT 24
Peak memory 242412 kb
Host smart-9b7c9d8e-612a-45ca-af8c-fcff527f46fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254572322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.4254572322
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.3863809506
Short name T1045
Test name
Test status
Simulation time 166182270 ps
CPU time 3.33 seconds
Started Jun 22 07:02:24 PM PDT 24
Finished Jun 22 07:02:30 PM PDT 24
Peak memory 242552 kb
Host smart-dd72eb83-3da8-4e6a-b606-36335917a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863809506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3863809506
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1016925254
Short name T212
Test name
Test status
Simulation time 145458291 ps
CPU time 4.2 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242332 kb
Host smart-ed63e7f6-245c-4842-8cf8-dfc2d1789efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016925254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1016925254
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.674219005
Short name T905
Test name
Test status
Simulation time 201951470 ps
CPU time 4.56 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:30 PM PDT 24
Peak memory 242640 kb
Host smart-36e67a2d-1389-45f4-a9d5-ebc765b8caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674219005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.674219005
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.3427776258
Short name T861
Test name
Test status
Simulation time 1425156910 ps
CPU time 4.61 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:34 PM PDT 24
Peak memory 242212 kb
Host smart-d30ea3ba-f9b4-4cab-bd67-b56b89c09e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427776258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3427776258
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2988007381
Short name T118
Test name
Test status
Simulation time 234788500 ps
CPU time 3.45 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:34 PM PDT 24
Peak memory 242040 kb
Host smart-7582b3bb-d210-4ead-b714-9658c3ae1b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988007381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2988007381
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1113970753
Short name T958
Test name
Test status
Simulation time 152801486 ps
CPU time 2.74 seconds
Started Jun 22 06:59:18 PM PDT 24
Finished Jun 22 06:59:27 PM PDT 24
Peak memory 241080 kb
Host smart-fe230562-2ee1-414a-acb3-0230182e681d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113970753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1113970753
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.1853086669
Short name T30
Test name
Test status
Simulation time 5634250481 ps
CPU time 9.02 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:31 PM PDT 24
Peak memory 242452 kb
Host smart-7bb7818f-90bb-497c-92f9-bfbbfff78415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853086669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1853086669
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.4030423379
Short name T485
Test name
Test status
Simulation time 22512990323 ps
CPU time 68.17 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 07:00:30 PM PDT 24
Peak memory 253604 kb
Host smart-a9fb826d-3591-47f8-a12e-2602e2b76154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030423379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.4030423379
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2549434447
Short name T1074
Test name
Test status
Simulation time 1785367627 ps
CPU time 26.29 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:48 PM PDT 24
Peak memory 242148 kb
Host smart-06159844-a5dd-4ae6-97a0-281ff2bb6532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549434447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2549434447
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3924132620
Short name T598
Test name
Test status
Simulation time 229740920 ps
CPU time 4.57 seconds
Started Jun 22 06:59:14 PM PDT 24
Finished Jun 22 06:59:25 PM PDT 24
Peak memory 242088 kb
Host smart-781a62e7-9c85-411d-8ba0-381181d10b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924132620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3924132620
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3692305340
Short name T659
Test name
Test status
Simulation time 978680262 ps
CPU time 19.25 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:41 PM PDT 24
Peak memory 242260 kb
Host smart-6b9a58b3-3136-4be0-9d92-227cea2e80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692305340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3692305340
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.1272607204
Short name T1147
Test name
Test status
Simulation time 237875538 ps
CPU time 6.89 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 242104 kb
Host smart-eebab38a-8e6b-4582-80ef-40ce0f19862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272607204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.1272607204
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.1354489886
Short name T101
Test name
Test status
Simulation time 11456650228 ps
CPU time 35.37 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:57 PM PDT 24
Peak memory 242252 kb
Host smart-06439fef-f041-4db2-a473-f98e9f266653
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354489886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.1354489886
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2168551236
Short name T712
Test name
Test status
Simulation time 1259686628 ps
CPU time 10.49 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242520 kb
Host smart-21e59b2e-5454-4927-8e82-85be70666900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168551236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2168551236
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2586468088
Short name T1122
Test name
Test status
Simulation time 1499975443 ps
CPU time 16.46 seconds
Started Jun 22 06:59:17 PM PDT 24
Finished Jun 22 06:59:40 PM PDT 24
Peak memory 248992 kb
Host smart-11963435-3aa6-4316-9048-8f372fc2acca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586468088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2586468088
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.168846596
Short name T760
Test name
Test status
Simulation time 1232215458 ps
CPU time 22.42 seconds
Started Jun 22 06:59:15 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 242544 kb
Host smart-b7116bbd-e0c7-4cfa-8cee-67c535eed3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168846596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.168846596
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.2133424963
Short name T964
Test name
Test status
Simulation time 1794105883 ps
CPU time 4.96 seconds
Started Jun 22 07:02:25 PM PDT 24
Finished Jun 22 07:02:33 PM PDT 24
Peak memory 242300 kb
Host smart-fdb16c13-9217-4278-afe7-8e0ee5a26cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133424963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2133424963
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.197584701
Short name T507
Test name
Test status
Simulation time 210105706 ps
CPU time 3.43 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:28 PM PDT 24
Peak memory 242312 kb
Host smart-3ecad863-8d0e-423d-8bc9-e1540c6da380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197584701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.197584701
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.1948302089
Short name T695
Test name
Test status
Simulation time 110180797 ps
CPU time 4.1 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:35 PM PDT 24
Peak memory 242208 kb
Host smart-e08ead78-a780-4477-ab50-e059a362c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948302089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.1948302089
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.3263521990
Short name T1094
Test name
Test status
Simulation time 253274872 ps
CPU time 3.57 seconds
Started Jun 22 07:02:24 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242156 kb
Host smart-045d7c2b-1db5-4f34-a013-5b5156a8c24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263521990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3263521990
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.40967170
Short name T637
Test name
Test status
Simulation time 166721676 ps
CPU time 3.88 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242356 kb
Host smart-e0eb28bd-4403-4c0f-b429-64804096e0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40967170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.40967170
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2360608981
Short name T173
Test name
Test status
Simulation time 2736432312 ps
CPU time 5.16 seconds
Started Jun 22 07:02:25 PM PDT 24
Finished Jun 22 07:02:32 PM PDT 24
Peak memory 242416 kb
Host smart-ab97c70a-e4fa-416b-9bb3-907a8bc05a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360608981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2360608981
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.263867363
Short name T467
Test name
Test status
Simulation time 1331759076 ps
CPU time 3.9 seconds
Started Jun 22 07:02:22 PM PDT 24
Finished Jun 22 07:02:28 PM PDT 24
Peak memory 242272 kb
Host smart-f0c71ad5-258d-4732-bda6-e4e240a5ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263867363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.263867363
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3306158073
Short name T826
Test name
Test status
Simulation time 1774601402 ps
CPU time 4.17 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:30 PM PDT 24
Peak memory 242220 kb
Host smart-49c746ce-f55b-4504-872d-04fcefbacc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306158073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3306158073
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1965676865
Short name T117
Test name
Test status
Simulation time 2077611435 ps
CPU time 5.95 seconds
Started Jun 22 07:02:26 PM PDT 24
Finished Jun 22 07:02:36 PM PDT 24
Peak memory 242340 kb
Host smart-704baada-f569-4156-93f4-638c01a44819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965676865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1965676865
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1344678530
Short name T748
Test name
Test status
Simulation time 152881395 ps
CPU time 2.18 seconds
Started Jun 22 06:59:18 PM PDT 24
Finished Jun 22 06:59:27 PM PDT 24
Peak memory 241048 kb
Host smart-d0358966-cdc9-4e16-8636-f764830e2e2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344678530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1344678530
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.690975044
Short name T40
Test name
Test status
Simulation time 2495290822 ps
CPU time 13.49 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:36 PM PDT 24
Peak memory 242380 kb
Host smart-4e635650-9afe-4631-bcfb-7857ee7d21b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690975044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.690975044
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3641129264
Short name T536
Test name
Test status
Simulation time 323882520 ps
CPU time 8.58 seconds
Started Jun 22 06:59:20 PM PDT 24
Finished Jun 22 06:59:34 PM PDT 24
Peak memory 242308 kb
Host smart-47073105-eb62-4459-a3d5-c3b5204f1123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641129264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3641129264
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1997581398
Short name T159
Test name
Test status
Simulation time 552193323 ps
CPU time 10.5 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:38 PM PDT 24
Peak memory 242624 kb
Host smart-cf994903-812d-403e-999e-dbc9b6e668c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997581398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1997581398
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1032661654
Short name T429
Test name
Test status
Simulation time 311340789 ps
CPU time 4.08 seconds
Started Jun 22 06:59:18 PM PDT 24
Finished Jun 22 06:59:28 PM PDT 24
Peak memory 242484 kb
Host smart-69450460-4144-47d1-adb0-6c56519682e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032661654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1032661654
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3949310507
Short name T953
Test name
Test status
Simulation time 1060861298 ps
CPU time 13.75 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 242556 kb
Host smart-afc7a27d-b596-4db6-96d1-9e7e004f5b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949310507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3949310507
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.3840967835
Short name T186
Test name
Test status
Simulation time 322003158 ps
CPU time 11.29 seconds
Started Jun 22 06:59:19 PM PDT 24
Finished Jun 22 06:59:36 PM PDT 24
Peak memory 249036 kb
Host smart-e14b6a0e-0e7f-4945-a81c-abf33df4d613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840967835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3840967835
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.681501348
Short name T1064
Test name
Test status
Simulation time 1971838498 ps
CPU time 9.3 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 242544 kb
Host smart-070e2c13-56bd-4d47-b854-e5f34d238981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681501348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.681501348
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.3494500294
Short name T1134
Test name
Test status
Simulation time 1355330204 ps
CPU time 16.76 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 242244 kb
Host smart-35f63e1d-08a3-43f4-b37d-79acec9a4a5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494500294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3494500294
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.1397274523
Short name T371
Test name
Test status
Simulation time 2447598200 ps
CPU time 6.45 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:29 PM PDT 24
Peak memory 242300 kb
Host smart-f8124391-3bea-4c34-b31e-8cdff7e33db6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397274523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1397274523
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.2369020099
Short name T559
Test name
Test status
Simulation time 5264133827 ps
CPU time 9.81 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:33 PM PDT 24
Peak memory 242608 kb
Host smart-438ac437-337b-4d7f-8d29-a96c87b0da19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369020099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2369020099
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.3635932360
Short name T482
Test name
Test status
Simulation time 2673843890 ps
CPU time 52.78 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 243656 kb
Host smart-01f23c05-aba1-4357-9d58-7c0788e3732c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635932360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.3635932360
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.937410147
Short name T701
Test name
Test status
Simulation time 2801771394 ps
CPU time 23.48 seconds
Started Jun 22 06:59:20 PM PDT 24
Finished Jun 22 06:59:49 PM PDT 24
Peak memory 249148 kb
Host smart-344dce5a-ef73-40ce-806d-a331f9458c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937410147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.937410147
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.4237281342
Short name T612
Test name
Test status
Simulation time 449366676 ps
CPU time 5.76 seconds
Started Jun 22 07:02:27 PM PDT 24
Finished Jun 22 07:02:36 PM PDT 24
Peak memory 242212 kb
Host smart-f8f51531-e7a7-487e-8f27-5b27d4e45f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237281342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.4237281342
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3749455551
Short name T807
Test name
Test status
Simulation time 172182756 ps
CPU time 4.57 seconds
Started Jun 22 07:02:25 PM PDT 24
Finished Jun 22 07:02:33 PM PDT 24
Peak memory 242152 kb
Host smart-465abe30-d41b-4b1a-95a8-20972f4d4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749455551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3749455551
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2157715079
Short name T882
Test name
Test status
Simulation time 250433817 ps
CPU time 3.78 seconds
Started Jun 22 07:02:23 PM PDT 24
Finished Jun 22 07:02:29 PM PDT 24
Peak memory 242288 kb
Host smart-0cb84761-4dc4-48ad-8253-68b44f967a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157715079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2157715079
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.750798656
Short name T630
Test name
Test status
Simulation time 434064070 ps
CPU time 5.5 seconds
Started Jun 22 07:02:25 PM PDT 24
Finished Jun 22 07:02:33 PM PDT 24
Peak memory 242160 kb
Host smart-7e40ac21-27d1-4717-9c4c-4723dfe0de1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750798656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.750798656
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.2025893213
Short name T755
Test name
Test status
Simulation time 1904077978 ps
CPU time 5.32 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242188 kb
Host smart-d292032d-93a3-467d-ae5a-d5496d581385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025893213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2025893213
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.1601482811
Short name T650
Test name
Test status
Simulation time 237395171 ps
CPU time 3.89 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242696 kb
Host smart-13b03edd-783c-4b9c-9b80-83a94d851330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601482811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1601482811
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.492445434
Short name T34
Test name
Test status
Simulation time 188087764 ps
CPU time 5.27 seconds
Started Jun 22 07:02:31 PM PDT 24
Finished Jun 22 07:02:38 PM PDT 24
Peak memory 242248 kb
Host smart-bff5907d-6638-4bb1-b09a-9d3193be3fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492445434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.492445434
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.1235652642
Short name T131
Test name
Test status
Simulation time 269634205 ps
CPU time 4.61 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242600 kb
Host smart-de25070b-59aa-4f28-a6e7-e7984aa63ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235652642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1235652642
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.4252204946
Short name T590
Test name
Test status
Simulation time 749012003 ps
CPU time 2.18 seconds
Started Jun 22 06:59:23 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 240676 kb
Host smart-74095c7f-cc00-4371-abf3-6affb96d6a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252204946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.4252204946
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1433302136
Short name T89
Test name
Test status
Simulation time 598192539 ps
CPU time 13.31 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 242564 kb
Host smart-1d26a559-c6c9-4236-8d5e-565b39195019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433302136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1433302136
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2337759967
Short name T1033
Test name
Test status
Simulation time 2240919181 ps
CPU time 8.32 seconds
Started Jun 22 06:59:22 PM PDT 24
Finished Jun 22 06:59:35 PM PDT 24
Peak memory 242432 kb
Host smart-f7e25e3e-f5d4-46b7-8390-77df072a1a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337759967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2337759967
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.577307916
Short name T1111
Test name
Test status
Simulation time 388755965 ps
CPU time 6.66 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 242536 kb
Host smart-fe3cb8c2-596c-4142-aa38-57706ab59250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577307916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.577307916
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.1909512456
Short name T1139
Test name
Test status
Simulation time 346313359 ps
CPU time 3.14 seconds
Started Jun 22 06:59:17 PM PDT 24
Finished Jun 22 06:59:27 PM PDT 24
Peak memory 242344 kb
Host smart-4c211b66-7c8d-4f65-b8e4-a78ea9d8c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909512456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1909512456
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3157135125
Short name T142
Test name
Test status
Simulation time 2693937344 ps
CPU time 6.23 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:37 PM PDT 24
Peak memory 243136 kb
Host smart-c2e90970-0c38-4e16-9398-01778eab7109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157135125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3157135125
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3223283771
Short name T589
Test name
Test status
Simulation time 356074754 ps
CPU time 16.67 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:47 PM PDT 24
Peak memory 242236 kb
Host smart-02b88992-52d4-45eb-862b-dc0065aa1465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223283771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3223283771
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.1120487531
Short name T494
Test name
Test status
Simulation time 336215987 ps
CPU time 8.55 seconds
Started Jun 22 06:59:18 PM PDT 24
Finished Jun 22 06:59:33 PM PDT 24
Peak memory 242488 kb
Host smart-aa5758eb-d6f8-4612-afef-31b0f9fe1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120487531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1120487531
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.4016334031
Short name T443
Test name
Test status
Simulation time 14494111246 ps
CPU time 43.58 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 07:00:06 PM PDT 24
Peak memory 242784 kb
Host smart-bdf6a449-b938-4591-89be-b8dd8e6bcc1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4016334031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.4016334031
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2864383397
Short name T272
Test name
Test status
Simulation time 150234126 ps
CPU time 5.21 seconds
Started Jun 22 06:59:23 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242256 kb
Host smart-fe11f1c7-c078-4d11-b4c2-32cd59719132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864383397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2864383397
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.1272378257
Short name T758
Test name
Test status
Simulation time 288062076 ps
CPU time 6.66 seconds
Started Jun 22 06:59:16 PM PDT 24
Finished Jun 22 06:59:30 PM PDT 24
Peak memory 242028 kb
Host smart-d5451e36-b7a9-46ad-9aab-8ebcba1df55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272378257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1272378257
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.274626720
Short name T303
Test name
Test status
Simulation time 1102237339210 ps
CPU time 2470.65 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 07:40:39 PM PDT 24
Peak memory 363624 kb
Host smart-5f526788-010c-4371-88ac-8ef2eb518957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274626720 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.274626720
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.361281457
Short name T1077
Test name
Test status
Simulation time 13135140611 ps
CPU time 41.99 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 243300 kb
Host smart-27bb4838-85c6-4a90-9532-8f5099ac882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361281457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.361281457
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3739080249
Short name T67
Test name
Test status
Simulation time 2087012022 ps
CPU time 8.3 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:50 PM PDT 24
Peak memory 242064 kb
Host smart-8ccbb0af-f4c8-4886-98d4-1a2b0165db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739080249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3739080249
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.2279230227
Short name T92
Test name
Test status
Simulation time 125909051 ps
CPU time 4.48 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242232 kb
Host smart-a0bb91a5-9f7f-41aa-8fe2-2c4db1194d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279230227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2279230227
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2297221579
Short name T639
Test name
Test status
Simulation time 139801631 ps
CPU time 3.69 seconds
Started Jun 22 07:02:34 PM PDT 24
Finished Jun 22 07:02:40 PM PDT 24
Peak memory 242060 kb
Host smart-41b13e82-c296-49f6-9398-0327e1bb2d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297221579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2297221579
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.3830580404
Short name T820
Test name
Test status
Simulation time 597697023 ps
CPU time 4.95 seconds
Started Jun 22 07:02:36 PM PDT 24
Finished Jun 22 07:02:42 PM PDT 24
Peak memory 242116 kb
Host smart-d5c67e74-ba8e-48b0-bdc8-702f031bee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830580404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.3830580404
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3278850331
Short name T54
Test name
Test status
Simulation time 176515898 ps
CPU time 4.63 seconds
Started Jun 22 07:02:37 PM PDT 24
Finished Jun 22 07:02:43 PM PDT 24
Peak memory 242100 kb
Host smart-17c64813-5bdf-4b50-aefb-4cb76ee69e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278850331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3278850331
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.2198056584
Short name T88
Test name
Test status
Simulation time 302059142 ps
CPU time 4.33 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:40 PM PDT 24
Peak memory 242304 kb
Host smart-d20bb215-ff5a-4875-85fb-a357f0476a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198056584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2198056584
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.946415493
Short name T460
Test name
Test status
Simulation time 381350325 ps
CPU time 3.93 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:46 PM PDT 24
Peak memory 242356 kb
Host smart-a41454d9-b8d0-426d-83cf-0243abe7c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946415493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.946415493
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2999384146
Short name T864
Test name
Test status
Simulation time 355163960 ps
CPU time 3.19 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:38 PM PDT 24
Peak memory 242300 kb
Host smart-7e6c86b6-7e0a-4fb4-9451-8ec4954f7113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999384146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2999384146
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.672925479
Short name T504
Test name
Test status
Simulation time 479102295 ps
CPU time 5.01 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242436 kb
Host smart-1ce5146a-89cc-4eab-b52f-a9ed37f92ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672925479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.672925479
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3854795836
Short name T440
Test name
Test status
Simulation time 320590248 ps
CPU time 3.43 seconds
Started Jun 22 07:02:36 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242420 kb
Host smart-51b2249a-171b-4ff1-bcf7-7fa7a6e1cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854795836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3854795836
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.474809855
Short name T400
Test name
Test status
Simulation time 87316911 ps
CPU time 1.79 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:35 PM PDT 24
Peak memory 241072 kb
Host smart-2587e58a-c40f-474c-8c98-c3b822f6cfe8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474809855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.474809855
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2366142720
Short name T75
Test name
Test status
Simulation time 448509427 ps
CPU time 16.41 seconds
Started Jun 22 06:59:23 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 243296 kb
Host smart-ed0ae78a-7181-4f14-8a2b-3c2ba1f940f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366142720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2366142720
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.1893321534
Short name T719
Test name
Test status
Simulation time 3072363470 ps
CPU time 9.15 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:40 PM PDT 24
Peak memory 242260 kb
Host smart-91a9d8b0-d67d-4385-a72f-cf9342983122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893321534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.1893321534
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4130221389
Short name T707
Test name
Test status
Simulation time 2246397392 ps
CPU time 29.25 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 07:00:00 PM PDT 24
Peak memory 242596 kb
Host smart-add64033-06f9-45ea-b325-1bbe051b54c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130221389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4130221389
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3407720667
Short name T685
Test name
Test status
Simulation time 608225470 ps
CPU time 4.61 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:33 PM PDT 24
Peak memory 242328 kb
Host smart-2982a9bc-a2ca-4405-b687-40e88f462c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407720667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3407720667
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3440828337
Short name T1000
Test name
Test status
Simulation time 902407143 ps
CPU time 20.18 seconds
Started Jun 22 06:59:26 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 246488 kb
Host smart-56adda73-9ec7-4f0e-af57-daa11e381f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440828337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3440828337
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.160983334
Short name T989
Test name
Test status
Simulation time 1491187774 ps
CPU time 38.31 seconds
Started Jun 22 06:59:25 PM PDT 24
Finished Jun 22 07:00:07 PM PDT 24
Peak memory 243388 kb
Host smart-83fad725-ac93-4f39-9e7e-5fb4ad094cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160983334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.160983334
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.450576853
Short name T1087
Test name
Test status
Simulation time 106561829 ps
CPU time 4.14 seconds
Started Jun 22 06:59:24 PM PDT 24
Finished Jun 22 06:59:32 PM PDT 24
Peak memory 242604 kb
Host smart-9814b851-67b4-4f4e-b824-409a49ecb22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450576853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.450576853
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2629059341
Short name T764
Test name
Test status
Simulation time 728241802 ps
CPU time 20.11 seconds
Started Jun 22 06:59:27 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 242552 kb
Host smart-68e43a9b-c87f-4e85-a530-1f4d1f0ad4f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2629059341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2629059341
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.2928486084
Short name T286
Test name
Test status
Simulation time 261535888 ps
CPU time 6.45 seconds
Started Jun 22 06:59:23 PM PDT 24
Finished Jun 22 06:59:34 PM PDT 24
Peak memory 242132 kb
Host smart-e5f3bd7b-f1bc-44d8-8940-1fcbeb5b2957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928486084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2928486084
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.2313622992
Short name T737
Test name
Test status
Simulation time 15958263958 ps
CPU time 22.15 seconds
Started Jun 22 06:59:26 PM PDT 24
Finished Jun 22 06:59:51 PM PDT 24
Peak memory 242612 kb
Host smart-b0e83b46-99b9-41af-9185-034b4065f316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313622992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2313622992
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.1671996623
Short name T576
Test name
Test status
Simulation time 462209651 ps
CPU time 4.81 seconds
Started Jun 22 07:02:38 PM PDT 24
Finished Jun 22 07:02:44 PM PDT 24
Peak memory 242040 kb
Host smart-80009ecd-1971-45d7-8474-1c84d317ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671996623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.1671996623
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3795426710
Short name T994
Test name
Test status
Simulation time 556410435 ps
CPU time 3.81 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:37 PM PDT 24
Peak memory 242180 kb
Host smart-d6370660-2f6b-42e1-a72c-bd6f209eaf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795426710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3795426710
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.2333915555
Short name T1052
Test name
Test status
Simulation time 124849905 ps
CPU time 4.97 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242516 kb
Host smart-21a6e0d9-ebe4-4935-aed0-1cfb8ed58d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333915555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.2333915555
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1980605231
Short name T752
Test name
Test status
Simulation time 462237492 ps
CPU time 5.08 seconds
Started Jun 22 07:02:34 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242408 kb
Host smart-d2e3cc1e-ffa8-4319-b714-c8bafb00f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980605231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1980605231
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.4256008893
Short name T809
Test name
Test status
Simulation time 551664581 ps
CPU time 3.89 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242440 kb
Host smart-aeb7ec05-8481-4c76-a967-e06f693e41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256008893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.4256008893
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.1497704092
Short name T145
Test name
Test status
Simulation time 102241156 ps
CPU time 3.78 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:40 PM PDT 24
Peak memory 242320 kb
Host smart-9f5b06c5-ddea-4c01-8c72-915250257253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497704092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1497704092
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.1497578194
Short name T423
Test name
Test status
Simulation time 337334647 ps
CPU time 5.68 seconds
Started Jun 22 07:02:31 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242136 kb
Host smart-a95f834d-309f-4c3a-9b2b-e834617f629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497578194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.1497578194
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.889776430
Short name T1073
Test name
Test status
Simulation time 558114036 ps
CPU time 4.27 seconds
Started Jun 22 07:02:37 PM PDT 24
Finished Jun 22 07:02:42 PM PDT 24
Peak memory 242628 kb
Host smart-0f08af27-97ec-43d9-b754-0bcf5a98816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889776430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.889776430
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.1208193007
Short name T1148
Test name
Test status
Simulation time 192657852 ps
CPU time 3.67 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242164 kb
Host smart-eab855dd-c81d-4355-9cf9-172317dae5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208193007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.1208193007
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1193814850
Short name T885
Test name
Test status
Simulation time 86542168 ps
CPU time 1.93 seconds
Started Jun 22 06:59:30 PM PDT 24
Finished Jun 22 06:59:35 PM PDT 24
Peak memory 240720 kb
Host smart-5392e901-1f3f-4b0d-ba9a-e6e24fb1a30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193814850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1193814850
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.1006128808
Short name T405
Test name
Test status
Simulation time 352604298 ps
CPU time 9.19 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 06:59:52 PM PDT 24
Peak memory 242600 kb
Host smart-9416f936-ba6b-48a3-955e-affcd06bd650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006128808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.1006128808
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.2084354956
Short name T823
Test name
Test status
Simulation time 1037350237 ps
CPU time 20.09 seconds
Started Jun 22 06:59:42 PM PDT 24
Finished Jun 22 07:00:06 PM PDT 24
Peak memory 242312 kb
Host smart-bad4705f-beab-4ed4-8ea5-fb0251203bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084354956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2084354956
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2703354486
Short name T143
Test name
Test status
Simulation time 212090663 ps
CPU time 4.09 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:38 PM PDT 24
Peak memory 242076 kb
Host smart-4017b143-4e43-40c8-b7f6-9729284fcf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703354486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2703354486
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.4057147376
Short name T238
Test name
Test status
Simulation time 731259730 ps
CPU time 5.18 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:39 PM PDT 24
Peak memory 242988 kb
Host smart-2c9320d1-ae84-4ff8-a682-17e27b58a0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057147376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.4057147376
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.61271755
Short name T252
Test name
Test status
Simulation time 912241108 ps
CPU time 20.14 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:53 PM PDT 24
Peak memory 242748 kb
Host smart-4a2d38aa-bca4-447b-8fb7-160437d6f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61271755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.61271755
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2884169367
Short name T605
Test name
Test status
Simulation time 249554517 ps
CPU time 4.28 seconds
Started Jun 22 06:59:32 PM PDT 24
Finished Jun 22 06:59:39 PM PDT 24
Peak memory 242140 kb
Host smart-3f5490fe-6534-46da-a10a-eb2f774bac53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884169367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2884169367
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2972138522
Short name T541
Test name
Test status
Simulation time 822456786 ps
CPU time 24.42 seconds
Started Jun 22 06:59:32 PM PDT 24
Finished Jun 22 07:00:00 PM PDT 24
Peak memory 242140 kb
Host smart-2871f133-4de6-48bd-8f3e-781aa1f4426c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2972138522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2972138522
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3493837303
Short name T1158
Test name
Test status
Simulation time 732457168 ps
CPU time 7.47 seconds
Started Jun 22 06:59:33 PM PDT 24
Finished Jun 22 06:59:43 PM PDT 24
Peak memory 242452 kb
Host smart-ba6e2db2-f72d-4d37-bfaa-b7d56799b008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493837303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3493837303
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.2720135339
Short name T497
Test name
Test status
Simulation time 302951729 ps
CPU time 6.59 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:40 PM PDT 24
Peak memory 242216 kb
Host smart-52c9f55d-c3b8-4f27-96fa-19171bc3c32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720135339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.2720135339
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.526391153
Short name T916
Test name
Test status
Simulation time 13358268667 ps
CPU time 330.36 seconds
Started Jun 22 06:59:32 PM PDT 24
Finished Jun 22 07:05:05 PM PDT 24
Peak memory 308524 kb
Host smart-8f56b91f-1ff8-4d34-8926-f8830579e34d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526391153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
526391153
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.524489950
Short name T215
Test name
Test status
Simulation time 802579205775 ps
CPU time 1964.68 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 07:32:29 PM PDT 24
Peak memory 328048 kb
Host smart-27fa9d80-70b5-4c2a-aa22-b4e19b85267c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524489950 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.524489950
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.515010711
Short name T913
Test name
Test status
Simulation time 1058678702 ps
CPU time 6.6 seconds
Started Jun 22 06:59:32 PM PDT 24
Finished Jun 22 06:59:41 PM PDT 24
Peak memory 242496 kb
Host smart-8c459c39-a913-4346-a2fb-fc2ac036eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515010711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.515010711
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.3752492069
Short name T528
Test name
Test status
Simulation time 194742979 ps
CPU time 3.67 seconds
Started Jun 22 07:02:32 PM PDT 24
Finished Jun 22 07:02:39 PM PDT 24
Peak memory 242300 kb
Host smart-39e04a91-927e-4e45-ab47-65dc079bb830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752492069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.3752492069
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.1495945714
Short name T33
Test name
Test status
Simulation time 152833194 ps
CPU time 4.79 seconds
Started Jun 22 07:02:34 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242536 kb
Host smart-8e00837c-e5d6-4edf-a85d-d0456fda272d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495945714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1495945714
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.3219532946
Short name T1109
Test name
Test status
Simulation time 1378741760 ps
CPU time 4.14 seconds
Started Jun 22 07:02:35 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242640 kb
Host smart-c1718000-0aa8-4a66-bd07-633d22fd61af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219532946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3219532946
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2394822517
Short name T815
Test name
Test status
Simulation time 168919011 ps
CPU time 4.83 seconds
Started Jun 22 07:02:33 PM PDT 24
Finished Jun 22 07:02:41 PM PDT 24
Peak memory 242396 kb
Host smart-81896194-1ba8-47f0-ac14-7f35d333b1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394822517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2394822517
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2433783409
Short name T448
Test name
Test status
Simulation time 134400363 ps
CPU time 4.71 seconds
Started Jun 22 07:02:36 PM PDT 24
Finished Jun 22 07:02:42 PM PDT 24
Peak memory 242200 kb
Host smart-7f93aefb-6cdd-42a6-b439-1c59a3db637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433783409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2433783409
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.1723235407
Short name T1021
Test name
Test status
Simulation time 149983336 ps
CPU time 4.11 seconds
Started Jun 22 07:02:44 PM PDT 24
Finished Jun 22 07:02:51 PM PDT 24
Peak memory 242608 kb
Host smart-9174ade3-6774-451c-b842-c1f132727837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723235407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1723235407
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1885501101
Short name T140
Test name
Test status
Simulation time 173426529 ps
CPU time 4.08 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:48 PM PDT 24
Peak memory 242424 kb
Host smart-77b81caa-e395-425c-a311-a8ccdc17715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885501101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1885501101
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1827803452
Short name T607
Test name
Test status
Simulation time 1532441253 ps
CPU time 4.01 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242332 kb
Host smart-b64ba0c4-86d2-4b96-bf7a-b28db0f8e720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827803452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1827803452
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.3513904285
Short name T738
Test name
Test status
Simulation time 169074125 ps
CPU time 1.69 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 06:59:46 PM PDT 24
Peak memory 240848 kb
Host smart-e02b2541-7e64-49ce-904b-f15eccc5a1f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513904285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3513904285
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.3590630378
Short name T64
Test name
Test status
Simulation time 520682017 ps
CPU time 12.94 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 06:59:58 PM PDT 24
Peak memory 242540 kb
Host smart-c1604e60-7af9-4562-b77e-f986cbed0bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590630378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.3590630378
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.2068665861
Short name T899
Test name
Test status
Simulation time 344268415 ps
CPU time 10.36 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 06:59:53 PM PDT 24
Peak memory 242256 kb
Host smart-37229880-d915-409e-8f9b-3de7283312dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068665861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2068665861
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3293158847
Short name T6
Test name
Test status
Simulation time 348784615 ps
CPU time 7.4 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 242156 kb
Host smart-15424f2a-9f3c-417c-92d8-5a171fcadf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293158847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3293158847
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1008815207
Short name T210
Test name
Test status
Simulation time 391822814 ps
CPU time 4.56 seconds
Started Jun 22 06:59:35 PM PDT 24
Finished Jun 22 06:59:42 PM PDT 24
Peak memory 242244 kb
Host smart-a4810938-064c-437e-b18d-15a174b58943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008815207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1008815207
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2293313314
Short name T217
Test name
Test status
Simulation time 2094437284 ps
CPU time 26.1 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 07:00:11 PM PDT 24
Peak memory 242516 kb
Host smart-a661a393-e30e-418e-b866-0e34ac5cf393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293313314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2293313314
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3870940598
Short name T499
Test name
Test status
Simulation time 604825578 ps
CPU time 8.79 seconds
Started Jun 22 06:59:31 PM PDT 24
Finished Jun 22 06:59:42 PM PDT 24
Peak memory 242548 kb
Host smart-afbe1091-050b-4c29-acc3-3120cc8f7235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870940598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3870940598
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2040139133
Short name T474
Test name
Test status
Simulation time 673420604 ps
CPU time 11.83 seconds
Started Jun 22 06:59:32 PM PDT 24
Finished Jun 22 06:59:47 PM PDT 24
Peak memory 242552 kb
Host smart-1b17e8f6-f439-4c28-a2db-f75bb423eb6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040139133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2040139133
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.459348855
Short name T370
Test name
Test status
Simulation time 116210632 ps
CPU time 4.56 seconds
Started Jun 22 06:59:38 PM PDT 24
Finished Jun 22 06:59:46 PM PDT 24
Peak memory 242388 kb
Host smart-e7a9aa06-cbac-4bb7-a018-4c2ae0985fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459348855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.459348855
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2405769667
Short name T851
Test name
Test status
Simulation time 342527898 ps
CPU time 5.9 seconds
Started Jun 22 06:59:35 PM PDT 24
Finished Jun 22 06:59:43 PM PDT 24
Peak memory 242280 kb
Host smart-094ce89c-6f65-4107-9fe9-bcc8169b2de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405769667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2405769667
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.4065919750
Short name T616
Test name
Test status
Simulation time 62934376097 ps
CPU time 421.93 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 07:06:45 PM PDT 24
Peak memory 272204 kb
Host smart-ee79cdcd-0d12-4934-8394-e808e37dd564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065919750 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.4065919750
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.3966699280
Short name T449
Test name
Test status
Simulation time 1923987253 ps
CPU time 12.45 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 06:59:55 PM PDT 24
Peak memory 242732 kb
Host smart-44f1d653-365d-4e13-a74c-f55ed9661951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966699280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3966699280
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2362348397
Short name T1036
Test name
Test status
Simulation time 2543538485 ps
CPU time 6.01 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:48 PM PDT 24
Peak memory 242192 kb
Host smart-27cf9a71-fd97-46cc-a8f6-d4668f169e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362348397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2362348397
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.1530442968
Short name T1044
Test name
Test status
Simulation time 394562558 ps
CPU time 3.96 seconds
Started Jun 22 07:02:43 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242268 kb
Host smart-cc8f5807-7558-4fe4-9b28-3ef1d025bdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530442968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.1530442968
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1567058111
Short name T521
Test name
Test status
Simulation time 97381684 ps
CPU time 3.56 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242140 kb
Host smart-999928b7-7d89-46c2-9ea9-c4ad2192d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567058111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1567058111
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.674487250
Short name T45
Test name
Test status
Simulation time 2054343044 ps
CPU time 6.13 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:51 PM PDT 24
Peak memory 242156 kb
Host smart-a2d21dff-d3ff-4a7c-af27-9027ba69e311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674487250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.674487250
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2076662675
Short name T608
Test name
Test status
Simulation time 494965639 ps
CPU time 4.9 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:50 PM PDT 24
Peak memory 242372 kb
Host smart-e8ee2656-d658-4af0-ab64-846dc8637140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076662675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2076662675
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2834524708
Short name T412
Test name
Test status
Simulation time 135507142 ps
CPU time 3.98 seconds
Started Jun 22 07:02:39 PM PDT 24
Finished Jun 22 07:02:45 PM PDT 24
Peak memory 242152 kb
Host smart-d82c7b79-f97b-46cb-af3c-53ea8dfb1db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834524708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2834524708
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1004756087
Short name T640
Test name
Test status
Simulation time 2099935821 ps
CPU time 4.76 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242100 kb
Host smart-b77dd318-0a67-4a4b-b7d4-1e872cf4f9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004756087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1004756087
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.2188739612
Short name T71
Test name
Test status
Simulation time 315502112 ps
CPU time 4.71 seconds
Started Jun 22 07:02:44 PM PDT 24
Finished Jun 22 07:02:52 PM PDT 24
Peak memory 242560 kb
Host smart-3aa73a13-bfbb-4250-84b7-ef6e23c4f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188739612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2188739612
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.2012640912
Short name T1173
Test name
Test status
Simulation time 304166185 ps
CPU time 4.47 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242260 kb
Host smart-5361e445-5937-4a5c-bff5-bce2babebed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012640912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.2012640912
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.3031380878
Short name T130
Test name
Test status
Simulation time 2124825144 ps
CPU time 4.82 seconds
Started Jun 22 07:02:44 PM PDT 24
Finished Jun 22 07:02:52 PM PDT 24
Peak memory 242188 kb
Host smart-4bc98d3a-07c4-4e9f-b3a8-fa816583447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031380878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3031380878
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1833673783
Short name T1154
Test name
Test status
Simulation time 84702298 ps
CPU time 1.61 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 240980 kb
Host smart-ac8ed93c-742b-4e8f-a565-188d062cfeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833673783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1833673783
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.1207426405
Short name T947
Test name
Test status
Simulation time 1382400758 ps
CPU time 19.32 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242100 kb
Host smart-4d5ff910-46d6-473f-b245-5548b689d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207426405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.1207426405
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.4165441498
Short name T744
Test name
Test status
Simulation time 4560890480 ps
CPU time 50.32 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 07:00:35 PM PDT 24
Peak memory 242872 kb
Host smart-72e9dc62-f105-43f3-ad56-0d144eb1af3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165441498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.4165441498
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.4126239345
Short name T179
Test name
Test status
Simulation time 2380700748 ps
CPU time 8.96 seconds
Started Jun 22 06:59:38 PM PDT 24
Finished Jun 22 06:59:49 PM PDT 24
Peak memory 242360 kb
Host smart-9434b98b-6231-48ad-8a7d-e495ab831951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126239345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.4126239345
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2958922699
Short name T425
Test name
Test status
Simulation time 4372016334 ps
CPU time 12.75 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 06:59:54 PM PDT 24
Peak memory 242860 kb
Host smart-61017d9a-0f0d-4874-8342-c7d0a9150e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958922699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2958922699
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.723793906
Short name T550
Test name
Test status
Simulation time 991364911 ps
CPU time 9.12 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 06:59:54 PM PDT 24
Peak memory 242432 kb
Host smart-842b7056-6f7e-4f3c-9a50-25f7982298f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723793906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.723793906
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3113172924
Short name T1101
Test name
Test status
Simulation time 363576260 ps
CPU time 10.89 seconds
Started Jun 22 06:59:38 PM PDT 24
Finished Jun 22 06:59:52 PM PDT 24
Peak memory 242068 kb
Host smart-059d6cdf-d34b-465f-bda9-26fa77322df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113172924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3113172924
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.2226965087
Short name T1133
Test name
Test status
Simulation time 2166558224 ps
CPU time 16.85 seconds
Started Jun 22 06:59:42 PM PDT 24
Finished Jun 22 07:00:03 PM PDT 24
Peak memory 242232 kb
Host smart-cce06e2c-bb80-413a-8631-8965a7a79b73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226965087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2226965087
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.1338648927
Short name T887
Test name
Test status
Simulation time 179123668 ps
CPU time 5.81 seconds
Started Jun 22 06:59:39 PM PDT 24
Finished Jun 22 06:59:48 PM PDT 24
Peak memory 242124 kb
Host smart-47743eb7-1375-43e3-af31-6eab89ce0129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338648927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1338648927
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1861513198
Short name T638
Test name
Test status
Simulation time 335972098 ps
CPU time 6.54 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 06:59:51 PM PDT 24
Peak memory 242160 kb
Host smart-8233d571-2378-4c41-b310-f40c9346d97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861513198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1861513198
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1730537286
Short name T1035
Test name
Test status
Simulation time 13226210599 ps
CPU time 234.62 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 07:03:40 PM PDT 24
Peak memory 257404 kb
Host smart-1e802fc1-e9e9-4c2e-82fc-f016da3ecbce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730537286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1730537286
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.20931509
Short name T657
Test name
Test status
Simulation time 1194596891085 ps
CPU time 2418.83 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 07:40:04 PM PDT 24
Peak memory 347312 kb
Host smart-bf44f998-0a6b-4c09-ad2b-6333a668f5a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931509 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.20931509
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.3889298129
Short name T1174
Test name
Test status
Simulation time 22682263941 ps
CPU time 29.89 seconds
Started Jun 22 06:59:40 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242664 kb
Host smart-e4bd5fcc-92aa-45f1-a17a-eae874afd347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889298129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3889298129
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3065165767
Short name T974
Test name
Test status
Simulation time 432136889 ps
CPU time 4.49 seconds
Started Jun 22 07:02:44 PM PDT 24
Finished Jun 22 07:02:51 PM PDT 24
Peak memory 242552 kb
Host smart-daa84410-8b50-4079-a38c-6cbfe70e740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065165767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3065165767
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.4053436430
Short name T148
Test name
Test status
Simulation time 171905831 ps
CPU time 4.41 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242244 kb
Host smart-fade8516-b943-44e4-83ad-49ac8be97f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053436430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.4053436430
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2408564871
Short name T717
Test name
Test status
Simulation time 119573121 ps
CPU time 3.65 seconds
Started Jun 22 07:02:41 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242152 kb
Host smart-13c3c16e-9bf7-4a19-9afa-5996a67450b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408564871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2408564871
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1735168525
Short name T492
Test name
Test status
Simulation time 252792299 ps
CPU time 3.54 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:48 PM PDT 24
Peak memory 242356 kb
Host smart-0ed037e0-936f-4167-a259-34a1206d79ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735168525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1735168525
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.1668455448
Short name T424
Test name
Test status
Simulation time 459092607 ps
CPU time 3.19 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:46 PM PDT 24
Peak memory 242192 kb
Host smart-959745ee-13fa-4dde-b167-3e5edbf7acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668455448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.1668455448
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1447352001
Short name T934
Test name
Test status
Simulation time 2615457445 ps
CPU time 6.75 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242380 kb
Host smart-2a83d582-fb3f-4a98-96eb-9ec798c53b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447352001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1447352001
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.2143310560
Short name T930
Test name
Test status
Simulation time 155008711 ps
CPU time 4.33 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242624 kb
Host smart-ee7d992a-59ad-4deb-b45f-bc039cfb18d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143310560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.2143310560
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.3640421164
Short name T626
Test name
Test status
Simulation time 153745747 ps
CPU time 4.06 seconds
Started Jun 22 07:02:41 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242652 kb
Host smart-e45e9873-c370-4a54-8e24-99b1560b608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640421164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3640421164
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.884455493
Short name T180
Test name
Test status
Simulation time 112855279 ps
CPU time 3.96 seconds
Started Jun 22 07:02:45 PM PDT 24
Finished Jun 22 07:02:52 PM PDT 24
Peak memory 242304 kb
Host smart-1bdda109-a55e-468f-b21a-1e30659d9314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884455493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.884455493
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2338715020
Short name T692
Test name
Test status
Simulation time 2257455566 ps
CPU time 4.73 seconds
Started Jun 22 07:02:39 PM PDT 24
Finished Jun 22 07:02:46 PM PDT 24
Peak memory 242136 kb
Host smart-4b15038f-55de-4b1b-a367-0eb31b9d26f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338715020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2338715020
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.3910729223
Short name T800
Test name
Test status
Simulation time 102186219 ps
CPU time 2.27 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 06:59:54 PM PDT 24
Peak memory 241080 kb
Host smart-547e5aea-64b8-425c-bada-30e982eca7c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910729223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3910729223
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1011440276
Short name T1031
Test name
Test status
Simulation time 1563752255 ps
CPU time 12.81 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242884 kb
Host smart-98dd584f-d280-4116-9b0c-6cf9add2127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011440276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1011440276
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.1489580089
Short name T992
Test name
Test status
Simulation time 1041905919 ps
CPU time 17.17 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242668 kb
Host smart-da40c1f3-23bb-4f73-8789-808372728d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489580089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1489580089
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3455165687
Short name T1
Test name
Test status
Simulation time 1815517825 ps
CPU time 19.37 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:11 PM PDT 24
Peak memory 242084 kb
Host smart-bc8e44ef-d041-481a-bd7b-d407f7a42f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455165687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3455165687
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3269846024
Short name T690
Test name
Test status
Simulation time 2763067621 ps
CPU time 4.68 seconds
Started Jun 22 06:59:42 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 242600 kb
Host smart-eb129bd0-610a-44ef-bada-0cc12f75cb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269846024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3269846024
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1476466714
Short name T1142
Test name
Test status
Simulation time 5294246028 ps
CPU time 17.62 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242336 kb
Host smart-3d31d1c8-ea4e-4b9c-a7f3-b5738fec47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476466714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1476466714
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3159426035
Short name T776
Test name
Test status
Simulation time 336827610 ps
CPU time 14.92 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 07:00:05 PM PDT 24
Peak memory 242156 kb
Host smart-2ab04ee3-3461-4179-8fd2-6de1d41e40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159426035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3159426035
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2403262694
Short name T501
Test name
Test status
Simulation time 238320584 ps
CPU time 3.59 seconds
Started Jun 22 06:59:38 PM PDT 24
Finished Jun 22 06:59:44 PM PDT 24
Peak memory 242268 kb
Host smart-d75414d8-f985-4988-a64a-4b9e6c058fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403262694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2403262694
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.2198268635
Short name T391
Test name
Test status
Simulation time 401127153 ps
CPU time 10.48 seconds
Started Jun 22 06:59:41 PM PDT 24
Finished Jun 22 06:59:55 PM PDT 24
Peak memory 242156 kb
Host smart-652ceafa-1736-4867-9681-eb7f9e4e28df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198268635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2198268635
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.3172475339
Short name T943
Test name
Test status
Simulation time 221012238 ps
CPU time 7.04 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 06:59:57 PM PDT 24
Peak memory 248728 kb
Host smart-0361f5af-181d-4451-8019-bddfcd29aadd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172475339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3172475339
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1543463032
Short name T827
Test name
Test status
Simulation time 233914191 ps
CPU time 5.27 seconds
Started Jun 22 06:59:44 PM PDT 24
Finished Jun 22 06:59:52 PM PDT 24
Peak memory 242244 kb
Host smart-199dc03e-048f-4efe-ad83-2f51b71d2998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543463032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1543463032
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.4133395946
Short name T338
Test name
Test status
Simulation time 269458027 ps
CPU time 2.39 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 06:59:54 PM PDT 24
Peak memory 241700 kb
Host smart-e99dea75-d76c-440c-a948-1ec45eecd2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133395946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.4133395946
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1093509771
Short name T68
Test name
Test status
Simulation time 172802834630 ps
CPU time 2868.09 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:47:40 PM PDT 24
Peak memory 719696 kb
Host smart-07adc702-7e38-400e-934f-f9d0422b7ce5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093509771 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1093509771
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.2362866718
Short name T845
Test name
Test status
Simulation time 1450052146 ps
CPU time 14.56 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242148 kb
Host smart-ad4ef0f1-506c-472a-96f1-100add7e16bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362866718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2362866718
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.1958683167
Short name T171
Test name
Test status
Simulation time 96535934 ps
CPU time 3.84 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:49 PM PDT 24
Peak memory 242340 kb
Host smart-d17949f2-5d55-445b-8726-ee3b04b0e6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958683167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1958683167
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.639695218
Short name T175
Test name
Test status
Simulation time 239911579 ps
CPU time 3.54 seconds
Started Jun 22 07:02:39 PM PDT 24
Finished Jun 22 07:02:45 PM PDT 24
Peak memory 242152 kb
Host smart-2b6e34b2-3173-453c-8795-7994376c85b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639695218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.639695218
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.2395848553
Short name T834
Test name
Test status
Simulation time 1680987312 ps
CPU time 5.41 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:47 PM PDT 24
Peak memory 242172 kb
Host smart-96dd9754-00a5-48b1-8b5c-b018ffbf40a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395848553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2395848553
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.1688724880
Short name T170
Test name
Test status
Simulation time 472542825 ps
CPU time 5.02 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:48 PM PDT 24
Peak memory 242268 kb
Host smart-bf23927a-c5da-42de-937e-4caee462b2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688724880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.1688724880
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3320387615
Short name T1043
Test name
Test status
Simulation time 265091841 ps
CPU time 4.76 seconds
Started Jun 22 07:02:43 PM PDT 24
Finished Jun 22 07:02:51 PM PDT 24
Peak memory 242416 kb
Host smart-27d1fd3a-cb50-4305-9f7f-504a11e9ab25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320387615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3320387615
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.829135282
Short name T631
Test name
Test status
Simulation time 148027444 ps
CPU time 4.03 seconds
Started Jun 22 07:02:44 PM PDT 24
Finished Jun 22 07:02:51 PM PDT 24
Peak memory 242116 kb
Host smart-37fbc7cf-62f4-4fc6-b001-f21e8e4746b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829135282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.829135282
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.182706868
Short name T56
Test name
Test status
Simulation time 442493808 ps
CPU time 3.83 seconds
Started Jun 22 07:02:42 PM PDT 24
Finished Jun 22 07:02:48 PM PDT 24
Peak memory 242156 kb
Host smart-3d1ef46e-65e5-4669-a88e-2ea4e780232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182706868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.182706868
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3049770897
Short name T676
Test name
Test status
Simulation time 178147987 ps
CPU time 3.51 seconds
Started Jun 22 07:02:39 PM PDT 24
Finished Jun 22 07:02:44 PM PDT 24
Peak memory 242168 kb
Host smart-32f1e447-7515-4b89-b6d3-2bc435b05596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049770897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3049770897
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2319366749
Short name T437
Test name
Test status
Simulation time 214103428 ps
CPU time 3.22 seconds
Started Jun 22 07:02:40 PM PDT 24
Finished Jun 22 07:02:46 PM PDT 24
Peak memory 242092 kb
Host smart-9c73352e-17f8-49e9-b557-af5accf01c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319366749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2319366749
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.1645960572
Short name T561
Test name
Test status
Simulation time 655976365 ps
CPU time 1.79 seconds
Started Jun 22 06:57:44 PM PDT 24
Finished Jun 22 06:57:48 PM PDT 24
Peak memory 240824 kb
Host smart-be5ccf29-5295-4b0e-8c09-6c52f1debf53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645960572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1645960572
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3341897780
Short name T382
Test name
Test status
Simulation time 491706062 ps
CPU time 17.04 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:54 PM PDT 24
Peak memory 243000 kb
Host smart-5f73a0df-a0b5-4ee1-8c34-15d193fcff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341897780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3341897780
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1401978460
Short name T76
Test name
Test status
Simulation time 1147991171 ps
CPU time 21.35 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:57 PM PDT 24
Peak memory 243064 kb
Host smart-b2119950-e099-4414-8939-3f60722149b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401978460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1401978460
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.3014148453
Short name T674
Test name
Test status
Simulation time 1006059580 ps
CPU time 15.11 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:52 PM PDT 24
Peak memory 242156 kb
Host smart-65ccd4a6-ea27-4372-b6c9-893edb0256cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014148453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.3014148453
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3100099495
Short name T574
Test name
Test status
Simulation time 362752881 ps
CPU time 10.25 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:46 PM PDT 24
Peak memory 242088 kb
Host smart-2a5a3855-3563-4266-bc85-39ce3e5994fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100099495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3100099495
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1427575727
Short name T176
Test name
Test status
Simulation time 276702611 ps
CPU time 3.95 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:41 PM PDT 24
Peak memory 242196 kb
Host smart-3aee546e-bf35-481e-ae17-018d7803aa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427575727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1427575727
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2326482646
Short name T778
Test name
Test status
Simulation time 1839539271 ps
CPU time 15.54 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:58:00 PM PDT 24
Peak memory 242156 kb
Host smart-3ee2e371-9725-49f1-bb39-8a816d31f1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326482646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2326482646
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3361636668
Short name T109
Test name
Test status
Simulation time 781330956 ps
CPU time 22.59 seconds
Started Jun 22 06:57:42 PM PDT 24
Finished Jun 22 06:58:07 PM PDT 24
Peak memory 242640 kb
Host smart-a3698d8c-7780-4acc-b0fb-a1fafca630ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361636668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3361636668
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.370312766
Short name T1153
Test name
Test status
Simulation time 634648707 ps
CPU time 12.11 seconds
Started Jun 22 06:57:36 PM PDT 24
Finished Jun 22 06:57:49 PM PDT 24
Peak memory 242156 kb
Host smart-804f7771-d94a-463c-bc5b-a1c2c13a1719
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370312766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.370312766
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3595060909
Short name T375
Test name
Test status
Simulation time 600102773 ps
CPU time 6.17 seconds
Started Jun 22 06:57:42 PM PDT 24
Finished Jun 22 06:57:51 PM PDT 24
Peak memory 242200 kb
Host smart-da35e510-82f4-493d-ad39-134cb678e7ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595060909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3595060909
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.1811910546
Short name T25
Test name
Test status
Simulation time 10553240190 ps
CPU time 164.65 seconds
Started Jun 22 06:57:42 PM PDT 24
Finished Jun 22 07:00:29 PM PDT 24
Peak memory 264740 kb
Host smart-1a0373ef-6b6d-42ac-a505-06f26f85af7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811910546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1811910546
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2018755744
Short name T1009
Test name
Test status
Simulation time 324344189 ps
CPU time 4.52 seconds
Started Jun 22 06:57:35 PM PDT 24
Finished Jun 22 06:57:40 PM PDT 24
Peak memory 242376 kb
Host smart-d2ed0906-ec4c-4083-80b8-613908b61cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018755744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2018755744
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2013778333
Short name T802
Test name
Test status
Simulation time 38436121695 ps
CPU time 206.54 seconds
Started Jun 22 06:57:46 PM PDT 24
Finished Jun 22 07:01:15 PM PDT 24
Peak memory 261036 kb
Host smart-de842212-110a-4cfa-83b9-a9894308c8a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013778333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2013778333
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3390305227
Short name T547
Test name
Test status
Simulation time 160057082319 ps
CPU time 2439.3 seconds
Started Jun 22 06:57:45 PM PDT 24
Finished Jun 22 07:38:27 PM PDT 24
Peak memory 498332 kb
Host smart-8f4bb0b5-94c4-4d1c-a5a9-5af9d4576f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390305227 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3390305227
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.1676626757
Short name T774
Test name
Test status
Simulation time 18905704784 ps
CPU time 26.82 seconds
Started Jun 22 06:57:45 PM PDT 24
Finished Jun 22 06:58:15 PM PDT 24
Peak memory 243812 kb
Host smart-f509787f-5b88-42c2-aba3-20d6bf464f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676626757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1676626757
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2885780317
Short name T473
Test name
Test status
Simulation time 171006974 ps
CPU time 1.79 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 06:59:50 PM PDT 24
Peak memory 240660 kb
Host smart-c5a76a7e-2c8f-411a-bde1-1acc40e98aae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885780317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2885780317
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.536689804
Short name T39
Test name
Test status
Simulation time 14830038934 ps
CPU time 23.91 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:15 PM PDT 24
Peak memory 242372 kb
Host smart-1c9388f2-312b-4acc-843e-bc42d52120d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536689804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.536689804
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2380511025
Short name T1114
Test name
Test status
Simulation time 2410613450 ps
CPU time 23.88 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242436 kb
Host smart-33efe256-9a88-414f-90db-022ac6fa9d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380511025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2380511025
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3772052381
Short name T383
Test name
Test status
Simulation time 603440079 ps
CPU time 23.3 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242688 kb
Host smart-5831a4e0-ab7b-4dbd-9567-9672614e132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772052381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3772052381
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.579787898
Short name T544
Test name
Test status
Simulation time 138242104 ps
CPU time 3.75 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 06:59:56 PM PDT 24
Peak memory 242288 kb
Host smart-8c065ca9-4c7d-4d45-899d-f12cf7f53b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579787898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.579787898
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1486246286
Short name T617
Test name
Test status
Simulation time 4388699828 ps
CPU time 32.85 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:25 PM PDT 24
Peak memory 249072 kb
Host smart-babee7c7-c277-4110-8fe5-8d4d017e041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486246286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1486246286
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.1012008888
Short name T394
Test name
Test status
Simulation time 1382123485 ps
CPU time 30.39 seconds
Started Jun 22 06:59:48 PM PDT 24
Finished Jun 22 07:00:22 PM PDT 24
Peak memory 242468 kb
Host smart-3b212ecc-2992-415f-b37a-93f94485624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012008888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.1012008888
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3098769719
Short name T723
Test name
Test status
Simulation time 1316743415 ps
CPU time 4.98 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 06:59:53 PM PDT 24
Peak memory 242400 kb
Host smart-ec054bd9-800c-45c7-a104-946036009099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098769719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3098769719
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1500706679
Short name T614
Test name
Test status
Simulation time 371208678 ps
CPU time 10.02 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 07:00:01 PM PDT 24
Peak memory 242676 kb
Host smart-96b96052-ce9e-4871-ac40-f7b2d75a8a5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1500706679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1500706679
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.810265344
Short name T164
Test name
Test status
Simulation time 285784887 ps
CPU time 5.54 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 06:59:56 PM PDT 24
Peak memory 242332 kb
Host smart-9961d239-837e-4110-9245-fdb311bc7706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810265344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.810265344
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1065454452
Short name T1069
Test name
Test status
Simulation time 639873078 ps
CPU time 5.37 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 06:59:56 PM PDT 24
Peak memory 242576 kb
Host smart-2cc7f4d7-4621-4f25-8539-ad3c2c998218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065454452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1065454452
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2974198335
Short name T1110
Test name
Test status
Simulation time 38345875781 ps
CPU time 268.57 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 07:04:18 PM PDT 24
Peak memory 281900 kb
Host smart-f15343e1-9fbf-44ec-b72e-19aea0948073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974198335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2974198335
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.3557909283
Short name T302
Test name
Test status
Simulation time 62293563710 ps
CPU time 1385.25 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 07:22:56 PM PDT 24
Peak memory 259772 kb
Host smart-46b6c0dc-d6a6-41fa-8d13-14109f04f716
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557909283 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.3557909283
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.133900976
Short name T588
Test name
Test status
Simulation time 445602540 ps
CPU time 9.98 seconds
Started Jun 22 06:59:46 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 242520 kb
Host smart-505ffa85-b34e-4b4f-b95d-c4b5e5869b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133900976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.133900976
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1997366364
Short name T645
Test name
Test status
Simulation time 209085568 ps
CPU time 1.99 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:00 PM PDT 24
Peak memory 240908 kb
Host smart-17708837-5b8b-401e-aab6-c8452aad5bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997366364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1997366364
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.1397357133
Short name T1163
Test name
Test status
Simulation time 163526796 ps
CPU time 6.15 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242364 kb
Host smart-c100eda4-fff0-432c-84a1-945ca516001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397357133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1397357133
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.365474998
Short name T591
Test name
Test status
Simulation time 556484076 ps
CPU time 9.66 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:07 PM PDT 24
Peak memory 242416 kb
Host smart-d70c93e8-b508-4dfa-b04a-5feebd0c5d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365474998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.365474998
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2288931657
Short name T414
Test name
Test status
Simulation time 717457187 ps
CPU time 13.92 seconds
Started Jun 22 06:59:53 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242668 kb
Host smart-11c823c3-b496-4339-b45c-e1c4171dcbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288931657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2288931657
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.2568537506
Short name T62
Test name
Test status
Simulation time 1720093037 ps
CPU time 4.57 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:01 PM PDT 24
Peak memory 242312 kb
Host smart-f6a97e45-a4fe-4294-9eb2-56ce56f67355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568537506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.2568537506
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2541161167
Short name T660
Test name
Test status
Simulation time 651640149 ps
CPU time 17.56 seconds
Started Jun 22 06:59:53 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242576 kb
Host smart-1521c398-4826-4053-8a7a-98c3615298a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541161167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2541161167
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.4048215521
Short name T104
Test name
Test status
Simulation time 1842824515 ps
CPU time 46.37 seconds
Started Jun 22 07:00:00 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 242224 kb
Host smart-e5050b79-264c-4acc-b028-5ea23a4c44ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048215521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.4048215521
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.3134000216
Short name T1020
Test name
Test status
Simulation time 457095943 ps
CPU time 4.99 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242116 kb
Host smart-0b590605-3601-446d-aba9-7832445d9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134000216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3134000216
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.3837419455
Short name T548
Test name
Test status
Simulation time 165098419 ps
CPU time 4.83 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 248040 kb
Host smart-7d3c429d-1330-4158-899d-1fba60d8ab97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3837419455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3837419455
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.3183734465
Short name T377
Test name
Test status
Simulation time 470222568 ps
CPU time 8.03 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:06 PM PDT 24
Peak memory 242228 kb
Host smart-ae8d3686-968f-4573-a0a9-2a87a4974a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183734465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3183734465
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3373929214
Short name T273
Test name
Test status
Simulation time 1079785749 ps
CPU time 8.39 seconds
Started Jun 22 06:59:47 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 242508 kb
Host smart-ac7b80e2-d5fe-40c4-b7e2-6a459ec6138b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373929214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3373929214
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1624070224
Short name T232
Test name
Test status
Simulation time 4244484024 ps
CPU time 151.88 seconds
Started Jun 22 06:59:56 PM PDT 24
Finished Jun 22 07:02:30 PM PDT 24
Peak memory 261908 kb
Host smart-44c513d7-253b-4a4e-b9c2-6a4d40b96837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624070224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1624070224
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1998815114
Short name T993
Test name
Test status
Simulation time 129566684409 ps
CPU time 1017.86 seconds
Started Jun 22 06:59:56 PM PDT 24
Finished Jun 22 07:16:56 PM PDT 24
Peak memory 341404 kb
Host smart-a0335e27-937b-476a-80f6-8cad718c0089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998815114 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1998815114
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.224216229
Short name T653
Test name
Test status
Simulation time 8879812377 ps
CPU time 28.39 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:25 PM PDT 24
Peak memory 242892 kb
Host smart-5474bebe-b490-41b0-8558-bb3b3b47c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224216229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.224216229
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.1504808323
Short name T1081
Test name
Test status
Simulation time 215207175 ps
CPU time 2.04 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 240660 kb
Host smart-a77c91ee-0456-4c10-b870-7dc328eed86a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504808323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.1504808323
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.2917265540
Short name T125
Test name
Test status
Simulation time 127410429 ps
CPU time 2.53 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 06:59:59 PM PDT 24
Peak memory 242080 kb
Host smart-87de36dd-e343-4002-b7c4-024d739c68b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917265540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2917265540
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1552686162
Short name T551
Test name
Test status
Simulation time 466496161 ps
CPU time 13.51 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242076 kb
Host smart-d3fa4ccb-b486-4fa2-8dcc-b27539018091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552686162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1552686162
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2220260635
Short name T634
Test name
Test status
Simulation time 15458405079 ps
CPU time 52.53 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 244172 kb
Host smart-42780d78-d5f7-4d4d-b39f-b2f02528a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220260635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2220260635
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3722997419
Short name T959
Test name
Test status
Simulation time 2696903982 ps
CPU time 6.42 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:05 PM PDT 24
Peak memory 242496 kb
Host smart-34953340-897b-480b-b52d-126020e48ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722997419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3722997419
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.680500177
Short name T196
Test name
Test status
Simulation time 6222861315 ps
CPU time 70.01 seconds
Started Jun 22 06:59:58 PM PDT 24
Finished Jun 22 07:01:11 PM PDT 24
Peak memory 263668 kb
Host smart-4664ae20-55a9-41b5-b26a-97e36a829bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680500177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.680500177
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.4273138606
Short name T187
Test name
Test status
Simulation time 3469916502 ps
CPU time 19.01 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:15 PM PDT 24
Peak memory 242956 kb
Host smart-e0bb8f0e-996f-4c13-a9af-a46ada09a706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273138606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.4273138606
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3677516366
Short name T585
Test name
Test status
Simulation time 505194319 ps
CPU time 3.91 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242488 kb
Host smart-1e9c113a-b881-4d11-9f70-5226154113e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677516366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3677516366
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1033548446
Short name T390
Test name
Test status
Simulation time 2833864647 ps
CPU time 23.81 seconds
Started Jun 22 06:59:53 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 242376 kb
Host smart-f2396059-c392-4d4a-8fe7-f269575be3f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1033548446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1033548446
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1570072320
Short name T341
Test name
Test status
Simulation time 293446595 ps
CPU time 5.29 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242376 kb
Host smart-78c06c18-be3f-46a7-b8be-1ba9e7e31f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1570072320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1570072320
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.4197029850
Short name T801
Test name
Test status
Simulation time 162115422 ps
CPU time 4.74 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242172 kb
Host smart-367f1a43-bbaf-4806-9d26-5d5ce69546ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197029850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.4197029850
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1706866725
Short name T233
Test name
Test status
Simulation time 6236781397 ps
CPU time 147.56 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:02:25 PM PDT 24
Peak memory 266856 kb
Host smart-0cbfa478-3496-4266-9ca3-cf2180196464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706866725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1706866725
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.1969330789
Short name T290
Test name
Test status
Simulation time 126884553041 ps
CPU time 3036.53 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:50:34 PM PDT 24
Peak memory 688684 kb
Host smart-ab113766-2413-4a78-b154-1fa907e8b882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969330789 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.1969330789
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.2615150328
Short name T743
Test name
Test status
Simulation time 1667357580 ps
CPU time 16.49 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242152 kb
Host smart-5cb84fb3-4ef5-4e35-8003-96035eefe65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615150328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2615150328
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.4153912940
Short name T931
Test name
Test status
Simulation time 614451623 ps
CPU time 2.07 seconds
Started Jun 22 07:00:00 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 240556 kb
Host smart-a24309d0-2e88-499c-a7b4-51cc2bd1b837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153912940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.4153912940
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.3591878225
Short name T625
Test name
Test status
Simulation time 1361426542 ps
CPU time 8.36 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:08 PM PDT 24
Peak memory 242340 kb
Host smart-b114cbef-98af-4d68-a4c4-c6c026e38158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591878225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3591878225
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.657521889
Short name T984
Test name
Test status
Simulation time 4488525039 ps
CPU time 18.23 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:17 PM PDT 24
Peak memory 242232 kb
Host smart-7ca6d69a-bc6c-42e5-8909-51784b4a813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657521889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.657521889
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.3298704054
Short name T623
Test name
Test status
Simulation time 531746309 ps
CPU time 15.21 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242148 kb
Host smart-3e179309-0922-4e25-9915-b1038d5b728f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298704054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3298704054
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.4192785515
Short name T795
Test name
Test status
Simulation time 372412591 ps
CPU time 4.64 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242480 kb
Host smart-9f35ae22-002d-4c2c-a287-2402ee2a634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192785515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.4192785515
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3979148977
Short name T350
Test name
Test status
Simulation time 1022449780 ps
CPU time 26.01 seconds
Started Jun 22 07:00:00 PM PDT 24
Finished Jun 22 07:00:29 PM PDT 24
Peak memory 243828 kb
Host smart-8a6742b3-e3e6-4e2e-b15b-a75a8d8d1f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979148977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3979148977
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.2751899755
Short name T679
Test name
Test status
Simulation time 767632641 ps
CPU time 32.4 seconds
Started Jun 22 06:59:55 PM PDT 24
Finished Jun 22 07:00:31 PM PDT 24
Peak memory 242612 kb
Host smart-bc8ec249-56b2-41f1-93fa-90102f57f798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751899755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2751899755
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.2913598029
Short name T971
Test name
Test status
Simulation time 1659509841 ps
CPU time 12.69 seconds
Started Jun 22 06:59:58 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242276 kb
Host smart-9b00db42-6dc5-404a-91fe-7d6da627ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913598029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2913598029
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.3362830433
Short name T780
Test name
Test status
Simulation time 314282259 ps
CPU time 6.21 seconds
Started Jun 22 06:59:56 PM PDT 24
Finished Jun 22 07:00:05 PM PDT 24
Peak memory 242116 kb
Host smart-e4ceef2c-2ee7-46e3-bc6b-77242d3638c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362830433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.3362830433
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.3701380882
Short name T1100
Test name
Test status
Simulation time 160785733 ps
CPU time 5.95 seconds
Started Jun 22 06:59:56 PM PDT 24
Finished Jun 22 07:00:04 PM PDT 24
Peak memory 242248 kb
Host smart-6b14e56e-b69c-4204-b789-6edf1597ac76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701380882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3701380882
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.207196444
Short name T1126
Test name
Test status
Simulation time 145926673 ps
CPU time 3.62 seconds
Started Jun 22 06:59:56 PM PDT 24
Finished Jun 22 07:00:02 PM PDT 24
Peak memory 242532 kb
Host smart-e2c22562-7747-4327-94f3-3ef825195d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207196444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.207196444
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.1250768665
Short name T835
Test name
Test status
Simulation time 39775489199 ps
CPU time 91.93 seconds
Started Jun 22 06:59:53 PM PDT 24
Finished Jun 22 07:01:28 PM PDT 24
Peak memory 246872 kb
Host smart-1c917c36-b6d9-4c1b-bf7e-2f418e164c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250768665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.1250768665
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.215554382
Short name T649
Test name
Test status
Simulation time 321877232960 ps
CPU time 1022.11 seconds
Started Jun 22 06:59:54 PM PDT 24
Finished Jun 22 07:16:59 PM PDT 24
Peak memory 331164 kb
Host smart-33f23131-45eb-4500-bf7e-e8199b9aab78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215554382 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.215554382
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1367745467
Short name T1050
Test name
Test status
Simulation time 370636495 ps
CPU time 5.7 seconds
Started Jun 22 06:59:57 PM PDT 24
Finished Jun 22 07:00:06 PM PDT 24
Peak memory 249040 kb
Host smart-839b3d62-129d-41ce-b594-86d964f1de98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367745467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1367745467
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.762908279
Short name T814
Test name
Test status
Simulation time 104154997 ps
CPU time 1.75 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:07 PM PDT 24
Peak memory 240680 kb
Host smart-3ed158cc-5324-4f48-8702-26878aa141a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762908279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.762908279
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3259565650
Short name T1184
Test name
Test status
Simulation time 1170525142 ps
CPU time 18.54 seconds
Started Jun 22 07:00:01 PM PDT 24
Finished Jun 22 07:00:21 PM PDT 24
Peak memory 243140 kb
Host smart-18f58b82-4d2a-4054-be25-f5dcf0d64981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259565650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3259565650
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.451126979
Short name T761
Test name
Test status
Simulation time 3640569246 ps
CPU time 37.9 seconds
Started Jun 22 07:00:02 PM PDT 24
Finished Jun 22 07:00:42 PM PDT 24
Peak memory 247292 kb
Host smart-855684e3-e60f-482c-8f1c-cf920383f740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451126979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.451126979
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.4035258991
Short name T799
Test name
Test status
Simulation time 15007062689 ps
CPU time 41.85 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:47 PM PDT 24
Peak memory 243136 kb
Host smart-b325df21-f9ef-40cd-a46d-3e63aa5a3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035258991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.4035258991
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.2747811186
Short name T881
Test name
Test status
Simulation time 361865364 ps
CPU time 4.15 seconds
Started Jun 22 07:00:07 PM PDT 24
Finished Jun 22 07:00:12 PM PDT 24
Peak memory 242244 kb
Host smart-149ecd13-6acd-4086-b381-b54c889e6a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747811186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2747811186
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3798549105
Short name T239
Test name
Test status
Simulation time 145353703 ps
CPU time 4.76 seconds
Started Jun 22 07:00:07 PM PDT 24
Finished Jun 22 07:00:13 PM PDT 24
Peak memory 242604 kb
Host smart-44237d34-5780-46b0-a289-40e0b824c90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798549105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3798549105
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.4260149570
Short name T167
Test name
Test status
Simulation time 15837465424 ps
CPU time 38.77 seconds
Started Jun 22 07:00:08 PM PDT 24
Finished Jun 22 07:00:48 PM PDT 24
Peak memory 242680 kb
Host smart-0c2700aa-c1ab-40a0-864b-9fd63699c918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260149570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.4260149570
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.2942742874
Short name T788
Test name
Test status
Simulation time 117425341 ps
CPU time 3.59 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242184 kb
Host smart-4ca06e98-721f-48c7-b27e-f580334a87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942742874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2942742874
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1135587944
Short name T484
Test name
Test status
Simulation time 612543943 ps
CPU time 17.82 seconds
Started Jun 22 07:00:02 PM PDT 24
Finished Jun 22 07:00:22 PM PDT 24
Peak memory 248980 kb
Host smart-c45a4a3d-954b-4a1a-870b-05aa311e6de2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135587944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1135587944
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2324300971
Short name T849
Test name
Test status
Simulation time 3256672771 ps
CPU time 7.18 seconds
Started Jun 22 07:00:06 PM PDT 24
Finished Jun 22 07:00:15 PM PDT 24
Peak memory 242252 kb
Host smart-d6c9c9c6-c44c-44b7-a22e-75f1bfa2d2cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2324300971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2324300971
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.3985470557
Short name T972
Test name
Test status
Simulation time 249842598 ps
CPU time 5.45 seconds
Started Jun 22 07:00:04 PM PDT 24
Finished Jun 22 07:00:11 PM PDT 24
Peak memory 242744 kb
Host smart-f02e5310-d220-46fd-9769-879d2d9a7f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985470557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3985470557
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.1602809263
Short name T883
Test name
Test status
Simulation time 21040763438 ps
CPU time 53.24 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:58 PM PDT 24
Peak memory 243796 kb
Host smart-b01c385b-f123-4084-8a77-39eb4cad5cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602809263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.1602809263
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.240469816
Short name T127
Test name
Test status
Simulation time 1126039365214 ps
CPU time 3057.21 seconds
Started Jun 22 07:00:02 PM PDT 24
Finished Jun 22 07:51:02 PM PDT 24
Peak memory 409056 kb
Host smart-097286cd-bd16-4d9b-9138-23ebdb14e9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240469816 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.240469816
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.461107965
Short name T677
Test name
Test status
Simulation time 1373065156 ps
CPU time 22.78 seconds
Started Jun 22 07:00:00 PM PDT 24
Finished Jun 22 07:00:25 PM PDT 24
Peak memory 242152 kb
Host smart-4492f1c8-00d4-46b7-b255-b903cbb87c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461107965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.461107965
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.3564116267
Short name T416
Test name
Test status
Simulation time 153941208 ps
CPU time 1.79 seconds
Started Jun 22 07:00:05 PM PDT 24
Finished Jun 22 07:00:08 PM PDT 24
Peak memory 240936 kb
Host smart-499c78a1-d6a6-477c-9f77-7eb3315d067a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564116267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3564116267
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.3203844489
Short name T824
Test name
Test status
Simulation time 2181066726 ps
CPU time 34.92 seconds
Started Jun 22 07:00:01 PM PDT 24
Finished Jun 22 07:00:38 PM PDT 24
Peak memory 246664 kb
Host smart-d5c43e37-648d-48d9-9117-41c1a62c40d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203844489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3203844489
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2926100226
Short name T566
Test name
Test status
Simulation time 13374400024 ps
CPU time 34.79 seconds
Started Jun 22 07:00:02 PM PDT 24
Finished Jun 22 07:00:39 PM PDT 24
Peak memory 242808 kb
Host smart-b340a111-6e42-40ec-ac36-2b8c06c6c30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926100226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2926100226
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1940408668
Short name T203
Test name
Test status
Simulation time 1952417152 ps
CPU time 6.06 seconds
Started Jun 22 07:00:01 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242648 kb
Host smart-2bf691ac-afbb-45b9-8ddf-f31d6d5db73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940408668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1940408668
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1735312739
Short name T1130
Test name
Test status
Simulation time 1646276964 ps
CPU time 26.54 seconds
Started Jun 22 07:00:01 PM PDT 24
Finished Jun 22 07:00:30 PM PDT 24
Peak memory 248944 kb
Host smart-80094ef0-dffb-4bf3-9bef-703daf2fe1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735312739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1735312739
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3855572523
Short name T421
Test name
Test status
Simulation time 8503280888 ps
CPU time 23.97 seconds
Started Jun 22 07:00:01 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 243036 kb
Host smart-436f490f-6a48-469d-bd9b-9d34c1cb5ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855572523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3855572523
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.412595750
Short name T683
Test name
Test status
Simulation time 677874748 ps
CPU time 5.5 seconds
Started Jun 22 07:00:07 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242900 kb
Host smart-08017cd5-1e18-41a2-847b-558e05ef779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412595750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.412595750
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.4253873068
Short name T647
Test name
Test status
Simulation time 832295592 ps
CPU time 14.65 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 249008 kb
Host smart-289faf16-b54c-47c6-b4a2-6e4bcd3e619b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253873068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.4253873068
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.1094312526
Short name T1026
Test name
Test status
Simulation time 281987677 ps
CPU time 9.51 seconds
Started Jun 22 07:00:06 PM PDT 24
Finished Jun 22 07:00:17 PM PDT 24
Peak memory 242080 kb
Host smart-28770950-9434-49e3-b485-14752f0db0ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1094312526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1094312526
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.3336123270
Short name T436
Test name
Test status
Simulation time 1405890450 ps
CPU time 10.32 seconds
Started Jun 22 07:00:02 PM PDT 24
Finished Jun 22 07:00:15 PM PDT 24
Peak memory 242320 kb
Host smart-9c1b834e-b9a9-4250-b8e6-9a22b038509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336123270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.3336123270
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.336231958
Short name T756
Test name
Test status
Simulation time 711370664 ps
CPU time 4.21 seconds
Started Jun 22 07:00:03 PM PDT 24
Finished Jun 22 07:00:09 PM PDT 24
Peak memory 242656 kb
Host smart-573ab6f0-3283-4292-8243-7455571a0fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336231958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.336231958
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2993934094
Short name T304
Test name
Test status
Simulation time 155090648 ps
CPU time 2.83 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:00:16 PM PDT 24
Peak memory 241144 kb
Host smart-e17e07b2-2450-4fc0-9689-bb80f6502098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993934094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2993934094
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.3814201436
Short name T133
Test name
Test status
Simulation time 1464875556 ps
CPU time 24.92 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:37 PM PDT 24
Peak memory 247012 kb
Host smart-156c29d9-fbfc-417e-8bd3-4027108277f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814201436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3814201436
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.4111190671
Short name T666
Test name
Test status
Simulation time 227479390 ps
CPU time 12.49 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:26 PM PDT 24
Peak memory 242412 kb
Host smart-9cfc3aa7-6bb6-4fc3-94dd-87474339b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111190671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.4111190671
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2590011460
Short name T813
Test name
Test status
Simulation time 847302313 ps
CPU time 24.73 seconds
Started Jun 22 07:00:14 PM PDT 24
Finished Jun 22 07:00:41 PM PDT 24
Peak memory 242940 kb
Host smart-1cfb1072-f697-4dd2-95a8-1e9d7abba460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590011460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2590011460
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.3961680386
Short name T1185
Test name
Test status
Simulation time 335235956 ps
CPU time 3.3 seconds
Started Jun 22 07:00:14 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 242136 kb
Host smart-3375addb-2829-4859-87ac-db456231f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961680386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3961680386
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1381777972
Short name T149
Test name
Test status
Simulation time 1008824721 ps
CPU time 38.81 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:50 PM PDT 24
Peak memory 248992 kb
Host smart-70cf26d5-b9c4-45ae-ae0d-573622b1dc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381777972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1381777972
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.388943964
Short name T1040
Test name
Test status
Simulation time 1310530362 ps
CPU time 37.45 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:50 PM PDT 24
Peak memory 242696 kb
Host smart-155fc8ce-9265-478f-9c16-851b813e31bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388943964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.388943964
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2408862145
Short name T893
Test name
Test status
Simulation time 172667496 ps
CPU time 4.91 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:18 PM PDT 24
Peak memory 242088 kb
Host smart-0dab9254-62f0-4dcf-8fb1-83ad9a40d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408862145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2408862145
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1642322764
Short name T996
Test name
Test status
Simulation time 977948494 ps
CPU time 9.79 seconds
Started Jun 22 07:00:15 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 242548 kb
Host smart-26d3bfa1-716e-4384-bc31-8d69231ff15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1642322764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1642322764
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.669156226
Short name T871
Test name
Test status
Simulation time 4126417249 ps
CPU time 11.32 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:24 PM PDT 24
Peak memory 242128 kb
Host smart-ca8f1795-f46b-4ed5-a823-47a8267e5c9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=669156226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.669156226
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.1440215692
Short name T983
Test name
Test status
Simulation time 238789979 ps
CPU time 4.71 seconds
Started Jun 22 07:00:08 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242164 kb
Host smart-5ad8d08d-699d-4487-85f7-892ec2ed4a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440215692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1440215692
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.1224654100
Short name T678
Test name
Test status
Simulation time 13875251863 ps
CPU time 180.73 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:03:15 PM PDT 24
Peak memory 257332 kb
Host smart-73af55d9-a0ea-4f4d-90e2-52283bf553a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224654100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.1224654100
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.401177935
Short name T480
Test name
Test status
Simulation time 2802823316 ps
CPU time 14.61 seconds
Started Jun 22 07:00:13 PM PDT 24
Finished Jun 22 07:00:30 PM PDT 24
Peak memory 242380 kb
Host smart-27cb1b0b-a348-4099-a33a-843b77cb84bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401177935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.401177935
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.2015463582
Short name T1029
Test name
Test status
Simulation time 51651399 ps
CPU time 1.7 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:00:17 PM PDT 24
Peak memory 240976 kb
Host smart-04fa5054-c9c7-4429-bc2e-8bb149890285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015463582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2015463582
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.933642770
Short name T735
Test name
Test status
Simulation time 952160385 ps
CPU time 15.85 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:28 PM PDT 24
Peak memory 242316 kb
Host smart-a5bc6efc-fbda-4d12-95e4-6929c82cfe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933642770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.933642770
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1149569836
Short name T741
Test name
Test status
Simulation time 491725000 ps
CPU time 8.84 seconds
Started Jun 22 07:00:08 PM PDT 24
Finished Jun 22 07:00:18 PM PDT 24
Peak memory 242140 kb
Host smart-a981ec79-bb64-48bf-b013-69ada64bba83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149569836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1149569836
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3073139617
Short name T48
Test name
Test status
Simulation time 3180994651 ps
CPU time 6.1 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:19 PM PDT 24
Peak memory 242192 kb
Host smart-de09a9f6-12bd-4850-b977-31e5713623e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073139617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3073139617
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.2670411160
Short name T726
Test name
Test status
Simulation time 548317427 ps
CPU time 5.02 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:18 PM PDT 24
Peak memory 242220 kb
Host smart-be57c0b8-39b6-4ac2-9efc-cad0bf653420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670411160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2670411160
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.822966203
Short name T389
Test name
Test status
Simulation time 9380595679 ps
CPU time 19.44 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:30 PM PDT 24
Peak memory 242580 kb
Host smart-ce902448-adb3-4f06-8b60-036b9102937c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822966203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.822966203
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.4025926778
Short name T1063
Test name
Test status
Simulation time 988982591 ps
CPU time 6.57 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:18 PM PDT 24
Peak memory 242600 kb
Host smart-ed7d9a35-91a3-4baf-a040-efa5e956982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025926778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4025926778
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2491531963
Short name T564
Test name
Test status
Simulation time 12717635051 ps
CPU time 45.14 seconds
Started Jun 22 07:00:13 PM PDT 24
Finished Jun 22 07:01:01 PM PDT 24
Peak memory 242220 kb
Host smart-a6d94031-67da-4d96-823f-06b50f0b37ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491531963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2491531963
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.446705080
Short name T361
Test name
Test status
Simulation time 166027704 ps
CPU time 5.56 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:00:20 PM PDT 24
Peak memory 242200 kb
Host smart-3e9fc74d-27cb-4aeb-8c1d-1336c323bfff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446705080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.446705080
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.620753613
Short name T245
Test name
Test status
Simulation time 1814297336 ps
CPU time 10.48 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:23 PM PDT 24
Peak memory 242320 kb
Host smart-baebb740-d8bb-4b6a-9d79-2fd4ff8a48d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620753613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.620753613
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.564393162
Short name T385
Test name
Test status
Simulation time 57836459551 ps
CPU time 194.75 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:03:26 PM PDT 24
Peak memory 257332 kb
Host smart-9534be81-d8a7-4b6a-aa63-2ad98cef065d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564393162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.
564393162
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.817199557
Short name T379
Test name
Test status
Simulation time 78822552201 ps
CPU time 1242.2 seconds
Started Jun 22 07:00:09 PM PDT 24
Finished Jun 22 07:20:53 PM PDT 24
Peak memory 345988 kb
Host smart-76cb949e-22a0-42e9-828d-8c0de756bb84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817199557 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.817199557
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.688526008
Short name T1135
Test name
Test status
Simulation time 6648149521 ps
CPU time 38.46 seconds
Started Jun 22 07:00:13 PM PDT 24
Finished Jun 22 07:00:53 PM PDT 24
Peak memory 242824 kb
Host smart-5c813eaf-51fc-4611-b66d-b3d041ad792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688526008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.688526008
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2713420102
Short name T162
Test name
Test status
Simulation time 314635576 ps
CPU time 2.61 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:21 PM PDT 24
Peak memory 240924 kb
Host smart-101d9763-e0e1-4b5c-9348-47af6e9ce4b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713420102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2713420102
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3363763580
Short name T539
Test name
Test status
Simulation time 183542586 ps
CPU time 6.05 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:19 PM PDT 24
Peak memory 242212 kb
Host smart-20b3bb0e-4618-44ea-a00b-0b0cbeb251fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363763580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3363763580
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2061984091
Short name T578
Test name
Test status
Simulation time 1334835284 ps
CPU time 39.86 seconds
Started Jun 22 07:00:14 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 249064 kb
Host smart-e757bcbb-cc82-4d9c-8a59-80ed37475b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061984091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2061984091
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.3403646224
Short name T102
Test name
Test status
Simulation time 656117982 ps
CPU time 18.92 seconds
Started Jun 22 07:00:14 PM PDT 24
Finished Jun 22 07:00:35 PM PDT 24
Peak memory 242396 kb
Host smart-7dd54bbc-a08a-4a41-ae21-6f9015be3ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403646224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3403646224
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.3444458927
Short name T841
Test name
Test status
Simulation time 126972658 ps
CPU time 4.55 seconds
Started Jun 22 07:00:08 PM PDT 24
Finished Jun 22 07:00:14 PM PDT 24
Peak memory 242132 kb
Host smart-e49ff27b-d5cb-4968-aa1b-41167a592972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444458927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3444458927
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1340671001
Short name T249
Test name
Test status
Simulation time 225462012 ps
CPU time 5.99 seconds
Started Jun 22 07:00:11 PM PDT 24
Finished Jun 22 07:00:19 PM PDT 24
Peak memory 242196 kb
Host smart-09160b0c-db1c-4dd8-8471-237aedfe7a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340671001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1340671001
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.2344521280
Short name T463
Test name
Test status
Simulation time 1623686042 ps
CPU time 31.75 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:00:46 PM PDT 24
Peak memory 242916 kb
Host smart-40c6460f-d078-4e65-b6bd-022347f4f121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344521280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2344521280
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3882849141
Short name T533
Test name
Test status
Simulation time 138772905 ps
CPU time 4.4 seconds
Started Jun 22 07:00:12 PM PDT 24
Finished Jun 22 07:00:18 PM PDT 24
Peak memory 242192 kb
Host smart-2bb0e1c5-cf94-4498-b3eb-52af72ebddd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882849141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3882849141
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.2978634586
Short name T10
Test name
Test status
Simulation time 6318252846 ps
CPU time 18.96 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:31 PM PDT 24
Peak memory 242600 kb
Host smart-8edd3c5b-d43a-4258-a99d-9d1e8998276c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978634586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.2978634586
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3629950037
Short name T681
Test name
Test status
Simulation time 146709612 ps
CPU time 5.17 seconds
Started Jun 22 07:00:10 PM PDT 24
Finished Jun 22 07:00:17 PM PDT 24
Peak memory 242184 kb
Host smart-50082a1c-aade-48d5-b6f0-d5ef3b27749f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629950037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3629950037
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.2857965788
Short name T1059
Test name
Test status
Simulation time 613939656 ps
CPU time 4.47 seconds
Started Jun 22 07:00:15 PM PDT 24
Finished Jun 22 07:00:21 PM PDT 24
Peak memory 242256 kb
Host smart-accb4e1c-7ac4-4e35-84bd-4a52c46cc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857965788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2857965788
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3628963283
Short name T875
Test name
Test status
Simulation time 1062930110 ps
CPU time 19.91 seconds
Started Jun 22 07:00:13 PM PDT 24
Finished Jun 22 07:00:35 PM PDT 24
Peak memory 242396 kb
Host smart-7dca1066-c23e-4b2c-ac8b-e0baa8aa3965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628963283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3628963283
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.297995727
Short name T868
Test name
Test status
Simulation time 83133190 ps
CPU time 1.9 seconds
Started Jun 22 07:00:23 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 240904 kb
Host smart-8644d4c7-34d0-4040-a126-3e7ca1579c01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297995727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.297995727
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.1442120707
Short name T60
Test name
Test status
Simulation time 5878420119 ps
CPU time 13.79 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:35 PM PDT 24
Peak memory 242964 kb
Host smart-26f803bc-27dc-4598-b86a-eba63154fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442120707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1442120707
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3366517266
Short name T874
Test name
Test status
Simulation time 22385896462 ps
CPU time 53.38 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 254276 kb
Host smart-a12ad902-25c4-4f5a-9277-953979a514d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366517266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3366517266
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.1795703506
Short name T430
Test name
Test status
Simulation time 733563332 ps
CPU time 4.54 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 242476 kb
Host smart-4f0bc43c-7cd7-457a-a534-3ac26f1565ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795703506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1795703506
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.490161890
Short name T869
Test name
Test status
Simulation time 219390504 ps
CPU time 3.53 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 242184 kb
Host smart-b307eed3-a87b-4d69-aa54-07202c14daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490161890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.490161890
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.4129580669
Short name T1027
Test name
Test status
Simulation time 1359992194 ps
CPU time 11.42 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:00:34 PM PDT 24
Peak memory 243588 kb
Host smart-7a26ff7d-c042-4a6e-9ca2-16a499559bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129580669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.4129580669
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.3788722806
Short name T990
Test name
Test status
Simulation time 661562500 ps
CPU time 29.27 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 242624 kb
Host smart-0eeace79-d69b-47db-b051-62ed2868b768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788722806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3788722806
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.1914608215
Short name T689
Test name
Test status
Simulation time 168138717 ps
CPU time 3.52 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:24 PM PDT 24
Peak memory 242036 kb
Host smart-35d43be0-c9a6-4964-b5d0-6baa4b3f8117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914608215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1914608215
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.3850818626
Short name T458
Test name
Test status
Simulation time 323506434 ps
CPU time 11.21 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:33 PM PDT 24
Peak memory 242348 kb
Host smart-c839d0c0-2b74-44fa-a232-8b03d4a4be35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850818626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3850818626
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.705254917
Short name T368
Test name
Test status
Simulation time 431295740 ps
CPU time 5.43 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:27 PM PDT 24
Peak memory 242188 kb
Host smart-1e59963c-0ed4-473a-8900-f9964b7fa26d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705254917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.705254917
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.502809033
Short name T287
Test name
Test status
Simulation time 384618435 ps
CPU time 7.45 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:29 PM PDT 24
Peak memory 242188 kb
Host smart-812f8ec0-6e1e-4e36-a9d8-37ec7f2cf92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502809033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.502809033
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2157958255
Short name T339
Test name
Test status
Simulation time 14851961570 ps
CPU time 101.01 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:02:03 PM PDT 24
Peak memory 259108 kb
Host smart-6dad4251-2cc0-4dcd-84c0-5bf3621a911f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157958255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2157958255
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.964706395
Short name T265
Test name
Test status
Simulation time 85638430643 ps
CPU time 856.48 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:14:38 PM PDT 24
Peak memory 273796 kb
Host smart-43ac5b97-9876-49f4-ab48-b1dc97e16e8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964706395 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.964706395
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.1649050837
Short name T493
Test name
Test status
Simulation time 3774634929 ps
CPU time 25.83 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 243076 kb
Host smart-d27213b2-c6e0-4512-8e22-00ea32acfd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649050837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1649050837
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3484358769
Short name T1079
Test name
Test status
Simulation time 181944093 ps
CPU time 1.93 seconds
Started Jun 22 06:57:50 PM PDT 24
Finished Jun 22 06:57:54 PM PDT 24
Peak memory 240832 kb
Host smart-4fba2931-7a85-4d83-bb4f-f437cd16a686
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484358769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3484358769
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.528127048
Short name T999
Test name
Test status
Simulation time 1443405723 ps
CPU time 24.42 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:58:09 PM PDT 24
Peak memory 242616 kb
Host smart-9ce692e7-6e01-467f-a3ae-26b321f4ea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528127048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.528127048
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.1100805791
Short name T731
Test name
Test status
Simulation time 1543177075 ps
CPU time 11.02 seconds
Started Jun 22 06:57:42 PM PDT 24
Finished Jun 22 06:57:56 PM PDT 24
Peak memory 242536 kb
Host smart-c1b0a3bb-bf76-4643-b5eb-9044f7a500ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100805791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1100805791
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2349361893
Short name T822
Test name
Test status
Simulation time 1866415355 ps
CPU time 14.22 seconds
Started Jun 22 06:57:45 PM PDT 24
Finished Jun 22 06:58:02 PM PDT 24
Peak memory 242492 kb
Host smart-31425e21-4b25-49e9-9469-9f81576aa5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349361893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2349361893
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1713952365
Short name T466
Test name
Test status
Simulation time 11127307417 ps
CPU time 18.21 seconds
Started Jun 22 06:57:45 PM PDT 24
Finished Jun 22 06:58:06 PM PDT 24
Peak memory 243276 kb
Host smart-6fc87899-6630-4037-a1ac-4b1ba110a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713952365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1713952365
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.326003818
Short name T124
Test name
Test status
Simulation time 159734436 ps
CPU time 4.11 seconds
Started Jun 22 06:57:44 PM PDT 24
Finished Jun 22 06:57:50 PM PDT 24
Peak memory 242216 kb
Host smart-655b733a-8ef9-4f1a-86f9-d5a244423db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326003818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.326003818
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1818941285
Short name T152
Test name
Test status
Simulation time 2289942071 ps
CPU time 16.93 seconds
Started Jun 22 06:57:44 PM PDT 24
Finished Jun 22 06:58:03 PM PDT 24
Peak memory 243492 kb
Host smart-21cf7b73-322e-4703-99c8-e8501fcf5305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818941285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1818941285
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.2292874006
Short name T1118
Test name
Test status
Simulation time 10376929824 ps
CPU time 31.99 seconds
Started Jun 22 06:57:46 PM PDT 24
Finished Jun 22 06:58:21 PM PDT 24
Peak memory 243952 kb
Host smart-d4c06ef6-7adf-4be4-b218-4bfd040ab6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292874006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.2292874006
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.1120420650
Short name T426
Test name
Test status
Simulation time 595606572 ps
CPU time 16.47 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:58:01 PM PDT 24
Peak memory 242048 kb
Host smart-9a41fd24-cb13-4811-b503-2a3641f649c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120420650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1120420650
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.2144494752
Short name T1132
Test name
Test status
Simulation time 1279230987 ps
CPU time 21.05 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:58:06 PM PDT 24
Peak memory 242136 kb
Host smart-4ad91844-50d4-450e-8366-5eff947619e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2144494752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2144494752
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3533643194
Short name T977
Test name
Test status
Simulation time 274376747 ps
CPU time 7.88 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:57:53 PM PDT 24
Peak memory 242288 kb
Host smart-c0e41fd9-51d2-4569-b830-344b030fda54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3533643194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3533643194
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.3171031143
Short name T246
Test name
Test status
Simulation time 10018499402 ps
CPU time 169.18 seconds
Started Jun 22 06:57:49 PM PDT 24
Finished Jun 22 07:00:40 PM PDT 24
Peak memory 268828 kb
Host smart-71519204-4934-4fbb-b130-085d2be314f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171031143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3171031143
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1914539376
Short name T1157
Test name
Test status
Simulation time 2302175420 ps
CPU time 7.78 seconds
Started Jun 22 06:57:44 PM PDT 24
Finished Jun 22 06:57:54 PM PDT 24
Peak memory 242356 kb
Host smart-7253ff1f-8faa-4303-acde-68ad7fb3d985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914539376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1914539376
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.626430459
Short name T300
Test name
Test status
Simulation time 12455753714 ps
CPU time 36.33 seconds
Started Jun 22 06:57:43 PM PDT 24
Finished Jun 22 06:58:21 PM PDT 24
Peak memory 242944 kb
Host smart-7dfab50a-7f4d-4f9c-8831-d6fbebb29183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626430459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.626430459
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.4024471861
Short name T727
Test name
Test status
Simulation time 58282828 ps
CPU time 1.85 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:22 PM PDT 24
Peak memory 240672 kb
Host smart-02470d9c-1d4e-4e66-8703-f18d51eb933d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024471861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.4024471861
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2677706243
Short name T1055
Test name
Test status
Simulation time 9022265321 ps
CPU time 74.16 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:01:34 PM PDT 24
Peak memory 243308 kb
Host smart-0f7557e5-d06e-40e3-8775-b0bcde08a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677706243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2677706243
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.1715437277
Short name T1056
Test name
Test status
Simulation time 6141043123 ps
CPU time 51.51 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 253724 kb
Host smart-17b4235c-65a2-485a-a8b0-ce728267cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715437277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.1715437277
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1535913418
Short name T525
Test name
Test status
Simulation time 3301246602 ps
CPU time 27.49 seconds
Started Jun 22 07:00:22 PM PDT 24
Finished Jun 22 07:00:52 PM PDT 24
Peak memory 242272 kb
Host smart-d5edd171-0c82-4a91-9465-3f1869c6bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535913418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1535913418
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1900652470
Short name T407
Test name
Test status
Simulation time 2572766394 ps
CPU time 5.37 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:26 PM PDT 24
Peak memory 242372 kb
Host smart-e45c5a87-4b17-422d-ad91-b8e9a7485f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900652470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1900652470
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1128049289
Short name T745
Test name
Test status
Simulation time 1286842289 ps
CPU time 25.09 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:44 PM PDT 24
Peak memory 245868 kb
Host smart-b20ee829-98f4-46e9-8f47-2ddeb6ed0d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128049289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1128049289
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.818410642
Short name T894
Test name
Test status
Simulation time 6665384892 ps
CPU time 51.37 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 243384 kb
Host smart-7b4e8c0c-7186-4503-b028-519f22e77181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818410642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.818410642
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.906336477
Short name T842
Test name
Test status
Simulation time 618900304 ps
CPU time 9.63 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:29 PM PDT 24
Peak memory 242440 kb
Host smart-2d337fed-316b-4498-b311-497461d2e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906336477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.906336477
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.4149241269
Short name T218
Test name
Test status
Simulation time 1460586549 ps
CPU time 26.01 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:47 PM PDT 24
Peak memory 242164 kb
Host smart-f933af5f-d2ba-410f-b277-4617eaf0158c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4149241269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.4149241269
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.356588410
Short name T369
Test name
Test status
Simulation time 1274933497 ps
CPU time 9.21 seconds
Started Jun 22 07:00:22 PM PDT 24
Finished Jun 22 07:00:34 PM PDT 24
Peak memory 242512 kb
Host smart-b39dbf99-cafb-4421-ac3a-53bcaf7df551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356588410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.356588410
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3513425333
Short name T575
Test name
Test status
Simulation time 2048442354 ps
CPU time 16.81 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:39 PM PDT 24
Peak memory 242272 kb
Host smart-81adbedd-a921-4731-a0da-8fda2a02dc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513425333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3513425333
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2960710911
Short name T606
Test name
Test status
Simulation time 12487254117 ps
CPU time 111.54 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:02:14 PM PDT 24
Peak memory 252708 kb
Host smart-a1cd2b02-627c-4b88-822d-a80fb7281946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960710911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2960710911
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3328798295
Short name T538
Test name
Test status
Simulation time 78036425784 ps
CPU time 615.67 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:10:38 PM PDT 24
Peak memory 257436 kb
Host smart-71352954-6eed-4f6f-ae53-54e9e29172f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328798295 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3328798295
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.1496522363
Short name T546
Test name
Test status
Simulation time 8911185696 ps
CPU time 19.64 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:39 PM PDT 24
Peak memory 249080 kb
Host smart-91ef474f-46a3-41e4-99ed-4824d227ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496522363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.1496522363
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.2693051635
Short name T783
Test name
Test status
Simulation time 57296010 ps
CPU time 1.83 seconds
Started Jun 22 07:00:29 PM PDT 24
Finished Jun 22 07:00:34 PM PDT 24
Peak memory 240628 kb
Host smart-98f36f88-ffd2-4a56-8abb-38e26f4d71ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693051635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.2693051635
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2214278299
Short name T837
Test name
Test status
Simulation time 3759335567 ps
CPU time 35.67 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:57 PM PDT 24
Peak memory 244176 kb
Host smart-d915cdca-d4c2-4e15-84db-34f6d0296ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214278299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2214278299
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2502196104
Short name T886
Test name
Test status
Simulation time 930630179 ps
CPU time 8.11 seconds
Started Jun 22 07:00:20 PM PDT 24
Finished Jun 22 07:00:31 PM PDT 24
Peak memory 248952 kb
Host smart-71e2558f-5755-4266-ba9b-fb0a2bdb9aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502196104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2502196104
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.3696278905
Short name T592
Test name
Test status
Simulation time 194565055 ps
CPU time 4.34 seconds
Started Jun 22 07:00:17 PM PDT 24
Finished Jun 22 07:00:23 PM PDT 24
Peak memory 242092 kb
Host smart-6fc96622-1c4d-425e-b335-13ed73ceb7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696278905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3696278905
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1082716951
Short name T97
Test name
Test status
Simulation time 375832130 ps
CPU time 8.65 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:36 PM PDT 24
Peak memory 242224 kb
Host smart-f41a4840-b6d7-4459-a93b-bed13c38d89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082716951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1082716951
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.1716971797
Short name T1141
Test name
Test status
Simulation time 174986133 ps
CPU time 3.93 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:26 PM PDT 24
Peak memory 242504 kb
Host smart-bae7cf66-5182-4363-b010-6ef54db7abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716971797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1716971797
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.3329721826
Short name T942
Test name
Test status
Simulation time 1555703847 ps
CPU time 26.08 seconds
Started Jun 22 07:00:18 PM PDT 24
Finished Jun 22 07:00:48 PM PDT 24
Peak memory 242136 kb
Host smart-e81ceae5-9654-48ed-85e8-01bbef84483a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3329721826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3329721826
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.159789256
Short name T1140
Test name
Test status
Simulation time 407210711 ps
CPU time 12 seconds
Started Jun 22 07:00:26 PM PDT 24
Finished Jun 22 07:00:42 PM PDT 24
Peak memory 242544 kb
Host smart-db2f56fd-d9c3-41bb-9429-c2de46814748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=159789256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.159789256
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.2528891356
Short name T243
Test name
Test status
Simulation time 294464314 ps
CPU time 10.78 seconds
Started Jun 22 07:00:19 PM PDT 24
Finished Jun 22 07:00:33 PM PDT 24
Peak memory 242616 kb
Host smart-46b9d1f0-4114-4dc9-9b46-708c90a7e716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528891356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2528891356
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1766353282
Short name T255
Test name
Test status
Simulation time 116509408859 ps
CPU time 195.3 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:03:44 PM PDT 24
Peak memory 265508 kb
Host smart-c78c1d01-d220-4935-bf43-6b317d27e10e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766353282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1766353282
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.790907768
Short name T1119
Test name
Test status
Simulation time 17830381884 ps
CPU time 425.99 seconds
Started Jun 22 07:00:29 PM PDT 24
Finished Jun 22 07:07:39 PM PDT 24
Peak memory 257088 kb
Host smart-0c6b9127-d273-46e7-b021-bef2f7bdf7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790907768 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.790907768
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1214831780
Short name T18
Test name
Test status
Simulation time 2945370999 ps
CPU time 28.64 seconds
Started Jun 22 07:00:29 PM PDT 24
Finished Jun 22 07:01:01 PM PDT 24
Peak memory 242424 kb
Host smart-d9bdfd3c-615f-471f-8469-948792bf6216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214831780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1214831780
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.3442589977
Short name T571
Test name
Test status
Simulation time 693144677 ps
CPU time 1.97 seconds
Started Jun 22 07:00:26 PM PDT 24
Finished Jun 22 07:00:32 PM PDT 24
Peak memory 240944 kb
Host smart-2cb7db00-ace8-487c-8665-0eec6b77b93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442589977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3442589977
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.708484977
Short name T31
Test name
Test status
Simulation time 2153149977 ps
CPU time 13.79 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:41 PM PDT 24
Peak memory 242720 kb
Host smart-e83f5e38-cd73-4dea-a533-393c8c3c2572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708484977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.708484977
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.21250132
Short name T1146
Test name
Test status
Simulation time 991092483 ps
CPU time 24.18 seconds
Started Jun 22 07:00:27 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 243256 kb
Host smart-b0299404-7071-4070-8520-415b5895c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21250132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.21250132
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3558037565
Short name T512
Test name
Test status
Simulation time 602505960 ps
CPU time 4.01 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:33 PM PDT 24
Peak memory 242600 kb
Host smart-8241b427-694d-4634-9e68-28190cff8493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558037565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3558037565
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.1073964919
Short name T662
Test name
Test status
Simulation time 188145956 ps
CPU time 4.67 seconds
Started Jun 22 07:00:24 PM PDT 24
Finished Jun 22 07:00:32 PM PDT 24
Peak memory 242252 kb
Host smart-5aa1b0cf-3d01-4cd6-95d9-89cc3fae479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073964919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1073964919
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.3788581732
Short name T98
Test name
Test status
Simulation time 1007249613 ps
CPU time 8.92 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:38 PM PDT 24
Peak memory 249040 kb
Host smart-cdd596a2-ee69-4775-b3d7-362fe3a043a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788581732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3788581732
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.3905374916
Short name T135
Test name
Test status
Simulation time 2759341998 ps
CPU time 20.89 seconds
Started Jun 22 07:00:27 PM PDT 24
Finished Jun 22 07:00:52 PM PDT 24
Peak memory 243192 kb
Host smart-4d8fb184-1a70-4a43-a5d1-cc747da87174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905374916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3905374916
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.631547952
Short name T337
Test name
Test status
Simulation time 516601938 ps
CPU time 15.79 seconds
Started Jun 22 07:00:29 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 241800 kb
Host smart-50805cb6-eb62-4de7-ab41-84676f7dc71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631547952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.631547952
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.2367217010
Short name T514
Test name
Test status
Simulation time 366269408 ps
CPU time 8.19 seconds
Started Jun 22 07:00:26 PM PDT 24
Finished Jun 22 07:00:38 PM PDT 24
Peak memory 242168 kb
Host smart-0768ae1a-d001-4a8b-aa1a-f0ae14bbd984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367217010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2367217010
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3693317098
Short name T1171
Test name
Test status
Simulation time 203168981 ps
CPU time 5.79 seconds
Started Jun 22 07:00:27 PM PDT 24
Finished Jun 22 07:00:37 PM PDT 24
Peak memory 242260 kb
Host smart-74d293b2-dec2-4057-88ee-5cc24b7f174b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3693317098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3693317098
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1396311005
Short name T1151
Test name
Test status
Simulation time 945450964 ps
CPU time 8.72 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:38 PM PDT 24
Peak memory 242212 kb
Host smart-60488992-fbd3-4ce4-9920-21b377123b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396311005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1396311005
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.1359274026
Short name T296
Test name
Test status
Simulation time 78594973972 ps
CPU time 274.83 seconds
Started Jun 22 07:00:26 PM PDT 24
Finished Jun 22 07:05:05 PM PDT 24
Peak memory 257308 kb
Host smart-6cb4cff6-c562-4ba6-a6aa-1d5686e9856c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359274026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.1359274026
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.2495792536
Short name T812
Test name
Test status
Simulation time 1120369210188 ps
CPU time 2706.81 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:45:36 PM PDT 24
Peak memory 681580 kb
Host smart-05cd7f8a-4779-48cb-aed8-049dffe660c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495792536 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.2495792536
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.917476397
Short name T900
Test name
Test status
Simulation time 2220283121 ps
CPU time 35 seconds
Started Jun 22 07:00:29 PM PDT 24
Finished Jun 22 07:01:08 PM PDT 24
Peak memory 242676 kb
Host smart-c3f52bd8-c792-42ee-b5fa-668dd305ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917476397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.917476397
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2142967102
Short name T664
Test name
Test status
Simulation time 739671581 ps
CPU time 2.98 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:41 PM PDT 24
Peak memory 240696 kb
Host smart-da04bd83-9587-4bd0-9be8-252ce52d606a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142967102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2142967102
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3102716945
Short name T948
Test name
Test status
Simulation time 7380915837 ps
CPU time 24.23 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 243524 kb
Host smart-51c97e01-c079-4882-8d80-f40fb1242f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102716945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3102716945
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.1410106047
Short name T1086
Test name
Test status
Simulation time 3833805980 ps
CPU time 42.02 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:01:20 PM PDT 24
Peak memory 246796 kb
Host smart-ea405486-f394-4466-b13a-2298244d3d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410106047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1410106047
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.869316208
Short name T380
Test name
Test status
Simulation time 4064257477 ps
CPU time 17.8 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:57 PM PDT 24
Peak memory 242592 kb
Host smart-d0945932-97cb-4096-b413-7fc5c3da3d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869316208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.869316208
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.2356134738
Short name T160
Test name
Test status
Simulation time 246390083 ps
CPU time 3.29 seconds
Started Jun 22 07:00:27 PM PDT 24
Finished Jun 22 07:00:34 PM PDT 24
Peak memory 242396 kb
Host smart-a5a3aeee-cb27-44e9-8f5c-817f9bf6f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356134738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2356134738
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.501510210
Short name T821
Test name
Test status
Simulation time 1728786847 ps
CPU time 21.45 seconds
Started Jun 22 07:00:38 PM PDT 24
Finished Jun 22 07:01:01 PM PDT 24
Peak memory 242880 kb
Host smart-914111e0-82da-4bc2-a598-31aeb5d82ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501510210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.501510210
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.706388594
Short name T620
Test name
Test status
Simulation time 16036137498 ps
CPU time 36.27 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:01:15 PM PDT 24
Peak memory 242368 kb
Host smart-8b02c2e7-0a5c-4cfc-a99e-ab34897ede8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706388594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.706388594
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.1797725664
Short name T884
Test name
Test status
Simulation time 3674486464 ps
CPU time 24.63 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:52 PM PDT 24
Peak memory 242208 kb
Host smart-ee2bc499-ece1-4d01-b2cb-e66739bcef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797725664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1797725664
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2310891210
Short name T468
Test name
Test status
Simulation time 14116064323 ps
CPU time 34.67 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:01:02 PM PDT 24
Peak memory 242380 kb
Host smart-7f089e62-d4b8-4fd6-b9f7-7158b0c46560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2310891210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2310891210
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.475675750
Short name T363
Test name
Test status
Simulation time 2717837017 ps
CPU time 9.49 seconds
Started Jun 22 07:00:39 PM PDT 24
Finished Jun 22 07:00:50 PM PDT 24
Peak memory 242520 kb
Host smart-5c2ae0d0-5c9e-4a87-a813-ed3552889ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=475675750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.475675750
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.538108154
Short name T444
Test name
Test status
Simulation time 306911837 ps
CPU time 7.85 seconds
Started Jun 22 07:00:25 PM PDT 24
Finished Jun 22 07:00:36 PM PDT 24
Peak memory 242260 kb
Host smart-aaf4b7c7-cef2-431f-9255-e4af8a479695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538108154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.538108154
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.2950984030
Short name T762
Test name
Test status
Simulation time 12484299845 ps
CPU time 176.08 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:03:34 PM PDT 24
Peak memory 262824 kb
Host smart-5bea1fc8-1d35-433f-8c57-1bfdd3e76c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950984030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.2950984030
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1330056626
Short name T703
Test name
Test status
Simulation time 1009941391 ps
CPU time 11.58 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:50 PM PDT 24
Peak memory 242548 kb
Host smart-ad049f30-ad8a-4d55-bbfd-5c9bb9093afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330056626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1330056626
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.835654256
Short name T1002
Test name
Test status
Simulation time 136762815 ps
CPU time 1.98 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:40 PM PDT 24
Peak memory 240828 kb
Host smart-221004f5-7f13-437b-a4af-7b7dc064ab57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835654256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.835654256
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.3756739029
Short name T1051
Test name
Test status
Simulation time 458027155 ps
CPU time 5.15 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:43 PM PDT 24
Peak memory 242216 kb
Host smart-73df59ee-603c-4b15-a835-7de703cf72f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756739029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3756739029
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.109336988
Short name T969
Test name
Test status
Simulation time 665685763 ps
CPU time 12.66 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:51 PM PDT 24
Peak memory 242264 kb
Host smart-81436d33-c341-4ae5-b868-f8a361e4be9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109336988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.109336988
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.548511784
Short name T502
Test name
Test status
Simulation time 563548307 ps
CPU time 9.38 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:48 PM PDT 24
Peak memory 242348 kb
Host smart-654b1b51-efc1-4ada-87be-9b2847a0824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548511784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.548511784
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1467712998
Short name T582
Test name
Test status
Simulation time 113734988 ps
CPU time 3.03 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:41 PM PDT 24
Peak memory 242260 kb
Host smart-89d1cc07-9f3b-48b2-8792-25cb4ef786c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467712998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1467712998
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.864454802
Short name T1167
Test name
Test status
Simulation time 2173739597 ps
CPU time 12.15 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:51 PM PDT 24
Peak memory 242880 kb
Host smart-d0948a25-c662-40b0-b65a-f1016d9e6904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864454802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.864454802
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2901282119
Short name T1012
Test name
Test status
Simulation time 1278052908 ps
CPU time 33.72 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:01:13 PM PDT 24
Peak memory 242152 kb
Host smart-feb33c5a-c4f7-4e16-9c49-90d308b5a9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901282119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2901282119
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1588941391
Short name T941
Test name
Test status
Simulation time 1798876507 ps
CPU time 23.22 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242544 kb
Host smart-f760f37f-1c55-4d5c-803c-a6406c32bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588941391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1588941391
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.2236753364
Short name T1042
Test name
Test status
Simulation time 569202557 ps
CPU time 17.16 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 242136 kb
Host smart-56a1f0e0-f671-44ec-a92b-c47b8a220487
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236753364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2236753364
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.3867750169
Short name T364
Test name
Test status
Simulation time 1033222582 ps
CPU time 9.51 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:47 PM PDT 24
Peak memory 242184 kb
Host smart-897534a1-2266-4527-91f9-61978d76f546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3867750169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3867750169
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.3623609167
Short name T522
Test name
Test status
Simulation time 324221743 ps
CPU time 9.51 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:48 PM PDT 24
Peak memory 242176 kb
Host smart-186138a0-ea2d-448b-a2ca-219b9a6ce529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623609167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.3623609167
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3899734706
Short name T387
Test name
Test status
Simulation time 3225098147 ps
CPU time 19.72 seconds
Started Jun 22 07:00:41 PM PDT 24
Finished Jun 22 07:01:02 PM PDT 24
Peak memory 242848 kb
Host smart-0b8ce63f-5463-4ce1-83b6-b05646ac1ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899734706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3899734706
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2922137742
Short name T1131
Test name
Test status
Simulation time 180171732318 ps
CPU time 632.98 seconds
Started Jun 22 07:00:38 PM PDT 24
Finished Jun 22 07:11:14 PM PDT 24
Peak memory 267880 kb
Host smart-e2df6491-235b-4939-bd7a-a2923f2d5ce6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922137742 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2922137742
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.1504264230
Short name T530
Test name
Test status
Simulation time 7396310588 ps
CPU time 17.13 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:00:57 PM PDT 24
Peak memory 243276 kb
Host smart-59ca7bd8-b50a-497f-94f8-4ae623979e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504264230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.1504264230
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2673633530
Short name T627
Test name
Test status
Simulation time 1011039219 ps
CPU time 2.69 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:00:50 PM PDT 24
Peak memory 240912 kb
Host smart-40429029-4e05-46bb-b901-b83d46c0f4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673633530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2673633530
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.2081951097
Short name T1028
Test name
Test status
Simulation time 1066159389 ps
CPU time 9.22 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:47 PM PDT 24
Peak memory 249044 kb
Host smart-65a789db-6850-4cc1-861b-1e597036189a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081951097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2081951097
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.2993178030
Short name T495
Test name
Test status
Simulation time 496310769 ps
CPU time 11.48 seconds
Started Jun 22 07:00:35 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 242440 kb
Host smart-d1e41a1c-1cb0-4664-8025-ff5fdb2a3d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993178030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.2993178030
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.619359647
Short name T740
Test name
Test status
Simulation time 2873322302 ps
CPU time 21.73 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:01:01 PM PDT 24
Peak memory 242272 kb
Host smart-cdac86c4-7f4b-4d42-9922-89d751f637af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619359647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.619359647
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.2720044323
Short name T897
Test name
Test status
Simulation time 2839391159 ps
CPU time 5.85 seconds
Started Jun 22 07:00:39 PM PDT 24
Finished Jun 22 07:00:47 PM PDT 24
Peak memory 242204 kb
Host smart-de3440cf-261a-442b-bfd2-a18501cd602b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720044323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2720044323
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3907114859
Short name T69
Test name
Test status
Simulation time 8092431203 ps
CPU time 15.85 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242664 kb
Host smart-cc5d3c94-34f4-4561-b0e3-7f940e8c31fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907114859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3907114859
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1009667707
Short name T520
Test name
Test status
Simulation time 2581025210 ps
CPU time 31.7 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:01:19 PM PDT 24
Peak memory 249068 kb
Host smart-544c41f0-9cf0-4f24-94e5-e720c7c2d20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009667707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1009667707
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1977375133
Short name T516
Test name
Test status
Simulation time 1786684562 ps
CPU time 5.4 seconds
Started Jun 22 07:00:36 PM PDT 24
Finished Jun 22 07:00:45 PM PDT 24
Peak memory 242264 kb
Host smart-442a43f6-931e-4c51-ab03-aadb8e342816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977375133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1977375133
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2127819378
Short name T388
Test name
Test status
Simulation time 1822598102 ps
CPU time 24.37 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 242184 kb
Host smart-132a834b-8aad-440b-81d0-678616368815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127819378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2127819378
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.1816740055
Short name T110
Test name
Test status
Simulation time 429188408 ps
CPU time 4.06 seconds
Started Jun 22 07:00:45 PM PDT 24
Finished Jun 22 07:00:55 PM PDT 24
Peak memory 242256 kb
Host smart-457eac64-3f0c-429d-9dbf-aade03c28bba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1816740055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.1816740055
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.557219696
Short name T442
Test name
Test status
Simulation time 710971896 ps
CPU time 9.24 seconds
Started Jun 22 07:00:37 PM PDT 24
Finished Jun 22 07:00:49 PM PDT 24
Peak memory 242092 kb
Host smart-31353a0e-7194-4fdb-944c-7dbe7a179703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557219696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.557219696
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.98140768
Short name T854
Test name
Test status
Simulation time 84475691848 ps
CPU time 160.04 seconds
Started Jun 22 07:00:42 PM PDT 24
Finished Jun 22 07:03:24 PM PDT 24
Peak memory 265512 kb
Host smart-a81abf47-8955-4d6e-bce0-38b478e2be39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98140768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.98140768
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.2199284177
Short name T342
Test name
Test status
Simulation time 1510517049 ps
CPU time 32.11 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:01:27 PM PDT 24
Peak memory 242704 kb
Host smart-2e6b706e-f576-4c42-adc1-3f910f529c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199284177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.2199284177
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.666712820
Short name T1046
Test name
Test status
Simulation time 146023207 ps
CPU time 2.17 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:00:54 PM PDT 24
Peak memory 240632 kb
Host smart-07fc9b55-ef21-4325-a180-1f80e6e07860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666712820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.666712820
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.1052562773
Short name T399
Test name
Test status
Simulation time 213145492 ps
CPU time 9.84 seconds
Started Jun 22 07:00:47 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242304 kb
Host smart-d1078983-9f81-49a5-ae97-732a6006df8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052562773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1052562773
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.4060956765
Short name T1177
Test name
Test status
Simulation time 877432873 ps
CPU time 25.44 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:01:20 PM PDT 24
Peak memory 242544 kb
Host smart-5d1996fa-3fc9-420a-9018-44a2875307ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060956765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.4060956765
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.401410975
Short name T903
Test name
Test status
Simulation time 1801699797 ps
CPU time 3.33 seconds
Started Jun 22 07:00:47 PM PDT 24
Finished Jun 22 07:00:57 PM PDT 24
Peak memory 242428 kb
Host smart-2382baff-2b68-4ebf-b4f6-fbeb75964cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401410975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.401410975
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3305661258
Short name T1178
Test name
Test status
Simulation time 1209379233 ps
CPU time 9.64 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:00:54 PM PDT 24
Peak memory 242736 kb
Host smart-32afe5d1-2f4d-453b-a583-d431a526956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305661258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3305661258
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.2690799507
Short name T1016
Test name
Test status
Simulation time 853677163 ps
CPU time 8.9 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 242548 kb
Host smart-0dfee88e-bd9f-4bc1-bcb6-f51ff84e388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690799507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2690799507
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1241086746
Short name T1090
Test name
Test status
Simulation time 980346633 ps
CPU time 11.23 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 242544 kb
Host smart-6911385f-79d8-4fc9-9d93-65e6285cdce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241086746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1241086746
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.2979131593
Short name T700
Test name
Test status
Simulation time 2730719925 ps
CPU time 23.9 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:01:11 PM PDT 24
Peak memory 242324 kb
Host smart-55b149c7-8dd6-4362-8182-ddd915c0f342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979131593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.2979131593
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.2768286563
Short name T980
Test name
Test status
Simulation time 826907374 ps
CPU time 11.16 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 242284 kb
Host smart-863b952d-7fd4-4556-9545-c2a189c88a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768286563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2768286563
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.2497384087
Short name T1048
Test name
Test status
Simulation time 1966677068 ps
CPU time 5.74 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:01:01 PM PDT 24
Peak memory 242080 kb
Host smart-1a9ead1e-72a9-44a4-b533-5871d319645e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497384087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.2497384087
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.488774621
Short name T299
Test name
Test status
Simulation time 65625156194 ps
CPU time 263.59 seconds
Started Jun 22 07:00:45 PM PDT 24
Finished Jun 22 07:05:14 PM PDT 24
Peak memory 258436 kb
Host smart-058ce4a1-eabd-4840-824d-c05d72589c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488774621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
488774621
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.437172939
Short name T954
Test name
Test status
Simulation time 116680396038 ps
CPU time 2190.57 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:37:26 PM PDT 24
Peak memory 302684 kb
Host smart-6db3218e-1882-4e42-b686-a2f487277df0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437172939 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.437172939
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.594528960
Short name T998
Test name
Test status
Simulation time 1193294704 ps
CPU time 7.5 seconds
Started Jun 22 07:00:45 PM PDT 24
Finished Jun 22 07:00:57 PM PDT 24
Peak memory 242216 kb
Host smart-925064e7-f0f8-42cb-ac4b-277b8b0d0d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594528960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.594528960
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1941963170
Short name T793
Test name
Test status
Simulation time 68279603 ps
CPU time 1.77 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:00:58 PM PDT 24
Peak memory 240624 kb
Host smart-d9edf497-095c-4b3f-9df7-180925d20b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941963170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1941963170
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.3390173700
Short name T917
Test name
Test status
Simulation time 401172525 ps
CPU time 3.14 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:00:52 PM PDT 24
Peak memory 242212 kb
Host smart-600f517b-3b67-477c-8c46-f64032ea8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390173700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3390173700
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.13260879
Short name T1124
Test name
Test status
Simulation time 780193650 ps
CPU time 23.65 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:01:15 PM PDT 24
Peak memory 242256 kb
Host smart-67c2c721-b791-4a64-a5db-ea51a3a2e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13260879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.13260879
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.70154230
Short name T1179
Test name
Test status
Simulation time 427276358 ps
CPU time 8.83 seconds
Started Jun 22 07:00:42 PM PDT 24
Finished Jun 22 07:00:53 PM PDT 24
Peak memory 242360 kb
Host smart-a261409d-481a-45c3-9915-fcb7fb82e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70154230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.70154230
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.1609043088
Short name T470
Test name
Test status
Simulation time 222859999 ps
CPU time 5.46 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:00:51 PM PDT 24
Peak memory 242152 kb
Host smart-ba6aff4e-939f-4902-a50b-2e903e02e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609043088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1609043088
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1880756564
Short name T411
Test name
Test status
Simulation time 391315734 ps
CPU time 7.88 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:01:00 PM PDT 24
Peak memory 242088 kb
Host smart-ffb5544d-b25e-4bf0-9c67-950b2c86dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880756564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1880756564
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.820051682
Short name T271
Test name
Test status
Simulation time 13410163760 ps
CPU time 28.76 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:01:20 PM PDT 24
Peak memory 242276 kb
Host smart-ea0adfab-9d43-4f95-ba17-0b9a0023e539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820051682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.820051682
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.586391528
Short name T775
Test name
Test status
Simulation time 378636347 ps
CPU time 11.34 seconds
Started Jun 22 07:00:48 PM PDT 24
Finished Jun 22 07:01:06 PM PDT 24
Peak memory 242196 kb
Host smart-94dd8728-ca9f-45a1-b1bd-45f077075053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=586391528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.586391528
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.3007027129
Short name T402
Test name
Test status
Simulation time 1559790098 ps
CPU time 11.66 seconds
Started Jun 22 07:00:48 PM PDT 24
Finished Jun 22 07:01:06 PM PDT 24
Peak memory 242584 kb
Host smart-65cbc593-1d8d-4391-8ecc-7a25c4d9bf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007027129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.3007027129
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.2485315870
Short name T428
Test name
Test status
Simulation time 394257923 ps
CPU time 11.97 seconds
Started Jun 22 07:00:43 PM PDT 24
Finished Jun 22 07:00:58 PM PDT 24
Peak memory 242496 kb
Host smart-24f0b185-ac50-45fa-b079-1c3650cd4998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485315870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2485315870
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1747883183
Short name T600
Test name
Test status
Simulation time 693184450 ps
CPU time 2.1 seconds
Started Jun 22 07:00:52 PM PDT 24
Finished Jun 22 07:01:00 PM PDT 24
Peak memory 240824 kb
Host smart-6ede649d-9838-4325-a680-813e0a71fa15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747883183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1747883183
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1884461541
Short name T351
Test name
Test status
Simulation time 262896846 ps
CPU time 3.55 seconds
Started Jun 22 07:00:45 PM PDT 24
Finished Jun 22 07:00:53 PM PDT 24
Peak memory 242164 kb
Host smart-75de7037-8e93-4c9b-886b-9f8b7a5928f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884461541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1884461541
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.1059644206
Short name T529
Test name
Test status
Simulation time 423020801 ps
CPU time 13.65 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:01:02 PM PDT 24
Peak memory 242152 kb
Host smart-b31e88a3-c4e8-4bd0-98e0-36a33667f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059644206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1059644206
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.1223602122
Short name T622
Test name
Test status
Simulation time 878102632 ps
CPU time 17.74 seconds
Started Jun 22 07:00:47 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 242260 kb
Host smart-819b0372-ea54-4359-bdea-811c7d600e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223602122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.1223602122
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.2259606553
Short name T1155
Test name
Test status
Simulation time 145878451 ps
CPU time 4.37 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:00:56 PM PDT 24
Peak memory 242148 kb
Host smart-a639ef80-341a-44b0-b1d8-8b7625d153d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259606553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.2259606553
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1149707398
Short name T749
Test name
Test status
Simulation time 724202812 ps
CPU time 19.98 seconds
Started Jun 22 07:00:47 PM PDT 24
Finished Jun 22 07:01:13 PM PDT 24
Peak memory 245508 kb
Host smart-7678471f-d147-4b46-9579-732929ccdbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149707398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1149707398
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.667775939
Short name T863
Test name
Test status
Simulation time 7394420916 ps
CPU time 22.87 seconds
Started Jun 22 07:00:44 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 243808 kb
Host smart-dc910051-f3f1-48ae-b56e-fa1ef740c32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667775939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.667775939
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.3227640845
Short name T108
Test name
Test status
Simulation time 135604808 ps
CPU time 4.75 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:01:00 PM PDT 24
Peak memory 242676 kb
Host smart-60be2f31-98b1-4d80-9f34-2bc23610350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227640845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.3227640845
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.640082334
Short name T1166
Test name
Test status
Simulation time 856333680 ps
CPU time 11.56 seconds
Started Jun 22 07:00:46 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 242548 kb
Host smart-e16a9180-86b7-4d8e-8242-b5dbe55a8aef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640082334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.640082334
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.3837637004
Short name T710
Test name
Test status
Simulation time 141076367 ps
CPU time 4.76 seconds
Started Jun 22 07:00:48 PM PDT 24
Finished Jun 22 07:00:59 PM PDT 24
Peak memory 242212 kb
Host smart-48674c95-3afa-4dc2-bbcf-f2940bbd7dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837637004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.3837637004
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.739214226
Short name T957
Test name
Test status
Simulation time 3198422171 ps
CPU time 10.98 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:07 PM PDT 24
Peak memory 248248 kb
Host smart-8c51f5f6-9903-4eb5-a6d1-9f930b122d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739214226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
739214226
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.2089552694
Short name T1092
Test name
Test status
Simulation time 64295713960 ps
CPU time 1101.72 seconds
Started Jun 22 07:00:52 PM PDT 24
Finished Jun 22 07:19:20 PM PDT 24
Peak memory 265564 kb
Host smart-a16b3bfa-39c2-49fc-bc5e-a31e639d9823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089552694 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.2089552694
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.3968124473
Short name T624
Test name
Test status
Simulation time 12220741301 ps
CPU time 25.99 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:22 PM PDT 24
Peak memory 249152 kb
Host smart-1e9e9ad8-3d27-4504-a771-312bd1d5a09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968124473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3968124473
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.3798666966
Short name T927
Test name
Test status
Simulation time 145487407 ps
CPU time 2.78 seconds
Started Jun 22 07:00:51 PM PDT 24
Finished Jun 22 07:01:00 PM PDT 24
Peak memory 240960 kb
Host smart-c62ed2af-b805-4fe4-84f9-dc34a8446400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798666966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.3798666966
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.3464661105
Short name T115
Test name
Test status
Simulation time 2821021258 ps
CPU time 26.11 seconds
Started Jun 22 07:00:55 PM PDT 24
Finished Jun 22 07:01:27 PM PDT 24
Peak memory 242420 kb
Host smart-f432e34a-2b23-4b84-8ce4-00d799ab814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464661105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3464661105
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.4046082142
Short name T733
Test name
Test status
Simulation time 281930629 ps
CPU time 17.61 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242052 kb
Host smart-60a2bd84-426f-46c2-b3ed-e3c32c34d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046082142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4046082142
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.1939597039
Short name T1022
Test name
Test status
Simulation time 1070258046 ps
CPU time 12.37 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:08 PM PDT 24
Peak memory 242704 kb
Host smart-6a06b6d8-817e-401a-a936-1f10e6fbc49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939597039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.1939597039
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.3197336386
Short name T862
Test name
Test status
Simulation time 2007898665 ps
CPU time 27.29 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:24 PM PDT 24
Peak memory 243128 kb
Host smart-a1e008a6-2da0-4a9c-9ec3-7f033e5a9cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197336386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3197336386
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.3398328492
Short name T982
Test name
Test status
Simulation time 189263314 ps
CPU time 6.08 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:05 PM PDT 24
Peak memory 242260 kb
Host smart-6aa34e8f-b06c-4a1b-b55e-ac44c0b54e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398328492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.3398328492
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.384775694
Short name T855
Test name
Test status
Simulation time 1311005537 ps
CPU time 4.04 seconds
Started Jun 22 07:00:52 PM PDT 24
Finished Jun 22 07:01:02 PM PDT 24
Peak memory 242108 kb
Host smart-f88f2369-f9f7-4367-885f-1a7d9a4785f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384775694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.384775694
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1296738283
Short name T487
Test name
Test status
Simulation time 432289286 ps
CPU time 6.82 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:06 PM PDT 24
Peak memory 242608 kb
Host smart-a46cdc89-e6b4-415a-b753-e73ebefbcb80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296738283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1296738283
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.2416191982
Short name T420
Test name
Test status
Simulation time 108870323 ps
CPU time 4.19 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242228 kb
Host smart-a3b7db81-89bf-45f4-b4af-ccabb361bfe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416191982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2416191982
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2262374848
Short name T908
Test name
Test status
Simulation time 6520327734 ps
CPU time 10.01 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:09 PM PDT 24
Peak memory 242296 kb
Host smart-c51f61a4-2d9e-4b77-af87-ab82521de6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262374848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2262374848
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1653769499
Short name T234
Test name
Test status
Simulation time 67509900189 ps
CPU time 249.05 seconds
Started Jun 22 07:00:48 PM PDT 24
Finished Jun 22 07:05:04 PM PDT 24
Peak memory 257404 kb
Host smart-690d08cf-cefb-4abf-b767-e75c6fe7a70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653769499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1653769499
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3948116456
Short name T763
Test name
Test status
Simulation time 642154293833 ps
CPU time 1347.75 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:23:24 PM PDT 24
Peak memory 375312 kb
Host smart-414843ae-b7b2-4fb6-9da3-0c7b2e76a83d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948116456 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.3948116456
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.562614237
Short name T951
Test name
Test status
Simulation time 10819440417 ps
CPU time 56.52 seconds
Started Jun 22 07:00:51 PM PDT 24
Finished Jun 22 07:01:54 PM PDT 24
Peak memory 242908 kb
Host smart-eb8ac050-cbd8-44b0-9e08-c81bc44154e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562614237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.562614237
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2636236925
Short name T240
Test name
Test status
Simulation time 172758595 ps
CPU time 2.24 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:03 PM PDT 24
Peak memory 240876 kb
Host smart-8c600b6e-e8fd-4d70-910c-7ae84d0e03bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636236925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2636236925
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.4124245102
Short name T123
Test name
Test status
Simulation time 1839758718 ps
CPU time 13.93 seconds
Started Jun 22 06:57:51 PM PDT 24
Finished Jun 22 06:58:06 PM PDT 24
Peak memory 242156 kb
Host smart-10a8b47a-918d-4e54-aa9e-16480a63a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124245102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.4124245102
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.270065289
Short name T51
Test name
Test status
Simulation time 1915925008 ps
CPU time 20.02 seconds
Started Jun 22 06:57:49 PM PDT 24
Finished Jun 22 06:58:10 PM PDT 24
Peak memory 244048 kb
Host smart-07c7f8c9-7c94-4954-bb88-1e60b16e5218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270065289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.270065289
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1135084301
Short name T831
Test name
Test status
Simulation time 4163703899 ps
CPU time 30.92 seconds
Started Jun 22 06:57:51 PM PDT 24
Finished Jun 22 06:58:23 PM PDT 24
Peak memory 247864 kb
Host smart-ce2ca61c-fb5a-4d33-b729-2ec4449c8dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135084301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1135084301
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.3222059517
Short name T655
Test name
Test status
Simulation time 4130898102 ps
CPU time 47.26 seconds
Started Jun 22 06:57:52 PM PDT 24
Finished Jun 22 06:58:41 PM PDT 24
Peak memory 242768 kb
Host smart-88f426ee-9624-4438-ac52-ca79757acc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222059517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.3222059517
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.1322664215
Short name T1169
Test name
Test status
Simulation time 596916298 ps
CPU time 7.43 seconds
Started Jun 22 06:57:51 PM PDT 24
Finished Jun 22 06:58:00 PM PDT 24
Peak memory 243636 kb
Host smart-33b3642d-9107-48e0-971d-22809abd423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322664215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.1322664215
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.4256060426
Short name T1053
Test name
Test status
Simulation time 1464322815 ps
CPU time 23.2 seconds
Started Jun 22 06:57:50 PM PDT 24
Finished Jun 22 06:58:15 PM PDT 24
Peak memory 242132 kb
Host smart-de61a066-2407-4002-904b-8ab30c89cacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256060426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.4256060426
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.2054980314
Short name T503
Test name
Test status
Simulation time 288948173 ps
CPU time 4.14 seconds
Started Jun 22 06:57:49 PM PDT 24
Finished Jun 22 06:57:55 PM PDT 24
Peak memory 242068 kb
Host smart-be07c632-2ce5-46fc-8473-3458d10f5c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054980314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2054980314
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3947323396
Short name T95
Test name
Test status
Simulation time 4287846176 ps
CPU time 9.88 seconds
Started Jun 22 06:57:51 PM PDT 24
Finished Jun 22 06:58:03 PM PDT 24
Peak memory 242260 kb
Host smart-58930fcc-4f75-4e93-8dc5-e36e6b83dc49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947323396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3947323396
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.588994929
Short name T1089
Test name
Test status
Simulation time 269294388 ps
CPU time 5.37 seconds
Started Jun 22 06:57:50 PM PDT 24
Finished Jun 22 06:57:57 PM PDT 24
Peak memory 242284 kb
Host smart-3b4b8f91-3496-43ca-979e-efb374aa9403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588994929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.588994929
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.651871617
Short name T1006
Test name
Test status
Simulation time 308208195 ps
CPU time 4.55 seconds
Started Jun 22 06:57:49 PM PDT 24
Finished Jun 22 06:57:56 PM PDT 24
Peak memory 242248 kb
Host smart-3f7c342b-f29b-46c4-81e0-a122d73ef802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651871617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.651871617
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2182324374
Short name T915
Test name
Test status
Simulation time 8172421556 ps
CPU time 95.31 seconds
Started Jun 22 06:58:02 PM PDT 24
Finished Jun 22 06:59:38 PM PDT 24
Peak memory 249016 kb
Host smart-f67d3467-c500-4db1-b3b6-0675794b1f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182324374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2182324374
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1396216374
Short name T305
Test name
Test status
Simulation time 118374959904 ps
CPU time 1173.59 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 07:17:34 PM PDT 24
Peak memory 288436 kb
Host smart-fbd7a37d-5032-4c9a-8b23-236e7c6d611c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396216374 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1396216374
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.4237518475
Short name T937
Test name
Test status
Simulation time 2010164240 ps
CPU time 29.5 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:28 PM PDT 24
Peak memory 242688 kb
Host smart-285f6dc0-d8f7-44a6-b54f-631893e9b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237518475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.4237518475
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.184437805
Short name T1076
Test name
Test status
Simulation time 321176609 ps
CPU time 3.8 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:00 PM PDT 24
Peak memory 242160 kb
Host smart-b52aeb9f-02d9-4a73-94f9-47fada1b550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184437805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.184437805
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1903392324
Short name T486
Test name
Test status
Simulation time 698909436 ps
CPU time 8.91 seconds
Started Jun 22 07:00:54 PM PDT 24
Finished Jun 22 07:01:09 PM PDT 24
Peak memory 242144 kb
Host smart-e376988a-2f00-4fd3-93c8-79cc70ad8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903392324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1903392324
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3568249765
Short name T510
Test name
Test status
Simulation time 92401475364 ps
CPU time 525.84 seconds
Started Jun 22 07:00:49 PM PDT 24
Finished Jun 22 07:09:42 PM PDT 24
Peak memory 277128 kb
Host smart-d47bceb1-3049-4251-8bde-31ad0f6c59b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568249765 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3568249765
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.3427463161
Short name T202
Test name
Test status
Simulation time 293606023 ps
CPU time 3.39 seconds
Started Jun 22 07:00:52 PM PDT 24
Finished Jun 22 07:01:02 PM PDT 24
Peak memory 242028 kb
Host smart-e33ad59d-5565-4454-bba1-fa978693e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427463161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3427463161
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.531616534
Short name T652
Test name
Test status
Simulation time 3706670949 ps
CPU time 18.49 seconds
Started Jun 22 07:00:50 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242788 kb
Host smart-f06083de-29fe-4dda-a61c-c1805fa5f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531616534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.531616534
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3694806640
Short name T698
Test name
Test status
Simulation time 1768869309 ps
CPU time 4.85 seconds
Started Jun 22 07:00:54 PM PDT 24
Finished Jun 22 07:01:04 PM PDT 24
Peak memory 242572 kb
Host smart-178a0edd-de96-440e-8e8d-7df974c6fb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694806640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3694806640
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.477154796
Short name T256
Test name
Test status
Simulation time 532442160 ps
CPU time 16.16 seconds
Started Jun 22 07:00:54 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242224 kb
Host smart-1de8e231-406d-40df-96e9-496730e62eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477154796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.477154796
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.778324959
Short name T496
Test name
Test status
Simulation time 1050778743910 ps
CPU time 2973.47 seconds
Started Jun 22 07:00:52 PM PDT 24
Finished Jun 22 07:50:32 PM PDT 24
Peak memory 265444 kb
Host smart-d221154c-7057-4630-a60a-626e83c96693
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778324959 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.778324959
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.479428150
Short name T116
Test name
Test status
Simulation time 114724870 ps
CPU time 3.99 seconds
Started Jun 22 07:00:53 PM PDT 24
Finished Jun 22 07:01:03 PM PDT 24
Peak memory 242240 kb
Host smart-c7cfdf9b-1018-413e-a870-54fa7a610a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479428150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.479428150
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.2364032739
Short name T113
Test name
Test status
Simulation time 600055255 ps
CPU time 16.39 seconds
Started Jun 22 07:00:51 PM PDT 24
Finished Jun 22 07:01:13 PM PDT 24
Peak memory 242268 kb
Host smart-4e5a94f0-f3f7-4556-9ac9-ed636d683af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364032739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2364032739
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.1312845668
Short name T295
Test name
Test status
Simulation time 1075402430687 ps
CPU time 2322.59 seconds
Started Jun 22 07:00:55 PM PDT 24
Finished Jun 22 07:39:43 PM PDT 24
Peak memory 382076 kb
Host smart-844b3cb7-37ef-4f8e-9f10-2d0e7cd2c306
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312845668 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.1312845668
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.257214161
Short name T214
Test name
Test status
Simulation time 2008590427 ps
CPU time 5.09 seconds
Started Jun 22 07:01:08 PM PDT 24
Finished Jun 22 07:01:18 PM PDT 24
Peak memory 242600 kb
Host smart-9533e852-ea23-4ec6-97a3-a0872e3bd64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257214161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.257214161
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.2520077677
Short name T435
Test name
Test status
Simulation time 224731618 ps
CPU time 9.46 seconds
Started Jun 22 07:01:03 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242580 kb
Host smart-8f53bab6-03d4-4950-aa8b-5f6a61c8e840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520077677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2520077677
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.1923980438
Short name T704
Test name
Test status
Simulation time 459333501 ps
CPU time 5.27 seconds
Started Jun 22 07:01:00 PM PDT 24
Finished Jun 22 07:01:09 PM PDT 24
Peak memory 242616 kb
Host smart-a2193bb8-74e9-4ada-afdc-9cd54ee1439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923980438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.1923980438
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.3768795097
Short name T754
Test name
Test status
Simulation time 592284692 ps
CPU time 4.62 seconds
Started Jun 22 07:01:00 PM PDT 24
Finished Jun 22 07:01:09 PM PDT 24
Peak memory 242724 kb
Host smart-f76ce092-0bc1-4c69-8149-4a67b7f0091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768795097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3768795097
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1332497872
Short name T154
Test name
Test status
Simulation time 59286130414 ps
CPU time 528.14 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:09:53 PM PDT 24
Peak memory 355712 kb
Host smart-0ef504bb-21c8-49b1-9e2f-db4af763e8b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332497872 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1332497872
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.668091471
Short name T597
Test name
Test status
Simulation time 562879659 ps
CPU time 4.7 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 242440 kb
Host smart-9799a31e-67b6-44ce-885c-04b14a01b5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668091471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.668091471
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.4195456145
Short name T759
Test name
Test status
Simulation time 2698530911 ps
CPU time 13.12 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:18 PM PDT 24
Peak memory 242276 kb
Host smart-53f7138a-be63-4c3f-b433-b40c2315781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195456145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.4195456145
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.285605426
Short name T301
Test name
Test status
Simulation time 102356363540 ps
CPU time 1890.79 seconds
Started Jun 22 07:01:02 PM PDT 24
Finished Jun 22 07:32:37 PM PDT 24
Peak memory 307628 kb
Host smart-ed538a8d-6ffe-4d6d-88c2-6d4765ada60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285605426 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.285605426
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.1959057365
Short name T147
Test name
Test status
Simulation time 201136967 ps
CPU time 4.15 seconds
Started Jun 22 07:01:03 PM PDT 24
Finished Jun 22 07:01:11 PM PDT 24
Peak memory 242368 kb
Host smart-e6b832e8-f62d-4dba-b775-53e6fb123118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959057365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.1959057365
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.3081901661
Short name T643
Test name
Test status
Simulation time 1432129057 ps
CPU time 19.89 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:25 PM PDT 24
Peak memory 242160 kb
Host smart-95583936-a3e6-4395-b5a4-c27bb77d0fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081901661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.3081901661
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3168519856
Short name T747
Test name
Test status
Simulation time 449624123 ps
CPU time 4.04 seconds
Started Jun 22 07:01:02 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 242196 kb
Host smart-656a187c-2131-4a43-8a7b-517cabdb33c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168519856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3168519856
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.2303126453
Short name T519
Test name
Test status
Simulation time 105587658 ps
CPU time 3.89 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 242608 kb
Host smart-edf9cf2d-3469-4c37-9c2b-7e9a2e6161c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303126453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2303126453
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.4009079683
Short name T772
Test name
Test status
Simulation time 127416872 ps
CPU time 1.93 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:02 PM PDT 24
Peak memory 240752 kb
Host smart-ec73a479-0079-4b39-9b60-9ee28c4f6a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009079683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.4009079683
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2593321737
Short name T912
Test name
Test status
Simulation time 827374464 ps
CPU time 19.89 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:20 PM PDT 24
Peak memory 242572 kb
Host smart-12c38975-2fd3-443f-94d1-9c7a69a65eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593321737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2593321737
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.772013105
Short name T850
Test name
Test status
Simulation time 16354763705 ps
CPU time 35.97 seconds
Started Jun 22 06:58:01 PM PDT 24
Finished Jun 22 06:58:39 PM PDT 24
Peak memory 246740 kb
Host smart-98d72514-1b0d-426d-b96f-4f375c55a2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772013105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.772013105
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2273884840
Short name T770
Test name
Test status
Simulation time 262770908 ps
CPU time 4.03 seconds
Started Jun 22 06:58:00 PM PDT 24
Finished Jun 22 06:58:05 PM PDT 24
Peak memory 242224 kb
Host smart-cc74806f-77dd-4551-9fa6-4dabde724903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273884840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2273884840
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.1296635263
Short name T483
Test name
Test status
Simulation time 3788298658 ps
CPU time 23.73 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:23 PM PDT 24
Peak memory 249420 kb
Host smart-ca8f838b-383b-4103-8e98-e36debd01546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296635263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.1296635263
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.3624969189
Short name T973
Test name
Test status
Simulation time 2400493368 ps
CPU time 30.5 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:31 PM PDT 24
Peak memory 242268 kb
Host smart-4246c6cc-cbcf-4aee-8b4c-3497c9f3c9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624969189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3624969189
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.877194143
Short name T641
Test name
Test status
Simulation time 1056631617 ps
CPU time 20.77 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:21 PM PDT 24
Peak memory 242052 kb
Host smart-bbb02083-f1d7-4acb-8765-804d7b95c2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877194143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.877194143
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1123467875
Short name T732
Test name
Test status
Simulation time 2174853424 ps
CPU time 17.45 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:18 PM PDT 24
Peak memory 242624 kb
Host smart-c5360e7f-f928-4432-b45c-60130163c594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123467875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1123467875
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3586958243
Short name T367
Test name
Test status
Simulation time 1893665314 ps
CPU time 4.98 seconds
Started Jun 22 06:58:01 PM PDT 24
Finished Jun 22 06:58:08 PM PDT 24
Peak memory 242088 kb
Host smart-c9db8ca2-5d0d-4493-91b0-dd1e83029014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586958243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3586958243
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.2262096132
Short name T526
Test name
Test status
Simulation time 616089341 ps
CPU time 5.87 seconds
Started Jun 22 06:58:00 PM PDT 24
Finished Jun 22 06:58:07 PM PDT 24
Peak memory 242512 kb
Host smart-73b3667c-62ce-4d25-8783-74b4c647395d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262096132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2262096132
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.3832055459
Short name T706
Test name
Test status
Simulation time 561014606 ps
CPU time 20.87 seconds
Started Jun 22 06:58:02 PM PDT 24
Finished Jun 22 06:58:24 PM PDT 24
Peak memory 242400 kb
Host smart-98e8bc15-c4ff-4540-9332-45d248dece80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832055459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3832055459
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.2457709570
Short name T925
Test name
Test status
Simulation time 543105954 ps
CPU time 13.2 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:01:22 PM PDT 24
Peak memory 242428 kb
Host smart-32f84eb4-0d4d-4f81-aa01-52842b95d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457709570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2457709570
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3124530845
Short name T540
Test name
Test status
Simulation time 198121604 ps
CPU time 3.23 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:01:11 PM PDT 24
Peak memory 242484 kb
Host smart-9d5c2632-f0fa-46f9-8d69-ac9d01daf419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124530845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3124530845
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1282803339
Short name T944
Test name
Test status
Simulation time 206635173 ps
CPU time 9.23 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:01:18 PM PDT 24
Peak memory 242092 kb
Host smart-756266ce-3975-4def-924e-2a195f82ae2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282803339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1282803339
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.1998195343
Short name T651
Test name
Test status
Simulation time 87261628907 ps
CPU time 744.24 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:13:33 PM PDT 24
Peak memory 258500 kb
Host smart-4df5b999-1a63-49e5-b14b-cb457d166e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998195343 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.1998195343
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1824825059
Short name T609
Test name
Test status
Simulation time 234886592 ps
CPU time 4.56 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 242392 kb
Host smart-457359e1-a49f-4ce9-9929-b17baf88753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824825059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1824825059
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.644719704
Short name T393
Test name
Test status
Simulation time 343620469 ps
CPU time 4.3 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:01:12 PM PDT 24
Peak memory 242456 kb
Host smart-64c6fa3b-e66f-49ae-8ac9-c7bbc75f31e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644719704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.644719704
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.919557491
Short name T328
Test name
Test status
Simulation time 105676610299 ps
CPU time 918.71 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:16:27 PM PDT 24
Peak memory 362372 kb
Host smart-29b05ef2-cd55-483e-8323-e1d070986301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919557491 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.919557491
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.4177878749
Short name T211
Test name
Test status
Simulation time 523456360 ps
CPU time 3.99 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:09 PM PDT 24
Peak memory 242220 kb
Host smart-abd89aff-fcae-42a3-af1a-f210c8422fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177878749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.4177878749
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.1505365128
Short name T797
Test name
Test status
Simulation time 628417796 ps
CPU time 17.17 seconds
Started Jun 22 07:01:01 PM PDT 24
Finished Jun 22 07:01:22 PM PDT 24
Peak memory 242060 kb
Host smart-a9d255d9-f575-48b7-84af-81004859f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505365128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.1505365128
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.2619270118
Short name T979
Test name
Test status
Simulation time 210818858 ps
CPU time 4.31 seconds
Started Jun 22 07:01:02 PM PDT 24
Finished Jun 22 07:01:10 PM PDT 24
Peak memory 242240 kb
Host smart-9f109262-6143-4b3f-9161-07463bc9e1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619270118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2619270118
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.2971092362
Short name T819
Test name
Test status
Simulation time 807611953 ps
CPU time 11.89 seconds
Started Jun 22 07:01:02 PM PDT 24
Finished Jun 22 07:01:18 PM PDT 24
Peak memory 242076 kb
Host smart-e9df08e8-2907-434b-bf14-13c32947cb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971092362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2971092362
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.909624943
Short name T158
Test name
Test status
Simulation time 223983090 ps
CPU time 4.22 seconds
Started Jun 22 07:01:06 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242116 kb
Host smart-18a58f6f-893a-41e2-9ff2-06a223da5ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909624943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.909624943
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1609704846
Short name T750
Test name
Test status
Simulation time 236976699 ps
CPU time 7.96 seconds
Started Jun 22 07:01:08 PM PDT 24
Finished Jun 22 07:01:21 PM PDT 24
Peak memory 242492 kb
Host smart-d27c11bb-2bb2-4d1c-b2d3-c7372d7ef2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609704846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1609704846
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.3126236995
Short name T1112
Test name
Test status
Simulation time 237020553393 ps
CPU time 1866.02 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:32:26 PM PDT 24
Peak memory 284536 kb
Host smart-c87611c7-5efe-42a2-ae46-223106843f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126236995 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.3126236995
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.3643655618
Short name T476
Test name
Test status
Simulation time 149377057 ps
CPU time 4.29 seconds
Started Jun 22 07:01:06 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242672 kb
Host smart-8d086073-7774-4ea0-96d2-094ac9e564d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643655618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3643655618
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.735673139
Short name T267
Test name
Test status
Simulation time 1706863803 ps
CPU time 14.95 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:33 PM PDT 24
Peak memory 242272 kb
Host smart-c5c0151e-43ec-4cbb-91fa-0dbbe66de57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735673139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.735673139
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.963144391
Short name T331
Test name
Test status
Simulation time 61849252337 ps
CPU time 808.67 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:14:40 PM PDT 24
Peak memory 307412 kb
Host smart-e9fa7443-e933-43fa-be2d-ea97e637ab46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963144391 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.963144391
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.3915818386
Short name T635
Test name
Test status
Simulation time 101854142 ps
CPU time 4.05 seconds
Started Jun 22 07:01:08 PM PDT 24
Finished Jun 22 07:01:17 PM PDT 24
Peak memory 242636 kb
Host smart-08e9dbdc-6845-4d7b-976f-7f129ba8b4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915818386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3915818386
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.587449646
Short name T715
Test name
Test status
Simulation time 4067626521 ps
CPU time 27.71 seconds
Started Jun 22 07:01:04 PM PDT 24
Finished Jun 22 07:01:37 PM PDT 24
Peak memory 242336 kb
Host smart-1dfc33b5-9669-4c02-b396-9991b8633b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587449646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.587449646
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3512040786
Short name T888
Test name
Test status
Simulation time 330821667 ps
CPU time 3.33 seconds
Started Jun 22 07:01:06 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242560 kb
Host smart-f00d0b99-c1cd-4171-a4f2-8a68ccacef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512040786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3512040786
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.2040797816
Short name T955
Test name
Test status
Simulation time 9287342722 ps
CPU time 26.46 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242188 kb
Host smart-0cab1038-e7d4-4b19-94c9-62413e96299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040797816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.2040797816
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.644543967
Short name T222
Test name
Test status
Simulation time 84094160753 ps
CPU time 1161.75 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:20:32 PM PDT 24
Peak memory 332584 kb
Host smart-e11154f2-d6bd-4dc6-81e6-8b6b4afa0342
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644543967 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.644543967
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.880112678
Short name T537
Test name
Test status
Simulation time 436128936 ps
CPU time 4.98 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242136 kb
Host smart-d3b59efa-b2cd-4d45-9aaa-9abf94957022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880112678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.880112678
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.3479382028
Short name T1095
Test name
Test status
Simulation time 263622694 ps
CPU time 5.74 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:17 PM PDT 24
Peak memory 242264 kb
Host smart-8bf75128-e461-46c8-8d48-6e7f40e24dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479382028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.3479382028
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2590651226
Short name T334
Test name
Test status
Simulation time 160434750503 ps
CPU time 649.53 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 07:12:03 PM PDT 24
Peak memory 258568 kb
Host smart-357a2e63-2977-46f1-b104-010608630138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590651226 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2590651226
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.3439268024
Short name T241
Test name
Test status
Simulation time 176567594 ps
CPU time 1.86 seconds
Started Jun 22 06:58:06 PM PDT 24
Finished Jun 22 06:58:09 PM PDT 24
Peak memory 240628 kb
Host smart-97b45352-6aeb-44aa-8436-763cd8b16422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439268024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3439268024
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.310169280
Short name T1137
Test name
Test status
Simulation time 362484823 ps
CPU time 5.12 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:05 PM PDT 24
Peak memory 242492 kb
Host smart-755eb712-3212-48f3-bcda-d21dea6c2f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310169280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.310169280
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.1245064799
Short name T859
Test name
Test status
Simulation time 266798016 ps
CPU time 6.19 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:05 PM PDT 24
Peak memory 242388 kb
Host smart-9043a35d-6a61-48af-be91-6c067b9184f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245064799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.1245064799
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2379647640
Short name T923
Test name
Test status
Simulation time 904121475 ps
CPU time 13.53 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:13 PM PDT 24
Peak memory 242472 kb
Host smart-58a71609-24fa-4304-b8e4-5cdeb91e7899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379647640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2379647640
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.3752957314
Short name T251
Test name
Test status
Simulation time 13274495837 ps
CPU time 31.15 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:32 PM PDT 24
Peak memory 243140 kb
Host smart-ddeaa870-e59d-4844-abb5-5cb7119b7e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752957314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.3752957314
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.3881822608
Short name T665
Test name
Test status
Simulation time 265370470 ps
CPU time 4.15 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:04 PM PDT 24
Peak memory 242304 kb
Host smart-277e203a-a3f9-4309-835f-47b44a683871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881822608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.3881822608
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2912784955
Short name T896
Test name
Test status
Simulation time 14398599154 ps
CPU time 25.16 seconds
Started Jun 22 06:57:59 PM PDT 24
Finished Jun 22 06:58:26 PM PDT 24
Peak memory 246400 kb
Host smart-be66fe62-08fc-411a-b288-141b8c88f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912784955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2912784955
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.719055846
Short name T956
Test name
Test status
Simulation time 3089025073 ps
CPU time 29.81 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:29 PM PDT 24
Peak memory 242744 kb
Host smart-e5d6d2bb-0596-41f6-8068-67237049eee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719055846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.719055846
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.588784867
Short name T191
Test name
Test status
Simulation time 707049044 ps
CPU time 4.61 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:05 PM PDT 24
Peak memory 242268 kb
Host smart-5482778a-77e5-4cda-a201-0229de0a2b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588784867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.588784867
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.859858831
Short name T833
Test name
Test status
Simulation time 581389144 ps
CPU time 17.75 seconds
Started Jun 22 06:58:01 PM PDT 24
Finished Jun 22 06:58:20 PM PDT 24
Peak memory 249008 kb
Host smart-3cb68a7a-aeab-434d-9ba6-0de9019ea1a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859858831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.859858831
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.874980188
Short name T1164
Test name
Test status
Simulation time 281635847 ps
CPU time 8.7 seconds
Started Jun 22 06:58:06 PM PDT 24
Finished Jun 22 06:58:17 PM PDT 24
Peak memory 242136 kb
Host smart-c32e7130-b2a7-4b1e-8b81-7c7d0bd9ca6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874980188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.874980188
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.2979511817
Short name T940
Test name
Test status
Simulation time 649108896 ps
CPU time 4.9 seconds
Started Jun 22 06:57:58 PM PDT 24
Finished Jun 22 06:58:05 PM PDT 24
Peak memory 242260 kb
Host smart-75e91fce-b5c3-492f-9e92-6ef2a56e78ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979511817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.2979511817
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.993436037
Short name T344
Test name
Test status
Simulation time 22576048467 ps
CPU time 81.83 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:59:28 PM PDT 24
Peak memory 249132 kb
Host smart-53bfc640-296c-4228-b350-9bbae0fdcb0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993436037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.993436037
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1832789514
Short name T417
Test name
Test status
Simulation time 216630816192 ps
CPU time 2463.81 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 07:39:13 PM PDT 24
Peak memory 274444 kb
Host smart-1ffca4d2-d0c2-434f-94ea-55aea821f62e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832789514 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.1832789514
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.452490655
Short name T563
Test name
Test status
Simulation time 1295363874 ps
CPU time 13.02 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:19 PM PDT 24
Peak memory 242480 kb
Host smart-2abf845c-44f1-4a0f-be2b-11a541b1b69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452490655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.452490655
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.799391345
Short name T1125
Test name
Test status
Simulation time 609622263 ps
CPU time 3.94 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242360 kb
Host smart-c284d0bd-729b-42f6-bcfb-1acf278d4ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799391345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.799391345
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.2494592636
Short name T935
Test name
Test status
Simulation time 512597857 ps
CPU time 6.48 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:25 PM PDT 24
Peak memory 242208 kb
Host smart-bff6afd8-be30-4297-b008-cdc5a7122ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494592636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.2494592636
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1909652652
Short name T1121
Test name
Test status
Simulation time 1061868997286 ps
CPU time 4859.85 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 08:22:14 PM PDT 24
Peak memory 771460 kb
Host smart-b28551e6-4768-414b-af8d-5fe80d23c808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909652652 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1909652652
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.4170252411
Short name T1115
Test name
Test status
Simulation time 625384901 ps
CPU time 4.89 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:17 PM PDT 24
Peak memory 242164 kb
Host smart-c27e5ba2-1561-4edc-ae9f-12f630ad6ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170252411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.4170252411
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2941493825
Short name T274
Test name
Test status
Simulation time 985646048 ps
CPU time 12.17 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 07:01:26 PM PDT 24
Peak memory 242464 kb
Host smart-b07f7ba9-59ec-421d-a2ff-6e49079ef382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941493825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2941493825
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.4148030807
Short name T235
Test name
Test status
Simulation time 235957054263 ps
CPU time 486.68 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:09:26 PM PDT 24
Peak memory 303008 kb
Host smart-db057562-4d12-4340-a84a-f9b8ff6bff9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148030807 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.4148030807
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.4050985389
Short name T1129
Test name
Test status
Simulation time 434502620 ps
CPU time 13.82 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:01:23 PM PDT 24
Peak memory 242212 kb
Host smart-f5b9d445-e9c7-4b33-b3ef-5fd37bab87af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050985389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.4050985389
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.3852193962
Short name T932
Test name
Test status
Simulation time 429059399 ps
CPU time 3.85 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:16 PM PDT 24
Peak memory 242308 kb
Host smart-7b5c1fd6-9e2c-4382-8a55-db70326752d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852193962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.3852193962
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.660956402
Short name T346
Test name
Test status
Simulation time 3350908657 ps
CPU time 29.53 seconds
Started Jun 22 07:01:08 PM PDT 24
Finished Jun 22 07:01:42 PM PDT 24
Peak memory 242320 kb
Host smart-ace556ee-4850-4d37-a029-0d6db1457689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660956402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.660956402
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.2270153263
Short name T327
Test name
Test status
Simulation time 794642063633 ps
CPU time 1008.46 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:18:00 PM PDT 24
Peak memory 259888 kb
Host smart-f7c94d86-4f19-4406-a6c8-dd9fe964fb56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270153263 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.2270153263
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3259085498
Short name T1183
Test name
Test status
Simulation time 1886154569 ps
CPU time 7.31 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 07:01:21 PM PDT 24
Peak memory 242184 kb
Host smart-b93c6efc-5e00-4bc4-9758-de4e63321f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259085498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3259085498
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3548099156
Short name T632
Test name
Test status
Simulation time 281316504 ps
CPU time 15.49 seconds
Started Jun 22 07:01:08 PM PDT 24
Finished Jun 22 07:01:28 PM PDT 24
Peak memory 242268 kb
Host smart-a7c803f0-3586-4ceb-9260-99c7b9064e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548099156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3548099156
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3272712146
Short name T21
Test name
Test status
Simulation time 343742798758 ps
CPU time 1847.94 seconds
Started Jun 22 07:01:09 PM PDT 24
Finished Jun 22 07:32:02 PM PDT 24
Peak memory 287928 kb
Host smart-376a044d-c0a2-47a5-b662-2c7b8cd4fec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272712146 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3272712146
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.3037402254
Short name T1067
Test name
Test status
Simulation time 2413200813 ps
CPU time 6.21 seconds
Started Jun 22 07:01:07 PM PDT 24
Finished Jun 22 07:01:17 PM PDT 24
Peak memory 242432 kb
Host smart-6148fc6d-4484-4db9-8ac3-0917359ded00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037402254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.3037402254
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.866554729
Short name T773
Test name
Test status
Simulation time 165793594 ps
CPU time 4.44 seconds
Started Jun 22 07:01:05 PM PDT 24
Finished Jun 22 07:01:14 PM PDT 24
Peak memory 242312 kb
Host smart-9543d468-b72a-4570-a46e-bb73607982d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866554729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.866554729
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.2311921897
Short name T490
Test name
Test status
Simulation time 197530934168 ps
CPU time 1286.18 seconds
Started Jun 22 07:01:06 PM PDT 24
Finished Jun 22 07:22:37 PM PDT 24
Peak memory 273836 kb
Host smart-58727d48-8091-4860-a6e4-152ea1d074e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311921897 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.2311921897
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.549340006
Short name T1014
Test name
Test status
Simulation time 652184780 ps
CPU time 5.78 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:24 PM PDT 24
Peak memory 242336 kb
Host smart-8555987b-257b-4b1d-8167-3775d8aff141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549340006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.549340006
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3756147082
Short name T781
Test name
Test status
Simulation time 255724461 ps
CPU time 4.4 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:01:25 PM PDT 24
Peak memory 242084 kb
Host smart-20d6ff99-c837-4ec6-82bb-78de68d3f047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756147082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3756147082
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.123890405
Short name T292
Test name
Test status
Simulation time 47673350735 ps
CPU time 559.28 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:10:40 PM PDT 24
Peak memory 330680 kb
Host smart-aeaebf0c-5a20-46ff-be6b-2f7e2232aa76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123890405 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.123890405
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.2106658106
Short name T1159
Test name
Test status
Simulation time 1981003383 ps
CPU time 5.97 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:01:26 PM PDT 24
Peak memory 242316 kb
Host smart-62040fcd-9b51-44d1-b24f-f37b75b96bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106658106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.2106658106
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.5433085
Short name T924
Test name
Test status
Simulation time 1889968538 ps
CPU time 27.53 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:45 PM PDT 24
Peak memory 242484 kb
Host smart-2cb860b6-a127-4b52-9b9c-694db1f7c336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5433085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.5433085
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.1978240274
Short name T751
Test name
Test status
Simulation time 106437956879 ps
CPU time 886.04 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:16:06 PM PDT 24
Peak memory 258084 kb
Host smart-25623dd8-69a5-46ab-8def-4c3310411573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978240274 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.1978240274
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.308709763
Short name T150
Test name
Test status
Simulation time 145694874 ps
CPU time 3.67 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:23 PM PDT 24
Peak memory 242444 kb
Host smart-86d1604d-96ec-419a-98c0-3e3b528d49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308709763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.308709763
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.3440727080
Short name T721
Test name
Test status
Simulation time 485300302 ps
CPU time 5.31 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:23 PM PDT 24
Peak memory 242492 kb
Host smart-e41d3e7e-b03e-41ae-80b8-681c63f5d2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440727080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3440727080
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.3283939330
Short name T297
Test name
Test status
Simulation time 48341096681 ps
CPU time 1138.25 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:20:18 PM PDT 24
Peak memory 265676 kb
Host smart-23bca9c0-4321-4a3c-9aa8-6385b3d41ee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283939330 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.3283939330
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.1512054272
Short name T1120
Test name
Test status
Simulation time 127831297 ps
CPU time 3.26 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:21 PM PDT 24
Peak memory 242308 kb
Host smart-c4742cad-99ad-459b-956e-60eb17710120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512054272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1512054272
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.523766150
Short name T230
Test name
Test status
Simulation time 434611808 ps
CPU time 6.5 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:24 PM PDT 24
Peak memory 242108 kb
Host smart-14d8215e-8eff-4252-863f-83f1e7cf7045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523766150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.523766150
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.3897945835
Short name T1018
Test name
Test status
Simulation time 1600527076295 ps
CPU time 2572.92 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:44:14 PM PDT 24
Peak memory 501104 kb
Host smart-8020d3ef-a7cb-409f-939d-40caa9972469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897945835 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3897945835
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.2494085096
Short name T615
Test name
Test status
Simulation time 65206978 ps
CPU time 1.82 seconds
Started Jun 22 06:58:09 PM PDT 24
Finished Jun 22 06:58:12 PM PDT 24
Peak memory 240628 kb
Host smart-67855586-02ec-4753-8cce-1f3eecb2f17e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494085096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.2494085096
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.695750443
Short name T1023
Test name
Test status
Simulation time 812922072 ps
CPU time 27.17 seconds
Started Jun 22 06:58:08 PM PDT 24
Finished Jun 22 06:58:37 PM PDT 24
Peak memory 242776 kb
Host smart-a4e2f0b3-8a40-4d88-b198-51eb8402a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695750443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.695750443
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.2528444060
Short name T1066
Test name
Test status
Simulation time 874114642 ps
CPU time 5.12 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:12 PM PDT 24
Peak memory 242468 kb
Host smart-82572a08-ca0e-41e4-bfe1-0a4b69b29f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528444060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2528444060
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.1957233633
Short name T1107
Test name
Test status
Simulation time 877174801 ps
CPU time 23.61 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 06:58:32 PM PDT 24
Peak memory 242344 kb
Host smart-f68a14c1-5725-41c3-85df-4c73fa5113ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957233633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.1957233633
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.3686860267
Short name T642
Test name
Test status
Simulation time 793301609 ps
CPU time 20.78 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 06:58:30 PM PDT 24
Peak memory 242456 kb
Host smart-443a15d5-69b8-4043-95ff-ebbbc256fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686860267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3686860267
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2387819306
Short name T1078
Test name
Test status
Simulation time 271939968 ps
CPU time 4.07 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 06:58:12 PM PDT 24
Peak memory 242560 kb
Host smart-7a9785e9-6a7d-4ca7-92b1-6e9950682556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387819306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2387819306
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1371325151
Short name T603
Test name
Test status
Simulation time 1120184701 ps
CPU time 12.9 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 06:58:22 PM PDT 24
Peak memory 242380 kb
Host smart-c65e97a1-0023-4721-a414-96d6f2889af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371325151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1371325151
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.2218052995
Short name T103
Test name
Test status
Simulation time 1123002352 ps
CPU time 30.65 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:37 PM PDT 24
Peak memory 242672 kb
Host smart-5dfd0a68-8ba7-45b7-8870-9fb04152d9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218052995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2218052995
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.4007934678
Short name T860
Test name
Test status
Simulation time 254181719 ps
CPU time 5.63 seconds
Started Jun 22 06:58:06 PM PDT 24
Finished Jun 22 06:58:13 PM PDT 24
Peak memory 242204 kb
Host smart-b216ba44-4005-4ea1-bec0-ad8f147d5530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007934678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.4007934678
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3812972630
Short name T929
Test name
Test status
Simulation time 3048785525 ps
CPU time 30.32 seconds
Started Jun 22 06:58:08 PM PDT 24
Finished Jun 22 06:58:40 PM PDT 24
Peak memory 242340 kb
Host smart-855f53f1-4781-4fe8-b5a8-7927f688c856
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812972630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3812972630
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.220259835
Short name T699
Test name
Test status
Simulation time 550611360 ps
CPU time 6.28 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:13 PM PDT 24
Peak memory 242288 kb
Host smart-19c48626-182b-440e-843c-dc0314676fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=220259835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.220259835
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.776747904
Short name T404
Test name
Test status
Simulation time 4821893925 ps
CPU time 17 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:23 PM PDT 24
Peak memory 242716 kb
Host smart-f71a54c3-7fd3-4ec5-bf00-1409f88c2f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776747904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.776747904
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.3986631974
Short name T332
Test name
Test status
Simulation time 31895989300 ps
CPU time 475.38 seconds
Started Jun 22 06:58:08 PM PDT 24
Finished Jun 22 07:06:05 PM PDT 24
Peak memory 325860 kb
Host smart-04d0fec9-ab5a-4ffd-8a03-a045a0e1acbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986631974 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.3986631974
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1310316265
Short name T910
Test name
Test status
Simulation time 1390911628 ps
CPU time 14.51 seconds
Started Jun 22 06:58:07 PM PDT 24
Finished Jun 22 06:58:23 PM PDT 24
Peak memory 242484 kb
Host smart-31a5f754-5a68-403b-ae9d-ccf99bfbfcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310316265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1310316265
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.4157416337
Short name T543
Test name
Test status
Simulation time 133866560 ps
CPU time 3.49 seconds
Started Jun 22 07:01:17 PM PDT 24
Finished Jun 22 07:01:26 PM PDT 24
Peak memory 242300 kb
Host smart-bcda83a9-0640-48d2-9415-e238dcefa1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157416337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.4157416337
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.227158352
Short name T594
Test name
Test status
Simulation time 754545658 ps
CPU time 14.78 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:32 PM PDT 24
Peak memory 242272 kb
Host smart-df8066f9-18fa-4ff2-9d8c-9a55a26df19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227158352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.227158352
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.4090643113
Short name T46
Test name
Test status
Simulation time 2052895242 ps
CPU time 8.62 seconds
Started Jun 22 07:01:16 PM PDT 24
Finished Jun 22 07:01:30 PM PDT 24
Peak memory 242100 kb
Host smart-ec192f65-f7c7-4e2a-b86f-b0f8be31df6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090643113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.4090643113
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.4143347190
Short name T1136
Test name
Test status
Simulation time 398946295 ps
CPU time 4.82 seconds
Started Jun 22 07:01:16 PM PDT 24
Finished Jun 22 07:01:26 PM PDT 24
Peak memory 242188 kb
Host smart-7d1171d9-988e-4ac8-aa03-2eeb6b2fdf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143347190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.4143347190
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.3302824313
Short name T333
Test name
Test status
Simulation time 51272466348 ps
CPU time 312.55 seconds
Started Jun 22 07:01:12 PM PDT 24
Finished Jun 22 07:06:29 PM PDT 24
Peak memory 265672 kb
Host smart-be091a7a-62de-4e85-98ae-3de93674fd68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302824313 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.3302824313
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.2144379190
Short name T613
Test name
Test status
Simulation time 282435555 ps
CPU time 4.86 seconds
Started Jun 22 07:01:15 PM PDT 24
Finished Jun 22 07:01:25 PM PDT 24
Peak memory 242212 kb
Host smart-cf111c1a-0c43-484e-911e-fb280743bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144379190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2144379190
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2199046941
Short name T1145
Test name
Test status
Simulation time 62319211924 ps
CPU time 874.3 seconds
Started Jun 22 07:01:16 PM PDT 24
Finished Jun 22 07:15:56 PM PDT 24
Peak memory 281016 kb
Host smart-f3d5b5c2-dbae-48ea-8de9-4bef821c4461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199046941 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.2199046941
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3000327206
Short name T584
Test name
Test status
Simulation time 146987827 ps
CPU time 4.37 seconds
Started Jun 22 07:01:13 PM PDT 24
Finished Jun 22 07:01:22 PM PDT 24
Peak memory 242292 kb
Host smart-304b8b9a-9782-4b95-9ab8-a188352e3fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000327206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3000327206
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.2643423178
Short name T684
Test name
Test status
Simulation time 194767630 ps
CPU time 10.2 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:28 PM PDT 24
Peak memory 242208 kb
Host smart-10932ee7-9bda-4202-90e0-2162521cd198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643423178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.2643423178
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2735821935
Short name T838
Test name
Test status
Simulation time 314829500291 ps
CPU time 812.6 seconds
Started Jun 22 07:01:16 PM PDT 24
Finished Jun 22 07:14:53 PM PDT 24
Peak memory 265952 kb
Host smart-18d58ca6-9aab-49de-a749-7fdb52a8824e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735821935 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2735821935
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3036636201
Short name T1061
Test name
Test status
Simulation time 112506854 ps
CPU time 3.32 seconds
Started Jun 22 07:01:14 PM PDT 24
Finished Jun 22 07:01:21 PM PDT 24
Peak memory 242200 kb
Host smart-af972f47-e62d-4f0a-8b9a-93f4c8bd1067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036636201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3036636201
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1950629889
Short name T668
Test name
Test status
Simulation time 399204637 ps
CPU time 2.88 seconds
Started Jun 22 07:01:21 PM PDT 24
Finished Jun 22 07:01:27 PM PDT 24
Peak memory 242636 kb
Host smart-fbf870bb-8bb4-42bb-bc75-4d7cca09b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950629889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1950629889
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.568987849
Short name T20
Test name
Test status
Simulation time 1230426957262 ps
CPU time 3096.44 seconds
Started Jun 22 07:01:21 PM PDT 24
Finished Jun 22 07:53:01 PM PDT 24
Peak memory 686936 kb
Host smart-ad0f6612-0937-464f-89c6-11ec4f0945a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568987849 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.568987849
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.570829761
Short name T817
Test name
Test status
Simulation time 397214207 ps
CPU time 4.6 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:29 PM PDT 24
Peak memory 242648 kb
Host smart-0ea4870b-c5f6-4cf3-ae02-dfeca44c018a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570829761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.570829761
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.215733226
Short name T1150
Test name
Test status
Simulation time 455793308 ps
CPU time 10.78 seconds
Started Jun 22 07:01:23 PM PDT 24
Finished Jun 22 07:01:37 PM PDT 24
Peak memory 242160 kb
Host smart-7d5141e6-d810-4171-bca5-3b4c776ebbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215733226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.215733226
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.2260960634
Short name T693
Test name
Test status
Simulation time 9902475878 ps
CPU time 268.92 seconds
Started Jun 22 07:01:21 PM PDT 24
Finished Jun 22 07:05:53 PM PDT 24
Peak memory 249244 kb
Host smart-96431adb-09c7-4ba4-8545-792ce1763b4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260960634 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.2260960634
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1350061644
Short name T669
Test name
Test status
Simulation time 632722401 ps
CPU time 4.19 seconds
Started Jun 22 07:01:23 PM PDT 24
Finished Jun 22 07:01:30 PM PDT 24
Peak memory 242492 kb
Host smart-806f8de6-a185-41aa-86b5-2ea5817d380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350061644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1350061644
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1105829009
Short name T163
Test name
Test status
Simulation time 690431113 ps
CPU time 5.95 seconds
Started Jun 22 07:01:21 PM PDT 24
Finished Jun 22 07:01:30 PM PDT 24
Peak memory 242072 kb
Host smart-8670d65a-4c75-4e52-81aa-f6935358800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105829009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1105829009
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1404427224
Short name T767
Test name
Test status
Simulation time 32219940376 ps
CPU time 260.7 seconds
Started Jun 22 07:01:21 PM PDT 24
Finished Jun 22 07:05:45 PM PDT 24
Peak memory 249176 kb
Host smart-d2d19c85-f0ff-4d2b-9bcf-0311adf1805d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404427224 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1404427224
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.309582058
Short name T595
Test name
Test status
Simulation time 238219354 ps
CPU time 4.02 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:29 PM PDT 24
Peak memory 242640 kb
Host smart-14380d88-a40a-44b2-82c2-e397658c6f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309582058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.309582058
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3629189244
Short name T1138
Test name
Test status
Simulation time 2773980107 ps
CPU time 6.54 seconds
Started Jun 22 07:01:24 PM PDT 24
Finished Jun 22 07:01:33 PM PDT 24
Peak memory 242328 kb
Host smart-7c5032b5-ec47-430e-80f9-0aec62e20d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629189244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3629189244
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.4155016591
Short name T667
Test name
Test status
Simulation time 151355011 ps
CPU time 4.42 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:30 PM PDT 24
Peak memory 242520 kb
Host smart-596cee6c-02ba-41c2-9d10-e0bb64678b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155016591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.4155016591
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.2379717602
Short name T611
Test name
Test status
Simulation time 414813228 ps
CPU time 3.26 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:28 PM PDT 24
Peak memory 242220 kb
Host smart-069f33b6-8e49-4f7f-828e-de0a4993ccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379717602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2379717602
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.104664584
Short name T1098
Test name
Test status
Simulation time 173904299530 ps
CPU time 1836.18 seconds
Started Jun 22 07:01:24 PM PDT 24
Finished Jun 22 07:32:03 PM PDT 24
Peak memory 476424 kb
Host smart-e3aceb39-3771-48de-b128-eee2113b2201
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104664584 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.104664584
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3935580267
Short name T177
Test name
Test status
Simulation time 2265170851 ps
CPU time 5.82 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:31 PM PDT 24
Peak memory 242452 kb
Host smart-767248e4-e1b4-4ce2-80db-9b2431c89d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935580267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3935580267
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.2164800715
Short name T165
Test name
Test status
Simulation time 246531250 ps
CPU time 4.94 seconds
Started Jun 22 07:01:27 PM PDT 24
Finished Jun 22 07:01:34 PM PDT 24
Peak memory 242056 kb
Host smart-f45f157b-3a5f-4766-beb7-81354d98b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164800715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.2164800715
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.2725210343
Short name T1088
Test name
Test status
Simulation time 124960928 ps
CPU time 1.87 seconds
Started Jun 22 06:58:15 PM PDT 24
Finished Jun 22 06:58:17 PM PDT 24
Peak memory 240628 kb
Host smart-7d26bed2-fe6d-4a1a-99d9-4a7da3e7ff5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725210343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2725210343
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.3612846066
Short name T560
Test name
Test status
Simulation time 7186196693 ps
CPU time 32.31 seconds
Started Jun 22 06:58:10 PM PDT 24
Finished Jun 22 06:58:43 PM PDT 24
Peak memory 242276 kb
Host smart-590d2c92-9995-474c-a6b6-84688a952627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612846066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.3612846066
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.1039320226
Short name T1041
Test name
Test status
Simulation time 3574956135 ps
CPU time 34.02 seconds
Started Jun 22 06:58:17 PM PDT 24
Finished Jun 22 06:58:52 PM PDT 24
Peak memory 242400 kb
Host smart-dfbe27f8-dbb7-47e2-b7e0-3c17d904a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039320226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1039320226
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2164544866
Short name T406
Test name
Test status
Simulation time 371823596 ps
CPU time 10.83 seconds
Started Jun 22 06:58:11 PM PDT 24
Finished Jun 22 06:58:24 PM PDT 24
Peak memory 242632 kb
Host smart-b21a9e30-9c86-4582-b0a5-82add3b5c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164544866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2164544866
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.1361951163
Short name T106
Test name
Test status
Simulation time 986774618 ps
CPU time 21.01 seconds
Started Jun 22 06:58:11 PM PDT 24
Finished Jun 22 06:58:34 PM PDT 24
Peak memory 242192 kb
Host smart-36c63b5e-808c-430a-9b07-6d81bfb2e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361951163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1361951163
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.678332546
Short name T1091
Test name
Test status
Simulation time 179631947 ps
CPU time 4.76 seconds
Started Jun 22 06:58:11 PM PDT 24
Finished Jun 22 06:58:17 PM PDT 24
Peak memory 242088 kb
Host smart-71905daf-729a-4ead-92d9-0252951aa12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678332546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.678332546
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1095887129
Short name T201
Test name
Test status
Simulation time 258192847 ps
CPU time 3.25 seconds
Started Jun 22 06:58:13 PM PDT 24
Finished Jun 22 06:58:18 PM PDT 24
Peak memory 242264 kb
Host smart-4420aa30-8157-499b-9142-545a8dce5a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095887129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1095887129
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.2096563907
Short name T724
Test name
Test status
Simulation time 444877070 ps
CPU time 14.54 seconds
Started Jun 22 06:58:13 PM PDT 24
Finished Jun 22 06:58:28 PM PDT 24
Peak memory 242124 kb
Host smart-b464352f-0e44-4147-8b25-b02f181f3f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096563907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2096563907
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.2771661520
Short name T904
Test name
Test status
Simulation time 1104447080 ps
CPU time 8.84 seconds
Started Jun 22 06:58:08 PM PDT 24
Finished Jun 22 06:58:19 PM PDT 24
Peak memory 242208 kb
Host smart-a7cc5d92-c7eb-453f-b0f0-b0d1f3a2143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771661520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2771661520
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.1864151509
Short name T184
Test name
Test status
Simulation time 306412933 ps
CPU time 5.62 seconds
Started Jun 22 06:58:10 PM PDT 24
Finished Jun 22 06:58:16 PM PDT 24
Peak memory 242272 kb
Host smart-9fbf481c-5c4b-423d-b3b1-624bbffa2cd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864151509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1864151509
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2345621927
Short name T372
Test name
Test status
Simulation time 780680854 ps
CPU time 9 seconds
Started Jun 22 06:58:12 PM PDT 24
Finished Jun 22 06:58:22 PM PDT 24
Peak memory 242220 kb
Host smart-437519e8-9965-4112-88ed-f29a97ed8b03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345621927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2345621927
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1995880788
Short name T648
Test name
Test status
Simulation time 327294884 ps
CPU time 5.41 seconds
Started Jun 22 06:58:05 PM PDT 24
Finished Jun 22 06:58:12 PM PDT 24
Peak memory 242228 kb
Host smart-4edae411-e9f0-499a-9150-209590801b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995880788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1995880788
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.95049553
Short name T1038
Test name
Test status
Simulation time 14656309246 ps
CPU time 114.02 seconds
Started Jun 22 06:58:13 PM PDT 24
Finished Jun 22 07:00:08 PM PDT 24
Peak memory 249020 kb
Host smart-7a0d75df-bc69-4f5b-9bf0-0b2e1e6f51f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95049553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.95049553
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.2691173084
Short name T997
Test name
Test status
Simulation time 888298290 ps
CPU time 27.04 seconds
Started Jun 22 06:58:14 PM PDT 24
Finished Jun 22 06:58:42 PM PDT 24
Peak memory 242568 kb
Host smart-c411abd9-1b13-48a1-8548-ef3c5c6ee3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691173084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.2691173084
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1404650680
Short name T921
Test name
Test status
Simulation time 1543562777 ps
CPU time 5.35 seconds
Started Jun 22 07:01:22 PM PDT 24
Finished Jun 22 07:01:30 PM PDT 24
Peak memory 242256 kb
Host smart-3df66259-e7a2-4bae-9c5f-8ea02efce034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404650680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1404650680
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3476760187
Short name T555
Test name
Test status
Simulation time 412989826 ps
CPU time 6.38 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:41 PM PDT 24
Peak memory 248960 kb
Host smart-917e78b2-9023-4e2f-bb9c-55195cec2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476760187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3476760187
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3286422383
Short name T1039
Test name
Test status
Simulation time 2052151856 ps
CPU time 7.06 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:01:39 PM PDT 24
Peak memory 242168 kb
Host smart-5f8020fa-efa9-4e47-81c8-bf506c057cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286422383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3286422383
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3319277023
Short name T1005
Test name
Test status
Simulation time 517077824 ps
CPU time 13.33 seconds
Started Jun 22 07:01:35 PM PDT 24
Finished Jun 22 07:01:52 PM PDT 24
Peak memory 242280 kb
Host smart-511f0c15-da9f-47ee-b904-77cdc3ba4219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319277023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3319277023
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1837212041
Short name T1083
Test name
Test status
Simulation time 374393980297 ps
CPU time 755.38 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:14:09 PM PDT 24
Peak memory 257456 kb
Host smart-4822f05f-49a8-45f9-9e90-be778a6f45db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837212041 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1837212041
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2259215369
Short name T702
Test name
Test status
Simulation time 188470718 ps
CPU time 3.75 seconds
Started Jun 22 07:01:29 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242324 kb
Host smart-4f0bcbcc-d4f9-4413-9a7d-ff77263c75d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259215369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2259215369
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.3369014524
Short name T1172
Test name
Test status
Simulation time 499932320 ps
CPU time 12.14 seconds
Started Jun 22 07:01:32 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242092 kb
Host smart-fe3bc6fe-b34e-4c9e-9d42-68e20b5731f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369014524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3369014524
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3893853065
Short name T768
Test name
Test status
Simulation time 99393987 ps
CPU time 3.82 seconds
Started Jun 22 07:01:32 PM PDT 24
Finished Jun 22 07:01:39 PM PDT 24
Peak memory 242400 kb
Host smart-6102857e-f678-4531-b38e-28c7a1c31bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893853065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3893853065
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.20318737
Short name T462
Test name
Test status
Simulation time 224222020 ps
CPU time 3.82 seconds
Started Jun 22 07:01:28 PM PDT 24
Finished Jun 22 07:01:34 PM PDT 24
Peak memory 242668 kb
Host smart-39658111-a8d2-404f-8308-efc5e5aa2d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20318737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.20318737
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3264266939
Short name T963
Test name
Test status
Simulation time 33610783035 ps
CPU time 439.07 seconds
Started Jun 22 07:01:33 PM PDT 24
Finished Jun 22 07:08:56 PM PDT 24
Peak memory 310232 kb
Host smart-19fdf70a-7150-434a-bf11-de9d36c1167b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264266939 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3264266939
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.813657595
Short name T714
Test name
Test status
Simulation time 209062373 ps
CPU time 3.56 seconds
Started Jun 22 07:01:37 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242440 kb
Host smart-9a3a35e7-8c24-4de5-99b9-b1ea732f4ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813657595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.813657595
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.2027197410
Short name T139
Test name
Test status
Simulation time 7352424782 ps
CPU time 13.62 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:47 PM PDT 24
Peak memory 242336 kb
Host smart-6b891ce7-09c3-4e72-9913-6980591e26cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027197410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.2027197410
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.1359416442
Short name T491
Test name
Test status
Simulation time 105432255 ps
CPU time 3 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:01:35 PM PDT 24
Peak memory 242308 kb
Host smart-2080d801-b710-42f6-abf5-63223be790cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359416442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1359416442
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.284348157
Short name T261
Test name
Test status
Simulation time 363609807 ps
CPU time 5.76 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:01:38 PM PDT 24
Peak memory 242684 kb
Host smart-4a2100c1-cc61-41c2-b237-db62e7c53dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284348157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.284348157
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.1916007758
Short name T169
Test name
Test status
Simulation time 333546721 ps
CPU time 4.18 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:38 PM PDT 24
Peak memory 242156 kb
Host smart-1efbacba-f72b-427c-8e9c-f02633f2fa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916007758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1916007758
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2375252804
Short name T397
Test name
Test status
Simulation time 3653083166 ps
CPU time 6.83 seconds
Started Jun 22 07:01:34 PM PDT 24
Finished Jun 22 07:01:44 PM PDT 24
Peak memory 242552 kb
Host smart-bb68a1b3-36c1-48b3-93f3-fbaea4ae5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375252804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2375252804
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.3470279156
Short name T335
Test name
Test status
Simulation time 42175542646 ps
CPU time 743.59 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:13:58 PM PDT 24
Peak memory 309336 kb
Host smart-6476f75a-4665-469d-9744-4fa1a0165d5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470279156 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.3470279156
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.4117437161
Short name T53
Test name
Test status
Simulation time 2016858369 ps
CPU time 4.84 seconds
Started Jun 22 07:01:31 PM PDT 24
Finished Jun 22 07:01:38 PM PDT 24
Peak memory 242368 kb
Host smart-4d2d9938-3230-4fa0-92e9-dda09cad39da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117437161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.4117437161
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.312251608
Short name T865
Test name
Test status
Simulation time 326954274 ps
CPU time 8.44 seconds
Started Jun 22 07:01:33 PM PDT 24
Finished Jun 22 07:01:45 PM PDT 24
Peak memory 242096 kb
Host smart-7d483462-59ab-4245-9893-1834f591fb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312251608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.312251608
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.4091644290
Short name T914
Test name
Test status
Simulation time 550822029 ps
CPU time 5.35 seconds
Started Jun 22 07:01:29 PM PDT 24
Finished Jun 22 07:01:37 PM PDT 24
Peak memory 242452 kb
Host smart-46238923-ce4f-4f92-a2b7-bfda91ebf8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091644290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.4091644290
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.456569054
Short name T1103
Test name
Test status
Simulation time 516100877 ps
CPU time 6.14 seconds
Started Jun 22 07:01:29 PM PDT 24
Finished Jun 22 07:01:37 PM PDT 24
Peak memory 242484 kb
Host smart-c5eb0c83-ee09-44d9-902f-3f45b6305ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456569054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.456569054
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.394660348
Short name T9
Test name
Test status
Simulation time 52072677543 ps
CPU time 1059.6 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:19:12 PM PDT 24
Peak memory 258452 kb
Host smart-64c1a9c4-b32e-456f-a60e-d125548c353f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394660348 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.394660348
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.3278602785
Short name T532
Test name
Test status
Simulation time 286174928 ps
CPU time 3.89 seconds
Started Jun 22 07:01:32 PM PDT 24
Finished Jun 22 07:01:39 PM PDT 24
Peak memory 242636 kb
Host smart-f19085bd-fbeb-4c2b-ba92-12c832f3da2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278602785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3278602785
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.2829115162
Short name T465
Test name
Test status
Simulation time 876686218 ps
CPU time 12.54 seconds
Started Jun 22 07:01:33 PM PDT 24
Finished Jun 22 07:01:49 PM PDT 24
Peak memory 242152 kb
Host smart-c225fd99-6de3-4c6d-a899-30042ca5c8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829115162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.2829115162
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.630493727
Short name T120
Test name
Test status
Simulation time 169275101622 ps
CPU time 2365.39 seconds
Started Jun 22 07:01:30 PM PDT 24
Finished Jun 22 07:40:58 PM PDT 24
Peak memory 652364 kb
Host smart-5c3e5067-a481-4c27-846d-1dde01026977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630493727 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.630493727
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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