Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_addr_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_addr_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_addr_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_addr_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11197

1

T2

44

T5

2

T6

4

auto[1]

1841

1

T2

6

T7

4

T15

22

---

Summary for Variable flash_addr_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_addr_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

12994

1

T2

50

T5

2

T6

4

lc_esc_on

44

1

T10

1

T204

1

T363

1

---

Summary for Variable flash_addr_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12164

1

T2

38

T5

2

T6

4

auto[1]

874

1

T2

12

T7

5

T16

4

---

Summary for Variable flash_addr_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2007

1

T2

6

T7

3

T10

1

auto[1]

11031

1

T2

44

T5

2

T6

4

---

Summary for Variable flash_addr_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12116

1

T2

38

T5

2

T6

4

auto[1]

922

1

T2

12

T7

5

T16

3

---

Summary for Variable flash_addr_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12489

1

T2

36

T5

2

T6

4

auto[1]

549

1

T2

14

T7

2

T103

2