Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	49017	1			T7	114		T10	468		T11	130
access_err	60411	1			T2	221		T7	509		T11	13
write_blank_err	458	1			T7	1		T15	1		T8	12
ecc_uncorr_err	74188	1			T7	314		T15	261		T114	93
ecc_corr_err	1214	1			T114	2		T139	5		T105	2
no_err	90608	1			T2	175		T5	33		T6	149

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	820	1			T8	21		T9	2		T14	2
secret2	25753	1			T2	75		T5	5		T6	29
secret1	28458	1			T2	43		T5	3		T6	12
secret0	34903	1			T2	26		T5	5		T6	17
hw_cfg1	41544	1			T2	42		T5	6		T6	18
hw_cfg0	27166	1			T2	36		T6	11		T7	237
rot_creator_auth_state	25372	1			T2	24		T5	4		T6	10
rot_creator_auth_codesign	19994	1			T2	42		T6	5		T7	153
owner_sw_cfg	18616	1			T2	18		T5	4		T6	14
creator_sw_cfg	21933	1			T2	45		T6	12		T7	155
vendor_test	31337	1			T2	45		T5	6		T6	21

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3316	1			T166	175		T171	30		T280	151
fsm_err	secret1	4122	1			T234	185		T261	160		T167	28
fsm_err	secret0	3410	1			T11	130		T357	105		T358	1
fsm_err	hw_cfg1	3614	1			T359	497		T360	111		T361	162
fsm_err	hw_cfg0	6788	1			T7	114		T10	468		T204	57
fsm_err	rot_creator_auth_state	3796	1			T222	64		T198	17		T263	498
fsm_err	rot_creator_auth_codesign	2578	1			T238	137		T213	79		T250	259
fsm_err	owner_sw_cfg	1916	1			T17	213		T252	148		T362	293
fsm_err	creator_sw_cfg	5155	1			T205	50		T105	4		T248	396
fsm_err	vendor_test	14322	1			T79	419		T69	3		T363	28
access_err	life_cycle	820	1			T8	21		T9	2		T14	2
access_err	secret2	10935	1			T2	70		T7	103		T15	59
access_err	secret1	5719	1			T2	26		T15	58		T29	1
access_err	secret0	4291	1			T2	17		T7	7		T15	36
access_err	hw_cfg1	1228	1			T2	1		T7	5		T15	9
access_err	hw_cfg0	2117	1			T2	8		T15	9		T29	4
access_err	rot_creator_auth_state	5818	1			T2	9		T7	74		T15	35
access_err	rot_creator_auth_codesign	7728	1			T2	24		T7	87		T11	6
access_err	owner_sw_cfg	6656	1			T2	2		T7	47		T15	14
access_err	creator_sw_cfg	7792	1			T2	36		T7	109		T11	2
access_err	vendor_test	7307	1			T2	28		T7	77		T11	5
write_blank_err	secret2	15	1			T13	1		T239	2		T364	1
write_blank_err	secret1	25	1			T14	1		T177	1		T300	1
write_blank_err	secret0	49	1			T7	1		T8	1		T13	1
write_blank_err	hw_cfg1	76	1			T9	2		T108	1		T365	1
write_blank_err	hw_cfg0	14	1			T366	1		T239	1		T303	1
write_blank_err	rot_creator_auth_state	136	1			T15	1		T8	3		T9	3
write_blank_err	rot_creator_auth_codesign	65	1			T8	7		T9	3		T13	6
write_blank_err	owner_sw_cfg	28	1			T367	1		T368	3		T153	5
write_blank_err	creator_sw_cfg	20	1			T177	1		T368	1		T369	1
write_blank_err	vendor_test	30	1			T8	1		T370	1		T371	1
ecc_uncorr_err	secret2	5949	1			T139	85		T105	2		T13	119
ecc_uncorr_err	secret1	9510	1			T14	730		T178	44		T177	383
ecc_uncorr_err	secret0	18318	1			T7	314		T8	191		T13	596
ecc_uncorr_err	hw_cfg1	25700	1			T9	230		T108	536		T178	40
ecc_uncorr_err	hw_cfg0	5760	1			T114	31		T139	44		T171	76
ecc_uncorr_err	rot_creator_auth_state	7124	1			T15	261		T114	29		T139	49
ecc_uncorr_err	rot_creator_auth_codesign	735	1			T178	35		T213	76		T167	30
ecc_uncorr_err	owner_sw_cfg	399	1			T114	33		T178	35		T213	38
ecc_uncorr_err	creator_sw_cfg	693	1			T222	62		T171	27		T198	17
ecc_corr_err	secret2	74	1			T30	3		T71	2		T171	4
ecc_corr_err	secret1	139	1			T105	1		T178	2		T222	4
ecc_corr_err	secret0	119	1			T114	1		T178	1		T30	1
ecc_corr_err	hw_cfg1	208	1			T114	1		T105	1		T178	2
ecc_corr_err	hw_cfg0	230	1			T139	1		T222	2		T215	3
ecc_corr_err	rot_creator_auth_state	111	1			T179	3		T31	2		T171	2
ecc_corr_err	rot_creator_auth_codesign	114	1			T139	4		T30	3		T71	5
ecc_corr_err	owner_sw_cfg	108	1			T222	1		T71	1		T171	1
ecc_corr_err	creator_sw_cfg	111	1			T30	2		T177	4		T171	1
no_err	secret2	5464	1			T2	5		T5	5		T6	29
no_err	secret1	8943	1			T2	17		T5	3		T6	12
no_err	secret0	8716	1			T2	9		T5	5		T6	17
no_err	hw_cfg1	10718	1			T2	41		T5	6		T6	18
no_err	hw_cfg0	12257	1			T2	28		T6	11		T7	123
no_err	rot_creator_auth_state	8387	1			T2	15		T5	4		T6	10
no_err	rot_creator_auth_codesign	8774	1			T2	18		T6	5		T7	66
no_err	owner_sw_cfg	9509	1			T2	16		T5	4		T6	14
no_err	creator_sw_cfg	8162	1			T2	9		T6	12		T7	46
no_err	vendor_test	9678	1			T2	17		T5	6		T6	21

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded