Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	0	4	100.00
Crosses	4	0	4	100.00

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_index	2	0	2	100.00	100	1	1	0
secret1_lock	2	0	2	100.00	100	1	1	2

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::flash_req_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
flash_req_lock_cross	4	0	4	100.00	100	1	1	0

Summary for Variable flash_index

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_index

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

flash_addr_key

6312

1

T1

7

T3

12

T5

33

flash_data_key

6257

1

T1

7

T3

12

T5

33

---

Summary for Variable secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for secret1_lock

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7513

1

T1

2

T3

2

T5

11

auto[1]

5056

1

T1

12

T3

22

T5

55

---

Summary for Cross flash_req_lock_cross

Samples crossed: flash_index secret1_lock

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for flash_req_lock_cross

Bins

flash_index

secret1_lock

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

flash_addr_key

auto[0]

3780

1

T1

1

T3

1

T5

6

flash_addr_key

auto[1]

2532

1

T1

6

T3

11

T5

27

flash_data_key

auto[0]

3733

1

T1

1

T3

1

T5

5

flash_data_key

auto[1]

2524

1

T1

6

T3

11

T5

28