Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1012 |
1 |
|
|
T6 |
23 |
|
T165 |
1 |
|
T129 |
1 |
auto[1] |
1056 |
1 |
|
|
T68 |
34 |
|
T170 |
17 |
|
T112 |
124 |
Summary for Variable sram_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for sram_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
54 |
1 |
|
|
T112 |
2 |
|
T381 |
3 |
|
T311 |
1 |
sram_key[0x1] |
664 |
1 |
|
|
T6 |
7 |
|
T165 |
1 |
|
T68 |
15 |
sram_key[0x2] |
672 |
1 |
|
|
T6 |
7 |
|
T68 |
16 |
|
T170 |
7 |
sram_key[0x3] |
678 |
1 |
|
|
T6 |
9 |
|
T129 |
1 |
|
T68 |
18 |
Summary for Cross sram_req_lock_cross
Samples crossed: sram_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for sram_req_lock_cross
Bins
sram_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
auto[0] |
33 |
1 |
|
|
T381 |
1 |
|
T311 |
1 |
|
T382 |
1 |
sram_key[0x0] |
auto[1] |
21 |
1 |
|
|
T112 |
2 |
|
T381 |
2 |
|
T383 |
2 |
sram_key[0x1] |
auto[0] |
315 |
1 |
|
|
T6 |
7 |
|
T165 |
1 |
|
T68 |
5 |
sram_key[0x1] |
auto[1] |
349 |
1 |
|
|
T68 |
10 |
|
T170 |
5 |
|
T112 |
40 |
sram_key[0x2] |
auto[0] |
330 |
1 |
|
|
T6 |
7 |
|
T68 |
4 |
|
T170 |
1 |
sram_key[0x2] |
auto[1] |
342 |
1 |
|
|
T68 |
12 |
|
T170 |
6 |
|
T112 |
43 |
sram_key[0x3] |
auto[0] |
334 |
1 |
|
|
T6 |
9 |
|
T129 |
1 |
|
T68 |
6 |
sram_key[0x3] |
auto[1] |
344 |
1 |
|
|
T68 |
12 |
|
T170 |
6 |
|
T112 |
39 |