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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10361 1 T1 5 T2 3 T3 3
true 16857 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11278 1 T1 5 T2 3 T3 3
true 16909 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T109 2 T100 2 T108 2
others[1] 106 1 T9 2 T34 2 T103 2
others[2] 106 1 T4 6 T103 2 T105 2
others[3] 126 1 T4 2 T99 2 T123 2
others[4] 74 1 T103 2 T105 2 T125 2
others[5] 100 1 T98 2 T104 2 T341 2
others[6] 112 1 T104 2 T224 2 T125 2
others[7] 136 1 T4 4 T5 2 T34 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 100 1 T104 2 T105 2 T106 2
others[1] 104 1 T4 4 T123 2 T276 2
others[2] 100 1 T34 2 T102 2 T123 4
others[3] 90 1 T4 4 T9 2 T272 2
others[4] 68 1 T102 2 T106 2 T123 2
others[5] 102 1 T4 2 T107 2 T124 2
others[6] 94 1 T4 6 T34 2 T107 2
others[7] 102 1 T4 2 T34 2 T98 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T4 2 T34 2 T103 2
others[1] 98 1 T4 4 T209 2 T93 2
others[2] 86 1 T68 2 T123 2 T125 4
others[3] 112 1 T4 4 T98 2 T123 2
others[4] 108 1 T4 2 T104 2 T379 2
others[5] 78 1 T9 2 T108 2 T103 2
others[6] 104 1 T4 2 T340 2 T341 2
others[7] 108 1 T4 2 T99 4 T102 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 58 1 T4 2 T9 4 T34 2
others[1] 66 1 T100 2 T123 2 T125 2
others[2] 62 1 T4 4 T272 2 T341 2
others[3] 74 1 T109 2 T102 2 T103 2
others[4] 72 1 T4 2 T68 2 T123 2
others[5] 96 1 T4 4 T9 2 T100 2
others[6] 76 1 T9 2 T68 2 T98 2
others[7] 78 1 T4 4 T9 2 T98 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 126 1 T4 4 T98 2 T103 2
others[1] 92 1 T4 4 T102 2 T107 2
others[2] 114 1 T4 2 T123 2 T340 2
others[3] 96 1 T4 4 T104 2 T380 2
others[4] 84 1 T4 2 T124 2 T130 2
others[5] 86 1 T4 2 T34 2 T108 2
others[6] 112 1 T4 4 T103 4 T104 2
others[7] 132 1 T4 4 T9 4 T34 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 42 1 T4 2 T103 2 T123 2
others[1] 40 1 T105 2 T381 2 T312 2
others[2] 36 1 T224 4 T173 2 T382 2
others[3] 28 1 T4 2 T133 2 T93 2
others[4] 26 1 T4 2 T125 2 T243 2
others[5] 28 1 T105 2 T125 2 T341 2
others[6] 36 1 T4 2 T103 2 T105 2
others[7] 58 1 T1 2 T4 2 T224 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 116 1 T34 2 T124 2 T209 4
others[1] 114 1 T4 4 T99 2 T100 2
others[2] 96 1 T4 2 T103 2 T105 2
others[3] 82 1 T4 2 T272 2 T95 2
others[4] 80 1 T68 2 T276 2 T341 6
others[5] 66 1 T4 2 T68 2 T275 2
others[6] 108 1 T104 2 T106 4 T125 4
others[7] 144 1 T4 8 T102 2 T123 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T4 2 T275 2 T341 2
others[1] 90 1 T4 2 T123 2 T95 2
others[2] 86 1 T4 4 T102 2 T103 2
others[3] 100 1 T4 2 T124 2 T340 2
others[4] 104 1 T209 2 T383 2 T310 4
others[5] 110 1 T34 2 T99 2 T104 2
others[6] 110 1 T98 4 T104 2 T123 2
others[7] 136 1 T4 2 T99 2 T103 4
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 92 1 T4 4 T105 2 T124 2
others[1] 100 1 T4 4 T98 2 T102 2
others[2] 118 1 T1 2 T102 2 T107 2
others[3] 90 1 T98 2 T101 2 T103 4
others[4] 98 1 T4 2 T9 2 T103 2
others[5] 100 1 T4 2 T105 2 T209 2
others[6] 146 1 T4 2 T68 2 T99 2
others[7] 116 1 T98 2 T103 2 T209 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T103 2 T104 2 T275 2
others[1] 90 1 T4 2 T100 2 T105 2
others[2] 96 1 T108 2 T124 2 T130 2
others[3] 98 1 T4 2 T68 2 T102 2
others[4] 96 1 T4 2 T102 2 T103 4
others[5] 90 1 T109 2 T209 2 T93 2
others[6] 92 1 T4 4 T9 2 T34 2
others[7] 138 1 T4 8 T101 2 T124 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T4 2 T103 2 T209 2
others[1] 106 1 T4 2 T102 2 T105 4
others[2] 92 1 T4 2 T123 4 T340 2
others[3] 82 1 T93 2 T341 2 T384 2
others[4] 116 1 T4 4 T68 4 T106 2
others[5] 100 1 T4 2 T104 2 T123 2
others[6] 114 1 T109 2 T99 2 T103 4
others[7] 104 1 T9 2 T34 2 T108 2
false 14454 1 T1 6 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 30 1 T1 2 T6 1 T139 1
others[1] 32 1 T25 1 T225 1 T121 1
others[2] 31 1 T139 1 T16 1 T225 1
others[3] 40 1 T6 1 T13 1 T15 1
others[4] 29 1 T274 2 T139 1 T121 1
others[5] 33 1 T15 1 T225 1 T247 1
others[6] 36 1 T139 1 T252 2 T277 1
others[7] 40 1 T138 2 T247 1 T252 1
false 14454 1 T1 6 T2 4 T3 4
true 2469 1 T1 3 T4 40 T8 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T139 1 T16 1 T121 1
others[1] 33 1 T25 1 T247 1 T252 1
others[2] 47 1 T6 1 T138 2 T225 1
others[3] 25 1 T121 1 T277 1 T350 1
others[4] 33 1 T13 1 T15 1 T274 2
others[5] 41 1 T225 1 T247 1 T277 1
others[6] 38 1 T6 1 T15 1 T209 2
others[7] 27 1 T1 2 T139 2 T225 1
false 11775 1 T1 5 T2 3 T3 3
true 19301 1 T1 9 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 122 1 T4 2 T104 6 T340 2
others[1] 94 1 T4 2 T109 2 T98 2
others[2] 100 1 T104 2 T209 2 T224 2
others[3] 112 1 T34 2 T108 2 T103 2
others[4] 100 1 T4 2 T34 2 T99 2
others[5] 98 1 T100 2 T125 2 T341 2
others[6] 98 1 T4 4 T103 2 T104 2
others[7] 132 1 T4 2 T5 2 T9 2
false 7707 1 T1 1 T2 3 T3 3
true 16916 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T105 2 T272 2 T275 2
others[1] 100 1 T106 2 T125 2 T341 2
others[2] 96 1 T105 2 T276 2 T93 2
others[3] 82 1 T4 2 T34 2 T98 2
others[4] 92 1 T103 2 T123 2 T124 2
others[5] 110 1 T4 6 T34 4 T124 2
others[6] 98 1 T4 2 T102 2 T106 2
others[7] 114 1 T4 8 T9 2 T107 2
false 6994 1 T1 1 T2 3 T3 3
true 16698 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 98 1 T4 6 T68 2 T104 2
others[1] 80 1 T123 2 T209 2 T340 2
others[2] 118 1 T4 6 T124 2 T209 2
others[3] 86 1 T9 2 T123 2 T124 2
others[4] 92 1 T4 2 T34 2 T124 2
others[5] 98 1 T102 2 T108 2 T104 2
others[6] 86 1 T4 2 T99 2 T103 4
others[7] 132 1 T98 2 T99 2 T106 4
false 7293 1 T1 1 T2 3 T3 3
true 16710 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 36 1 T15 1 T341 2 T225 1
others[1] 31 1 T138 1 T225 1 T247 1
others[2] 43 1 T4 2 T102 2 T138 3
others[3] 35 1 T16 1 T225 1 T247 1
others[4] 51 1 T4 2 T5 2 T13 1
others[5] 36 1 T103 2 T15 1 T138 1
others[6] 40 1 T98 2 T139 1 T341 2
others[7] 40 1 T135 1 T252 1 T234 1
false 11714 1 T1 5 T2 3 T3 3
true 19222 1 T1 9 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 56 1 T102 2 T124 2 T385 2
others[1] 88 1 T4 2 T68 2 T98 2
others[2] 72 1 T4 2 T9 2 T34 2
others[3] 62 1 T9 2 T98 2 T106 2
others[4] 74 1 T4 4 T124 2 T341 2
others[5] 60 1 T104 2 T383 2 T341 2
others[6] 82 1 T4 4 T9 6 T103 2
others[7] 88 1 T4 4 T68 2 T100 2
false 8923 1 T1 5 T2 3 T3 3
true 16925 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 35 1 T9 2 T103 2 T106 2
others[1] 26 1 T4 2 T6 1 T138 1
others[2] 32 1 T15 1 T139 1 T16 1
others[3] 41 1 T139 1 T225 2 T247 1
others[4] 33 1 T139 1 T225 3 T121 1
others[5] 31 1 T276 2 T139 1 T225 1
others[6] 44 1 T275 2 T138 1 T16 1
others[7] 43 1 T103 2 T138 1 T225 2
false 11668 1 T1 5 T2 3 T3 3
true 19169 1 T1 8 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 104 1 T4 2 T9 2 T209 2
others[1] 116 1 T4 8 T104 2 T123 4
others[2] 90 1 T4 2 T103 4 T124 2
others[3] 84 1 T34 4 T102 2 T108 2
others[4] 104 1 T4 4 T98 2 T107 2
others[5] 112 1 T103 2 T104 2 T224 2
others[6] 88 1 T4 2 T9 2 T124 2
others[7] 144 1 T4 8 T103 2 T124 2
false 7586 1 T1 1 T2 3 T3 3
true 16843 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 45 1 T16 1 T121 4 T252 1
others[1] 30 1 T225 1 T247 3 T252 1
others[2] 26 1 T15 1 T225 1 T121 2
others[3] 46 1 T4 2 T276 2 T16 1
others[4] 32 1 T277 2 T59 2 T386 1
others[5] 36 1 T138 1 T16 1 T225 1
others[6] 30 1 T225 1 T121 1 T277 1
others[7] 38 1 T103 2 T135 1 T330 1
false 11630 1 T1 5 T2 3 T3 3
true 19201 1 T1 8 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 26 1 T310 2 T387 2 T382 2
others[1] 48 1 T1 2 T4 4 T133 2
others[2] 42 1 T103 2 T105 6 T125 2
others[3] 48 1 T4 4 T224 4 T243 2
others[4] 32 1 T103 2 T123 2 T125 4
others[5] 28 1 T125 2 T132 2 T382 2
others[6] 32 1 T209 2 T93 2 T382 2
others[7] 38 1 T4 2 T95 2 T341 2
false 10098 1 T1 1 T2 3 T3 3
true 16921 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T105 2 T124 2 T388 2
others[1] 82 1 T4 2 T102 2 T106 2
others[2] 102 1 T106 2 T272 4 T276 2
others[3] 104 1 T68 2 T102 2 T103 2
others[4] 106 1 T4 4 T99 2 T209 2
others[5] 84 1 T4 2 T104 2 T123 2
others[6] 108 1 T4 4 T68 2 T104 2
others[7] 126 1 T4 6 T34 2 T100 2
false 6986 1 T1 2 T2 3 T3 3
true 16690 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T103 2 T274 2 T125 2
others[1] 96 1 T34 2 T99 2 T209 4
others[2] 96 1 T4 2 T99 2 T106 2
others[3] 100 1 T4 2 T123 2 T340 2
others[4] 102 1 T4 2 T98 4 T125 2
others[5] 110 1 T102 2 T103 2 T123 2
others[6] 88 1 T4 2 T103 2 T104 2
others[7] 130 1 T4 4 T104 4 T93 4
false 6986 1 T1 2 T2 3 T3 3
true 16690 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 124 1 T4 2 T99 2 T101 2
others[1] 104 1 T103 2 T105 2 T123 2
others[2] 104 1 T9 2 T98 2 T102 4
others[3] 114 1 T4 2 T68 2 T209 4
others[4] 94 1 T4 4 T103 2 T276 2
others[5] 92 1 T4 2 T98 2 T103 2
others[6] 100 1 T1 2 T4 2 T102 2
others[7] 128 1 T4 2 T98 2 T123 2
false 6414 1 T1 2 T2 3 T3 2
true 16684 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T109 2 T101 2 T103 2
others[1] 110 1 T98 2 T102 2 T389 2
others[2] 82 1 T209 4 T275 2 T125 2
others[3] 98 1 T4 4 T109 2 T100 2
others[4] 120 1 T4 6 T34 2 T209 2
others[5] 96 1 T104 2 T105 2 T95 2
others[6] 88 1 T4 2 T103 2 T124 2
others[7] 116 1 T4 6 T9 2 T68 2
false 6414 1 T1 2 T2 3 T3 2
true 16684 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 86 1 T4 4 T104 2 T105 2
others[1] 48 1 T124 2 T209 4 T93 2
others[2] 76 1 T4 2 T9 2 T209 2
others[3] 78 1 T103 2 T106 2 T272 2
others[4] 56 1 T9 2 T34 2 T380 2
others[5] 74 1 T99 2 T100 2 T102 2
others[6] 74 1 T98 2 T276 2 T132 2
others[7] 62 1 T4 2 T98 2 T102 2
false 6977 1 T1 4 T2 2 T3 2
true 18205 1 T1 9 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 48 1 T103 2 T253 2 T246 2
others[1] 62 1 T98 2 T124 2 T95 2
others[2] 74 1 T9 2 T209 2 T93 2
others[3] 86 1 T4 2 T9 2 T68 2
others[4] 52 1 T103 2 T124 2 T272 2
others[5] 42 1 T102 2 T275 2 T125 2
others[6] 64 1 T4 2 T103 2 T95 2
others[7] 58 1 T105 2 T106 2 T272 2
false 6977 1 T1 4 T2 2 T3 2
true 18205 1 T1 9 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 34 1 T13 1 T138 1 T135 1
others[1] 33 1 T380 2 T173 2 T330 2
others[2] 41 1 T138 1 T16 1 T125 2
others[3] 27 1 T125 2 T380 2 T249 1
others[4] 39 1 T6 1 T138 1 T225 1
others[5] 45 1 T13 1 T95 2 T139 1
others[6] 34 1 T15 1 T276 2 T139 1
others[7] 36 1 T6 1 T138 1 T341 2
false 11868 1 T1 5 T2 3 T3 3
true 19363 1 T1 8 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 96 1 T4 2 T340 2 T380 2
others[1] 122 1 T4 6 T108 2 T103 2
others[2] 114 1 T103 2 T104 2 T105 2
others[3] 86 1 T9 2 T123 2 T341 2
others[4] 102 1 T109 2 T68 2 T99 2
others[5] 82 1 T4 2 T123 2 T125 6
others[6] 110 1 T34 2 T102 2 T103 2
others[7] 100 1 T4 2 T68 2 T106 2
false 7575 1 T1 1 T2 3 T3 3
true 16880 1 T1 6 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 32 1 T4 2 T138 1 T341 2
others[1] 40 1 T5 2 T16 1 T135 1
others[2] 40 1 T98 2 T139 1 T341 2
others[3] 41 1 T4 2 T13 1 T138 1
others[4] 34 1 T15 1 T138 1 T139 1
others[5] 47 1 T102 2 T25 1 T225 1
others[6] 31 1 T103 2 T225 1 T121 1
others[7] 44 1 T15 1 T274 2 T138 2
false 14454 1 T1 6 T2 4 T3 4
true 2435 1 T1 3 T4 40 T5 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%