Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
otbn_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
otbn_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
otbn_req_during_lc_esc	2	0	2	100.00	100	1	1	0
otbn_req_during_otp_idle	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable otbn_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13489

1

T1

2

T4

163

T5

6

auto[1]

991

1

T4

13

T6

13

T109

2

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Summary for Variable otbn_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13464

1

T1

2

T4

152

T5

6

auto[1]

1016

1

T4

24

T6

18

T7

1

---

Summary for Variable otbn_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for otbn_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

14444

1

T1

2

T4

176

T5

6

lc_esc_on

36

1

T96

1

T16

1

T125

1

---

Summary for Variable otbn_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2357

1

T4

16

T9

9

T6

5

auto[1]

12123

1

T1

2

T4

160

T5

6

---

Summary for Variable otbn_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13395

1

T1

2

T4

163

T5

6

auto[1]

1085

1

T4

13

T6

20

T109

1

---

Summary for Variable otbn_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14020

1

T1

2

T4

167

T5

6

auto[1]

460

1

T4

9

T6

7

T209

2