Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr_pin 2 0 2 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] 179007 1 T1 130 T2 3 T3 3
all_pins[1] 179007 1 T1 130 T2 3 T3 3



Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x0] 296096 1 T1 260 T2 5 T3 4
values[0x1] 61918 1 T2 1 T3 2 T4 1078
transitions[0x0=>0x1] 44561 1 T3 2 T4 691 T5 30
transitions[0x1=>0x0] 44487 1 T2 1 T3 2 T4 691



Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pincp_intr_pin_valueCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_pins[0] values[0x0] 135154 1 T1 130 T2 3 T3 1
all_pins[0] values[0x1] 43853 1 T3 2 T4 609 T5 26
all_pins[0] transitions[0x0=>0x1] 35216 1 T3 2 T4 416 T5 20
all_pins[0] transitions[0x1=>0x0] 9428 1 T2 1 T4 276 T5 10
all_pins[1] values[0x0] 160942 1 T1 130 T2 2 T3 3
all_pins[1] values[0x1] 18065 1 T2 1 T4 469 T5 16
all_pins[1] transitions[0x0=>0x1] 9345 1 T4 275 T5 10 T8 5
all_pins[1] transitions[0x1=>0x0] 35059 1 T3 2 T4 415 T5 20

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%