Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	47917	1			T2	99		T3	52		T11	44
access_err	65592	1			T1	90		T2	2		T4	1010
write_blank_err	438	1			T4	8		T14	7		T13	11
ecc_uncorr_err	66289	1			T4	773		T133	219		T14	64
ecc_corr_err	1340	1			T8	3		T133	2		T68	45
no_err	94070	1			T1	128		T2	1		T3	2

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	658	1			T4	4		T14	31		T13	14
secret2	24560	1			T1	8		T2	2		T4	207
secret1	29492	1			T1	28		T4	834		T5	8
secret0	33868	1			T1	24		T2	99		T4	193
hw_cfg1	40938	1			T1	17		T4	396		T5	10
hw_cfg0	25273	1			T1	18		T4	210		T5	8
rot_creator_auth_state	22840	1			T1	37		T4	203		T5	7
rot_creator_auth_codesign	21936	1			T1	27		T3	53		T4	249
owner_sw_cfg	21519	1			T1	13		T4	257		T5	5
creator_sw_cfg	20460	1			T1	17		T4	197		T5	10
vendor_test	34102	1			T1	29		T2	1		T3	1

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4087	1			T138	16		T341	496		T343	199
fsm_err	secret1	3920	1			T154	334		T344	345		T157	45
fsm_err	secret0	4920	1			T2	99		T211	209		T145	608
fsm_err	hw_cfg1	4294	1			T208	461		T150	491		T288	308
fsm_err	hw_cfg0	2873	1			T147	56		T16	31		T241	111
fsm_err	rot_creator_auth_state	3749	1			T12	291		T210	157		T172	55
fsm_err	rot_creator_auth_codesign	3254	1			T3	52		T11	44		T168	44
fsm_err	owner_sw_cfg	2692	1			T25	363		T96	135		T204	63
fsm_err	creator_sw_cfg	2602	1			T345	69		T346	143		T173	38
fsm_err	vendor_test	15526	1			T68	118		T73	28		T171	64
access_err	life_cycle	658	1			T4	4		T14	31		T13	14
access_err	secret2	11597	1			T1	6		T2	2		T4	133
access_err	secret1	6141	1			T1	8		T4	176		T5	2
access_err	secret0	4804	1			T1	5		T4	104		T9	5
access_err	hw_cfg1	1401	1			T1	1		T4	15		T5	3
access_err	hw_cfg0	2235	1			T1	1		T4	47		T9	1
access_err	rot_creator_auth_state	6206	1			T1	14		T4	74		T5	2
access_err	rot_creator_auth_codesign	8462	1			T1	17		T4	133		T5	7
access_err	owner_sw_cfg	7552	1			T1	5		T4	118		T5	2
access_err	creator_sw_cfg	8331	1			T1	13		T4	95		T5	3
access_err	vendor_test	8205	1			T1	20		T4	111		T11	2
write_blank_err	secret2	7	1			T103	1		T312	1		T347	1
write_blank_err	secret1	27	1			T4	1		T125	1		T226	1
write_blank_err	secret0	46	1			T161	1		T25	1		T209	1
write_blank_err	hw_cfg1	72	1			T4	1		T14	1		T13	2
write_blank_err	hw_cfg0	22	1			T13	1		T103	1		T209	1
write_blank_err	rot_creator_auth_state	135	1			T4	4		T14	6		T13	1
write_blank_err	rot_creator_auth_codesign	64	1			T13	7		T125	2		T341	1
write_blank_err	owner_sw_cfg	30	1			T103	2		T348	1		T136	1
write_blank_err	creator_sw_cfg	15	1			T4	1		T349	1		T350	1
write_blank_err	vendor_test	20	1			T4	1		T103	1		T209	1
ecc_uncorr_err	secret2	3391	1			T103	643		T215	13		T173	80
ecc_uncorr_err	secret1	10023	1			T4	566		T133	42		T160	6
ecc_uncorr_err	secret0	15351	1			T133	34		T161	261		T25	351
ecc_uncorr_err	hw_cfg1	23646	1			T4	207		T14	64		T13	193
ecc_uncorr_err	hw_cfg0	7058	1			T13	412		T103	94		T162	21
ecc_uncorr_err	rot_creator_auth_state	3834	1			T133	29		T215	14		T351	31
ecc_uncorr_err	rot_creator_auth_codesign	622	1			T133	58		T168	82		T172	63
ecc_uncorr_err	owner_sw_cfg	1598	1			T133	27		T162	21		T219	31
ecc_uncorr_err	creator_sw_cfg	766	1			T133	29		T97	93		T168	47
ecc_corr_err	secret2	73	1			T68	4		T130	2		T168	1
ecc_corr_err	secret1	110	1			T8	1		T133	1		T274	1
ecc_corr_err	secret0	188	1			T68	4		T160	1		T73	1
ecc_corr_err	hw_cfg1	242	1			T8	2		T68	18		T99	3
ecc_corr_err	hw_cfg0	255	1			T133	1		T68	7		T73	2
ecc_corr_err	rot_creator_auth_state	94	1			T99	1		T97	2		T168	3
ecc_corr_err	rot_creator_auth_codesign	139	1			T68	4		T99	3		T130	2
ecc_corr_err	owner_sw_cfg	104	1			T68	5		T130	1		T168	1
ecc_corr_err	creator_sw_cfg	135	1			T68	3		T99	1		T130	1
no_err	secret2	5405	1			T1	2		T4	74		T5	9
no_err	secret1	9271	1			T1	20		T4	91		T5	6
no_err	secret0	8559	1			T1	19		T4	89		T5	4
no_err	hw_cfg1	11283	1			T1	16		T4	173		T5	7
no_err	hw_cfg0	12830	1			T1	17		T4	163		T5	8
no_err	rot_creator_auth_state	8822	1			T1	23		T4	125		T5	5
no_err	rot_creator_auth_codesign	9395	1			T1	10		T3	1		T4	116
no_err	owner_sw_cfg	9543	1			T1	8		T4	139		T5	3
no_err	creator_sw_cfg	8611	1			T1	4		T4	101		T5	7
no_err	vendor_test	10351	1			T1	9		T2	1		T3	1

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded