Summary for Variable keymgr_rd_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for keymgr_rd_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
3869 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
45 |
auto[1] |
2576 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
25 |
Summary for Variable secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret2_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
4480 |
1 |
|
|
T1 |
4 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
1965 |
1 |
|
|
T4 |
22 |
|
T5 |
1 |
|
T9 |
8 |
Summary for Cross keymgr_output_conditions
Samples crossed: keymgr_rd_en secret2_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for keymgr_output_conditions
Bins
keymgr_rd_en | secret2_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
2676 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
30 |
auto[0] |
auto[1] |
1193 |
1 |
|
|
T4 |
15 |
|
T5 |
1 |
|
T9 |
5 |
auto[1] |
auto[0] |
1804 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T4 |
18 |
auto[1] |
auto[1] |
772 |
1 |
|
|
T4 |
7 |
|
T9 |
3 |
|
T34 |
2 |