Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
167044 |
1 |
|
|
T1 |
49 |
|
T2 |
40 |
|
T3 |
58 |
all_pins[1] |
167044 |
1 |
|
|
T1 |
49 |
|
T2 |
40 |
|
T3 |
58 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
277386 |
1 |
|
|
T1 |
50 |
|
T2 |
80 |
|
T3 |
58 |
values[0x1] |
56702 |
1 |
|
|
T1 |
48 |
|
T3 |
58 |
|
T9 |
65 |
transitions[0x0=>0x1] |
41762 |
1 |
|
|
T1 |
30 |
|
T3 |
58 |
|
T9 |
65 |
transitions[0x1=>0x0] |
41694 |
1 |
|
|
T1 |
30 |
|
T3 |
57 |
|
T9 |
64 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
125353 |
1 |
|
|
T1 |
16 |
|
T2 |
40 |
|
T4 |
76 |
all_pins[0] |
values[0x1] |
41691 |
1 |
|
|
T1 |
33 |
|
T3 |
58 |
|
T9 |
65 |
all_pins[0] |
transitions[0x0=>0x1] |
34258 |
1 |
|
|
T1 |
24 |
|
T3 |
58 |
|
T9 |
65 |
all_pins[0] |
transitions[0x1=>0x0] |
7578 |
1 |
|
|
T1 |
6 |
|
T5 |
2 |
|
T18 |
27 |
all_pins[1] |
values[0x0] |
152033 |
1 |
|
|
T1 |
34 |
|
T2 |
40 |
|
T3 |
58 |
all_pins[1] |
values[0x1] |
15011 |
1 |
|
|
T1 |
15 |
|
T5 |
2 |
|
T18 |
78 |
all_pins[1] |
transitions[0x0=>0x1] |
7504 |
1 |
|
|
T1 |
6 |
|
T5 |
2 |
|
T18 |
27 |
all_pins[1] |
transitions[0x1=>0x0] |
34116 |
1 |
|
|
T1 |
24 |
|
T3 |
57 |
|
T9 |
64 |