SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 43252 | 1 | T7 | 100 | T115 | 488 | T15 | 54 | ||||
access_err | 56161 | 1 | T1 | 22 | T5 | 5 | T18 | 229 | ||||
write_blank_err | 401 | 1 | T6 | 1 | T73 | 1 | T7 | 1 | ||||
ecc_uncorr_err | 64429 | 1 | T6 | 578 | T73 | 340 | T7 | 293 | ||||
ecc_corr_err | 1241 | 1 | T104 | 5 | T105 | 2 | T106 | 32 | ||||
no_err | 86199 | 1 | T1 | 50 | T4 | 111 | T5 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 669 | 1 | T6 | 9 | T7 | 11 | T8 | 7 | ||||
secret2 | 23993 | 1 | T1 | 7 | T4 | 6 | T18 | 29 | ||||
secret1 | 25150 | 1 | T1 | 11 | T4 | 20 | T18 | 66 | ||||
secret0 | 28292 | 1 | T1 | 4 | T4 | 8 | T18 | 48 | ||||
hw_cfg1 | 37303 | 1 | T1 | 5 | T4 | 9 | T5 | 2 | ||||
hw_cfg0 | 22980 | 1 | T1 | 5 | T4 | 15 | T18 | 50 | ||||
rot_creator_auth_state | 21579 | 1 | T1 | 6 | T4 | 8 | T5 | 1 | ||||
rot_creator_auth_codesign | 20317 | 1 | T1 | 9 | T4 | 14 | T18 | 40 | ||||
owner_sw_cfg | 19380 | 1 | T1 | 7 | T4 | 11 | T18 | 53 | ||||
creator_sw_cfg | 19949 | 1 | T1 | 5 | T4 | 8 | T18 | 59 | ||||
vendor_test | 32071 | 1 | T1 | 13 | T4 | 12 | T5 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 3421 | 1 | T161 | 29 | T395 | 106 | T396 | 337 | ||||
fsm_err | secret1 | 4842 | 1 | T270 | 318 | T100 | 109 | T397 | 204 | ||||
fsm_err | secret0 | 1913 | 1 | T140 | 59 | T158 | 141 | T169 | 57 | ||||
fsm_err | hw_cfg1 | 3037 | 1 | T141 | 89 | T398 | 208 | T172 | 122 | ||||
fsm_err | hw_cfg0 | 3158 | 1 | T21 | 17 | T285 | 19 | T399 | 113 | ||||
fsm_err | rot_creator_auth_state | 2041 | 1 | T263 | 157 | T400 | 370 | T284 | 413 | ||||
fsm_err | rot_creator_auth_codesign | 3169 | 1 | T15 | 54 | T100 | 43 | T97 | 256 | ||||
fsm_err | owner_sw_cfg | 2967 | 1 | T183 | 80 | T41 | 19 | T100 | 245 | ||||
fsm_err | creator_sw_cfg | 3196 | 1 | T7 | 100 | T20 | 407 | T22 | 79 | ||||
fsm_err | vendor_test | 15508 | 1 | T115 | 488 | T183 | 67 | T71 | 246 | ||||
access_err | life_cycle | 669 | 1 | T6 | 9 | T7 | 11 | T8 | 7 | ||||
access_err | secret2 | 9676 | 1 | T1 | 3 | T18 | 21 | T19 | 8 | ||||
access_err | secret1 | 5150 | 1 | T18 | 38 | T19 | 4 | T110 | 2 | ||||
access_err | secret0 | 4071 | 1 | T1 | 1 | T18 | 4 | T19 | 2 | ||||
access_err | hw_cfg1 | 1200 | 1 | T1 | 4 | T5 | 2 | T18 | 6 | ||||
access_err | hw_cfg0 | 1865 | 1 | T18 | 15 | T19 | 4 | T55 | 6 | ||||
access_err | rot_creator_auth_state | 5490 | 1 | T1 | 1 | T18 | 36 | T48 | 2 | ||||
access_err | rot_creator_auth_codesign | 7382 | 1 | T18 | 25 | T19 | 6 | T7 | 41 | ||||
access_err | owner_sw_cfg | 6379 | 1 | T18 | 17 | T19 | 2 | T48 | 3 | ||||
access_err | creator_sw_cfg | 7242 | 1 | T1 | 3 | T18 | 35 | T19 | 13 | ||||
access_err | vendor_test | 7037 | 1 | T1 | 10 | T5 | 3 | T18 | 32 | ||||
write_blank_err | secret2 | 15 | 1 | T6 | 1 | T138 | 1 | T100 | 1 | ||||
write_blank_err | secret1 | 15 | 1 | T161 | 1 | T401 | 1 | T402 | 2 | ||||
write_blank_err | secret0 | 38 | 1 | T7 | 1 | T403 | 1 | T101 | 1 | ||||
write_blank_err | hw_cfg1 | 72 | 1 | T73 | 1 | T8 | 1 | T15 | 2 | ||||
write_blank_err | hw_cfg0 | 17 | 1 | T8 | 1 | T146 | 1 | T151 | 1 | ||||
write_blank_err | rot_creator_auth_state | 133 | 1 | T8 | 1 | T41 | 1 | T381 | 1 | ||||
write_blank_err | rot_creator_auth_codesign | 38 | 1 | T32 | 1 | T146 | 3 | T151 | 1 | ||||
write_blank_err | owner_sw_cfg | 40 | 1 | T15 | 1 | T32 | 10 | T146 | 1 | ||||
write_blank_err | creator_sw_cfg | 15 | 1 | T15 | 3 | T32 | 1 | T146 | 1 | ||||
write_blank_err | vendor_test | 18 | 1 | T8 | 2 | T32 | 1 | T404 | 1 | ||||
ecc_uncorr_err | secret2 | 5739 | 1 | T6 | 578 | T104 | 23 | T138 | 156 | ||||
ecc_uncorr_err | secret1 | 6293 | 1 | T105 | 41 | T183 | 137 | T161 | 404 | ||||
ecc_uncorr_err | secret0 | 13956 | 1 | T7 | 293 | T104 | 14 | T403 | 250 | ||||
ecc_uncorr_err | hw_cfg1 | 22791 | 1 | T73 | 340 | T104 | 23 | T15 | 412 | ||||
ecc_uncorr_err | hw_cfg0 | 5990 | 1 | T104 | 13 | T8 | 634 | T151 | 610 | ||||
ecc_uncorr_err | rot_creator_auth_state | 5962 | 1 | T104 | 15 | T183 | 214 | T41 | 394 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 1172 | 1 | T104 | 22 | T183 | 51 | T195 | 44 | ||||
ecc_uncorr_err | owner_sw_cfg | 1035 | 1 | T105 | 47 | T183 | 69 | T195 | 20 | ||||
ecc_uncorr_err | creator_sw_cfg | 1491 | 1 | T104 | 39 | T32 | 325 | T248 | 39 | ||||
ecc_corr_err | secret2 | 56 | 1 | T106 | 1 | T183 | 1 | T64 | 1 | ||||
ecc_corr_err | secret1 | 118 | 1 | T104 | 3 | T183 | 2 | T71 | 4 | ||||
ecc_corr_err | secret0 | 119 | 1 | T104 | 1 | T106 | 2 | T72 | 1 | ||||
ecc_corr_err | hw_cfg1 | 225 | 1 | T106 | 13 | T8 | 1 | T183 | 4 | ||||
ecc_corr_err | hw_cfg0 | 230 | 1 | T105 | 1 | T106 | 3 | T183 | 1 | ||||
ecc_corr_err | rot_creator_auth_state | 134 | 1 | T106 | 2 | T183 | 1 | T72 | 4 | ||||
ecc_corr_err | rot_creator_auth_codesign | 106 | 1 | T183 | 3 | T71 | 3 | T72 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 127 | 1 | T104 | 1 | T106 | 5 | T72 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 126 | 1 | T105 | 1 | T106 | 6 | T72 | 9 | ||||
no_err | secret2 | 5086 | 1 | T1 | 4 | T4 | 6 | T18 | 8 | ||||
no_err | secret1 | 8732 | 1 | T1 | 11 | T4 | 20 | T18 | 28 | ||||
no_err | secret0 | 8195 | 1 | T1 | 3 | T4 | 8 | T18 | 44 | ||||
no_err | hw_cfg1 | 9978 | 1 | T1 | 1 | T4 | 9 | T18 | 37 | ||||
no_err | hw_cfg0 | 11720 | 1 | T1 | 5 | T4 | 15 | T18 | 35 | ||||
no_err | rot_creator_auth_state | 7819 | 1 | T1 | 5 | T4 | 8 | T5 | 1 | ||||
no_err | rot_creator_auth_codesign | 8450 | 1 | T1 | 9 | T4 | 14 | T18 | 15 | ||||
no_err | owner_sw_cfg | 8832 | 1 | T1 | 7 | T4 | 11 | T18 | 36 | ||||
no_err | creator_sw_cfg | 7879 | 1 | T1 | 2 | T4 | 8 | T18 | 24 | ||||
no_err | vendor_test | 9508 | 1 | T1 | 3 | T4 | 12 | T18 | 34 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |