Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1843 |
1 |
|
|
T104 |
17 |
|
T183 |
24 |
|
T16 |
15 |
auto[1] |
1161 |
1 |
|
|
T116 |
2 |
|
T107 |
4 |
|
T74 |
75 |
Summary for Variable sram_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for sram_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
120 |
1 |
|
|
T280 |
6 |
|
T307 |
9 |
|
T145 |
4 |
sram_key[0x1] |
1003 |
1 |
|
|
T104 |
8 |
|
T107 |
2 |
|
T183 |
8 |
sram_key[0x2] |
963 |
1 |
|
|
T116 |
1 |
|
T104 |
1 |
|
T107 |
2 |
sram_key[0x3] |
918 |
1 |
|
|
T116 |
1 |
|
T104 |
8 |
|
T183 |
8 |
Summary for Cross sram_req_lock_cross
Samples crossed: sram_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for sram_req_lock_cross
Bins
sram_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
auto[0] |
71 |
1 |
|
|
T280 |
1 |
|
T307 |
2 |
|
T145 |
1 |
sram_key[0x0] |
auto[1] |
49 |
1 |
|
|
T280 |
5 |
|
T307 |
7 |
|
T145 |
3 |
sram_key[0x1] |
auto[0] |
629 |
1 |
|
|
T104 |
8 |
|
T183 |
8 |
|
T16 |
5 |
sram_key[0x1] |
auto[1] |
374 |
1 |
|
|
T107 |
2 |
|
T74 |
25 |
|
T100 |
29 |
sram_key[0x2] |
auto[0] |
599 |
1 |
|
|
T104 |
1 |
|
T183 |
8 |
|
T16 |
5 |
sram_key[0x2] |
auto[1] |
364 |
1 |
|
|
T116 |
1 |
|
T107 |
2 |
|
T74 |
25 |
sram_key[0x3] |
auto[0] |
544 |
1 |
|
|
T104 |
8 |
|
T183 |
8 |
|
T16 |
5 |
sram_key[0x3] |
auto[1] |
374 |
1 |
|
|
T116 |
1 |
|
T74 |
25 |
|
T100 |
29 |