Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	43806	1			T8	114		T10	43		T28	210
access_err	50218	1			T5	19		T8	1		T4	25
write_blank_err	250	1			T5	1		T6	3		T7	2
ecc_uncorr_err	47482	1			T5	644		T6	376		T7	517
ecc_corr_err	1179	1			T10	3		T28	26		T14	1
no_err	72685	1			T1	13		T2	10		T5	43

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	537	1			T5	7		T6	5		T7	6
secret2	18430	1			T2	2		T5	2		T4	5
secret1	20489	1			T5	7		T4	7		T10	2
secret0	28068	1			T1	4		T2	2		T5	2
hw_cfg1	33291	1			T1	2		T5	650		T4	6
hw_cfg0	18985	1			T2	2		T5	2		T8	114
rot_creator_auth_state	17128	1			T1	2		T5	7		T4	1
rot_creator_auth_codesign	18375	1			T1	2		T5	7		T4	18
owner_sw_cfg	18137	1			T2	1		T5	6		T8	1
creator_sw_cfg	16824	1			T2	1		T5	8		T4	2
vendor_test	25356	1			T1	3		T2	2		T5	9

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4233	1			T6	289		T223	292		T352	198
fsm_err	secret1	3990	1			T137	11		T204	162		T214	155
fsm_err	secret0	2887	1			T177	196		T16	241		T195	218
fsm_err	hw_cfg1	2905	1			T96	266		T221	45		T353	73
fsm_err	hw_cfg0	4932	1			T8	114		T96	418		T176	606
fsm_err	rot_creator_auth_state	2852	1			T64	415		T141	56		T176	427
fsm_err	rot_creator_auth_codesign	4018	1			T6	249		T205	557		T354	405
fsm_err	owner_sw_cfg	3485	1			T194	134		T230	11		T355	119
fsm_err	creator_sw_cfg	3123	1			T169	131		T141	50		T207	70
fsm_err	vendor_test	11381	1			T10	43		T28	210		T67	173
access_err	life_cycle	537	1			T5	7		T6	5		T7	6
access_err	secret2	8647	1			T4	2		T101	6		T28	32
access_err	secret1	5256	1			T28	20		T29	16		T39	18
access_err	secret0	3977	1			T4	8		T12	1		T28	22
access_err	hw_cfg1	1015	1			T4	2		T12	1		T101	1
access_err	hw_cfg0	1954	1			T29	1		T39	5		T15	2
access_err	rot_creator_auth_state	4505	1			T5	2		T12	1		T101	1
access_err	rot_creator_auth_codesign	6566	1			T5	4		T4	5		T28	8
access_err	owner_sw_cfg	5830	1			T5	3		T4	3		T12	3
access_err	creator_sw_cfg	6050	1			T5	3		T4	1		T12	3
access_err	vendor_test	5881	1			T8	1		T4	4		T101	4
write_blank_err	secret2	4	1			T225	1		T232	1		T356	1
write_blank_err	secret1	11	1			T357	1		T358	1		T359	1
write_blank_err	secret0	37	1			T6	1		T14	2		T96	1
write_blank_err	hw_cfg1	64	1			T5	1		T7	1		T14	1
write_blank_err	hw_cfg0	11	1			T13	1		T357	1		T207	1
write_blank_err	rot_creator_auth_state	69	1			T6	2		T7	1		T225	3
write_blank_err	rot_creator_auth_codesign	32	1			T14	2		T65	1		T239	1
write_blank_err	owner_sw_cfg	9	1			T360	1		T361	1		T334	1
write_blank_err	creator_sw_cfg	4	1			T234	1		T338	1		T362	2
write_blank_err	vendor_test	9	1			T202	1		T363	1		T364	1
ecc_uncorr_err	secret2	1264	1			T141	40		T365	14		T366	5
ecc_uncorr_err	secret1	3865	1			T358	604		T367	56		T359	614
ecc_uncorr_err	secret0	14401	1			T6	376		T14	369		T96	397
ecc_uncorr_err	hw_cfg1	20575	1			T5	644		T7	517		T14	25
ecc_uncorr_err	hw_cfg0	2242	1			T13	149		T137	22		T357	317
ecc_uncorr_err	rot_creator_auth_state	2655	1			T141	58		T367	125		T368	26
ecc_uncorr_err	rot_creator_auth_codesign	599	1			T141	36		T367	71		T365	51
ecc_uncorr_err	owner_sw_cfg	1121	1			T141	99		T268	24		T360	543
ecc_uncorr_err	creator_sw_cfg	760	1			T137	12		T186	14		T369	12
ecc_corr_err	secret2	59	1			T225	1		T137	1		T139	1
ecc_corr_err	secret1	101	1			T10	2		T28	1		T137	1
ecc_corr_err	secret0	109	1			T28	1		T14	1		T139	1
ecc_corr_err	hw_cfg1	238	1			T28	7		T203	3		T75	3
ecc_corr_err	hw_cfg0	249	1			T10	1		T28	7		T75	6
ecc_corr_err	rot_creator_auth_state	102	1			T28	4		T202	1		T139	2
ecc_corr_err	rot_creator_auth_codesign	122	1			T28	2		T137	1		T75	6
ecc_corr_err	owner_sw_cfg	101	1			T28	2		T141	4		T30	20
ecc_corr_err	creator_sw_cfg	98	1			T28	2		T75	3		T141	3
no_err	secret2	4223	1			T2	2		T5	2		T4	3
no_err	secret1	7266	1			T5	7		T4	7		T11	14
no_err	secret0	6657	1			T1	4		T2	2		T5	2
no_err	hw_cfg1	8494	1			T1	2		T5	5		T4	4
no_err	hw_cfg0	9597	1			T2	2		T5	2		T4	2
no_err	rot_creator_auth_state	6945	1			T1	2		T5	5		T4	1
no_err	rot_creator_auth_codesign	7038	1			T1	2		T5	3		T4	13
no_err	owner_sw_cfg	7591	1			T2	1		T5	3		T8	1
no_err	creator_sw_cfg	6789	1			T2	1		T5	5		T4	1
no_err	vendor_test	8085	1			T1	3		T2	2		T5	9

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded