Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1555 |
1 |
|
|
T13 |
28 |
|
T14 |
21 |
|
T104 |
1 |
auto[1] |
1290 |
1 |
|
|
T39 |
8 |
|
T95 |
3 |
|
T104 |
9 |
Summary for Variable sram_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for sram_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
114 |
1 |
|
|
T39 |
1 |
|
T13 |
3 |
|
T258 |
4 |
sram_key[0x1] |
935 |
1 |
|
|
T39 |
1 |
|
T13 |
7 |
|
T14 |
9 |
sram_key[0x2] |
957 |
1 |
|
|
T39 |
2 |
|
T13 |
8 |
|
T14 |
4 |
sram_key[0x3] |
839 |
1 |
|
|
T39 |
4 |
|
T13 |
10 |
|
T14 |
8 |
Summary for Cross sram_req_lock_cross
Samples crossed: sram_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for sram_req_lock_cross
Bins
sram_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
auto[0] |
76 |
1 |
|
|
T13 |
3 |
|
T258 |
4 |
|
T206 |
6 |
sram_key[0x0] |
auto[1] |
38 |
1 |
|
|
T39 |
1 |
|
T206 |
4 |
|
T207 |
1 |
sram_key[0x1] |
auto[0] |
505 |
1 |
|
|
T13 |
7 |
|
T14 |
9 |
|
T96 |
17 |
sram_key[0x1] |
auto[1] |
430 |
1 |
|
|
T39 |
1 |
|
T95 |
1 |
|
T104 |
1 |
sram_key[0x2] |
auto[0] |
536 |
1 |
|
|
T13 |
8 |
|
T14 |
4 |
|
T104 |
1 |
sram_key[0x2] |
auto[1] |
421 |
1 |
|
|
T39 |
2 |
|
T95 |
1 |
|
T104 |
4 |
sram_key[0x3] |
auto[0] |
438 |
1 |
|
|
T13 |
10 |
|
T14 |
8 |
|
T96 |
19 |
sram_key[0x3] |
auto[1] |
401 |
1 |
|
|
T39 |
4 |
|
T95 |
1 |
|
T104 |
4 |