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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.79 93.71 96.65 95.99 90.69 97.05 96.28 93.14


Total test records in report: 1194
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T1044 /workspace/coverage/default/19.otp_ctrl_test_access.1495815100 Jun 27 07:18:41 PM PDT 24 Jun 27 07:21:12 PM PDT 24 12218566403 ps
T1045 /workspace/coverage/default/36.otp_ctrl_dai_errs.660371498 Jun 27 07:21:01 PM PDT 24 Jun 27 07:23:42 PM PDT 24 1774593996 ps
T1046 /workspace/coverage/default/41.otp_ctrl_smoke.856390898 Jun 27 07:24:10 PM PDT 24 Jun 27 07:27:08 PM PDT 24 315325006 ps
T1047 /workspace/coverage/default/19.otp_ctrl_macro_errs.1448879799 Jun 27 07:18:42 PM PDT 24 Jun 27 07:23:55 PM PDT 24 1788936442 ps
T1048 /workspace/coverage/default/15.otp_ctrl_init_fail.4047694151 Jun 27 07:18:08 PM PDT 24 Jun 27 07:21:05 PM PDT 24 98700241 ps
T1049 /workspace/coverage/default/37.otp_ctrl_dai_errs.3920823200 Jun 27 07:21:17 PM PDT 24 Jun 27 07:24:14 PM PDT 24 1804572979 ps
T1050 /workspace/coverage/default/214.otp_ctrl_init_fail.3595002179 Jun 27 07:26:41 PM PDT 24 Jun 27 07:28:52 PM PDT 24 2021665990 ps
T1051 /workspace/coverage/default/162.otp_ctrl_init_fail.34225844 Jun 27 07:27:11 PM PDT 24 Jun 27 07:29:13 PM PDT 24 164984966 ps
T1052 /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2607805286 Jun 27 07:20:10 PM PDT 24 Jun 27 07:55:41 PM PDT 24 353388370747 ps
T1053 /workspace/coverage/default/257.otp_ctrl_init_fail.2821584845 Jun 27 07:26:39 PM PDT 24 Jun 27 07:28:49 PM PDT 24 295753237 ps
T1054 /workspace/coverage/default/28.otp_ctrl_test_access.2907719214 Jun 27 07:20:07 PM PDT 24 Jun 27 07:22:55 PM PDT 24 831399056 ps
T1055 /workspace/coverage/default/41.otp_ctrl_parallel_key_req.4033564457 Jun 27 07:25:15 PM PDT 24 Jun 27 07:27:45 PM PDT 24 7067672837 ps
T1056 /workspace/coverage/default/298.otp_ctrl_init_fail.1540866944 Jun 27 07:27:17 PM PDT 24 Jun 27 07:29:43 PM PDT 24 1419048643 ps
T1057 /workspace/coverage/default/33.otp_ctrl_dai_errs.665636689 Jun 27 07:22:19 PM PDT 24 Jun 27 07:25:00 PM PDT 24 726386317 ps
T1058 /workspace/coverage/default/25.otp_ctrl_check_fail.3166793002 Jun 27 07:19:59 PM PDT 24 Jun 27 07:22:48 PM PDT 24 4426872150 ps
T1059 /workspace/coverage/default/49.otp_ctrl_macro_errs.2045315358 Jun 27 07:26:15 PM PDT 24 Jun 27 07:28:38 PM PDT 24 312657996 ps
T1060 /workspace/coverage/default/150.otp_ctrl_init_fail.76775483 Jun 27 07:25:16 PM PDT 24 Jun 27 07:27:22 PM PDT 24 102059570 ps
T1061 /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2663602785 Jun 27 07:28:37 PM PDT 24 Jun 27 07:30:44 PM PDT 24 1996758810 ps
T1062 /workspace/coverage/default/216.otp_ctrl_init_fail.3000294370 Jun 27 07:26:40 PM PDT 24 Jun 27 07:28:50 PM PDT 24 124374638 ps
T252 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1602860390 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:13 PM PDT 24 425761204 ps
T249 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3242902759 Jun 27 07:15:36 PM PDT 24 Jun 27 07:17:31 PM PDT 24 1745885079 ps
T1063 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2761693430 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 104277945 ps
T253 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4094039861 Jun 27 07:13:44 PM PDT 24 Jun 27 07:15:37 PM PDT 24 556695832 ps
T1064 /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2946243116 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:54 PM PDT 24 143345208 ps
T1065 /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3558050401 Jun 27 07:15:26 PM PDT 24 Jun 27 07:17:03 PM PDT 24 519612268 ps
T283 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3697509990 Jun 27 07:14:12 PM PDT 24 Jun 27 07:16:01 PM PDT 24 68814662 ps
T254 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3140739801 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:54 PM PDT 24 55158255 ps
T1066 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1280089667 Jun 27 07:15:03 PM PDT 24 Jun 27 07:16:41 PM PDT 24 619128590 ps
T1067 /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.42078763 Jun 27 07:15:06 PM PDT 24 Jun 27 07:16:37 PM PDT 24 56031375 ps
T1068 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.166395345 Jun 27 07:15:25 PM PDT 24 Jun 27 07:17:02 PM PDT 24 39957763 ps
T284 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.719311180 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:54 PM PDT 24 131471441 ps
T1069 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2384632087 Jun 27 07:14:40 PM PDT 24 Jun 27 07:16:17 PM PDT 24 37995635 ps
T387 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.650592828 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:39 PM PDT 24 103358663 ps
T1070 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.986397960 Jun 27 07:16:05 PM PDT 24 Jun 27 07:17:53 PM PDT 24 40810459 ps
T1071 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.369179313 Jun 27 07:15:37 PM PDT 24 Jun 27 07:17:12 PM PDT 24 42743944 ps
T1072 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1008493335 Jun 27 07:15:03 PM PDT 24 Jun 27 07:16:37 PM PDT 24 129820763 ps
T1073 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3631484339 Jun 27 07:13:46 PM PDT 24 Jun 27 07:15:37 PM PDT 24 57518417 ps
T1074 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3445141288 Jun 27 07:14:59 PM PDT 24 Jun 27 07:16:31 PM PDT 24 153998618 ps
T1075 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.171149847 Jun 27 07:16:04 PM PDT 24 Jun 27 07:17:53 PM PDT 24 137975159 ps
T1076 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3044987850 Jun 27 07:15:52 PM PDT 24 Jun 27 07:17:34 PM PDT 24 37212364 ps
T1077 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.383670601 Jun 27 07:13:47 PM PDT 24 Jun 27 07:15:35 PM PDT 24 41003811 ps
T1078 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3135228511 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:02 PM PDT 24 39335024 ps
T1079 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.361181169 Jun 27 07:14:23 PM PDT 24 Jun 27 07:16:01 PM PDT 24 40995314 ps
T250 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1528642988 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:21 PM PDT 24 694639962 ps
T1080 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1446820174 Jun 27 07:13:46 PM PDT 24 Jun 27 07:15:36 PM PDT 24 607039010 ps
T337 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2773053722 Jun 27 07:14:26 PM PDT 24 Jun 27 07:16:05 PM PDT 24 187366921 ps
T285 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2803458103 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:49 PM PDT 24 494310372 ps
T326 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.781088729 Jun 27 07:15:02 PM PDT 24 Jun 27 07:16:33 PM PDT 24 285502515 ps
T327 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1787062207 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:54 PM PDT 24 146453449 ps
T1081 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2875147348 Jun 27 07:14:51 PM PDT 24 Jun 27 07:16:26 PM PDT 24 204697287 ps
T251 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.850395258 Jun 27 07:15:23 PM PDT 24 Jun 27 07:17:11 PM PDT 24 1220360721 ps
T286 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4069738538 Jun 27 07:14:29 PM PDT 24 Jun 27 07:16:02 PM PDT 24 88293280 ps
T1082 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.32655741 Jun 27 07:16:17 PM PDT 24 Jun 27 07:18:11 PM PDT 24 136265905 ps
T372 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3688955139 Jun 27 07:13:49 PM PDT 24 Jun 27 07:15:50 PM PDT 24 2840884210 ps
T1083 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.716614270 Jun 27 07:16:18 PM PDT 24 Jun 27 07:18:12 PM PDT 24 127734675 ps
T328 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.865906135 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:13 PM PDT 24 181459794 ps
T373 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.198573416 Jun 27 07:15:05 PM PDT 24 Jun 27 07:16:57 PM PDT 24 4714299894 ps
T376 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1993921897 Jun 27 07:15:40 PM PDT 24 Jun 27 07:17:31 PM PDT 24 1698297232 ps
T329 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2682452801 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:56 PM PDT 24 1215820527 ps
T374 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1910967400 Jun 27 07:14:12 PM PDT 24 Jun 27 07:16:18 PM PDT 24 2621765644 ps
T1084 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1095001486 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:45 PM PDT 24 112624518 ps
T1085 /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1442027968 Jun 27 07:16:04 PM PDT 24 Jun 27 07:17:53 PM PDT 24 44764785 ps
T377 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.502950597 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:13 PM PDT 24 1066202263 ps
T1086 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3643593083 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:14 PM PDT 24 114471897 ps
T330 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.969971198 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:04 PM PDT 24 455689351 ps
T1087 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1805048967 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:20 PM PDT 24 2512826257 ps
T331 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1038352266 Jun 27 07:15:38 PM PDT 24 Jun 27 07:17:13 PM PDT 24 186542215 ps
T295 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.994936273 Jun 27 07:14:12 PM PDT 24 Jun 27 07:16:03 PM PDT 24 81092965 ps
T1088 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.919687550 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:56 PM PDT 24 127054805 ps
T1089 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2179822414 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:12 PM PDT 24 176137618 ps
T1090 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1187650242 Jun 27 07:15:41 PM PDT 24 Jun 27 07:17:23 PM PDT 24 252185138 ps
T1091 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2724514208 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:03 PM PDT 24 1309481713 ps
T1092 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.962978197 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:58 PM PDT 24 160991452 ps
T1093 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.276882835 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 85901361 ps
T1094 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2110096514 Jun 27 07:14:30 PM PDT 24 Jun 27 07:16:06 PM PDT 24 41068512 ps
T1095 /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1121455778 Jun 27 07:15:03 PM PDT 24 Jun 27 07:16:38 PM PDT 24 338760967 ps
T1096 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3485136184 Jun 27 07:16:05 PM PDT 24 Jun 27 07:17:53 PM PDT 24 38083486 ps
T1097 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2939311272 Jun 27 07:14:54 PM PDT 24 Jun 27 07:16:23 PM PDT 24 44019336 ps
T255 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3536824079 Jun 27 07:15:25 PM PDT 24 Jun 27 07:17:12 PM PDT 24 5014588602 ps
T1098 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3354442365 Jun 27 07:15:22 PM PDT 24 Jun 27 07:16:55 PM PDT 24 50217161 ps
T1099 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1600924931 Jun 27 07:15:38 PM PDT 24 Jun 27 07:17:16 PM PDT 24 255299389 ps
T1100 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2221365090 Jun 27 07:14:10 PM PDT 24 Jun 27 07:16:00 PM PDT 24 142064045 ps
T1101 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2513227915 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:44 PM PDT 24 41257075 ps
T1102 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.633987641 Jun 27 07:14:30 PM PDT 24 Jun 27 07:16:06 PM PDT 24 84006003 ps
T296 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.20947556 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:01 PM PDT 24 1055659936 ps
T1103 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.628358340 Jun 27 07:15:50 PM PDT 24 Jun 27 07:17:34 PM PDT 24 46752140 ps
T1104 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.80012251 Jun 27 07:14:23 PM PDT 24 Jun 27 07:16:05 PM PDT 24 195708313 ps
T297 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.392289769 Jun 27 07:14:25 PM PDT 24 Jun 27 07:16:07 PM PDT 24 1192704055 ps
T1105 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.890636702 Jun 27 07:16:03 PM PDT 24 Jun 27 07:17:53 PM PDT 24 94732101 ps
T1106 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3189021788 Jun 27 07:15:52 PM PDT 24 Jun 27 07:17:34 PM PDT 24 75468045 ps
T1107 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.291807593 Jun 27 07:15:51 PM PDT 24 Jun 27 07:17:34 PM PDT 24 140467056 ps
T1108 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1421880542 Jun 27 07:15:51 PM PDT 24 Jun 27 07:17:39 PM PDT 24 1844199393 ps
T1109 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2271849364 Jun 27 07:14:52 PM PDT 24 Jun 27 07:16:25 PM PDT 24 86103718 ps
T1110 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3621799090 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:12 PM PDT 24 80153824 ps
T1111 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1738099676 Jun 27 07:15:50 PM PDT 24 Jun 27 07:17:34 PM PDT 24 75431294 ps
T1112 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.811369691 Jun 27 07:14:50 PM PDT 24 Jun 27 07:16:26 PM PDT 24 269875345 ps
T1113 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.980213795 Jun 27 07:14:10 PM PDT 24 Jun 27 07:16:02 PM PDT 24 444954768 ps
T1114 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3919684266 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:48 PM PDT 24 741420053 ps
T298 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2028976567 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:54 PM PDT 24 54214326 ps
T1115 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1461101711 Jun 27 07:15:06 PM PDT 24 Jun 27 07:16:38 PM PDT 24 99882926 ps
T1116 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2093609566 Jun 27 07:15:22 PM PDT 24 Jun 27 07:16:55 PM PDT 24 401405884 ps
T1117 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3048170978 Jun 27 07:15:36 PM PDT 24 Jun 27 07:17:12 PM PDT 24 73764281 ps
T299 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2105178902 Jun 27 07:14:00 PM PDT 24 Jun 27 07:15:50 PM PDT 24 129537969 ps
T1118 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2376009451 Jun 27 07:13:47 PM PDT 24 Jun 27 07:15:38 PM PDT 24 213489967 ps
T1119 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3977203562 Jun 27 07:14:10 PM PDT 24 Jun 27 07:16:00 PM PDT 24 101641836 ps
T1120 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2720241757 Jun 27 07:15:37 PM PDT 24 Jun 27 07:17:15 PM PDT 24 388512752 ps
T1121 /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2174435758 Jun 27 07:15:52 PM PDT 24 Jun 27 07:17:34 PM PDT 24 84364293 ps
T1122 /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4291169420 Jun 27 07:14:51 PM PDT 24 Jun 27 07:16:26 PM PDT 24 162468491 ps
T1123 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3293788736 Jun 27 07:16:18 PM PDT 24 Jun 27 07:18:12 PM PDT 24 508774523 ps
T311 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.481261882 Jun 27 07:14:36 PM PDT 24 Jun 27 07:16:11 PM PDT 24 173528293 ps
T1124 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2970078928 Jun 27 07:14:53 PM PDT 24 Jun 27 07:16:30 PM PDT 24 747909401 ps
T300 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3762139138 Jun 27 07:15:02 PM PDT 24 Jun 27 07:16:32 PM PDT 24 55405173 ps
T1125 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.879353309 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:11 PM PDT 24 40387449 ps
T1126 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2608019871 Jun 27 07:13:46 PM PDT 24 Jun 27 07:15:41 PM PDT 24 686597174 ps
T1127 /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2199628296 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 88150883 ps
T1128 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1690469543 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:45 PM PDT 24 656566238 ps
T1129 /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1228215703 Jun 27 07:16:04 PM PDT 24 Jun 27 07:17:53 PM PDT 24 37300809 ps
T1130 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.492576264 Jun 27 07:14:25 PM PDT 24 Jun 27 07:16:05 PM PDT 24 124407485 ps
T1131 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.988436085 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 44226095 ps
T1132 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1330769902 Jun 27 07:15:54 PM PDT 24 Jun 27 07:17:35 PM PDT 24 140717337 ps
T1133 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2237897961 Jun 27 07:15:50 PM PDT 24 Jun 27 07:17:34 PM PDT 24 134419222 ps
T1134 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1287561553 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:04 PM PDT 24 135970767 ps
T1135 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3491699698 Jun 27 07:14:51 PM PDT 24 Jun 27 07:16:29 PM PDT 24 1226048430 ps
T312 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3281817235 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:12 PM PDT 24 38562528 ps
T1136 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3205653170 Jun 27 07:14:23 PM PDT 24 Jun 27 07:16:01 PM PDT 24 43497883 ps
T1137 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2449239715 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:46 PM PDT 24 1282430363 ps
T1138 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3326401658 Jun 27 07:14:45 PM PDT 24 Jun 27 07:16:26 PM PDT 24 87130614 ps
T1139 /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1074988118 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:51 PM PDT 24 130701574 ps
T1140 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2451727190 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:13 PM PDT 24 145018471 ps
T1141 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.495469524 Jun 27 07:15:28 PM PDT 24 Jun 27 07:17:06 PM PDT 24 218880239 ps
T1142 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.420250596 Jun 27 07:13:45 PM PDT 24 Jun 27 07:15:39 PM PDT 24 1944356797 ps
T1143 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2268131262 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:03 PM PDT 24 121552559 ps
T375 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.272861341 Jun 27 07:15:25 PM PDT 24 Jun 27 07:17:12 PM PDT 24 1447465391 ps
T1144 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1971473237 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:37 PM PDT 24 79705488 ps
T1145 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.65704083 Jun 27 07:14:25 PM PDT 24 Jun 27 07:16:02 PM PDT 24 170962589 ps
T1146 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2692005860 Jun 27 07:16:20 PM PDT 24 Jun 27 07:18:13 PM PDT 24 139949234 ps
T1147 /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1333230859 Jun 27 07:15:54 PM PDT 24 Jun 27 07:17:35 PM PDT 24 72889207 ps
T1148 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3329821554 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:44 PM PDT 24 76848376 ps
T302 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.112377474 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:00 PM PDT 24 50121245 ps
T1149 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3093606938 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:44 PM PDT 24 131047529 ps
T1150 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.703839608 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:54 PM PDT 24 41451450 ps
T1151 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2782444083 Jun 27 07:16:17 PM PDT 24 Jun 27 07:18:11 PM PDT 24 151316090 ps
T379 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.299924361 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:21 PM PDT 24 718720904 ps
T1152 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3099147475 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:57 PM PDT 24 670768654 ps
T1153 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.364854612 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:54 PM PDT 24 75661410 ps
T1154 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3197492220 Jun 27 07:15:03 PM PDT 24 Jun 27 07:16:33 PM PDT 24 51285629 ps
T1155 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1239036617 Jun 27 07:15:23 PM PDT 24 Jun 27 07:16:58 PM PDT 24 178930044 ps
T1156 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3618643749 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:39 PM PDT 24 153122127 ps
T1157 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1559221035 Jun 27 07:13:45 PM PDT 24 Jun 27 07:15:35 PM PDT 24 90993301 ps
T1158 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2888818331 Jun 27 07:15:03 PM PDT 24 Jun 27 07:16:55 PM PDT 24 4712323091 ps
T1159 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.4033913656 Jun 27 07:16:03 PM PDT 24 Jun 27 07:17:53 PM PDT 24 39506130 ps
T1160 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2651074110 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:37 PM PDT 24 45163904 ps
T1161 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2450780482 Jun 27 07:15:52 PM PDT 24 Jun 27 07:17:35 PM PDT 24 44267866 ps
T1162 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2132555523 Jun 27 07:15:54 PM PDT 24 Jun 27 07:17:35 PM PDT 24 533962046 ps
T1163 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2895403991 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:14 PM PDT 24 112266651 ps
T371 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3213447941 Jun 27 07:13:49 PM PDT 24 Jun 27 07:15:52 PM PDT 24 2557432699 ps
T1164 /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2192329080 Jun 27 07:16:18 PM PDT 24 Jun 27 07:18:12 PM PDT 24 43096668 ps
T1165 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3608006482 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:45 PM PDT 24 628806868 ps
T1166 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.800259895 Jun 27 07:16:05 PM PDT 24 Jun 27 07:17:53 PM PDT 24 513410727 ps
T1167 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4031025750 Jun 27 07:14:41 PM PDT 24 Jun 27 07:16:19 PM PDT 24 162402232 ps
T1168 /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3193975921 Jun 27 07:15:04 PM PDT 24 Jun 27 07:16:39 PM PDT 24 57780409 ps
T1169 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2716133127 Jun 27 07:15:40 PM PDT 24 Jun 27 07:17:25 PM PDT 24 99854797 ps
T1170 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3415128511 Jun 27 07:13:59 PM PDT 24 Jun 27 07:15:51 PM PDT 24 204543965 ps
T1171 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1890902728 Jun 27 07:14:54 PM PDT 24 Jun 27 07:16:42 PM PDT 24 1267382922 ps
T1172 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2009956913 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:01 PM PDT 24 130355284 ps
T1173 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3210594788 Jun 27 07:14:40 PM PDT 24 Jun 27 07:16:19 PM PDT 24 817695829 ps
T1174 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3996097999 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 70175723 ps
T1175 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.755483117 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:44 PM PDT 24 55923568 ps
T378 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2285427231 Jun 27 07:14:35 PM PDT 24 Jun 27 07:16:19 PM PDT 24 616533192 ps
T1176 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1225920885 Jun 27 07:14:50 PM PDT 24 Jun 27 07:16:24 PM PDT 24 60606441 ps
T1177 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3221177298 Jun 27 07:13:45 PM PDT 24 Jun 27 07:15:35 PM PDT 24 76455161 ps
T1178 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.435328487 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:00 PM PDT 24 560196322 ps
T1179 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3378255280 Jun 27 07:13:45 PM PDT 24 Jun 27 07:15:35 PM PDT 24 37438571 ps
T1180 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.4233387098 Jun 27 07:15:54 PM PDT 24 Jun 27 07:17:36 PM PDT 24 279144154 ps
T1181 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2840268164 Jun 27 07:15:39 PM PDT 24 Jun 27 07:17:17 PM PDT 24 190950995 ps
T1182 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2407320006 Jun 27 07:14:49 PM PDT 24 Jun 27 07:16:41 PM PDT 24 1287464003 ps
T1183 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.4194211016 Jun 27 07:14:30 PM PDT 24 Jun 27 07:16:06 PM PDT 24 74134721 ps
T1184 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.792717609 Jun 27 07:13:49 PM PDT 24 Jun 27 07:15:41 PM PDT 24 110943992 ps
T313 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.407806201 Jun 27 07:14:11 PM PDT 24 Jun 27 07:16:16 PM PDT 24 6802278488 ps
T256 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.214576387 Jun 27 07:14:10 PM PDT 24 Jun 27 07:16:17 PM PDT 24 1912611635 ps
T1185 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2742671764 Jun 27 07:15:49 PM PDT 24 Jun 27 07:17:34 PM PDT 24 76688632 ps
T1186 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2622865601 Jun 27 07:15:24 PM PDT 24 Jun 27 07:16:55 PM PDT 24 145629162 ps
T1187 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.589487528 Jun 27 07:15:50 PM PDT 24 Jun 27 07:17:34 PM PDT 24 150627531 ps
T1188 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2601440484 Jun 27 07:15:40 PM PDT 24 Jun 27 07:17:13 PM PDT 24 76484433 ps
T301 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.303179422 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:46 PM PDT 24 196977428 ps
T1189 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3931699259 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:46 PM PDT 24 1089802473 ps
T1190 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.555720871 Jun 27 07:13:48 PM PDT 24 Jun 27 07:16:05 PM PDT 24 1607876678 ps
T1191 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4146849625 Jun 27 07:13:58 PM PDT 24 Jun 27 07:15:48 PM PDT 24 118537439 ps
T314 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1705911051 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:45 PM PDT 24 193114787 ps
T1192 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2705417060 Jun 27 07:15:02 PM PDT 24 Jun 27 07:16:32 PM PDT 24 97080565 ps
T315 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3963895339 Jun 27 07:13:59 PM PDT 24 Jun 27 07:15:50 PM PDT 24 1412390127 ps
T1193 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2504633074 Jun 27 07:14:36 PM PDT 24 Jun 27 07:16:14 PM PDT 24 119301889 ps
T316 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2078545260 Jun 27 07:13:57 PM PDT 24 Jun 27 07:15:47 PM PDT 24 90935641 ps
T1194 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1269676575 Jun 27 07:14:24 PM PDT 24 Jun 27 07:16:02 PM PDT 24 42756621 ps

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.2852556615
Short name T4
Test name
Test status
Simulation time 859233600 ps
CPU time 8.89 seconds
Started Jun 27 07:22:24 PM PDT 24
Finished Jun 27 07:25:11 PM PDT 24
Peak memory 242320 kb
Host smart-9e76e0eb-e436-40b8-906f-3a2356ec16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852556615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.2852556615
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.3648092826
Short name T64
Test name
Test status
Simulation time 41899360507 ps
CPU time 338.26 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:25:54 PM PDT 24
Peak memory 257028 kb
Host smart-b153a10f-f720-4bd5-8723-e6b3dff41afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648092826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
3648092826
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1708932240
Short name T6
Test name
Test status
Simulation time 1009337398727 ps
CPU time 2594.54 seconds
Started Jun 27 07:23:19 PM PDT 24
Finished Jun 27 08:09:28 PM PDT 24
Peak memory 361524 kb
Host smart-57b01f76-bc20-4f4c-9f43-f97abdbc8c89
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708932240 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1708932240
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.2053510449
Short name T96
Test name
Test status
Simulation time 244910144558 ps
CPU time 447.83 seconds
Started Jun 27 07:23:31 PM PDT 24
Finished Jun 27 07:34:44 PM PDT 24
Peak memory 322532 kb
Host smart-98e9bc88-a625-497a-ba46-a610e93bd4c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053510449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.2053510449
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.3885629895
Short name T28
Test name
Test status
Simulation time 729477401 ps
CPU time 21.16 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:24:19 PM PDT 24
Peak memory 248816 kb
Host smart-79ba6376-7e96-44b5-bcdd-654c8d4f591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885629895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.3885629895
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3030724978
Short name T21
Test name
Test status
Simulation time 169713133340 ps
CPU time 295.49 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:23:35 PM PDT 24
Peak memory 274352 kb
Host smart-900fa1fa-602d-4be3-9cf0-ece84db676b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030724978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3030724978
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.1348656946
Short name T138
Test name
Test status
Simulation time 608102838 ps
CPU time 4.48 seconds
Started Jun 27 07:27:11 PM PDT 24
Finished Jun 27 07:29:26 PM PDT 24
Peak memory 242348 kb
Host smart-4ea91c43-646b-4ebf-baa5-d5c881c66545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348656946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1348656946
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.3484532690
Short name T207
Test name
Test status
Simulation time 30784780200 ps
CPU time 207.68 seconds
Started Jun 27 07:21:22 PM PDT 24
Finished Jun 27 07:27:29 PM PDT 24
Peak memory 262552 kb
Host smart-467a82fe-572d-4195-aef7-5d770a8b8619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484532690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.3484532690
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.2479694787
Short name T275
Test name
Test status
Simulation time 99401520996 ps
CPU time 873.98 seconds
Started Jun 27 07:23:28 PM PDT 24
Finished Jun 27 07:40:47 PM PDT 24
Peak memory 265336 kb
Host smart-37db62ca-5991-4cf7-8483-856e3e446d3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479694787 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.2479694787
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.198573416
Short name T373
Test name
Test status
Simulation time 4714299894 ps
CPU time 20.63 seconds
Started Jun 27 07:15:05 PM PDT 24
Finished Jun 27 07:16:57 PM PDT 24
Peak memory 239408 kb
Host smart-6f9f49a9-4597-4620-a350-68e8b9c81eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198573416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.198573416
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.625090891
Short name T141
Test name
Test status
Simulation time 8029774080 ps
CPU time 40.37 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:56 PM PDT 24
Peak memory 250732 kb
Host smart-ec2dd09d-71cd-4119-b8d7-9d4af93bdbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625090891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.625090891
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2055666577
Short name T57
Test name
Test status
Simulation time 522628732 ps
CPU time 3.86 seconds
Started Jun 27 07:27:03 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242084 kb
Host smart-a0c113f5-368f-4721-811e-b1e9d4a2e84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055666577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2055666577
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1681195317
Short name T16
Test name
Test status
Simulation time 95002207460 ps
CPU time 492.2 seconds
Started Jun 27 07:23:41 PM PDT 24
Finished Jun 27 07:34:12 PM PDT 24
Peak memory 266776 kb
Host smart-400522e4-d569-4572-887c-2f40231ebcf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681195317 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1681195317
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.3023479476
Short name T26
Test name
Test status
Simulation time 832695207 ps
CPU time 5.68 seconds
Started Jun 27 07:17:05 PM PDT 24
Finished Jun 27 07:19:32 PM PDT 24
Peak memory 242176 kb
Host smart-97dc75a3-8bf9-4afd-8303-fec48f8a114b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023479476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3023479476
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.775395714
Short name T3
Test name
Test status
Simulation time 1966335052 ps
CPU time 4.71 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:09 PM PDT 24
Peak memory 241888 kb
Host smart-16b46e23-3de9-4983-a642-b439649d3399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775395714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.775395714
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.312252702
Short name T241
Test name
Test status
Simulation time 9868245967 ps
CPU time 170.7 seconds
Started Jun 27 07:16:46 PM PDT 24
Finished Jun 27 07:22:00 PM PDT 24
Peak memory 250300 kb
Host smart-db135aa2-013b-4d47-a748-af1b165abb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312252702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.312252702
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.1020028826
Short name T42
Test name
Test status
Simulation time 1843558630 ps
CPU time 4.55 seconds
Started Jun 27 07:24:53 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 241980 kb
Host smart-34daa621-2657-4bac-81fb-ee3d538ef8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020028826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1020028826
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.754887297
Short name T60
Test name
Test status
Simulation time 840886878 ps
CPU time 23.88 seconds
Started Jun 27 07:26:15 PM PDT 24
Finished Jun 27 07:28:55 PM PDT 24
Peak memory 243072 kb
Host smart-dbdfd1ea-d664-4eb3-bbf9-84f09ceed5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754887297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.754887297
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3040858652
Short name T18
Test name
Test status
Simulation time 537326617170 ps
CPU time 1675.62 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:54:34 PM PDT 24
Peak memory 322504 kb
Host smart-366f9622-1081-4a44-b27a-7ffe9a7d787b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040858652 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3040858652
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1674467570
Short name T46
Test name
Test status
Simulation time 3054469862 ps
CPU time 16.77 seconds
Started Jun 27 07:24:25 PM PDT 24
Finished Jun 27 07:27:20 PM PDT 24
Peak memory 242156 kb
Host smart-c984658c-8774-4084-9026-e9921d839d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674467570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1674467570
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.1569524754
Short name T968
Test name
Test status
Simulation time 203507376 ps
CPU time 4.96 seconds
Started Jun 27 07:25:39 PM PDT 24
Finished Jun 27 07:28:37 PM PDT 24
Peak memory 242192 kb
Host smart-10819360-08cb-4ffc-8a32-40561fe16042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569524754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.1569524754
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3601532459
Short name T66
Test name
Test status
Simulation time 128488476 ps
CPU time 3.55 seconds
Started Jun 27 07:26:37 PM PDT 24
Finished Jun 27 07:28:47 PM PDT 24
Peak memory 241896 kb
Host smart-931180f4-bf6c-4ebf-a722-0c2c6f55b2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601532459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3601532459
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.804822909
Short name T71
Test name
Test status
Simulation time 121394471 ps
CPU time 3.88 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:25:31 PM PDT 24
Peak memory 242012 kb
Host smart-6eef7c25-67bc-48ab-b8b2-e8c0485759f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804822909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.804822909
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1283820462
Short name T68
Test name
Test status
Simulation time 198796204640 ps
CPU time 1695.03 seconds
Started Jun 27 07:30:33 PM PDT 24
Finished Jun 27 08:00:50 PM PDT 24
Peak memory 337636 kb
Host smart-d66dabe9-55cd-42cc-b379-eaefbda72caf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283820462 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1283820462
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.4288037237
Short name T50
Test name
Test status
Simulation time 267417042 ps
CPU time 4.18 seconds
Started Jun 27 07:26:26 PM PDT 24
Finished Jun 27 07:28:35 PM PDT 24
Peak memory 242380 kb
Host smart-a7439a20-676c-4836-bdf5-1bbb4d1a919f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288037237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.4288037237
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.374754251
Short name T83
Test name
Test status
Simulation time 142052160 ps
CPU time 3.83 seconds
Started Jun 27 07:25:18 PM PDT 24
Finished Jun 27 07:27:41 PM PDT 24
Peak memory 241804 kb
Host smart-19e637ed-14be-4752-b891-51be01a1e135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374754251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.374754251
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2450637163
Short name T74
Test name
Test status
Simulation time 2608784364 ps
CPU time 5.02 seconds
Started Jun 27 07:25:43 PM PDT 24
Finished Jun 27 07:28:40 PM PDT 24
Peak memory 242100 kb
Host smart-6e8cefb0-53e6-4bda-ad16-c4a21bdb4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450637163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2450637163
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.4215409607
Short name T54
Test name
Test status
Simulation time 311777268 ps
CPU time 3.98 seconds
Started Jun 27 07:27:39 PM PDT 24
Finished Jun 27 07:29:56 PM PDT 24
Peak memory 242020 kb
Host smart-261695de-7520-4262-ba7f-1609e9ec2d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215409607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.4215409607
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.80181301
Short name T35
Test name
Test status
Simulation time 147597715 ps
CPU time 3.8 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:41 PM PDT 24
Peak memory 242372 kb
Host smart-17991601-11c0-4237-a387-7f0be812f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80181301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.80181301
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.463038211
Short name T219
Test name
Test status
Simulation time 9736766430 ps
CPU time 129 seconds
Started Jun 27 07:27:16 PM PDT 24
Finished Jun 27 07:31:59 PM PDT 24
Peak memory 248788 kb
Host smart-54fc27fd-0ff6-4a0b-ae86-3254699b6c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463038211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
463038211
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.807111666
Short name T13
Test name
Test status
Simulation time 1000685074881 ps
CPU time 1497.43 seconds
Started Jun 27 07:16:55 PM PDT 24
Finished Jun 27 07:44:15 PM PDT 24
Peak memory 275312 kb
Host smart-fa262d2a-a72e-433d-ad42-e7ddceeaa0fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807111666 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.807111666
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.788376095
Short name T184
Test name
Test status
Simulation time 1146734626 ps
CPU time 16.96 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:20:28 PM PDT 24
Peak memory 242196 kb
Host smart-07ef1729-7fb5-419a-8e4b-940ef0216af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788376095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.788376095
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.696753184
Short name T409
Test name
Test status
Simulation time 88874151 ps
CPU time 1.53 seconds
Started Jun 27 07:16:31 PM PDT 24
Finished Jun 27 07:18:40 PM PDT 24
Peak memory 240400 kb
Host smart-3339e970-eaef-4d95-a646-189a583c215e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696753184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.696753184
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.356523854
Short name T195
Test name
Test status
Simulation time 390015548 ps
CPU time 11.86 seconds
Started Jun 27 07:25:54 PM PDT 24
Finished Jun 27 07:28:58 PM PDT 24
Peak memory 241880 kb
Host smart-e7e4c01e-1a8e-421e-b458-a28f37847e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356523854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.356523854
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.3854610534
Short name T176
Test name
Test status
Simulation time 28541519431 ps
CPU time 175.63 seconds
Started Jun 27 07:23:38 PM PDT 24
Finished Jun 27 07:29:34 PM PDT 24
Peak memory 256984 kb
Host smart-289fd244-e94b-4522-9ae6-d7561e6326f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854610534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.3854610534
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.810934868
Short name T338
Test name
Test status
Simulation time 291438372072 ps
CPU time 728.04 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:30:48 PM PDT 24
Peak memory 313272 kb
Host smart-93e5be55-02bb-493c-9a82-dd6e150b3665
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810934868 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.810934868
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.1726122766
Short name T37
Test name
Test status
Simulation time 453611950 ps
CPU time 4.01 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:20:53 PM PDT 24
Peak memory 242120 kb
Host smart-98db9066-9595-4b80-805d-f6dbf0a16d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726122766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1726122766
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.1364838897
Short name T1
Test name
Test status
Simulation time 4193485416 ps
CPU time 10.07 seconds
Started Jun 27 07:20:21 PM PDT 24
Finished Jun 27 07:22:57 PM PDT 24
Peak memory 242696 kb
Host smart-4ebffef4-6add-49c2-ac7b-7e62898c56dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1364838897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1364838897
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.581087372
Short name T232
Test name
Test status
Simulation time 13327968343 ps
CPU time 105.36 seconds
Started Jun 27 07:18:40 PM PDT 24
Finished Jun 27 07:22:52 PM PDT 24
Peak memory 248672 kb
Host smart-6ec47706-ecd3-4f70-90c8-9544aee8e575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581087372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.
581087372
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.13578859
Short name T210
Test name
Test status
Simulation time 51434824608 ps
CPU time 194.28 seconds
Started Jun 27 07:20:26 PM PDT 24
Finished Jun 27 07:26:05 PM PDT 24
Peak memory 256968 kb
Host smart-57971224-89d4-4268-a07b-b5545b9d6445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13578859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.13578859
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3140739801
Short name T254
Test name
Test status
Simulation time 55158255 ps
CPU time 1.6 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 241552 kb
Host smart-a56922ad-c448-49ec-b1ca-a788536d83a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140739801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3140739801
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.2870858035
Short name T198
Test name
Test status
Simulation time 250807852 ps
CPU time 3.04 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:43 PM PDT 24
Peak memory 242168 kb
Host smart-6c0077a1-525e-40af-a1e8-af37ca2bf0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870858035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2870858035
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.4181503744
Short name T159
Test name
Test status
Simulation time 154112485 ps
CPU time 3.98 seconds
Started Jun 27 07:24:42 PM PDT 24
Finished Jun 27 07:26:52 PM PDT 24
Peak memory 242000 kb
Host smart-993ef37f-1e0d-4a39-b476-2aa7860097f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181503744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.4181503744
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.3388142722
Short name T10
Test name
Test status
Simulation time 4260241386 ps
CPU time 13.55 seconds
Started Jun 27 07:17:59 PM PDT 24
Finished Jun 27 07:20:57 PM PDT 24
Peak memory 248848 kb
Host smart-989a563b-96da-44b0-8aed-1cbc2584745e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388142722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.3388142722
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.3020014931
Short name T380
Test name
Test status
Simulation time 523859793 ps
CPU time 8.5 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:48 PM PDT 24
Peak memory 242280 kb
Host smart-1af85153-4f3c-4dd4-a743-32c3d052b30f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3020014931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.3020014931
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.2298338081
Short name T218
Test name
Test status
Simulation time 129544158 ps
CPU time 4.84 seconds
Started Jun 27 07:22:49 PM PDT 24
Finished Jun 27 07:26:43 PM PDT 24
Peak memory 241868 kb
Host smart-b8d1b029-7b8e-4096-8e85-03d74ea39ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298338081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2298338081
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.3176295824
Short name T234
Test name
Test status
Simulation time 6809480031 ps
CPU time 62.98 seconds
Started Jun 27 07:21:42 PM PDT 24
Finished Jun 27 07:25:36 PM PDT 24
Peak memory 248792 kb
Host smart-dc8fc07c-df26-486b-9b2d-35253addbe42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176295824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.3176295824
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.1532428713
Short name T118
Test name
Test status
Simulation time 1928910694 ps
CPU time 6.29 seconds
Started Jun 27 07:26:47 PM PDT 24
Finished Jun 27 07:29:00 PM PDT 24
Peak memory 242060 kb
Host smart-1deaa45b-164b-402c-aa3c-9c6395139bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532428713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.1532428713
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.850395258
Short name T251
Test name
Test status
Simulation time 1220360721 ps
CPU time 19.18 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:17:11 PM PDT 24
Peak memory 244272 kb
Host smart-07b647d8-26ac-432d-af93-52fac8451082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850395258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_in
tg_err.850395258
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.2679994554
Short name T88
Test name
Test status
Simulation time 1607987528 ps
CPU time 20.08 seconds
Started Jun 27 07:24:31 PM PDT 24
Finished Jun 27 07:27:14 PM PDT 24
Peak memory 241856 kb
Host smart-19730b62-d89e-446f-aaa5-31f3cc2b58a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679994554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.2679994554
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.4120234792
Short name T132
Test name
Test status
Simulation time 170493414 ps
CPU time 4.85 seconds
Started Jun 27 07:24:54 PM PDT 24
Finished Jun 27 07:27:13 PM PDT 24
Peak memory 242056 kb
Host smart-6fa43280-9463-4dff-bdb5-bfa6840f0db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120234792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.4120234792
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1197899033
Short name T72
Test name
Test status
Simulation time 349211166 ps
CPU time 7.53 seconds
Started Jun 27 07:18:23 PM PDT 24
Finished Jun 27 07:22:14 PM PDT 24
Peak memory 242076 kb
Host smart-82f602f5-eac3-4222-962f-cdb91fda5eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197899033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1197899033
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3156676417
Short name T69
Test name
Test status
Simulation time 409094422 ps
CPU time 9.32 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:44 PM PDT 24
Peak memory 241920 kb
Host smart-dfcb173e-cec8-4be4-9bd8-cfb13434118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156676417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3156676417
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2175118912
Short name T82
Test name
Test status
Simulation time 151673897 ps
CPU time 3.62 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242396 kb
Host smart-8faba818-1e81-43b8-9cbb-b91a894f7088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175118912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2175118912
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3058555317
Short name T179
Test name
Test status
Simulation time 4163876222 ps
CPU time 81.52 seconds
Started Jun 27 07:21:51 PM PDT 24
Finished Jun 27 07:25:23 PM PDT 24
Peak memory 248300 kb
Host smart-4612ebcc-a9a1-4b5c-bd5c-aea52939bd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058555317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3058555317
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.68649897
Short name T516
Test name
Test status
Simulation time 51061679656 ps
CPU time 686.87 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:30:35 PM PDT 24
Peak memory 260640 kb
Host smart-73bc0ede-c8d7-4035-87ff-40dd215eea20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68649897 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.68649897
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.214576387
Short name T256
Test name
Test status
Simulation time 1912611635 ps
CPU time 18.41 seconds
Started Jun 27 07:14:10 PM PDT 24
Finished Jun 27 07:16:17 PM PDT 24
Peak memory 244428 kb
Host smart-c9a927a8-6c48-4d45-8b18-632b179883ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214576387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_int
g_err.214576387
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.968624585
Short name T135
Test name
Test status
Simulation time 207668647119 ps
CPU time 1577.81 seconds
Started Jun 27 07:23:24 PM PDT 24
Finished Jun 27 07:52:19 PM PDT 24
Peak memory 265276 kb
Host smart-dfedc47b-bdcb-490e-8945-e41ad94eae58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968624585 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.968624585
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.2141379982
Short name T31
Test name
Test status
Simulation time 21779949194 ps
CPU time 30.13 seconds
Started Jun 27 07:16:49 PM PDT 24
Finished Jun 27 07:19:53 PM PDT 24
Peak memory 248852 kb
Host smart-6d029f01-4125-4bc7-b673-349e0d69662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141379982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2141379982
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.3242902759
Short name T249
Test name
Test status
Simulation time 1745885079 ps
CPU time 20.21 seconds
Started Jun 27 07:15:36 PM PDT 24
Finished Jun 27 07:17:31 PM PDT 24
Peak memory 244524 kb
Host smart-ebff0621-7ea9-4195-84ea-b323545012a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242902759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.3242902759
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.3910981125
Short name T348
Test name
Test status
Simulation time 1140169475 ps
CPU time 10.19 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:20:54 PM PDT 24
Peak memory 242004 kb
Host smart-0a14f9c2-94ab-4c1e-a699-e07d9847c15b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3910981125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.3910981125
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2884245072
Short name T84
Test name
Test status
Simulation time 319362635 ps
CPU time 4.25 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:26:44 PM PDT 24
Peak memory 242008 kb
Host smart-68e3f5ea-39c0-4d1b-b27c-4784bc79dc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884245072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2884245072
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.189840509
Short name T77
Test name
Test status
Simulation time 1989659387 ps
CPU time 18.5 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:34 PM PDT 24
Peak memory 242264 kb
Host smart-61ef445f-ccd7-4737-aff2-5bd0cacdd8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189840509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.189840509
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3454330416
Short name T75
Test name
Test status
Simulation time 1861905457 ps
CPU time 17.62 seconds
Started Jun 27 07:20:11 PM PDT 24
Finished Jun 27 07:23:07 PM PDT 24
Peak memory 248828 kb
Host smart-2e01e7e8-aee2-4f28-8dd5-4eedc531a760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454330416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3454330416
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.2555426257
Short name T206
Test name
Test status
Simulation time 5978448983 ps
CPU time 90.42 seconds
Started Jun 27 07:18:55 PM PDT 24
Finished Jun 27 07:23:11 PM PDT 24
Peak memory 245376 kb
Host smart-c6485335-fad4-413b-b21c-7d2a9800d89c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555426257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.2555426257
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.315806664
Short name T238
Test name
Test status
Simulation time 884651073 ps
CPU time 13.93 seconds
Started Jun 27 07:30:24 PM PDT 24
Finished Jun 27 07:32:40 PM PDT 24
Peak memory 241888 kb
Host smart-07edb680-5821-4a4d-86a1-3bb3f45964bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315806664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.315806664
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.914376050
Short name T81
Test name
Test status
Simulation time 1741907729 ps
CPU time 4.14 seconds
Started Jun 27 07:19:24 PM PDT 24
Finished Jun 27 07:21:55 PM PDT 24
Peak memory 241900 kb
Host smart-084ab4aa-2462-4460-bb12-024bd295ce3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914376050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.914376050
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.62021134
Short name T45
Test name
Test status
Simulation time 1009789133 ps
CPU time 25.17 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:35 PM PDT 24
Peak memory 242576 kb
Host smart-38e0decb-a7f2-47c2-bf36-68535b8443e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62021134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.62021134
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2622188543
Short name T620
Test name
Test status
Simulation time 146692999 ps
CPU time 3.81 seconds
Started Jun 27 07:24:53 PM PDT 24
Finished Jun 27 07:27:10 PM PDT 24
Peak memory 242052 kb
Host smart-2e0c3ab5-3284-4770-8eb1-d613caf9037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622188543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2622188543
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3213447941
Short name T371
Test name
Test status
Simulation time 2557432699 ps
CPU time 12.6 seconds
Started Jun 27 07:13:49 PM PDT 24
Finished Jun 27 07:15:52 PM PDT 24
Peak memory 244172 kb
Host smart-9e358228-e3e6-4bca-aa1e-21de5be2d795
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213447941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3213447941
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.502950597
Short name T377
Test name
Test status
Simulation time 1066202263 ps
CPU time 12.23 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:13 PM PDT 24
Peak memory 244104 kb
Host smart-1c87ede0-65ec-43a8-a39d-715ac3320339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502950597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_int
g_err.502950597
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.791924479
Short name T361
Test name
Test status
Simulation time 4854766711 ps
CPU time 17.39 seconds
Started Jun 27 07:18:00 PM PDT 24
Finished Jun 27 07:21:01 PM PDT 24
Peak memory 242156 kb
Host smart-7519f58f-dd7d-42d4-a86a-4be1d06bef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791924479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.791924479
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.3105514361
Short name T847
Test name
Test status
Simulation time 2155304119 ps
CPU time 32.16 seconds
Started Jun 27 07:17:56 PM PDT 24
Finished Jun 27 07:22:00 PM PDT 24
Peak memory 247040 kb
Host smart-f75ab211-33ad-40d0-95f8-de2b86c5a029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105514361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3105514361
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3536824079
Short name T255
Test name
Test status
Simulation time 5014588602 ps
CPU time 19.69 seconds
Started Jun 27 07:15:25 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 244816 kb
Host smart-c87b8b1e-f42f-45ec-b9be-03f556cedf40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536824079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3536824079
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.119020616
Short name T78
Test name
Test status
Simulation time 2136333051 ps
CPU time 4.36 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 241932 kb
Host smart-e3fb3895-c2f0-4136-83aa-a5503460f347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119020616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.119020616
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.3835056180
Short name T129
Test name
Test status
Simulation time 273280748 ps
CPU time 3.31 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 07:26:16 PM PDT 24
Peak memory 242336 kb
Host smart-001976df-8482-49b3-9b80-b28411aaa0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835056180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3835056180
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.2435545349
Short name T490
Test name
Test status
Simulation time 992338850 ps
CPU time 11.78 seconds
Started Jun 27 07:17:31 PM PDT 24
Finished Jun 27 07:20:28 PM PDT 24
Peak memory 242116 kb
Host smart-2d8670cd-25e8-4ec7-8244-73eb092abb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435545349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2435545349
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.2717326543
Short name T123
Test name
Test status
Simulation time 131528748 ps
CPU time 4.02 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:26:43 PM PDT 24
Peak memory 241844 kb
Host smart-a07eecfb-b427-4dfb-b396-a2ab3010826b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717326543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.2717326543
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.471714803
Short name T364
Test name
Test status
Simulation time 89293458683 ps
CPU time 223.38 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:23:55 PM PDT 24
Peak memory 273420 kb
Host smart-1d2d351f-6b68-46db-bf1c-27e337e5b33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471714803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.
471714803
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2376009451
Short name T1118
Test name
Test status
Simulation time 213489967 ps
CPU time 3.52 seconds
Started Jun 27 07:13:47 PM PDT 24
Finished Jun 27 07:15:38 PM PDT 24
Peak memory 239148 kb
Host smart-ebab3b6a-d47b-4606-9c19-7fb48724b7f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376009451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.2376009451
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2608019871
Short name T1126
Test name
Test status
Simulation time 686597174 ps
CPU time 7.89 seconds
Started Jun 27 07:13:46 PM PDT 24
Finished Jun 27 07:15:41 PM PDT 24
Peak memory 239200 kb
Host smart-e10b61df-cf7a-4d69-89d7-28c0d9b4a4c6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608019871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2608019871
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.555720871
Short name T1190
Test name
Test status
Simulation time 1607876678 ps
CPU time 4.75 seconds
Started Jun 27 07:13:48 PM PDT 24
Finished Jun 27 07:16:05 PM PDT 24
Peak memory 240880 kb
Host smart-5780a6c0-9150-4d4f-9d42-eb57182a76d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555720871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_re
set.555720871
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.792717609
Short name T1184
Test name
Test status
Simulation time 110943992 ps
CPU time 2.69 seconds
Started Jun 27 07:13:49 PM PDT 24
Finished Jun 27 07:15:41 PM PDT 24
Peak memory 247068 kb
Host smart-f280b804-9911-49ec-b59d-9672ad5befe3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792717609 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.792717609
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1559221035
Short name T1157
Test name
Test status
Simulation time 90993301 ps
CPU time 1.7 seconds
Started Jun 27 07:13:45 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 240852 kb
Host smart-c635c990-5c7b-4a61-b15b-4ddc696e7e42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559221035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1559221035
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1446820174
Short name T1080
Test name
Test status
Simulation time 607039010 ps
CPU time 1.76 seconds
Started Jun 27 07:13:46 PM PDT 24
Finished Jun 27 07:15:36 PM PDT 24
Peak memory 230312 kb
Host smart-9cbded38-1773-4b12-b1e2-60a7a0dd49a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446820174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1446820174
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.383670601
Short name T1077
Test name
Test status
Simulation time 41003811 ps
CPU time 1.35 seconds
Started Jun 27 07:13:47 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 229824 kb
Host smart-19b311c4-ab47-46a9-b6dc-a5ce8d62da01
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383670601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.383670601
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3378255280
Short name T1179
Test name
Test status
Simulation time 37438571 ps
CPU time 1.32 seconds
Started Jun 27 07:13:45 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 230120 kb
Host smart-bc0b6341-0c40-456d-abff-da7caa1aad41
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378255280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.3378255280
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4094039861
Short name T253
Test name
Test status
Simulation time 556695832 ps
CPU time 4.26 seconds
Started Jun 27 07:13:44 PM PDT 24
Finished Jun 27 07:15:37 PM PDT 24
Peak memory 239280 kb
Host smart-0a5b1502-0165-4555-9262-0d412167b41e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094039861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.4094039861
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.420250596
Short name T1142
Test name
Test status
Simulation time 1944356797 ps
CPU time 6.23 seconds
Started Jun 27 07:13:45 PM PDT 24
Finished Jun 27 07:15:39 PM PDT 24
Peak memory 245984 kb
Host smart-42ccbb94-9d21-4052-838e-e85b80398aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420250596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.420250596
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3688955139
Short name T372
Test name
Test status
Simulation time 2840884210 ps
CPU time 10.55 seconds
Started Jun 27 07:13:49 PM PDT 24
Finished Jun 27 07:15:50 PM PDT 24
Peak memory 244284 kb
Host smart-3b26328a-7570-46e9-9b35-282aa7c32799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688955139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3688955139
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.303179422
Short name T301
Test name
Test status
Simulation time 196977428 ps
CPU time 3.57 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:46 PM PDT 24
Peak memory 239252 kb
Host smart-788e1313-2833-408d-b7c0-96169c9d217d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303179422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.303179422
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3919684266
Short name T1114
Test name
Test status
Simulation time 741420053 ps
CPU time 5.26 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:48 PM PDT 24
Peak memory 239148 kb
Host smart-6533cf2f-33f3-49a4-899e-1914fe4bcc70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919684266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.3919684266
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.1705911051
Short name T314
Test name
Test status
Simulation time 193114787 ps
CPU time 2.53 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:45 PM PDT 24
Peak memory 241188 kb
Host smart-33d8899d-7118-4a19-bfa8-3d9f94c9cb34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705911051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.1705911051
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.3931699259
Short name T1189
Test name
Test status
Simulation time 1089802473 ps
CPU time 2.77 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:46 PM PDT 24
Peak memory 246424 kb
Host smart-e898035f-4ab5-47a6-bf5b-aed49bfa4785
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931699259 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.3931699259
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2105178902
Short name T299
Test name
Test status
Simulation time 129537969 ps
CPU time 1.56 seconds
Started Jun 27 07:14:00 PM PDT 24
Finished Jun 27 07:15:50 PM PDT 24
Peak memory 240872 kb
Host smart-a9763a5c-d47b-408c-ba97-6e3316072fee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105178902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2105178902
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3221177298
Short name T1177
Test name
Test status
Simulation time 76455161 ps
CPU time 1.36 seconds
Started Jun 27 07:13:45 PM PDT 24
Finished Jun 27 07:15:35 PM PDT 24
Peak memory 230316 kb
Host smart-bee77093-9054-4bd8-bc1a-2cf0d162af6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221177298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3221177298
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.4146849625
Short name T1191
Test name
Test status
Simulation time 118537439 ps
CPU time 1.34 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:48 PM PDT 24
Peak memory 230132 kb
Host smart-5377da86-8981-4838-9c40-dbdb53baf25d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146849625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.4146849625
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.755483117
Short name T1175
Test name
Test status
Simulation time 55923568 ps
CPU time 1.3 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 230096 kb
Host smart-cbe45406-87f1-4ba8-a167-f983837968da
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755483117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
755483117
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1074988118
Short name T1139
Test name
Test status
Simulation time 130701574 ps
CPU time 3.37 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:51 PM PDT 24
Peak memory 239148 kb
Host smart-b49cd220-de71-4b07-a282-18368969d4b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074988118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1074988118
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3631484339
Short name T1073
Test name
Test status
Simulation time 57518417 ps
CPU time 3.02 seconds
Started Jun 27 07:13:46 PM PDT 24
Finished Jun 27 07:15:37 PM PDT 24
Peak memory 246036 kb
Host smart-15b360ba-b188-4d31-8365-a229669b8d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631484339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3631484339
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1008493335
Short name T1072
Test name
Test status
Simulation time 129820763 ps
CPU time 2.22 seconds
Started Jun 27 07:15:03 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 247172 kb
Host smart-f738c59a-0d9e-4cea-a1ac-6d9b2e5deb89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008493335 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1008493335
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3762139138
Short name T300
Test name
Test status
Simulation time 55405173 ps
CPU time 1.51 seconds
Started Jun 27 07:15:02 PM PDT 24
Finished Jun 27 07:16:32 PM PDT 24
Peak memory 239200 kb
Host smart-a825a22c-94fb-43e3-9f20-ae8d77d6ff62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762139138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3762139138
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.2271849364
Short name T1109
Test name
Test status
Simulation time 86103718 ps
CPU time 1.37 seconds
Started Jun 27 07:14:52 PM PDT 24
Finished Jun 27 07:16:25 PM PDT 24
Peak memory 231012 kb
Host smart-6812b53a-f257-4dd8-bb84-0eb1f9f8fbe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271849364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.2271849364
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3197492220
Short name T1154
Test name
Test status
Simulation time 51285629 ps
CPU time 1.94 seconds
Started Jun 27 07:15:03 PM PDT 24
Finished Jun 27 07:16:33 PM PDT 24
Peak memory 242240 kb
Host smart-87497659-2a62-4c03-a35a-338d3b50ede3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197492220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.3197492220
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2970078928
Short name T1124
Test name
Test status
Simulation time 747909401 ps
CPU time 6.27 seconds
Started Jun 27 07:14:53 PM PDT 24
Finished Jun 27 07:16:30 PM PDT 24
Peak memory 246516 kb
Host smart-fe574669-24b8-4bae-96c7-bfe53c96eb51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970078928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2970078928
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.1890902728
Short name T1171
Test name
Test status
Simulation time 1267382922 ps
CPU time 14.5 seconds
Started Jun 27 07:14:54 PM PDT 24
Finished Jun 27 07:16:42 PM PDT 24
Peak memory 239232 kb
Host smart-2aafeef3-f6eb-4fba-8e5d-4021e02f2355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890902728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.1890902728
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.1461101711
Short name T1115
Test name
Test status
Simulation time 99882926 ps
CPU time 2.71 seconds
Started Jun 27 07:15:06 PM PDT 24
Finished Jun 27 07:16:38 PM PDT 24
Peak memory 247420 kb
Host smart-eb1ab256-fb14-4a04-acf1-8154fa99dc0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461101711 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.1461101711
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.2705417060
Short name T1192
Test name
Test status
Simulation time 97080565 ps
CPU time 1.55 seconds
Started Jun 27 07:15:02 PM PDT 24
Finished Jun 27 07:16:32 PM PDT 24
Peak memory 239236 kb
Host smart-f245a376-1269-49b6-8c16-fb7e92d85f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705417060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.2705417060
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1971473237
Short name T1144
Test name
Test status
Simulation time 79705488 ps
CPU time 1.45 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 230296 kb
Host smart-b7fd3fb9-67b3-49b7-aa73-0ab7ae576849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971473237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1971473237
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.781088729
Short name T326
Test name
Test status
Simulation time 285502515 ps
CPU time 2.45 seconds
Started Jun 27 07:15:02 PM PDT 24
Finished Jun 27 07:16:33 PM PDT 24
Peak memory 242296 kb
Host smart-fd168067-b469-41b4-aa17-87dbc7cdf32b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781088729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c
trl_same_csr_outstanding.781088729
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3618643749
Short name T1156
Test name
Test status
Simulation time 153122127 ps
CPU time 2.95 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 245952 kb
Host smart-83a42d79-9dff-4a76-848a-5e956f714eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618643749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3618643749
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.3608006482
Short name T1165
Test name
Test status
Simulation time 628806868 ps
CPU time 9.03 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:45 PM PDT 24
Peak memory 243924 kb
Host smart-5d81832f-0705-4ed4-ae63-ea8bde51309f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608006482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.3608006482
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.650592828
Short name T387
Test name
Test status
Simulation time 103358663 ps
CPU time 3.04 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 247340 kb
Host smart-5280047a-9d23-4ccb-8941-e37556b58776
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650592828 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.650592828
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.2651074110
Short name T1160
Test name
Test status
Simulation time 45163904 ps
CPU time 1.45 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 239104 kb
Host smart-5193d89d-42c9-463f-aeb5-1098c03022f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651074110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.2651074110
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.42078763
Short name T1067
Test name
Test status
Simulation time 56031375 ps
CPU time 1.4 seconds
Started Jun 27 07:15:06 PM PDT 24
Finished Jun 27 07:16:37 PM PDT 24
Peak memory 230340 kb
Host smart-24b044d0-60f3-4246-9a09-c17c17a7a90c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42078763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.42078763
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1121455778
Short name T1095
Test name
Test status
Simulation time 338760967 ps
CPU time 2.97 seconds
Started Jun 27 07:15:03 PM PDT 24
Finished Jun 27 07:16:38 PM PDT 24
Peak memory 239200 kb
Host smart-56147216-b1c4-44b5-898a-5aa186257934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121455778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1121455778
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3193975921
Short name T1168
Test name
Test status
Simulation time 57780409 ps
CPU time 3.25 seconds
Started Jun 27 07:15:04 PM PDT 24
Finished Jun 27 07:16:39 PM PDT 24
Peak memory 239380 kb
Host smart-26b9c5ce-d6ed-408f-b478-fd7fc6f103dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193975921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3193975921
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2888818331
Short name T1158
Test name
Test status
Simulation time 4712323091 ps
CPU time 19.33 seconds
Started Jun 27 07:15:03 PM PDT 24
Finished Jun 27 07:16:55 PM PDT 24
Peak memory 246112 kb
Host smart-735e6505-a1e4-4d1e-9df9-cb6ab5db9ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888818331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2888818331
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.495469524
Short name T1141
Test name
Test status
Simulation time 218880239 ps
CPU time 2.96 seconds
Started Jun 27 07:15:28 PM PDT 24
Finished Jun 27 07:17:06 PM PDT 24
Peak memory 247476 kb
Host smart-ace7966f-377a-44ee-9eae-ac13960de156
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495469524 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.495469524
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.719311180
Short name T284
Test name
Test status
Simulation time 131471441 ps
CPU time 1.4 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 239164 kb
Host smart-b6d7da7c-aa50-44a6-a8f2-c7130f11c5c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719311180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.719311180
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.2946243116
Short name T1064
Test name
Test status
Simulation time 143345208 ps
CPU time 1.4 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 230256 kb
Host smart-577df956-c504-4076-996f-69fa9ef22c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946243116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.2946243116
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.2622865601
Short name T1186
Test name
Test status
Simulation time 145629162 ps
CPU time 3.06 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:55 PM PDT 24
Peak memory 239144 kb
Host smart-a1d2c5cf-8dbb-45b1-ab51-cc4f941c17ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622865601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.2622865601
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1280089667
Short name T1066
Test name
Test status
Simulation time 619128590 ps
CPU time 6.03 seconds
Started Jun 27 07:15:03 PM PDT 24
Finished Jun 27 07:16:41 PM PDT 24
Peak memory 247512 kb
Host smart-29163acf-9954-4eb9-853e-eeb2540f9744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280089667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1280089667
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.364854612
Short name T1153
Test name
Test status
Simulation time 75661410 ps
CPU time 2.03 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 244180 kb
Host smart-833dc875-af61-489d-84bc-a55a64a08c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364854612 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.364854612
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1787062207
Short name T327
Test name
Test status
Simulation time 146453449 ps
CPU time 1.43 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 241168 kb
Host smart-230f6807-d1b7-45c4-8c47-20ceb86da856
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787062207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1787062207
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3558050401
Short name T1065
Test name
Test status
Simulation time 519612268 ps
CPU time 1.88 seconds
Started Jun 27 07:15:26 PM PDT 24
Finished Jun 27 07:17:03 PM PDT 24
Peak memory 230584 kb
Host smart-93e4f235-1be9-4c8f-9ff4-fc89809d1a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558050401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3558050401
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2682452801
Short name T329
Test name
Test status
Simulation time 1215820527 ps
CPU time 3.86 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:56 PM PDT 24
Peak memory 239148 kb
Host smart-3a3863fa-94e7-40df-bf19-6842b1e87e33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682452801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2682452801
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1239036617
Short name T1155
Test name
Test status
Simulation time 178930044 ps
CPU time 6.15 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:58 PM PDT 24
Peak memory 239420 kb
Host smart-aa42f35c-1a3d-48ca-b0f9-af24b5a6dea7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239036617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1239036617
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2093609566
Short name T1116
Test name
Test status
Simulation time 401405884 ps
CPU time 2.92 seconds
Started Jun 27 07:15:22 PM PDT 24
Finished Jun 27 07:16:55 PM PDT 24
Peak memory 247368 kb
Host smart-26912a61-d0e5-4467-9d0c-73c0b733841e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093609566 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2093609566
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.2028976567
Short name T298
Test name
Test status
Simulation time 54214326 ps
CPU time 1.67 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 241232 kb
Host smart-cfeb3d7f-eaf3-4bbc-9534-b4d306adcf0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028976567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.2028976567
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.703839608
Short name T1150
Test name
Test status
Simulation time 41451450 ps
CPU time 1.39 seconds
Started Jun 27 07:15:23 PM PDT 24
Finished Jun 27 07:16:54 PM PDT 24
Peak memory 231076 kb
Host smart-4ca3494e-f351-4674-a4cb-15f955c60216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703839608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.703839608
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.919687550
Short name T1088
Test name
Test status
Simulation time 127054805 ps
CPU time 3.24 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:56 PM PDT 24
Peak memory 239172 kb
Host smart-361b7f2e-c874-49dc-8bcf-4e5adac0ee14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919687550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.919687550
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.3354442365
Short name T1098
Test name
Test status
Simulation time 50217161 ps
CPU time 2.71 seconds
Started Jun 27 07:15:22 PM PDT 24
Finished Jun 27 07:16:55 PM PDT 24
Peak memory 246264 kb
Host smart-cd1af2bf-c820-4cba-944e-42a3b745d932
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354442365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.3354442365
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.272861341
Short name T375
Test name
Test status
Simulation time 1447465391 ps
CPU time 11.14 seconds
Started Jun 27 07:15:25 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 243848 kb
Host smart-a24c89c6-f693-45fc-a6b4-0a3288976005
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272861341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.272861341
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2451727190
Short name T1140
Test name
Test status
Simulation time 145018471 ps
CPU time 2.14 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:13 PM PDT 24
Peak memory 245676 kb
Host smart-2dfe9f1b-bcda-484f-9f59-c534c854f6e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451727190 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2451727190
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.166395345
Short name T1068
Test name
Test status
Simulation time 39957763 ps
CPU time 1.35 seconds
Started Jun 27 07:15:25 PM PDT 24
Finished Jun 27 07:17:02 PM PDT 24
Peak memory 230284 kb
Host smart-2d8f9318-45a9-4188-a40b-4a49983f2555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166395345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.166395345
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.865906135
Short name T328
Test name
Test status
Simulation time 181459794 ps
CPU time 1.9 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:13 PM PDT 24
Peak memory 242312 kb
Host smart-f62a7363-749b-4a88-9d78-55c5be7d8783
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865906135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.865906135
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.962978197
Short name T1092
Test name
Test status
Simulation time 160991452 ps
CPU time 5.4 seconds
Started Jun 27 07:15:24 PM PDT 24
Finished Jun 27 07:16:58 PM PDT 24
Peak memory 246664 kb
Host smart-5048bf66-d82b-4862-aa61-b1a70a487b61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962978197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.962978197
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2716133127
Short name T1169
Test name
Test status
Simulation time 99854797 ps
CPU time 3.2 seconds
Started Jun 27 07:15:40 PM PDT 24
Finished Jun 27 07:17:25 PM PDT 24
Peak memory 247448 kb
Host smart-43e0d1bd-de6f-4d6d-af82-b25dcc6c411f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716133127 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2716133127
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3048170978
Short name T1117
Test name
Test status
Simulation time 73764281 ps
CPU time 1.48 seconds
Started Jun 27 07:15:36 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 240840 kb
Host smart-e44091df-3129-48b5-8c8f-121cd4be0037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048170978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3048170978
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2601440484
Short name T1188
Test name
Test status
Simulation time 76484433 ps
CPU time 1.38 seconds
Started Jun 27 07:15:40 PM PDT 24
Finished Jun 27 07:17:13 PM PDT 24
Peak memory 230616 kb
Host smart-35ae801b-9a84-4198-9d2c-8ac3bc7bf99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601440484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2601440484
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1187650242
Short name T1090
Test name
Test status
Simulation time 252185138 ps
CPU time 2.25 seconds
Started Jun 27 07:15:41 PM PDT 24
Finished Jun 27 07:17:23 PM PDT 24
Peak memory 239156 kb
Host smart-babfdc43-d00f-492a-a075-32927c3b4376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187650242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1187650242
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.2720241757
Short name T1120
Test name
Test status
Simulation time 388512752 ps
CPU time 4.39 seconds
Started Jun 27 07:15:37 PM PDT 24
Finished Jun 27 07:17:15 PM PDT 24
Peak memory 247480 kb
Host smart-ca361211-7d4a-46ff-b3ac-e63dcb8b1c14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720241757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.2720241757
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1528642988
Short name T250
Test name
Test status
Simulation time 694639962 ps
CPU time 9.9 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:21 PM PDT 24
Peak memory 239248 kb
Host smart-34898e50-d0f8-4393-bdb6-d929c17b31e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528642988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.1528642988
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.3643593083
Short name T1086
Test name
Test status
Simulation time 114471897 ps
CPU time 2.82 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:14 PM PDT 24
Peak memory 247296 kb
Host smart-bc7fbd5d-b2fa-4976-84af-9c07ebe2e1ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643593083 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.3643593083
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3281817235
Short name T312
Test name
Test status
Simulation time 38562528 ps
CPU time 1.6 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 239232 kb
Host smart-079c1b24-2fbc-4db6-b803-36bc9ab16df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281817235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3281817235
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.369179313
Short name T1071
Test name
Test status
Simulation time 42743944 ps
CPU time 1.37 seconds
Started Jun 27 07:15:37 PM PDT 24
Finished Jun 27 07:17:12 PM PDT 24
Peak memory 230332 kb
Host smart-cb69f5dc-12d6-4ab9-b0b4-7833368e6854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369179313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.369179313
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1038352266
Short name T331
Test name
Test status
Simulation time 186542215 ps
CPU time 1.92 seconds
Started Jun 27 07:15:38 PM PDT 24
Finished Jun 27 07:17:13 PM PDT 24
Peak memory 239168 kb
Host smart-7fc083c7-76c7-4db9-9e57-a419a0a05808
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038352266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.1038352266
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1600924931
Short name T1099
Test name
Test status
Simulation time 255299389 ps
CPU time 4.42 seconds
Started Jun 27 07:15:38 PM PDT 24
Finished Jun 27 07:17:16 PM PDT 24
Peak memory 246412 kb
Host smart-cfa6f1e3-ce81-4841-95a5-15f48ccfc96f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600924931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1600924931
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.4233387098
Short name T1180
Test name
Test status
Simulation time 279144154 ps
CPU time 2.28 seconds
Started Jun 27 07:15:54 PM PDT 24
Finished Jun 27 07:17:36 PM PDT 24
Peak memory 246148 kb
Host smart-6a2ff9ad-2bb5-41ab-a7d3-5f1ee2ea3a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233387098 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.4233387098
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.589487528
Short name T1187
Test name
Test status
Simulation time 150627531 ps
CPU time 1.61 seconds
Started Jun 27 07:15:50 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 241136 kb
Host smart-9709c1d7-6c9c-41b4-a7ab-467dcacbde7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589487528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.589487528
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2761693430
Short name T1063
Test name
Test status
Simulation time 104277945 ps
CPU time 1.38 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231000 kb
Host smart-628e62b3-ddbc-4cf6-b11a-4b4a715e3410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761693430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2761693430
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1421880542
Short name T1108
Test name
Test status
Simulation time 1844199393 ps
CPU time 5.89 seconds
Started Jun 27 07:15:51 PM PDT 24
Finished Jun 27 07:17:39 PM PDT 24
Peak memory 242480 kb
Host smart-924717a0-e230-4888-a191-df97798a12dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421880542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1421880542
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2840268164
Short name T1181
Test name
Test status
Simulation time 190950995 ps
CPU time 5.15 seconds
Started Jun 27 07:15:39 PM PDT 24
Finished Jun 27 07:17:17 PM PDT 24
Peak memory 246412 kb
Host smart-8cf08c7c-625a-4db7-8268-3545031c398b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840268164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2840268164
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1993921897
Short name T376
Test name
Test status
Simulation time 1698297232 ps
CPU time 9.36 seconds
Started Jun 27 07:15:40 PM PDT 24
Finished Jun 27 07:17:31 PM PDT 24
Peak memory 243916 kb
Host smart-a44aec92-4984-4b4e-a56a-4125252095a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993921897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.1993921897
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2078545260
Short name T316
Test name
Test status
Simulation time 90935641 ps
CPU time 4.48 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:47 PM PDT 24
Peak memory 239180 kb
Host smart-4796acee-b126-47dc-9074-f89729489619
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078545260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2078545260
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2803458103
Short name T285
Test name
Test status
Simulation time 494310372 ps
CPU time 5.98 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:49 PM PDT 24
Peak memory 239188 kb
Host smart-d971c115-bc32-49ca-8a93-8c070471baff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803458103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2803458103
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3963895339
Short name T315
Test name
Test status
Simulation time 1412390127 ps
CPU time 2.62 seconds
Started Jun 27 07:13:59 PM PDT 24
Finished Jun 27 07:15:50 PM PDT 24
Peak memory 241100 kb
Host smart-61a62738-0ca7-4fca-8d34-39236281930d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963895339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.3963895339
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1095001486
Short name T1084
Test name
Test status
Simulation time 112624518 ps
CPU time 2.05 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:45 PM PDT 24
Peak memory 244800 kb
Host smart-1fae4c40-e941-4c5d-a4ee-f4d77d5b71a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095001486 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1095001486
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1690469543
Short name T1128
Test name
Test status
Simulation time 656566238 ps
CPU time 1.64 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:45 PM PDT 24
Peak memory 241484 kb
Host smart-70192eb6-e391-47a2-9678-b09be198cbef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690469543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1690469543
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.3329821554
Short name T1148
Test name
Test status
Simulation time 76848376 ps
CPU time 1.44 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 230392 kb
Host smart-d1d6e4f4-b15c-45d2-84cb-e1dfe410d387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329821554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3329821554
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2513227915
Short name T1101
Test name
Test status
Simulation time 41257075 ps
CPU time 1.31 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 229848 kb
Host smart-91d4bada-0885-4ff0-b1e9-e6310c3f79be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513227915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.2513227915
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3093606938
Short name T1149
Test name
Test status
Simulation time 131047529 ps
CPU time 1.4 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:44 PM PDT 24
Peak memory 230796 kb
Host smart-751d8987-9eec-4f39-b40c-bf8dc526457b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093606938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3093606938
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3415128511
Short name T1170
Test name
Test status
Simulation time 204543965 ps
CPU time 3.06 seconds
Started Jun 27 07:13:59 PM PDT 24
Finished Jun 27 07:15:51 PM PDT 24
Peak memory 242300 kb
Host smart-9c613e91-d1e2-47c9-9e86-678863cdf42e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415128511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3415128511
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2449239715
Short name T1137
Test name
Test status
Simulation time 1282430363 ps
CPU time 3.26 seconds
Started Jun 27 07:13:57 PM PDT 24
Finished Jun 27 07:15:46 PM PDT 24
Peak memory 246972 kb
Host smart-508d760d-bfce-40cd-8614-f4c8905bcb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449239715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2449239715
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3099147475
Short name T1152
Test name
Test status
Simulation time 670768654 ps
CPU time 9.78 seconds
Started Jun 27 07:13:58 PM PDT 24
Finished Jun 27 07:15:57 PM PDT 24
Peak memory 243920 kb
Host smart-bbd121ad-3d97-4646-bc50-3b589b9e6b16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099147475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.3099147475
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.988436085
Short name T1131
Test name
Test status
Simulation time 44226095 ps
CPU time 1.39 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231084 kb
Host smart-2bcd130d-c63c-4984-aaba-5c13c32cda19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988436085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.988436085
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2132555523
Short name T1162
Test name
Test status
Simulation time 533962046 ps
CPU time 1.48 seconds
Started Jun 27 07:15:54 PM PDT 24
Finished Jun 27 07:17:35 PM PDT 24
Peak memory 230320 kb
Host smart-3058cf79-78c7-488f-8e76-3a913f5f1212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132555523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2132555523
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1330769902
Short name T1132
Test name
Test status
Simulation time 140717337 ps
CPU time 1.37 seconds
Started Jun 27 07:15:54 PM PDT 24
Finished Jun 27 07:17:35 PM PDT 24
Peak memory 230588 kb
Host smart-ea8f390b-78d9-4b91-b293-25d19e2cc5ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330769902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1330769902
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.2174435758
Short name T1121
Test name
Test status
Simulation time 84364293 ps
CPU time 1.43 seconds
Started Jun 27 07:15:52 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231052 kb
Host smart-4561af72-e92c-47f9-abc7-461a4a95a514
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174435758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2174435758
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3044987850
Short name T1076
Test name
Test status
Simulation time 37212364 ps
CPU time 1.37 seconds
Started Jun 27 07:15:52 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230268 kb
Host smart-baf8e4f7-fd8c-48e8-9c7b-dfeee8105ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044987850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3044987850
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.628358340
Short name T1103
Test name
Test status
Simulation time 46752140 ps
CPU time 1.37 seconds
Started Jun 27 07:15:50 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230488 kb
Host smart-2df5cc57-7af4-4776-9498-f8f97b4c4cbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628358340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.628358340
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2237897961
Short name T1133
Test name
Test status
Simulation time 134419222 ps
CPU time 1.41 seconds
Started Jun 27 07:15:50 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230284 kb
Host smart-540fb21c-7c38-438c-b193-c459af0f5c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237897961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2237897961
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.2450780482
Short name T1161
Test name
Test status
Simulation time 44267866 ps
CPU time 1.44 seconds
Started Jun 27 07:15:52 PM PDT 24
Finished Jun 27 07:17:35 PM PDT 24
Peak memory 230348 kb
Host smart-ee4a2aa1-a856-4773-9f13-30580c51c49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450780482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.2450780482
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1738099676
Short name T1111
Test name
Test status
Simulation time 75431294 ps
CPU time 1.4 seconds
Started Jun 27 07:15:50 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230240 kb
Host smart-02e3a8cd-8fbe-4619-9c61-a927ed8b3ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738099676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1738099676
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.276882835
Short name T1093
Test name
Test status
Simulation time 85901361 ps
CPU time 1.37 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230544 kb
Host smart-9a4bac64-5d2f-42a5-a614-40ab087b9ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276882835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.276882835
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.994936273
Short name T295
Test name
Test status
Simulation time 81092965 ps
CPU time 4.31 seconds
Started Jun 27 07:14:12 PM PDT 24
Finished Jun 27 07:16:03 PM PDT 24
Peak memory 239028 kb
Host smart-399cc5cd-ed7c-4534-a270-771fe778bcff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994936273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alias
ing.994936273
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.407806201
Short name T313
Test name
Test status
Simulation time 6802278488 ps
CPU time 16.73 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:16 PM PDT 24
Peak memory 239320 kb
Host smart-d62f6e8a-bd6f-43e5-9281-dbc56e4402e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407806201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.407806201
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.20947556
Short name T296
Test name
Test status
Simulation time 1055659936 ps
CPU time 2.48 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:01 PM PDT 24
Peak memory 239112 kb
Host smart-75231b98-f1d1-4ba4-89a3-6989f98261ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20947556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_res
et.20947556
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.980213795
Short name T1113
Test name
Test status
Simulation time 444954768 ps
CPU time 3.15 seconds
Started Jun 27 07:14:10 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 247444 kb
Host smart-d2d62545-8748-40c5-9ceb-5f675e75256b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980213795 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.980213795
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.112377474
Short name T302
Test name
Test status
Simulation time 50121245 ps
CPU time 1.64 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:00 PM PDT 24
Peak memory 241188 kb
Host smart-7d2d42c3-a437-4d84-9d5d-b3e46f62289f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112377474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.112377474
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2221365090
Short name T1100
Test name
Test status
Simulation time 142064045 ps
CPU time 1.49 seconds
Started Jun 27 07:14:10 PM PDT 24
Finished Jun 27 07:16:00 PM PDT 24
Peak memory 231076 kb
Host smart-ff6bef1a-e33d-45f4-9813-e6c084a57821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221365090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2221365090
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.435328487
Short name T1178
Test name
Test status
Simulation time 560196322 ps
CPU time 1.59 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:00 PM PDT 24
Peak memory 229868 kb
Host smart-6a94a9e2-21c9-48d4-a8fd-78e422278926
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435328487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.435328487
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3977203562
Short name T1119
Test name
Test status
Simulation time 101641836 ps
CPU time 1.4 seconds
Started Jun 27 07:14:10 PM PDT 24
Finished Jun 27 07:16:00 PM PDT 24
Peak memory 229888 kb
Host smart-0b363791-fd58-4c20-8b43-b1ba3dda7a9d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977203562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3977203562
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3697509990
Short name T283
Test name
Test status
Simulation time 68814662 ps
CPU time 2.23 seconds
Started Jun 27 07:14:12 PM PDT 24
Finished Jun 27 07:16:01 PM PDT 24
Peak memory 239168 kb
Host smart-d9fdd1e0-3a37-4f2f-8252-86cbe2fbc04e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697509990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3697509990
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1287561553
Short name T1134
Test name
Test status
Simulation time 135970767 ps
CPU time 5.48 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:04 PM PDT 24
Peak memory 246596 kb
Host smart-34abf789-c692-4d66-b58d-cadf50427865
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287561553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1287561553
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3996097999
Short name T1174
Test name
Test status
Simulation time 70175723 ps
CPU time 1.41 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231076 kb
Host smart-c2a08d95-eef8-4499-9da0-f4aed0f9eccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996097999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3996097999
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.291807593
Short name T1107
Test name
Test status
Simulation time 140467056 ps
CPU time 1.38 seconds
Started Jun 27 07:15:51 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230236 kb
Host smart-f6766387-0b48-4775-a520-6583fa3daca5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291807593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.291807593
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.2199628296
Short name T1127
Test name
Test status
Simulation time 88150883 ps
CPU time 1.35 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231076 kb
Host smart-4bd64185-e80c-49ef-8447-2c715fc71073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199628296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2199628296
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.2742671764
Short name T1185
Test name
Test status
Simulation time 76688632 ps
CPU time 1.56 seconds
Started Jun 27 07:15:49 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 231064 kb
Host smart-6223619d-a8b9-4a0c-a603-91f0a1c57a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742671764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2742671764
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.1333230859
Short name T1147
Test name
Test status
Simulation time 72889207 ps
CPU time 1.41 seconds
Started Jun 27 07:15:54 PM PDT 24
Finished Jun 27 07:17:35 PM PDT 24
Peak memory 230500 kb
Host smart-b2a33ab0-f34d-46ce-9c14-f7c60a91368f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333230859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1333230859
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3189021788
Short name T1106
Test name
Test status
Simulation time 75468045 ps
CPU time 1.32 seconds
Started Jun 27 07:15:52 PM PDT 24
Finished Jun 27 07:17:34 PM PDT 24
Peak memory 230328 kb
Host smart-063c97e1-f3c8-49e2-8a31-e160b5f4cb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189021788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3189021788
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3485136184
Short name T1096
Test name
Test status
Simulation time 38083486 ps
CPU time 1.35 seconds
Started Jun 27 07:16:05 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 231008 kb
Host smart-e82f787b-ea65-45f4-8bef-0dcb2bfd224f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485136184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3485136184
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.986397960
Short name T1070
Test name
Test status
Simulation time 40810459 ps
CPU time 1.42 seconds
Started Jun 27 07:16:05 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 230660 kb
Host smart-a67c3582-df33-44f2-85b3-b98f044820e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986397960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.986397960
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.890636702
Short name T1105
Test name
Test status
Simulation time 94732101 ps
CPU time 1.38 seconds
Started Jun 27 07:16:03 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 231036 kb
Host smart-8e66ba90-7059-4c5e-a29f-3a6000f1aeb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890636702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.890636702
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.4033913656
Short name T1159
Test name
Test status
Simulation time 39506130 ps
CPU time 1.37 seconds
Started Jun 27 07:16:03 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 231080 kb
Host smart-28b227a3-83b0-4ec1-a78e-3671a09177b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033913656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.4033913656
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.392289769
Short name T297
Test name
Test status
Simulation time 1192704055 ps
CPU time 6.06 seconds
Started Jun 27 07:14:25 PM PDT 24
Finished Jun 27 07:16:07 PM PDT 24
Peak memory 241496 kb
Host smart-94550add-4c78-49fc-9831-f137fbd6ee3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392289769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alias
ing.392289769
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2773053722
Short name T337
Test name
Test status
Simulation time 187366921 ps
CPU time 4.83 seconds
Started Jun 27 07:14:26 PM PDT 24
Finished Jun 27 07:16:05 PM PDT 24
Peak memory 239112 kb
Host smart-addf5c21-4078-49dc-bed0-cf2dfeccc847
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773053722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2773053722
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.4069738538
Short name T286
Test name
Test status
Simulation time 88293280 ps
CPU time 1.78 seconds
Started Jun 27 07:14:29 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 240800 kb
Host smart-7fe711a9-1f55-4ada-868f-aced6e75a026
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069738538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.4069738538
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.633987641
Short name T1102
Test name
Test status
Simulation time 84006003 ps
CPU time 2.11 seconds
Started Jun 27 07:14:30 PM PDT 24
Finished Jun 27 07:16:06 PM PDT 24
Peak memory 245812 kb
Host smart-01534bdb-999e-4507-8363-2ed2073d8432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633987641 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.633987641
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.1269676575
Short name T1194
Test name
Test status
Simulation time 42756621 ps
CPU time 1.66 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 241188 kb
Host smart-658e727f-2a90-4dab-96f2-18c87ba91659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269676575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1269676575
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.2110096514
Short name T1094
Test name
Test status
Simulation time 41068512 ps
CPU time 1.46 seconds
Started Jun 27 07:14:30 PM PDT 24
Finished Jun 27 07:16:06 PM PDT 24
Peak memory 230396 kb
Host smart-b4bc875f-a4a8-4257-80eb-7432d5ed94a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110096514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2110096514
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.4194211016
Short name T1183
Test name
Test status
Simulation time 74134721 ps
CPU time 1.31 seconds
Started Jun 27 07:14:30 PM PDT 24
Finished Jun 27 07:16:06 PM PDT 24
Peak memory 230740 kb
Host smart-805fd6ee-c310-44e5-b80b-ba323011ba55
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194211016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.4194211016
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2009956913
Short name T1172
Test name
Test status
Simulation time 130355284 ps
CPU time 1.32 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:01 PM PDT 24
Peak memory 230348 kb
Host smart-4688ba2e-54e5-4cb3-a68f-048e730ebc38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009956913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2009956913
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.969971198
Short name T330
Test name
Test status
Simulation time 455689351 ps
CPU time 3.47 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:04 PM PDT 24
Peak memory 239276 kb
Host smart-6c0984f0-37e0-4bb5-8b59-e4950056fe31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969971198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_same_csr_outstanding.969971198
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2724514208
Short name T1091
Test name
Test status
Simulation time 1309481713 ps
CPU time 4.45 seconds
Started Jun 27 07:14:11 PM PDT 24
Finished Jun 27 07:16:03 PM PDT 24
Peak memory 246424 kb
Host smart-cc8b0eac-c600-4ceb-b66e-b34f54d92aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724514208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2724514208
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1910967400
Short name T374
Test name
Test status
Simulation time 2621765644 ps
CPU time 19.14 seconds
Started Jun 27 07:14:12 PM PDT 24
Finished Jun 27 07:16:18 PM PDT 24
Peak memory 244764 kb
Host smart-cac91bf2-9edd-470d-a44e-c969e201758e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910967400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.1910967400
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.171149847
Short name T1075
Test name
Test status
Simulation time 137975159 ps
CPU time 1.39 seconds
Started Jun 27 07:16:04 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 230564 kb
Host smart-3c1be6f1-bc89-4422-9650-f23136fd81c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171149847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.171149847
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.800259895
Short name T1166
Test name
Test status
Simulation time 513410727 ps
CPU time 1.37 seconds
Started Jun 27 07:16:05 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 230488 kb
Host smart-4628f4b2-0980-4726-9113-588f2801527d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800259895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.800259895
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1228215703
Short name T1129
Test name
Test status
Simulation time 37300809 ps
CPU time 1.38 seconds
Started Jun 27 07:16:04 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 230392 kb
Host smart-16a20971-3f67-457c-b8d2-b4aa43da2d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228215703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1228215703
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1442027968
Short name T1085
Test name
Test status
Simulation time 44764785 ps
CPU time 1.4 seconds
Started Jun 27 07:16:04 PM PDT 24
Finished Jun 27 07:17:53 PM PDT 24
Peak memory 230344 kb
Host smart-87117904-47ad-4689-818c-7b3a6b669b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442027968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1442027968
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.2782444083
Short name T1151
Test name
Test status
Simulation time 151316090 ps
CPU time 1.42 seconds
Started Jun 27 07:16:17 PM PDT 24
Finished Jun 27 07:18:11 PM PDT 24
Peak memory 230664 kb
Host smart-a837211a-990d-4950-af40-d3383f9e2a64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782444083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2782444083
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.716614270
Short name T1083
Test name
Test status
Simulation time 127734675 ps
CPU time 1.43 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:12 PM PDT 24
Peak memory 230316 kb
Host smart-0336f226-78c5-4b69-a7c2-7a2debacfc8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716614270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.716614270
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2192329080
Short name T1164
Test name
Test status
Simulation time 43096668 ps
CPU time 1.43 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:12 PM PDT 24
Peak memory 230332 kb
Host smart-9e8542df-f530-4802-b9a3-f533164eacc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192329080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2192329080
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.3293788736
Short name T1123
Test name
Test status
Simulation time 508774523 ps
CPU time 1.46 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:12 PM PDT 24
Peak memory 230244 kb
Host smart-b01deff5-5ba8-4a7f-bd0b-3b6ef60fc1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293788736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3293788736
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2692005860
Short name T1146
Test name
Test status
Simulation time 139949234 ps
CPU time 1.37 seconds
Started Jun 27 07:16:20 PM PDT 24
Finished Jun 27 07:18:13 PM PDT 24
Peak memory 230292 kb
Host smart-c9f6be3a-571d-4a9e-86e6-90e02a06db2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692005860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2692005860
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.32655741
Short name T1082
Test name
Test status
Simulation time 136265905 ps
CPU time 1.41 seconds
Started Jun 27 07:16:17 PM PDT 24
Finished Jun 27 07:18:11 PM PDT 24
Peak memory 231072 kb
Host smart-b576c8be-f7c7-48d7-bbbb-6539eb702af8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32655741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.32655741
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2268131262
Short name T1143
Test name
Test status
Simulation time 121552559 ps
CPU time 3.1 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:03 PM PDT 24
Peak memory 247500 kb
Host smart-6e38ed29-bffe-4f3d-8856-52cda5cec1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268131262 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2268131262
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3205653170
Short name T1136
Test name
Test status
Simulation time 43497883 ps
CPU time 1.58 seconds
Started Jun 27 07:14:23 PM PDT 24
Finished Jun 27 07:16:01 PM PDT 24
Peak memory 239216 kb
Host smart-e2d0db0d-2d8e-4c8c-8623-6598133b7a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205653170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3205653170
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.361181169
Short name T1079
Test name
Test status
Simulation time 40995314 ps
CPU time 1.42 seconds
Started Jun 27 07:14:23 PM PDT 24
Finished Jun 27 07:16:01 PM PDT 24
Peak memory 230324 kb
Host smart-6140b9de-0908-40c3-8244-3972c3db28dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361181169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.361181169
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.65704083
Short name T1145
Test name
Test status
Simulation time 170962589 ps
CPU time 1.85 seconds
Started Jun 27 07:14:25 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 239164 kb
Host smart-06c98ea3-73f1-4008-85b9-e8cfce3186aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65704083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctr
l_same_csr_outstanding.65704083
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.492576264
Short name T1130
Test name
Test status
Simulation time 124407485 ps
CPU time 4.73 seconds
Started Jun 27 07:14:25 PM PDT 24
Finished Jun 27 07:16:05 PM PDT 24
Peak memory 246540 kb
Host smart-d5e86ab8-a8ad-433b-aded-ed18b233a62b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492576264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.492576264
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2895403991
Short name T1163
Test name
Test status
Simulation time 112266651 ps
CPU time 4.04 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:14 PM PDT 24
Peak memory 246648 kb
Host smart-17dcbfe3-8a9c-4b0b-a262-e1837c00c912
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895403991 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2895403991
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.481261882
Short name T311
Test name
Test status
Simulation time 173528293 ps
CPU time 1.84 seconds
Started Jun 27 07:14:36 PM PDT 24
Finished Jun 27 07:16:11 PM PDT 24
Peak memory 239092 kb
Host smart-a6620913-132b-4299-9851-5ebdb29c6e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481261882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.481261882
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.3135228511
Short name T1078
Test name
Test status
Simulation time 39335024 ps
CPU time 1.42 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:02 PM PDT 24
Peak memory 230604 kb
Host smart-9629affe-5fd1-47a3-a1aa-40a760718205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135228511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3135228511
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.2179822414
Short name T1089
Test name
Test status
Simulation time 176137618 ps
CPU time 2.4 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:12 PM PDT 24
Peak memory 239192 kb
Host smart-0de81c6a-5165-41c1-a5ba-dc7e62e90ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179822414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.2179822414
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.80012251
Short name T1104
Test name
Test status
Simulation time 195708313 ps
CPU time 5.57 seconds
Started Jun 27 07:14:23 PM PDT 24
Finished Jun 27 07:16:05 PM PDT 24
Peak memory 246976 kb
Host smart-d2b77d57-0521-485a-9ea4-6be110d607d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80012251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.80012251
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1805048967
Short name T1087
Test name
Test status
Simulation time 2512826257 ps
CPU time 20.13 seconds
Started Jun 27 07:14:24 PM PDT 24
Finished Jun 27 07:16:20 PM PDT 24
Peak memory 244612 kb
Host smart-2cf6e7ae-fb64-4307-bb0f-2869129d4853
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805048967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.1805048967
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1602860390
Short name T252
Test name
Test status
Simulation time 425761204 ps
CPU time 3.43 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:13 PM PDT 24
Peak memory 247456 kb
Host smart-67769800-2533-4198-bb05-55e643a510f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602860390 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1602860390
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3326401658
Short name T1138
Test name
Test status
Simulation time 87130614 ps
CPU time 1.65 seconds
Started Jun 27 07:14:45 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 241468 kb
Host smart-5cdfa8b2-d4d9-4a93-bd54-39d6a03df848
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326401658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3326401658
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3445141288
Short name T1074
Test name
Test status
Simulation time 153998618 ps
CPU time 1.28 seconds
Started Jun 27 07:14:59 PM PDT 24
Finished Jun 27 07:16:31 PM PDT 24
Peak memory 230156 kb
Host smart-476b4fda-04f9-4dea-8670-cb05b8d379c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445141288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3445141288
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.3621799090
Short name T1110
Test name
Test status
Simulation time 80153824 ps
CPU time 1.94 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:12 PM PDT 24
Peak memory 242100 kb
Host smart-d1af17eb-2099-4749-8fa8-49bbbbc88ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621799090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.3621799090
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3210594788
Short name T1173
Test name
Test status
Simulation time 817695829 ps
CPU time 3.28 seconds
Started Jun 27 07:14:40 PM PDT 24
Finished Jun 27 07:16:19 PM PDT 24
Peak memory 246052 kb
Host smart-b4b64470-be90-43c6-8a2d-85edd9eaeabf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210594788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3210594788
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.299924361
Short name T379
Test name
Test status
Simulation time 718720904 ps
CPU time 10.89 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:21 PM PDT 24
Peak memory 244040 kb
Host smart-64aeea2d-0cc6-48fb-b6c7-16cbcde27118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299924361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.299924361
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2875147348
Short name T1081
Test name
Test status
Simulation time 204697287 ps
CPU time 3.15 seconds
Started Jun 27 07:14:51 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 247556 kb
Host smart-4b3ad26c-af1e-4173-9063-c125a8821565
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875147348 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2875147348
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.879353309
Short name T1125
Test name
Test status
Simulation time 40387449 ps
CPU time 1.55 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:11 PM PDT 24
Peak memory 241508 kb
Host smart-ba522244-1360-42f3-bb4f-f6e3d6d72be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879353309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.879353309
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.2384632087
Short name T1069
Test name
Test status
Simulation time 37995635 ps
CPU time 1.44 seconds
Started Jun 27 07:14:40 PM PDT 24
Finished Jun 27 07:16:17 PM PDT 24
Peak memory 231304 kb
Host smart-d6cc1361-b50a-42a6-8847-962d1c7a4b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384632087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.2384632087
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4031025750
Short name T1167
Test name
Test status
Simulation time 162402232 ps
CPU time 2.8 seconds
Started Jun 27 07:14:41 PM PDT 24
Finished Jun 27 07:16:19 PM PDT 24
Peak memory 242524 kb
Host smart-ee79cab0-41ea-4678-b624-77693c7d6ec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031025750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.4031025750
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2504633074
Short name T1193
Test name
Test status
Simulation time 119301889 ps
CPU time 4.57 seconds
Started Jun 27 07:14:36 PM PDT 24
Finished Jun 27 07:16:14 PM PDT 24
Peak memory 239280 kb
Host smart-82417804-da57-450d-adba-9c671e56eecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504633074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2504633074
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2285427231
Short name T378
Test name
Test status
Simulation time 616533192 ps
CPU time 9.88 seconds
Started Jun 27 07:14:35 PM PDT 24
Finished Jun 27 07:16:19 PM PDT 24
Peak memory 239552 kb
Host smart-fb46f2bd-1b11-4709-bfe1-afd8f3c65133
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285427231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.2285427231
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.811369691
Short name T1112
Test name
Test status
Simulation time 269875345 ps
CPU time 3.47 seconds
Started Jun 27 07:14:50 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 247392 kb
Host smart-d408aab8-250b-438c-8bf2-661d8d3aee33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811369691 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.811369691
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.2939311272
Short name T1097
Test name
Test status
Simulation time 44019336 ps
CPU time 1.57 seconds
Started Jun 27 07:14:54 PM PDT 24
Finished Jun 27 07:16:23 PM PDT 24
Peak memory 241160 kb
Host smart-29d5e9a4-0acd-41a4-8b10-259026302f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939311272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.2939311272
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.1225920885
Short name T1176
Test name
Test status
Simulation time 60606441 ps
CPU time 1.4 seconds
Started Jun 27 07:14:50 PM PDT 24
Finished Jun 27 07:16:24 PM PDT 24
Peak memory 230312 kb
Host smart-a17caae3-3bb9-4bcc-8161-8dc48b4baee2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225920885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.1225920885
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.4291169420
Short name T1122
Test name
Test status
Simulation time 162468491 ps
CPU time 2.93 seconds
Started Jun 27 07:14:51 PM PDT 24
Finished Jun 27 07:16:26 PM PDT 24
Peak memory 239188 kb
Host smart-6d243146-b545-4cff-b16a-8094607f17e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291169420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.4291169420
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3491699698
Short name T1135
Test name
Test status
Simulation time 1226048430 ps
CPU time 5.85 seconds
Started Jun 27 07:14:51 PM PDT 24
Finished Jun 27 07:16:29 PM PDT 24
Peak memory 246356 kb
Host smart-de7bc62f-3252-4af1-8713-fd52d574f25c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491699698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3491699698
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2407320006
Short name T1182
Test name
Test status
Simulation time 1287464003 ps
CPU time 18.91 seconds
Started Jun 27 07:14:49 PM PDT 24
Finished Jun 27 07:16:41 PM PDT 24
Peak memory 239328 kb
Host smart-b39a3e39-fe2f-4850-9b86-61492e35f61e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407320006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.2407320006
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.1458247217
Short name T106
Test name
Test status
Simulation time 20061168809 ps
CPU time 54.55 seconds
Started Jun 27 07:16:20 PM PDT 24
Finished Jun 27 07:19:07 PM PDT 24
Peak memory 242844 kb
Host smart-b1d9a186-f865-4fa2-8ef3-1f7027ae5b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458247217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.1458247217
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3324049616
Short name T992
Test name
Test status
Simulation time 2188786497 ps
CPU time 12.86 seconds
Started Jun 27 07:16:20 PM PDT 24
Finished Jun 27 07:18:25 PM PDT 24
Peak memory 242100 kb
Host smart-d9ea8bc3-9b16-456e-bb5e-865f0b06bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324049616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3324049616
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.3215944403
Short name T363
Test name
Test status
Simulation time 243287769 ps
CPU time 10.28 seconds
Started Jun 27 07:16:22 PM PDT 24
Finished Jun 27 07:18:31 PM PDT 24
Peak memory 242048 kb
Host smart-a6def53b-79d5-4577-b928-c18e13d8f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215944403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3215944403
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3428353856
Short name T577
Test name
Test status
Simulation time 2445252621 ps
CPU time 35.34 seconds
Started Jun 27 07:16:19 PM PDT 24
Finished Jun 27 07:18:46 PM PDT 24
Peak memory 242284 kb
Host smart-26159383-cc2d-4932-bd05-31e9f48c9fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428353856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3428353856
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.1180418161
Short name T322
Test name
Test status
Simulation time 381832964 ps
CPU time 3.86 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:14 PM PDT 24
Peak memory 241944 kb
Host smart-bc2e2c51-01fd-4f36-8632-947ec1828177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180418161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1180418161
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.3505462932
Short name T555
Test name
Test status
Simulation time 3016497451 ps
CPU time 11.07 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:22 PM PDT 24
Peak memory 241996 kb
Host smart-25fe3191-d8ca-422c-8f9a-9fc31d32dad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505462932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3505462932
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.105168802
Short name T183
Test name
Test status
Simulation time 1940260734 ps
CPU time 42.18 seconds
Started Jun 27 07:16:19 PM PDT 24
Finished Jun 27 07:18:54 PM PDT 24
Peak memory 258452 kb
Host smart-f656ef1f-f16d-46f1-8470-1b4d117594a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105168802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.105168802
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.2188283518
Short name T491
Test name
Test status
Simulation time 725673738 ps
CPU time 6.47 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:18:47 PM PDT 24
Peak memory 242424 kb
Host smart-5460dc1f-c1b4-469d-a304-70023891a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188283518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.2188283518
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.436682569
Short name T601
Test name
Test status
Simulation time 1228366050 ps
CPU time 14.94 seconds
Started Jun 27 07:16:17 PM PDT 24
Finished Jun 27 07:18:25 PM PDT 24
Peak memory 241792 kb
Host smart-1b9ff08b-1298-4a37-8615-03cb0177bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436682569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.436682569
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.126478041
Short name T29
Test name
Test status
Simulation time 11605146756 ps
CPU time 22.28 seconds
Started Jun 27 07:16:16 PM PDT 24
Finished Jun 27 07:18:32 PM PDT 24
Peak memory 242472 kb
Host smart-e32fc322-ac4c-4bae-9329-c09aaa9de8cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126478041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.126478041
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.3731310481
Short name T486
Test name
Test status
Simulation time 576325666 ps
CPU time 17.65 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:28 PM PDT 24
Peak memory 241508 kb
Host smart-96db4956-d6b3-485d-a23f-6603bb331015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731310481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3731310481
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.1124167044
Short name T757
Test name
Test status
Simulation time 3206715654 ps
CPU time 8.69 seconds
Started Jun 27 07:16:18 PM PDT 24
Finished Jun 27 07:18:19 PM PDT 24
Peak memory 242320 kb
Host smart-6d144055-fb0f-4e3d-b7e1-6873bc7b1c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124167044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1124167044
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.2451688474
Short name T147
Test name
Test status
Simulation time 774637598 ps
CPU time 17.12 seconds
Started Jun 27 07:16:34 PM PDT 24
Finished Jun 27 07:19:10 PM PDT 24
Peak memory 241896 kb
Host smart-9badc704-5f66-4abf-8a44-12c73d83e1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451688474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
2451688474
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3961976811
Short name T274
Test name
Test status
Simulation time 90983249531 ps
CPU time 810.81 seconds
Started Jun 27 07:16:30 PM PDT 24
Finished Jun 27 07:32:09 PM PDT 24
Peak memory 262500 kb
Host smart-20a41629-35f3-497b-bc85-5087161c3dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961976811 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3961976811
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.810787328
Short name T522
Test name
Test status
Simulation time 3116778797 ps
CPU time 17.78 seconds
Started Jun 27 07:16:34 PM PDT 24
Finished Jun 27 07:19:12 PM PDT 24
Peak memory 242312 kb
Host smart-24fc158d-09d5-4ad6-acfc-791ed0e69d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810787328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.810787328
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.3206077541
Short name T1012
Test name
Test status
Simulation time 799242844 ps
CPU time 1.93 seconds
Started Jun 27 07:16:17 PM PDT 24
Finished Jun 27 07:18:12 PM PDT 24
Peak memory 240444 kb
Host smart-add3d9bb-bcfa-4f07-8900-552749d5e033
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3206077541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3206077541
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.4118172117
Short name T458
Test name
Test status
Simulation time 63614542 ps
CPU time 1.82 seconds
Started Jun 27 07:16:31 PM PDT 24
Finished Jun 27 07:18:41 PM PDT 24
Peak memory 240188 kb
Host smart-4418767c-b29e-494d-96c2-e56517c70eb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118172117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4118172117
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1221124359
Short name T571
Test name
Test status
Simulation time 353479430 ps
CPU time 7.25 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:47 PM PDT 24
Peak memory 242300 kb
Host smart-0957e8d2-3417-41d8-bb07-c7f4115b56a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221124359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1221124359
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.2670769168
Short name T639
Test name
Test status
Simulation time 506135614 ps
CPU time 10.23 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:50 PM PDT 24
Peak memory 242232 kb
Host smart-e5536fde-8a8a-4ffe-a999-57d37caa96be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670769168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2670769168
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.2702465289
Short name T5
Test name
Test status
Simulation time 907192505 ps
CPU time 22.32 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:19:02 PM PDT 24
Peak memory 242204 kb
Host smart-fa69e007-ffb7-4dc9-b159-c7b8720f0c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702465289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.2702465289
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.2168514556
Short name T406
Test name
Test status
Simulation time 120860503 ps
CPU time 2.89 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:18:43 PM PDT 24
Peak memory 242404 kb
Host smart-f76c88ed-eb84-4e6d-af8b-161e78c3ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168514556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2168514556
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2794936699
Short name T599
Test name
Test status
Simulation time 854755098 ps
CPU time 14.54 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:54 PM PDT 24
Peak memory 242588 kb
Host smart-bd16d01d-cad4-447b-9d1e-118053042398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794936699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2794936699
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.4143224852
Short name T1022
Test name
Test status
Simulation time 121692963 ps
CPU time 3.44 seconds
Started Jun 27 07:16:31 PM PDT 24
Finished Jun 27 07:18:42 PM PDT 24
Peak memory 242240 kb
Host smart-b7c877e7-fb0b-4f7f-8739-1e98abb16075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143224852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.4143224852
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2650710626
Short name T811
Test name
Test status
Simulation time 294175837 ps
CPU time 4.44 seconds
Started Jun 27 07:16:36 PM PDT 24
Finished Jun 27 07:18:57 PM PDT 24
Peak memory 242232 kb
Host smart-6de2dd86-0d3b-42cf-ae8e-39372e3da041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650710626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2650710626
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3882492035
Short name T288
Test name
Test status
Simulation time 543106072 ps
CPU time 10.51 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:50 PM PDT 24
Peak memory 242188 kb
Host smart-328ca21d-949b-4114-b03e-c77aa256ec3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882492035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3882492035
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2400735949
Short name T899
Test name
Test status
Simulation time 337259994 ps
CPU time 5.54 seconds
Started Jun 27 07:16:31 PM PDT 24
Finished Jun 27 07:18:44 PM PDT 24
Peak memory 242144 kb
Host smart-fe677add-3ab2-4b12-a7ff-f8f1bc3648fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400735949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2400735949
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.553281857
Short name T228
Test name
Test status
Simulation time 38715488108 ps
CPU time 187.71 seconds
Started Jun 27 07:16:35 PM PDT 24
Finished Jun 27 07:21:57 PM PDT 24
Peak memory 274100 kb
Host smart-6df9f4a4-ee4a-4428-9c1c-ebd5c009b632
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553281857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.553281857
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.2836443080
Short name T102
Test name
Test status
Simulation time 267823340 ps
CPU time 4.16 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:18:44 PM PDT 24
Peak memory 241896 kb
Host smart-4bd57c94-39ed-4ad2-84d0-626e8b410bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836443080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2836443080
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.3853084909
Short name T121
Test name
Test status
Simulation time 54933029024 ps
CPU time 114.89 seconds
Started Jun 27 07:16:31 PM PDT 24
Finished Jun 27 07:20:34 PM PDT 24
Peak memory 264764 kb
Host smart-1f66ef03-0756-456f-9d41-400e84bce52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853084909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
3853084909
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2818532199
Short name T445
Test name
Test status
Simulation time 12629292543 ps
CPU time 26.73 seconds
Started Jun 27 07:16:34 PM PDT 24
Finished Jun 27 07:19:16 PM PDT 24
Peak memory 248876 kb
Host smart-a98bad7b-e2da-48e4-a853-1ddb682ede73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818532199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2818532199
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.1775026127
Short name T690
Test name
Test status
Simulation time 53827402 ps
CPU time 1.75 seconds
Started Jun 27 07:17:46 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 240168 kb
Host smart-75047056-6570-4acd-8fda-547aea033b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775026127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1775026127
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.3333691601
Short name T803
Test name
Test status
Simulation time 2998019524 ps
CPU time 23.61 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:21:35 PM PDT 24
Peak memory 242044 kb
Host smart-9c3d7d45-a25a-43ff-a0be-45a83bfca99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333691601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.3333691601
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.132407872
Short name T768
Test name
Test status
Simulation time 742637075 ps
CPU time 11.87 seconds
Started Jun 27 07:17:46 PM PDT 24
Finished Jun 27 07:20:24 PM PDT 24
Peak memory 242284 kb
Host smart-6e22870f-4502-48e4-8a41-a64f977cea2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132407872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.132407872
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.4264360254
Short name T668
Test name
Test status
Simulation time 1911685096 ps
CPU time 4.59 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 242116 kb
Host smart-adaea417-99cc-4af7-bd6a-0428a52d65bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264360254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.4264360254
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.3232324077
Short name T181
Test name
Test status
Simulation time 632387797 ps
CPU time 13.82 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:30 PM PDT 24
Peak memory 242264 kb
Host smart-34ea7767-b35b-4a62-ae20-80ca205de654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232324077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3232324077
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.4268642945
Short name T697
Test name
Test status
Simulation time 253578039 ps
CPU time 6.06 seconds
Started Jun 27 07:17:49 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 242312 kb
Host smart-ef92c597-d781-466e-b39d-a7ff56be9446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268642945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.4268642945
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.314603432
Short name T222
Test name
Test status
Simulation time 1745066540 ps
CPU time 23.71 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:39 PM PDT 24
Peak memory 242200 kb
Host smart-d9c1ffae-6580-4d11-9f7d-8290af48108f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314603432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.314603432
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.57009922
Short name T182
Test name
Test status
Simulation time 722842271 ps
CPU time 10.89 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:27 PM PDT 24
Peak memory 242092 kb
Host smart-ee947c3d-1a92-4bfa-b904-b0da6bef9161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57009922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.57009922
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2553912760
Short name T110
Test name
Test status
Simulation time 2151289135 ps
CPU time 5.55 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:22 PM PDT 24
Peak memory 242100 kb
Host smart-2b1fc4da-b24a-4212-bd9d-a5c5d763b271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553912760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2553912760
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.563369059
Short name T303
Test name
Test status
Simulation time 1052818991 ps
CPU time 2.63 seconds
Started Jun 27 07:17:44 PM PDT 24
Finished Jun 27 07:20:19 PM PDT 24
Peak memory 241332 kb
Host smart-20627d29-7983-44e5-9bdf-949bceafd8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563369059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
563369059
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.3982016736
Short name T267
Test name
Test status
Simulation time 132645662459 ps
CPU time 885.28 seconds
Started Jun 27 07:17:44 PM PDT 24
Finished Jun 27 07:35:02 PM PDT 24
Peak memory 305636 kb
Host smart-c2826147-8f5a-4c4f-b0c6-2234e7fd0107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982016736 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.3982016736
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.2111330042
Short name T393
Test name
Test status
Simulation time 2011124045 ps
CPU time 21.13 seconds
Started Jun 27 07:17:46 PM PDT 24
Finished Jun 27 07:20:39 PM PDT 24
Peak memory 242504 kb
Host smart-51d29533-e1a4-4311-b67a-e6ae9a12ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111330042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.2111330042
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.2915703982
Short name T271
Test name
Test status
Simulation time 1536726368 ps
CPU time 4.96 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:26:18 PM PDT 24
Peak memory 242088 kb
Host smart-e7bd1f8a-2bb7-4846-b804-3707b7cce714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915703982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2915703982
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.4161832897
Short name T765
Test name
Test status
Simulation time 650884595 ps
CPU time 5.41 seconds
Started Jun 27 07:26:58 PM PDT 24
Finished Jun 27 07:29:10 PM PDT 24
Peak memory 241740 kb
Host smart-dacd54b1-7e4b-4b50-8705-37df9737501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161832897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.4161832897
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1043257718
Short name T154
Test name
Test status
Simulation time 1527716931 ps
CPU time 26.31 seconds
Started Jun 27 07:25:07 PM PDT 24
Finished Jun 27 07:27:45 PM PDT 24
Peak memory 242020 kb
Host smart-baf832f5-9147-44b4-8f6f-ae7f9174cdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043257718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1043257718
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1286646421
Short name T429
Test name
Test status
Simulation time 583224214 ps
CPU time 4.03 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242276 kb
Host smart-69afefd8-7d51-486f-8536-0aaf3e027cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286646421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1286646421
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.2403086471
Short name T665
Test name
Test status
Simulation time 1751764128 ps
CPU time 4.98 seconds
Started Jun 27 07:25:57 PM PDT 24
Finished Jun 27 07:27:56 PM PDT 24
Peak memory 242024 kb
Host smart-02079d36-6823-4cda-b8c8-d073a7cb739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403086471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.2403086471
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2384341596
Short name T1001
Test name
Test status
Simulation time 1845620152 ps
CPU time 15.21 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:27:32 PM PDT 24
Peak memory 248568 kb
Host smart-886494c8-5a7e-42fb-8d2d-b2e079822a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384341596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2384341596
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1410191968
Short name T706
Test name
Test status
Simulation time 274805305 ps
CPU time 7.39 seconds
Started Jun 27 07:28:37 PM PDT 24
Finished Jun 27 07:30:37 PM PDT 24
Peak memory 242356 kb
Host smart-64a4316e-f780-4b0e-a06a-fcdcadd0594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410191968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1410191968
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1707769139
Short name T894
Test name
Test status
Simulation time 356135629 ps
CPU time 4.7 seconds
Started Jun 27 07:26:14 PM PDT 24
Finished Jun 27 07:28:41 PM PDT 24
Peak memory 242020 kb
Host smart-ddf50582-5cc3-4a9f-a286-9e50f1d9851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707769139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1707769139
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.1517652133
Short name T582
Test name
Test status
Simulation time 360276601 ps
CPU time 9.64 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:23 PM PDT 24
Peak memory 242304 kb
Host smart-8edc92b2-9389-46e3-843c-e62bf03c9eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517652133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1517652133
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3320214109
Short name T770
Test name
Test status
Simulation time 149583075 ps
CPU time 3.72 seconds
Started Jun 27 07:26:57 PM PDT 24
Finished Jun 27 07:29:46 PM PDT 24
Peak memory 242408 kb
Host smart-6522c9f4-963d-49ec-bf50-a0bfcfe5f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320214109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3320214109
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.777481682
Short name T131
Test name
Test status
Simulation time 1267779822 ps
CPU time 8.86 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:22 PM PDT 24
Peak memory 241820 kb
Host smart-5192a043-aa0c-4195-8602-7cb1d416bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777481682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.777481682
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.215969600
Short name T576
Test name
Test status
Simulation time 199237639 ps
CPU time 4.19 seconds
Started Jun 27 07:25:23 PM PDT 24
Finished Jun 27 07:27:42 PM PDT 24
Peak memory 241884 kb
Host smart-c8916c37-7037-4e59-9a03-7e8268ffa4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215969600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.215969600
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3249743937
Short name T988
Test name
Test status
Simulation time 248189654 ps
CPU time 3.61 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:22 PM PDT 24
Peak memory 242088 kb
Host smart-54751fd5-d12e-4bf0-980f-530ff6b7c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249743937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3249743937
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.3276568756
Short name T1031
Test name
Test status
Simulation time 150008114 ps
CPU time 4.19 seconds
Started Jun 27 07:27:21 PM PDT 24
Finished Jun 27 07:29:53 PM PDT 24
Peak memory 241932 kb
Host smart-1c99cec6-42ad-4f50-9280-380f20782859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276568756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3276568756
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.1090994311
Short name T235
Test name
Test status
Simulation time 113313362 ps
CPU time 3.9 seconds
Started Jun 27 07:24:25 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 241764 kb
Host smart-f93d7f9a-fc47-4cdb-be21-d882fcee6f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090994311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1090994311
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.503662710
Short name T511
Test name
Test status
Simulation time 146650035 ps
CPU time 1.78 seconds
Started Jun 27 07:17:41 PM PDT 24
Finished Jun 27 07:20:11 PM PDT 24
Peak memory 240412 kb
Host smart-557186c4-5736-4ed5-9f12-93f9501d7444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503662710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.503662710
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.920227213
Short name T816
Test name
Test status
Simulation time 159125970 ps
CPU time 3.63 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:19 PM PDT 24
Peak memory 248684 kb
Host smart-d607903c-feb3-4a24-9032-ffdf636fc788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920227213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.920227213
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1489986442
Short name T438
Test name
Test status
Simulation time 610718150 ps
CPU time 18.39 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:20:35 PM PDT 24
Peak memory 241888 kb
Host smart-63a91334-1981-46d5-bd09-c1182ad5cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489986442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1489986442
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.810183815
Short name T1043
Test name
Test status
Simulation time 19366058119 ps
CPU time 26.82 seconds
Started Jun 27 07:17:48 PM PDT 24
Finished Jun 27 07:20:41 PM PDT 24
Peak memory 242464 kb
Host smart-5b224e9a-3964-4bab-be90-62740512c262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810183815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.810183815
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.2865906590
Short name T157
Test name
Test status
Simulation time 94789581 ps
CPU time 3.22 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:20:15 PM PDT 24
Peak memory 241908 kb
Host smart-468d308e-38d0-49f1-a662-2ea3f81d3563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865906590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2865906590
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2835992462
Short name T865
Test name
Test status
Simulation time 1482892767 ps
CPU time 18.5 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:34 PM PDT 24
Peak memory 248776 kb
Host smart-2ba0206a-dd78-4c8d-aa3a-c80a10aa5f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835992462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2835992462
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1032396162
Short name T424
Test name
Test status
Simulation time 257270394 ps
CPU time 3.86 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 241824 kb
Host smart-aaa29d69-d4bd-499d-862a-5ae5afeceab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032396162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1032396162
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1414953847
Short name T417
Test name
Test status
Simulation time 3306261597 ps
CPU time 9.87 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:26 PM PDT 24
Peak memory 242240 kb
Host smart-2e0e5016-3724-432d-ad70-dc48aa0def7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414953847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1414953847
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.433774416
Short name T385
Test name
Test status
Simulation time 551509382 ps
CPU time 9.19 seconds
Started Jun 27 07:17:47 PM PDT 24
Finished Jun 27 07:20:28 PM PDT 24
Peak memory 241956 kb
Host smart-3c213d20-a624-4d06-a681-5831c484e8e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433774416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.433774416
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2367643136
Short name T619
Test name
Test status
Simulation time 552796201 ps
CPU time 12.53 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:28 PM PDT 24
Peak memory 242276 kb
Host smart-98d06035-1552-41ce-ba8d-916fbf15ca47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367643136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2367643136
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.943128406
Short name T27
Test name
Test status
Simulation time 1599711628204 ps
CPU time 4980.06 seconds
Started Jun 27 07:17:46 PM PDT 24
Finished Jun 27 08:43:19 PM PDT 24
Peak memory 536228 kb
Host smart-3f75c46b-1291-43f5-94c5-03dcb8fdceb6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943128406 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.943128406
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2791209924
Short name T208
Test name
Test status
Simulation time 1419431709 ps
CPU time 13.44 seconds
Started Jun 27 07:17:44 PM PDT 24
Finished Jun 27 07:20:30 PM PDT 24
Peak memory 242000 kb
Host smart-c13c4bb7-b333-4139-9bd6-a2676008f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791209924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2791209924
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.3120167976
Short name T686
Test name
Test status
Simulation time 1947488840 ps
CPU time 7.02 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:00 PM PDT 24
Peak memory 242084 kb
Host smart-3eb30113-01bc-4731-a369-22c3c1ca5bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120167976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3120167976
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3767366704
Short name T113
Test name
Test status
Simulation time 185420305 ps
CPU time 4.94 seconds
Started Jun 27 07:25:22 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 242112 kb
Host smart-ff6fc2d3-ea62-456e-9b4a-86df84778b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767366704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3767366704
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3172735439
Short name T428
Test name
Test status
Simulation time 251097063 ps
CPU time 5.69 seconds
Started Jun 27 07:24:49 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 241972 kb
Host smart-ce113769-7616-4600-8601-a366e013e087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172735439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3172735439
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.2657118514
Short name T782
Test name
Test status
Simulation time 2076799865 ps
CPU time 6.29 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:27:01 PM PDT 24
Peak memory 242044 kb
Host smart-aa38a76a-0c89-4902-9ec1-eac57e24a8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657118514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2657118514
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.1357608344
Short name T217
Test name
Test status
Simulation time 293582652 ps
CPU time 16.52 seconds
Started Jun 27 07:24:40 PM PDT 24
Finished Jun 27 07:27:11 PM PDT 24
Peak memory 242192 kb
Host smart-c3c69ee1-926b-4de9-b80e-2eb178658ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357608344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1357608344
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2772809959
Short name T655
Test name
Test status
Simulation time 126333267 ps
CPU time 3.3 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:27:09 PM PDT 24
Peak memory 242088 kb
Host smart-4c5f78a8-3ce3-4888-85d8-0f02bafab639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772809959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2772809959
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2663602785
Short name T1061
Test name
Test status
Simulation time 1996758810 ps
CPU time 14.4 seconds
Started Jun 27 07:28:37 PM PDT 24
Finished Jun 27 07:30:44 PM PDT 24
Peak memory 242196 kb
Host smart-a6f31193-9369-41cf-99a7-98ae9e821e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663602785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2663602785
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3295297545
Short name T984
Test name
Test status
Simulation time 146369001 ps
CPU time 4.32 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:26:58 PM PDT 24
Peak memory 242020 kb
Host smart-865ae84e-1389-4483-9525-c4440d89ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295297545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3295297545
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.3287131140
Short name T308
Test name
Test status
Simulation time 338453299 ps
CPU time 8.74 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:27:04 PM PDT 24
Peak memory 241956 kb
Host smart-fb71fcc7-ae8e-40ee-8330-14d3d3f01048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287131140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3287131140
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2789202931
Short name T93
Test name
Test status
Simulation time 528274299 ps
CPU time 3.8 seconds
Started Jun 27 07:24:58 PM PDT 24
Finished Jun 27 07:27:07 PM PDT 24
Peak memory 242392 kb
Host smart-7c2cf7d9-cac7-4530-a0f7-0025b59a7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789202931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2789202931
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3385951893
Short name T87
Test name
Test status
Simulation time 242296411 ps
CPU time 6.05 seconds
Started Jun 27 07:24:42 PM PDT 24
Finished Jun 27 07:27:12 PM PDT 24
Peak memory 241768 kb
Host smart-5ecbd12e-dd22-4140-bc28-bea59b45ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385951893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3385951893
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.4119125668
Short name T703
Test name
Test status
Simulation time 195008363 ps
CPU time 3.39 seconds
Started Jun 27 07:24:58 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 242076 kb
Host smart-9d2849f1-128e-435e-a013-f0fe8d360450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119125668 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4119125668
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1666756438
Short name T194
Test name
Test status
Simulation time 5193808580 ps
CPU time 9.09 seconds
Started Jun 27 07:25:54 PM PDT 24
Finished Jun 27 07:28:45 PM PDT 24
Peak memory 242344 kb
Host smart-217143b9-cf9a-4425-a858-300e54683970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666756438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1666756438
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.151237582
Short name T423
Test name
Test status
Simulation time 171578353 ps
CPU time 1.67 seconds
Started Jun 27 07:17:59 PM PDT 24
Finished Jun 27 07:20:45 PM PDT 24
Peak memory 240064 kb
Host smart-d55ab6a7-fb39-4f24-aaa9-5feecac4b12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151237582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.151237582
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.59231648
Short name T41
Test name
Test status
Simulation time 4073555657 ps
CPU time 24.9 seconds
Started Jun 27 07:17:45 PM PDT 24
Finished Jun 27 07:20:37 PM PDT 24
Peak memory 242472 kb
Host smart-2a00942d-ff0b-44e3-93db-0841858ee31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59231648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.59231648
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.794362741
Short name T455
Test name
Test status
Simulation time 4414171017 ps
CPU time 34.11 seconds
Started Jun 27 07:17:44 PM PDT 24
Finished Jun 27 07:20:50 PM PDT 24
Peak memory 249276 kb
Host smart-3536b422-8329-4292-8029-779503111a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794362741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.794362741
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2758853554
Short name T153
Test name
Test status
Simulation time 442051600 ps
CPU time 5 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:21 PM PDT 24
Peak memory 242244 kb
Host smart-f78d4f6d-d9db-4cb8-a08c-fccbb941b590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758853554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2758853554
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.540019335
Short name T1038
Test name
Test status
Simulation time 230533670 ps
CPU time 4.47 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 241932 kb
Host smart-54a85b33-ba04-40fc-ad5b-9d4a3033e1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540019335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.540019335
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.889587757
Short name T904
Test name
Test status
Simulation time 2277022430 ps
CPU time 18.52 seconds
Started Jun 27 07:17:48 PM PDT 24
Finished Jun 27 07:20:32 PM PDT 24
Peak memory 242320 kb
Host smart-67815b0e-afc4-4bca-a9fb-80802ef06a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889587757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.889587757
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.2736892225
Short name T717
Test name
Test status
Simulation time 1672391065 ps
CPU time 37.35 seconds
Started Jun 27 07:17:46 PM PDT 24
Finished Jun 27 07:20:56 PM PDT 24
Peak memory 242268 kb
Host smart-2b1025af-24fd-4437-bd93-d79eed81252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736892225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2736892225
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1981281995
Short name T682
Test name
Test status
Simulation time 500522678 ps
CPU time 14.36 seconds
Started Jun 27 07:17:44 PM PDT 24
Finished Jun 27 07:20:31 PM PDT 24
Peak memory 242340 kb
Host smart-9c6d2d27-656a-406f-a7eb-df398e6c4506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981281995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1981281995
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1827159804
Short name T684
Test name
Test status
Simulation time 669677224 ps
CPU time 15.97 seconds
Started Jun 27 07:17:43 PM PDT 24
Finished Jun 27 07:20:32 PM PDT 24
Peak memory 242236 kb
Host smart-d68a235b-b91f-4c29-85d8-8b635d914e27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827159804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1827159804
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.3865020603
Short name T967
Test name
Test status
Simulation time 162892184 ps
CPU time 4.92 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 242208 kb
Host smart-69b91b31-2ce4-4ab3-b60f-ed5104965dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3865020603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3865020603
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.1454858974
Short name T876
Test name
Test status
Simulation time 283622887 ps
CPU time 3.3 seconds
Started Jun 27 07:18:48 PM PDT 24
Finished Jun 27 07:21:26 PM PDT 24
Peak memory 241876 kb
Host smart-4ee2c928-76c0-4f5d-97c3-57b753c05063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454858974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.1454858974
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3481539260
Short name T787
Test name
Test status
Simulation time 3303344688 ps
CPU time 15.27 seconds
Started Jun 27 07:17:58 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 241576 kb
Host smart-0bf9cac1-4fd2-4789-bf7f-9a154c6d5cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481539260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3481539260
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.4167411466
Short name T580
Test name
Test status
Simulation time 3971615401 ps
CPU time 10.01 seconds
Started Jun 27 07:17:55 PM PDT 24
Finished Jun 27 07:20:56 PM PDT 24
Peak memory 242356 kb
Host smart-58bde469-ceac-4d57-8cab-2e0c35ca3efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167411466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.4167411466
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.1124282563
Short name T849
Test name
Test status
Simulation time 147541742 ps
CPU time 3.66 seconds
Started Jun 27 07:24:55 PM PDT 24
Finished Jun 27 07:27:12 PM PDT 24
Peak memory 242500 kb
Host smart-c00f38af-7986-40a9-9ce2-aac8dc065746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124282563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.1124282563
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.1524618804
Short name T264
Test name
Test status
Simulation time 235131713 ps
CPU time 5.27 seconds
Started Jun 27 07:25:40 PM PDT 24
Finished Jun 27 07:27:58 PM PDT 24
Peak memory 241960 kb
Host smart-ef134939-6ce6-40f5-a220-604cd5e14374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524618804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.1524618804
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2912407116
Short name T127
Test name
Test status
Simulation time 474491293 ps
CPU time 3.72 seconds
Started Jun 27 07:27:04 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242228 kb
Host smart-09767e38-6f3a-40aa-9ca5-acc1282f2660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912407116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2912407116
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3617554480
Short name T903
Test name
Test status
Simulation time 634879683 ps
CPU time 9.47 seconds
Started Jun 27 07:24:43 PM PDT 24
Finished Jun 27 07:27:03 PM PDT 24
Peak memory 241356 kb
Host smart-15320685-4500-429e-9efb-a5452aad8374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617554480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3617554480
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.520435502
Short name T883
Test name
Test status
Simulation time 93514985 ps
CPU time 3.42 seconds
Started Jun 27 07:24:43 PM PDT 24
Finished Jun 27 07:26:59 PM PDT 24
Peak memory 241332 kb
Host smart-2b491a46-68af-427d-ba0a-85e7239bd1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520435502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.520435502
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.741039462
Short name T978
Test name
Test status
Simulation time 1303264754 ps
CPU time 8.85 seconds
Started Jun 27 07:24:40 PM PDT 24
Finished Jun 27 07:27:03 PM PDT 24
Peak memory 241968 kb
Host smart-740bcd46-9d0a-49c9-ad01-83208f08d455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741039462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.741039462
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1940856252
Short name T818
Test name
Test status
Simulation time 2478200510 ps
CPU time 8.03 seconds
Started Jun 27 07:24:44 PM PDT 24
Finished Jun 27 07:27:27 PM PDT 24
Peak memory 242428 kb
Host smart-87a5a154-a82a-4b98-ab61-6d97aa5054e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940856252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1940856252
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.648906155
Short name T213
Test name
Test status
Simulation time 3476040660 ps
CPU time 12.93 seconds
Started Jun 27 07:25:52 PM PDT 24
Finished Jun 27 07:27:57 PM PDT 24
Peak memory 241840 kb
Host smart-e1bebdf5-a5ed-4a71-9a49-4448fe5cd728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648906155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.648906155
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.1026595183
Short name T520
Test name
Test status
Simulation time 249084789 ps
CPU time 4.06 seconds
Started Jun 27 07:25:01 PM PDT 24
Finished Jun 27 07:27:21 PM PDT 24
Peak memory 241964 kb
Host smart-ccf42dfd-ba51-4d7e-8bed-a1e731ea3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026595183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1026595183
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.977435968
Short name T86
Test name
Test status
Simulation time 5809830090 ps
CPU time 12.45 seconds
Started Jun 27 07:24:48 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 241932 kb
Host smart-a9841885-b117-4363-b4e4-07d18a5c70c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977435968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.977435968
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.656010150
Short name T215
Test name
Test status
Simulation time 209379258 ps
CPU time 4.17 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:27:55 PM PDT 24
Peak memory 242208 kb
Host smart-a2109a22-6420-4ad4-8fc4-ffda033e9b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656010150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.656010150
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.875955104
Short name T558
Test name
Test status
Simulation time 460701398 ps
CPU time 5.98 seconds
Started Jun 27 07:24:54 PM PDT 24
Finished Jun 27 07:27:14 PM PDT 24
Peak memory 242256 kb
Host smart-5bd1d852-b070-43e4-99b0-3c147acfbe3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875955104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.875955104
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.667483725
Short name T701
Test name
Test status
Simulation time 414268849 ps
CPU time 3.68 seconds
Started Jun 27 07:24:53 PM PDT 24
Finished Jun 27 07:27:22 PM PDT 24
Peak memory 242320 kb
Host smart-16cf8512-6d25-4979-8175-13072b6df238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667483725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.667483725
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.937163853
Short name T12
Test name
Test status
Simulation time 569445455 ps
CPU time 7.12 seconds
Started Jun 27 07:24:54 PM PDT 24
Finished Jun 27 07:27:14 PM PDT 24
Peak memory 241776 kb
Host smart-ace4b989-b06a-4f95-b68e-cde9e8e69ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937163853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.937163853
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.3557407566
Short name T510
Test name
Test status
Simulation time 236763242 ps
CPU time 3.49 seconds
Started Jun 27 07:24:54 PM PDT 24
Finished Jun 27 07:27:11 PM PDT 24
Peak memory 241964 kb
Host smart-9ed694e5-ed86-413d-9e92-d8fe1724a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557407566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3557407566
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.3401485191
Short name T220
Test name
Test status
Simulation time 149318238 ps
CPU time 5.96 seconds
Started Jun 27 07:28:19 PM PDT 24
Finished Jun 27 07:30:48 PM PDT 24
Peak memory 241896 kb
Host smart-663c2bf7-cada-489d-b785-874b24f4fd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401485191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.3401485191
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.974133398
Short name T762
Test name
Test status
Simulation time 263200011 ps
CPU time 2.29 seconds
Started Jun 27 07:17:55 PM PDT 24
Finished Jun 27 07:20:19 PM PDT 24
Peak memory 240068 kb
Host smart-6edbf0b6-d0aa-4ada-a92f-3e8e13aefdf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974133398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.974133398
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.2351110351
Short name T748
Test name
Test status
Simulation time 1736031752 ps
CPU time 25.11 seconds
Started Jun 27 07:17:56 PM PDT 24
Finished Jun 27 07:21:26 PM PDT 24
Peak memory 241952 kb
Host smart-09ca5bf6-6b59-4ac5-87a7-f94bfd68dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351110351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2351110351
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.108862802
Short name T626
Test name
Test status
Simulation time 2292943240 ps
CPU time 4.8 seconds
Started Jun 27 07:18:07 PM PDT 24
Finished Jun 27 07:21:06 PM PDT 24
Peak memory 241988 kb
Host smart-4a9ed668-d680-41ed-b2b7-126c503fe86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108862802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.108862802
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.2153110573
Short name T922
Test name
Test status
Simulation time 848341170 ps
CPU time 19.45 seconds
Started Jun 27 07:17:57 PM PDT 24
Finished Jun 27 07:21:21 PM PDT 24
Peak memory 242200 kb
Host smart-e31d7bdf-995d-455c-8f7a-862b7067d9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153110573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2153110573
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.4086322301
Short name T467
Test name
Test status
Simulation time 1094751222 ps
CPU time 12.67 seconds
Started Jun 27 07:17:57 PM PDT 24
Finished Jun 27 07:21:14 PM PDT 24
Peak memory 242356 kb
Host smart-70e5b199-1a7a-4401-89ae-785c02b8d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086322301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.4086322301
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1793466389
Short name T673
Test name
Test status
Simulation time 7774220009 ps
CPU time 20.76 seconds
Started Jun 27 07:17:55 PM PDT 24
Finished Jun 27 07:21:49 PM PDT 24
Peak memory 242312 kb
Host smart-f95537ab-f912-479f-ae9c-ae6873727496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793466389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1793466389
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2809738266
Short name T94
Test name
Test status
Simulation time 254564203 ps
CPU time 5.24 seconds
Started Jun 27 07:18:06 PM PDT 24
Finished Jun 27 07:21:07 PM PDT 24
Peak memory 242160 kb
Host smart-ef64e67c-bdee-4397-b9ab-2b6bf070e047
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809738266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2809738266
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.3570479003
Short name T470
Test name
Test status
Simulation time 669466121 ps
CPU time 6.51 seconds
Started Jun 27 07:18:07 PM PDT 24
Finished Jun 27 07:21:08 PM PDT 24
Peak memory 242064 kb
Host smart-24f5c3c8-4351-4526-b1e0-60415f91dc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570479003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.3570479003
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.353878364
Short name T634
Test name
Test status
Simulation time 12198181907 ps
CPU time 250.96 seconds
Started Jun 27 07:17:55 PM PDT 24
Finished Jun 27 07:26:03 PM PDT 24
Peak memory 250032 kb
Host smart-c39b3620-ba0f-4539-9d89-90ee71343f57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353878364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
353878364
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.1353565143
Short name T999
Test name
Test status
Simulation time 795534113 ps
CPU time 19.35 seconds
Started Jun 27 07:17:56 PM PDT 24
Finished Jun 27 07:21:21 PM PDT 24
Peak memory 242508 kb
Host smart-c936102e-27ef-4671-b96b-60af44714ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353565143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1353565143
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.3045616104
Short name T1009
Test name
Test status
Simulation time 166402042 ps
CPU time 3.96 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:11 PM PDT 24
Peak memory 241784 kb
Host smart-661d70af-0313-4c61-af4b-ac86e125e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045616104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.3045616104
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3444284501
Short name T332
Test name
Test status
Simulation time 234917645 ps
CPU time 5.59 seconds
Started Jun 27 07:25:01 PM PDT 24
Finished Jun 27 07:27:10 PM PDT 24
Peak memory 242252 kb
Host smart-11fe7367-45ca-481d-a242-80167be083a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444284501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3444284501
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.897620336
Short name T654
Test name
Test status
Simulation time 345547304 ps
CPU time 3.62 seconds
Started Jun 27 07:25:08 PM PDT 24
Finished Jun 27 07:27:55 PM PDT 24
Peak memory 241984 kb
Host smart-a51474cd-8ea0-403e-8537-1ddb19aa693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897620336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.897620336
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3013045582
Short name T741
Test name
Test status
Simulation time 266573838 ps
CPU time 15.37 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 241692 kb
Host smart-08ba3b8a-b293-42be-afa2-442ed67b9636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013045582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3013045582
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.217123160
Short name T962
Test name
Test status
Simulation time 277879526 ps
CPU time 3.67 seconds
Started Jun 27 07:25:05 PM PDT 24
Finished Jun 27 07:27:33 PM PDT 24
Peak memory 242480 kb
Host smart-d0ecf4cf-0c1e-4abb-9970-34e33067e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217123160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.217123160
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.3941745311
Short name T67
Test name
Test status
Simulation time 1369585196 ps
CPU time 10.37 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:18 PM PDT 24
Peak memory 241788 kb
Host smart-956aa4ab-8aa5-4369-9c72-4b49e2a2e094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941745311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.3941745311
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.1729342504
Short name T672
Test name
Test status
Simulation time 2626762504 ps
CPU time 4.58 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:34 PM PDT 24
Peak memory 242392 kb
Host smart-04a458ca-50b1-48da-bb9c-dae0af81198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729342504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1729342504
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2651264994
Short name T914
Test name
Test status
Simulation time 519358335 ps
CPU time 5.04 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:24 PM PDT 24
Peak memory 241924 kb
Host smart-e8cbee63-2eee-42e1-9b68-d542e922982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651264994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2651264994
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1299265023
Short name T56
Test name
Test status
Simulation time 1876918099 ps
CPU time 5.27 seconds
Started Jun 27 07:25:03 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242108 kb
Host smart-6884c3e1-f5e8-4dcb-a51c-e2ed0f73810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299265023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1299265023
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.4115994924
Short name T237
Test name
Test status
Simulation time 724464459 ps
CPU time 16.82 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:36 PM PDT 24
Peak memory 241808 kb
Host smart-3d06d97f-539b-48e1-a7bb-548acd639c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115994924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.4115994924
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2281739687
Short name T638
Test name
Test status
Simulation time 235177217 ps
CPU time 3.76 seconds
Started Jun 27 07:25:06 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242180 kb
Host smart-6875d513-1ca1-460a-a331-c036796b1706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281739687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2281739687
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.1076768262
Short name T243
Test name
Test status
Simulation time 195982836 ps
CPU time 3.37 seconds
Started Jun 27 07:25:01 PM PDT 24
Finished Jun 27 07:27:07 PM PDT 24
Peak memory 241884 kb
Host smart-092da332-d13c-405f-80fc-26580ac6b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076768262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1076768262
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.2117912007
Short name T61
Test name
Test status
Simulation time 123247768 ps
CPU time 4.52 seconds
Started Jun 27 07:25:01 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 241948 kb
Host smart-0a9976a1-8d8b-476f-8d1e-8244705c4a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117912007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2117912007
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.2813734863
Short name T432
Test name
Test status
Simulation time 637566602 ps
CPU time 16.21 seconds
Started Jun 27 07:25:07 PM PDT 24
Finished Jun 27 07:27:53 PM PDT 24
Peak memory 241956 kb
Host smart-8119535c-1ffd-4178-8da7-2c713c9ff72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813734863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2813734863
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.1202864771
Short name T559
Test name
Test status
Simulation time 615691104 ps
CPU time 4.44 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242488 kb
Host smart-586da299-0a0f-48bc-adba-b2ef974136df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202864771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1202864771
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1557742108
Short name T815
Test name
Test status
Simulation time 285755643 ps
CPU time 2.66 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:10 PM PDT 24
Peak memory 241880 kb
Host smart-ebbfffa5-ba34-4b28-8a3d-884a7cc186eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557742108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1557742108
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.598160582
Short name T63
Test name
Test status
Simulation time 179755493 ps
CPU time 4.51 seconds
Started Jun 27 07:25:03 PM PDT 24
Finished Jun 27 07:27:11 PM PDT 24
Peak memory 242360 kb
Host smart-09fa45ec-950e-4348-b4a9-f12d359bc8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598160582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.598160582
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2722900760
Short name T422
Test name
Test status
Simulation time 588052534 ps
CPU time 7.38 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:26 PM PDT 24
Peak memory 241888 kb
Host smart-aece8816-5b60-495b-9cf0-fbe49640d0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722900760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2722900760
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.1510408769
Short name T160
Test name
Test status
Simulation time 275565990 ps
CPU time 3.49 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:22 PM PDT 24
Peak memory 241876 kb
Host smart-724ae87c-d4b3-42f0-a22d-2f98dccedd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510408769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1510408769
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.595835290
Short name T901
Test name
Test status
Simulation time 157220570 ps
CPU time 2.94 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:22 PM PDT 24
Peak memory 242016 kb
Host smart-205c5666-ab22-4e2d-bcf1-a86cc79596bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595835290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.595835290
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.3877814705
Short name T541
Test name
Test status
Simulation time 74525521 ps
CPU time 1.85 seconds
Started Jun 27 07:17:58 PM PDT 24
Finished Jun 27 07:21:03 PM PDT 24
Peak memory 240244 kb
Host smart-d6d1c20b-62a9-43f4-9df7-5537d5b4aa84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877814705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.3877814705
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.2695977308
Short name T111
Test name
Test status
Simulation time 3052477543 ps
CPU time 32.49 seconds
Started Jun 27 07:18:00 PM PDT 24
Finished Jun 27 07:21:23 PM PDT 24
Peak memory 242460 kb
Host smart-a94ade7e-9ec6-4488-b19a-4c2e675eb261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695977308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2695977308
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.1387728030
Short name T440
Test name
Test status
Simulation time 724453951 ps
CPU time 22.45 seconds
Started Jun 27 07:17:57 PM PDT 24
Finished Jun 27 07:21:24 PM PDT 24
Peak memory 242288 kb
Host smart-95f5c271-3492-444e-99f1-0120600a1860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387728030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1387728030
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.4244260272
Short name T95
Test name
Test status
Simulation time 5123883955 ps
CPU time 15.65 seconds
Started Jun 27 07:18:07 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 242004 kb
Host smart-464b755e-bf2d-4e5a-bce0-23144a2b170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244260272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.4244260272
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3226994825
Short name T667
Test name
Test status
Simulation time 95271036 ps
CPU time 3.55 seconds
Started Jun 27 07:17:57 PM PDT 24
Finished Jun 27 07:21:05 PM PDT 24
Peak memory 242092 kb
Host smart-206207e3-c52d-4ca6-8eeb-0c788a80cbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226994825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3226994825
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.3903396544
Short name T542
Test name
Test status
Simulation time 290065624 ps
CPU time 7.84 seconds
Started Jun 27 07:17:58 PM PDT 24
Finished Jun 27 07:21:10 PM PDT 24
Peak memory 242288 kb
Host smart-8d34156f-a3c3-41d8-a4f1-64109ab872f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903396544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3903396544
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.1539219966
Short name T832
Test name
Test status
Simulation time 6311581294 ps
CPU time 15.71 seconds
Started Jun 27 07:17:57 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 242040 kb
Host smart-be057b76-4f9e-4215-b342-05f780edd3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539219966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1539219966
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.652071321
Short name T708
Test name
Test status
Simulation time 8017969264 ps
CPU time 23.25 seconds
Started Jun 27 07:17:58 PM PDT 24
Finished Jun 27 07:21:25 PM PDT 24
Peak memory 242004 kb
Host smart-42d7879a-2bf6-4cbd-a882-811a0d911ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652071321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.652071321
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2143317897
Short name T513
Test name
Test status
Simulation time 369331465 ps
CPU time 5.15 seconds
Started Jun 27 07:17:55 PM PDT 24
Finished Jun 27 07:21:33 PM PDT 24
Peak memory 247900 kb
Host smart-ac4c6b3f-f456-4a36-be13-5b7164d38c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143317897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2143317897
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.3104418798
Short name T925
Test name
Test status
Simulation time 237254179 ps
CPU time 6.59 seconds
Started Jun 27 07:18:07 PM PDT 24
Finished Jun 27 07:21:08 PM PDT 24
Peak memory 241876 kb
Host smart-b76a7492-c819-4724-ac42-679a7dd8e608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3104418798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3104418798
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3696377636
Short name T273
Test name
Test status
Simulation time 367566767 ps
CPU time 6.88 seconds
Started Jun 27 07:17:56 PM PDT 24
Finished Jun 27 07:20:53 PM PDT 24
Peak memory 242052 kb
Host smart-2b63d428-6741-498c-84c1-ae47e56b4b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696377636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3696377636
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.187140688
Short name T119
Test name
Test status
Simulation time 1374540789 ps
CPU time 44.95 seconds
Started Jun 27 07:17:59 PM PDT 24
Finished Jun 27 07:21:10 PM PDT 24
Peak memory 248740 kb
Host smart-4baae920-8284-4f12-b95f-4127cea3a75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187140688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.
187140688
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.4036029390
Short name T752
Test name
Test status
Simulation time 818101505 ps
CPU time 14.9 seconds
Started Jun 27 07:17:56 PM PDT 24
Finished Jun 27 07:20:33 PM PDT 24
Peak memory 242416 kb
Host smart-d32f8c4d-a41c-4be6-b006-251f305e2910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036029390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.4036029390
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2497503373
Short name T304
Test name
Test status
Simulation time 385247604 ps
CPU time 3.35 seconds
Started Jun 27 07:25:18 PM PDT 24
Finished Jun 27 07:27:48 PM PDT 24
Peak memory 241948 kb
Host smart-d46bdb12-33c3-4357-a277-9b50d448ecff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497503373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2497503373
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.329700014
Short name T476
Test name
Test status
Simulation time 557498163 ps
CPU time 7.87 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:26 PM PDT 24
Peak memory 241880 kb
Host smart-dfbc83c9-16b9-4a39-9f9b-b65102b2f41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329700014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.329700014
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3598221231
Short name T480
Test name
Test status
Simulation time 674410237 ps
CPU time 9.68 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:28:41 PM PDT 24
Peak memory 242356 kb
Host smart-ff4d04ea-89be-4d0c-886c-a32c163e88e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598221231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3598221231
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.1250232336
Short name T507
Test name
Test status
Simulation time 460417060 ps
CPU time 4.52 seconds
Started Jun 27 07:27:04 PM PDT 24
Finished Jun 27 07:29:34 PM PDT 24
Peak memory 242160 kb
Host smart-add98a68-a7f6-45ed-92e7-cfbcf5c3ff8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250232336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1250232336
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2394184829
Short name T353
Test name
Test status
Simulation time 4073773851 ps
CPU time 7.83 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:26 PM PDT 24
Peak memory 241936 kb
Host smart-3cca20c1-fe89-473d-859a-e29b11bc6fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394184829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2394184829
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.1431356140
Short name T880
Test name
Test status
Simulation time 284183299 ps
CPU time 3.81 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:28:35 PM PDT 24
Peak memory 241916 kb
Host smart-1678ff13-0f50-4a4d-9c39-de4bdca216f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431356140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.1431356140
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3418171076
Short name T272
Test name
Test status
Simulation time 12066266249 ps
CPU time 32.44 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:52 PM PDT 24
Peak memory 241984 kb
Host smart-239d2640-1c5f-4df4-815e-c46449596b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418171076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3418171076
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.3055263638
Short name T70
Test name
Test status
Simulation time 2296739206 ps
CPU time 4.83 seconds
Started Jun 27 07:27:00 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242112 kb
Host smart-ab6dd16f-8fef-4f57-b80d-e6b10ec3e07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055263638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3055263638
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.1930972031
Short name T221
Test name
Test status
Simulation time 522767064 ps
CPU time 6.02 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:27:25 PM PDT 24
Peak memory 241872 kb
Host smart-cff1adc2-f56b-4ca1-802c-2352a2298aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930972031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1930972031
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.967478220
Short name T294
Test name
Test status
Simulation time 1407768667 ps
CPU time 3.93 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:33 PM PDT 24
Peak memory 242152 kb
Host smart-0f335067-b204-45c1-be7f-a3985974f097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967478220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.967478220
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.4064474968
Short name T760
Test name
Test status
Simulation time 181948622 ps
CPU time 3.77 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242096 kb
Host smart-0c7b7c63-af97-4ae3-a534-323a17bbf057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064474968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.4064474968
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.1790216102
Short name T530
Test name
Test status
Simulation time 425659872 ps
CPU time 11.8 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 241956 kb
Host smart-c981437b-2350-45d6-9cff-2d1a6032d16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790216102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.1790216102
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.1172316576
Short name T519
Test name
Test status
Simulation time 100430988 ps
CPU time 3.41 seconds
Started Jun 27 07:26:50 PM PDT 24
Finished Jun 27 07:29:52 PM PDT 24
Peak memory 242088 kb
Host smart-eac25388-b0af-499e-abb6-ef987804dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172316576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1172316576
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1011240644
Short name T603
Test name
Test status
Simulation time 160012439 ps
CPU time 3.34 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:27:41 PM PDT 24
Peak memory 241840 kb
Host smart-5375d872-7544-4c34-af00-3e8611c89664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011240644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1011240644
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.3397841775
Short name T92
Test name
Test status
Simulation time 427913698 ps
CPU time 3.98 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 242532 kb
Host smart-cb49f0da-8747-496f-9239-bf11c6c949a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397841775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.3397841775
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2807365473
Short name T355
Test name
Test status
Simulation time 283425125 ps
CPU time 6.8 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:27:26 PM PDT 24
Peak memory 241932 kb
Host smart-c8632d80-6be0-41ea-a72b-052b8dc9cedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807365473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2807365473
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.680252835
Short name T771
Test name
Test status
Simulation time 1863734011 ps
CPU time 5.85 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:25 PM PDT 24
Peak memory 241920 kb
Host smart-49b25f87-fc85-4cae-abf3-161637a4cd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680252835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.680252835
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.4009207459
Short name T324
Test name
Test status
Simulation time 137523354 ps
CPU time 5.93 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:25 PM PDT 24
Peak memory 241860 kb
Host smart-21f2d88f-76ca-4b6e-8986-72dcf1954930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009207459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.4009207459
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2007227445
Short name T488
Test name
Test status
Simulation time 1535899191 ps
CPU time 31.12 seconds
Started Jun 27 07:18:10 PM PDT 24
Finished Jun 27 07:21:15 PM PDT 24
Peak memory 241988 kb
Host smart-b1ff22d5-4b60-47d3-8257-5b122e12d948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007227445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2007227445
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.756533277
Short name T401
Test name
Test status
Simulation time 5336693383 ps
CPU time 19.33 seconds
Started Jun 27 07:18:11 PM PDT 24
Finished Jun 27 07:21:27 PM PDT 24
Peak memory 242564 kb
Host smart-91f5eb22-2357-42d7-b3fc-318e1a562f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756533277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.756533277
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.4047694151
Short name T1048
Test name
Test status
Simulation time 98700241 ps
CPU time 3.48 seconds
Started Jun 27 07:18:08 PM PDT 24
Finished Jun 27 07:21:05 PM PDT 24
Peak memory 241928 kb
Host smart-fa648f83-39d3-45ad-9089-29c92300259e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047694151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.4047694151
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3864235560
Short name T976
Test name
Test status
Simulation time 2396471996 ps
CPU time 23.68 seconds
Started Jun 27 07:18:10 PM PDT 24
Finished Jun 27 07:21:07 PM PDT 24
Peak memory 245220 kb
Host smart-d386ed16-ddcc-4156-9b5e-e712b2ae7bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864235560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3864235560
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.2633000622
Short name T791
Test name
Test status
Simulation time 258763602 ps
CPU time 8.8 seconds
Started Jun 27 07:18:10 PM PDT 24
Finished Jun 27 07:21:16 PM PDT 24
Peak memory 242144 kb
Host smart-baed52ed-77c6-428e-8f30-1fbfa446dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633000622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2633000622
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.2954188170
Short name T905
Test name
Test status
Simulation time 169590347 ps
CPU time 8.65 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:20:52 PM PDT 24
Peak memory 241880 kb
Host smart-4fb885b6-8750-4939-8847-0b917abe3895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954188170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2954188170
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3336083794
Short name T918
Test name
Test status
Simulation time 5579678751 ps
CPU time 17.93 seconds
Started Jun 27 07:18:07 PM PDT 24
Finished Jun 27 07:21:19 PM PDT 24
Peak memory 242076 kb
Host smart-6e0a7b26-796c-4dd4-842f-4684fccd39c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336083794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3336083794
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.1448622997
Short name T725
Test name
Test status
Simulation time 367123408 ps
CPU time 3.48 seconds
Started Jun 27 07:17:59 PM PDT 24
Finished Jun 27 07:20:47 PM PDT 24
Peak memory 241904 kb
Host smart-a6ecf518-c1ea-4f9d-b941-382320e402cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448622997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1448622997
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.882667071
Short name T592
Test name
Test status
Simulation time 2697644753 ps
CPU time 56.51 seconds
Started Jun 27 07:18:12 PM PDT 24
Finished Jun 27 07:23:06 PM PDT 24
Peak memory 244432 kb
Host smart-f2c35c72-7e95-4092-b6a4-cb221ef43c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882667071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.
882667071
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.2014987851
Short name T1013
Test name
Test status
Simulation time 506636606 ps
CPU time 11.53 seconds
Started Jun 27 07:18:10 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 242356 kb
Host smart-302335a9-7f1c-40b6-bc7b-1912658522b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014987851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2014987851
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.76775483
Short name T1060
Test name
Test status
Simulation time 102059570 ps
CPU time 3.49 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:22 PM PDT 24
Peak memory 242376 kb
Host smart-71465fca-a00a-45e7-825c-3ae60f17b864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76775483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.76775483
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3515170610
Short name T858
Test name
Test status
Simulation time 340041265 ps
CPU time 9.71 seconds
Started Jun 27 07:25:23 PM PDT 24
Finished Jun 27 07:27:47 PM PDT 24
Peak memory 242208 kb
Host smart-ff09f138-aa40-4561-8599-07ade6ee14cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515170610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3515170610
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3112176330
Short name T640
Test name
Test status
Simulation time 101654447 ps
CPU time 3.15 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:22 PM PDT 24
Peak memory 241916 kb
Host smart-860ac07c-9d6e-4c3f-b06f-845700b3fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112176330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3112176330
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2625393215
Short name T796
Test name
Test status
Simulation time 189921963 ps
CPU time 7.78 seconds
Started Jun 27 07:26:36 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 241876 kb
Host smart-fcabd2a1-80e8-4a21-997d-d3dd7129f90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625393215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2625393215
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.3443281400
Short name T144
Test name
Test status
Simulation time 416025827 ps
CPU time 4.6 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:42 PM PDT 24
Peak memory 242360 kb
Host smart-2e4a407f-5ba8-40a3-a8d1-171a6aa8a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443281400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3443281400
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2930759490
Short name T860
Test name
Test status
Simulation time 1315777674 ps
CPU time 7.68 seconds
Started Jun 27 07:25:23 PM PDT 24
Finished Jun 27 07:27:52 PM PDT 24
Peak memory 242288 kb
Host smart-7a97c1bf-0cf5-4cca-8e6d-e60fe84f88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930759490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2930759490
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2111694073
Short name T743
Test name
Test status
Simulation time 212818236 ps
CPU time 5.22 seconds
Started Jun 27 07:25:19 PM PDT 24
Finished Jun 27 07:27:58 PM PDT 24
Peak memory 242104 kb
Host smart-364f57be-f290-494a-ac27-5a6253525c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111694073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2111694073
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.3677563562
Short name T590
Test name
Test status
Simulation time 6088760543 ps
CPU time 11.42 seconds
Started Jun 27 07:25:17 PM PDT 24
Finished Jun 27 07:27:31 PM PDT 24
Peak memory 241928 kb
Host smart-e8f03fab-1a81-4801-b5ff-7d7fc35a332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677563562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3677563562
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.4029180956
Short name T133
Test name
Test status
Simulation time 458409482 ps
CPU time 4.63 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:24 PM PDT 24
Peak memory 242408 kb
Host smart-94fac089-4c34-4b37-9488-b3867adc66c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029180956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.4029180956
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.2583914414
Short name T354
Test name
Test status
Simulation time 262609237 ps
CPU time 13.61 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 241924 kb
Host smart-76afa765-e966-4e4c-9681-ebed008baf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583914414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.2583914414
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1853367864
Short name T191
Test name
Test status
Simulation time 486112117 ps
CPU time 4.21 seconds
Started Jun 27 07:25:16 PM PDT 24
Finished Jun 27 07:27:23 PM PDT 24
Peak memory 241880 kb
Host smart-59190de5-4200-4f32-b9fa-43c1bdfdb63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853367864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1853367864
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.705458971
Short name T814
Test name
Test status
Simulation time 903314576 ps
CPU time 11.59 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:30 PM PDT 24
Peak memory 241816 kb
Host smart-99419e32-dcf2-4674-bf6d-784fddd1180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705458971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.705458971
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1892937234
Short name T948
Test name
Test status
Simulation time 261219959 ps
CPU time 4.06 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 241844 kb
Host smart-b23f409d-92c1-4ac2-b7d7-d02c0d91840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892937234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1892937234
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.1847049120
Short name T972
Test name
Test status
Simulation time 150938936 ps
CPU time 3.83 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:27:48 PM PDT 24
Peak memory 242208 kb
Host smart-5057e238-aa5e-43d7-b58f-09c89188c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847049120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.1847049120
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3066544709
Short name T475
Test name
Test status
Simulation time 252238745 ps
CPU time 6.67 seconds
Started Jun 27 07:25:29 PM PDT 24
Finished Jun 27 07:27:43 PM PDT 24
Peak memory 242240 kb
Host smart-dc69378b-df2f-492c-bb36-b230856afd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066544709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3066544709
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.2699272452
Short name T609
Test name
Test status
Simulation time 614843715 ps
CPU time 5.06 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:59 PM PDT 24
Peak memory 242024 kb
Host smart-c736d102-3a1f-434a-9b7f-60625ea57204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699272452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.2699272452
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.465837904
Short name T565
Test name
Test status
Simulation time 376198826 ps
CPU time 9.79 seconds
Started Jun 27 07:25:31 PM PDT 24
Finished Jun 27 07:27:54 PM PDT 24
Peak memory 241868 kb
Host smart-1f94d0a1-a650-4a27-82d3-15739be815f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465837904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.465837904
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.2105871930
Short name T614
Test name
Test status
Simulation time 136791703 ps
CPU time 3.79 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:23 PM PDT 24
Peak memory 246924 kb
Host smart-0c4ff9bf-9468-4deb-8f2f-c9bb7e20b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105871930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.2105871930
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3055564735
Short name T921
Test name
Test status
Simulation time 115600001 ps
CPU time 1.9 seconds
Started Jun 27 07:18:23 PM PDT 24
Finished Jun 27 07:20:52 PM PDT 24
Peak memory 240284 kb
Host smart-b0dcae4d-5177-4ed9-9982-2f521af77698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055564735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3055564735
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.2276819921
Short name T47
Test name
Test status
Simulation time 9487744835 ps
CPU time 25.88 seconds
Started Jun 27 07:18:14 PM PDT 24
Finished Jun 27 07:21:56 PM PDT 24
Peak memory 248816 kb
Host smart-00babff4-f6eb-49a3-9f94-eb12471796c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276819921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2276819921
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.802758525
Short name T180
Test name
Test status
Simulation time 3075140882 ps
CPU time 10.87 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 242480 kb
Host smart-1bf1fae2-1a37-4c82-b1cb-69bd1c93185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802758525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.802758525
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.2431775377
Short name T100
Test name
Test status
Simulation time 12493007711 ps
CPU time 23.23 seconds
Started Jun 27 07:18:11 PM PDT 24
Finished Jun 27 07:21:22 PM PDT 24
Peak memory 248808 kb
Host smart-1fe644ad-9efe-4d40-9f94-2df5d7720c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431775377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2431775377
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1652292954
Short name T856
Test name
Test status
Simulation time 2292908926 ps
CPU time 6.97 seconds
Started Jun 27 07:18:10 PM PDT 24
Finished Jun 27 07:20:51 PM PDT 24
Peak memory 241988 kb
Host smart-e8b20c88-5c04-41aa-a4d0-230e900163e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652292954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1652292954
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.2636406258
Short name T367
Test name
Test status
Simulation time 1730998042 ps
CPU time 36.43 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:21:20 PM PDT 24
Peak memory 245100 kb
Host smart-7f0b8046-7901-4dc9-be7e-04fc5ed27328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636406258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.2636406258
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.497775135
Short name T954
Test name
Test status
Simulation time 1603288243 ps
CPU time 15.43 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:20:59 PM PDT 24
Peak memory 242392 kb
Host smart-fd251d49-2679-4e05-bc35-03244e00f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497775135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.497775135
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.363861242
Short name T152
Test name
Test status
Simulation time 336318388 ps
CPU time 5.35 seconds
Started Jun 27 07:18:14 PM PDT 24
Finished Jun 27 07:20:56 PM PDT 24
Peak memory 241956 kb
Host smart-283feddc-4b10-42b4-b4c9-7e8c1487063d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363861242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.363861242
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.1685447239
Short name T775
Test name
Test status
Simulation time 3854499400 ps
CPU time 86.26 seconds
Started Jun 27 07:18:09 PM PDT 24
Finished Jun 27 07:22:10 PM PDT 24
Peak memory 248836 kb
Host smart-c3832b14-2ce7-4fec-824c-b6d11ba75d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685447239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.1685447239
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.4143233928
Short name T336
Test name
Test status
Simulation time 456832737384 ps
CPU time 817.61 seconds
Started Jun 27 07:18:13 PM PDT 24
Finished Jun 27 07:36:43 PM PDT 24
Peak memory 365440 kb
Host smart-229ebb53-2fe3-43ed-89ae-6baab9956f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143233928 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.4143233928
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.83263329
Short name T784
Test name
Test status
Simulation time 1703130413 ps
CPU time 27.73 seconds
Started Jun 27 07:18:12 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 242444 kb
Host smart-a57c0062-00da-470d-93c2-45d6143e921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83263329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.83263329
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2022564657
Short name T388
Test name
Test status
Simulation time 535341655 ps
CPU time 12.8 seconds
Started Jun 27 07:25:32 PM PDT 24
Finished Jun 27 07:27:51 PM PDT 24
Peak memory 241760 kb
Host smart-9d66d993-112e-458b-8200-3ffe2cc19bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022564657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2022564657
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.3493035085
Short name T869
Test name
Test status
Simulation time 506547276 ps
CPU time 3.25 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:27:41 PM PDT 24
Peak memory 242140 kb
Host smart-8d1ed9cd-efb4-4e65-be37-4a8b59cddc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493035085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3493035085
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.851851030
Short name T389
Test name
Test status
Simulation time 9815843639 ps
CPU time 17.5 seconds
Started Jun 27 07:25:46 PM PDT 24
Finished Jun 27 07:28:10 PM PDT 24
Peak memory 241964 kb
Host smart-8b726491-c1b3-4a40-8e55-98b34ada570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851851030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.851851030
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.34225844
Short name T1051
Test name
Test status
Simulation time 164984966 ps
CPU time 4.2 seconds
Started Jun 27 07:27:11 PM PDT 24
Finished Jun 27 07:29:13 PM PDT 24
Peak memory 242128 kb
Host smart-0e440820-3d7f-4758-af30-faefbe476365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34225844 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.34225844
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.2830949197
Short name T593
Test name
Test status
Simulation time 460299768 ps
CPU time 12.19 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:27:50 PM PDT 24
Peak memory 241672 kb
Host smart-da2c9e3c-fd50-4e4f-82ca-73af3c4af836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830949197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2830949197
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2368782807
Short name T732
Test name
Test status
Simulation time 233583745 ps
CPU time 4.23 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 241920 kb
Host smart-f846237c-99f9-4ce1-ab85-3fcb7bd3fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368782807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2368782807
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.2566797643
Short name T694
Test name
Test status
Simulation time 506273393 ps
CPU time 11.72 seconds
Started Jun 27 07:25:34 PM PDT 24
Finished Jun 27 07:28:48 PM PDT 24
Peak memory 241728 kb
Host smart-ef5a41ac-9de7-40df-b930-d7c888d3a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566797643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2566797643
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.1234503532
Short name T679
Test name
Test status
Simulation time 139092408 ps
CPU time 4.13 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 242184 kb
Host smart-f663eed5-6ebe-4fe8-8dac-9b1e61201eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234503532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.1234503532
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2020495660
Short name T505
Test name
Test status
Simulation time 188957770 ps
CPU time 4.19 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:39 PM PDT 24
Peak memory 242388 kb
Host smart-f31e6a8f-6482-45a8-9d58-a55753c21960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020495660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2020495660
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.1401715920
Short name T443
Test name
Test status
Simulation time 144832961 ps
CPU time 5.2 seconds
Started Jun 27 07:26:47 PM PDT 24
Finished Jun 27 07:28:58 PM PDT 24
Peak memory 241824 kb
Host smart-74dd7872-c28b-4d2b-a721-6cf87b17bd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401715920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1401715920
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.862448545
Short name T212
Test name
Test status
Simulation time 6248980458 ps
CPU time 10.65 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:43 PM PDT 24
Peak memory 242408 kb
Host smart-89f4912c-23f8-4f4d-947b-12ef6d202d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862448545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.862448545
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.885396677
Short name T518
Test name
Test status
Simulation time 122682114 ps
CPU time 4.04 seconds
Started Jun 27 07:25:46 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 242052 kb
Host smart-f1732cee-6943-42af-84eb-3c84a96defed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885396677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.885396677
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.556799701
Short name T936
Test name
Test status
Simulation time 612931017 ps
CPU time 7.7 seconds
Started Jun 27 07:27:12 PM PDT 24
Finished Jun 27 07:29:38 PM PDT 24
Peak memory 242100 kb
Host smart-0e5da68d-8a67-4ba6-ad98-4b4121e77e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556799701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.556799701
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.3477749632
Short name T758
Test name
Test status
Simulation time 2179724446 ps
CPU time 5.05 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:37 PM PDT 24
Peak memory 242172 kb
Host smart-47e46f9f-d3ba-43f6-8894-5bf154ac14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477749632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3477749632
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.225594895
Short name T205
Test name
Test status
Simulation time 12639394235 ps
CPU time 40.02 seconds
Started Jun 27 07:25:31 PM PDT 24
Finished Jun 27 07:28:24 PM PDT 24
Peak memory 242112 kb
Host smart-1df14001-d01a-44c5-959c-8e98654920f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225594895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.225594895
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.2728900164
Short name T1028
Test name
Test status
Simulation time 373250053 ps
CPU time 3.43 seconds
Started Jun 27 07:25:32 PM PDT 24
Finished Jun 27 07:28:23 PM PDT 24
Peak memory 242088 kb
Host smart-c008cbce-9151-406e-85f7-655b030fc010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728900164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.2728900164
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2656972520
Short name T915
Test name
Test status
Simulation time 151089883 ps
CPU time 5.91 seconds
Started Jun 27 07:27:17 PM PDT 24
Finished Jun 27 07:29:26 PM PDT 24
Peak memory 241824 kb
Host smart-7c2fff49-9138-4848-8254-cec5b8b246de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656972520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2656972520
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.4292850004
Short name T40
Test name
Test status
Simulation time 796920007 ps
CPU time 21.41 seconds
Started Jun 27 07:18:25 PM PDT 24
Finished Jun 27 07:23:08 PM PDT 24
Peak memory 242440 kb
Host smart-226db93d-d3f1-4050-b38e-c2fd676b53e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292850004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4292850004
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.4126741530
Short name T441
Test name
Test status
Simulation time 5942003746 ps
CPU time 39.15 seconds
Started Jun 27 07:18:24 PM PDT 24
Finished Jun 27 07:21:30 PM PDT 24
Peak memory 249812 kb
Host smart-26de84ca-c1e6-432b-b93d-a7bd947fceb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126741530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.4126741530
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3883888517
Short name T390
Test name
Test status
Simulation time 1904234675 ps
CPU time 31.87 seconds
Started Jun 27 07:18:25 PM PDT 24
Finished Jun 27 07:22:28 PM PDT 24
Peak memory 242460 kb
Host smart-e3f5ac6b-2efd-4a98-b43f-c5b2f7424204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883888517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3883888517
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.36992489
Short name T1003
Test name
Test status
Simulation time 342253845 ps
CPU time 3.38 seconds
Started Jun 27 07:18:25 PM PDT 24
Finished Jun 27 07:21:52 PM PDT 24
Peak memory 242184 kb
Host smart-6f1fd409-2a9f-4e82-ac41-67f3d5c1a738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36992489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.36992489
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.1105759896
Short name T365
Test name
Test status
Simulation time 22088931705 ps
CPU time 28.43 seconds
Started Jun 27 07:18:23 PM PDT 24
Finished Jun 27 07:21:50 PM PDT 24
Peak memory 248852 kb
Host smart-171031de-2a3b-45ce-a936-d3e96440b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105759896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1105759896
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.764153048
Short name T610
Test name
Test status
Simulation time 915349518 ps
CPU time 17.98 seconds
Started Jun 27 07:18:24 PM PDT 24
Finished Jun 27 07:21:40 PM PDT 24
Peak memory 248752 kb
Host smart-a589d2c7-0844-414c-83b8-f06c2dc91f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=764153048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.764153048
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.3222965624
Short name T448
Test name
Test status
Simulation time 355930150 ps
CPU time 5.8 seconds
Started Jun 27 07:18:24 PM PDT 24
Finished Jun 27 07:21:13 PM PDT 24
Peak memory 241988 kb
Host smart-fe807be9-f8b2-4070-89b7-1f1ac7babe23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222965624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3222965624
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.1750082526
Short name T504
Test name
Test status
Simulation time 203929471 ps
CPU time 5.52 seconds
Started Jun 27 07:18:24 PM PDT 24
Finished Jun 27 07:21:13 PM PDT 24
Peak memory 241956 kb
Host smart-bee56e66-9198-472c-820e-2d616f89babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750082526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.1750082526
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.4098975664
Short name T930
Test name
Test status
Simulation time 8094654071 ps
CPU time 179.48 seconds
Started Jun 27 07:18:23 PM PDT 24
Finished Jun 27 07:25:23 PM PDT 24
Peak memory 248848 kb
Host smart-f18d5d6b-4bfe-413c-8349-a93348e8815c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098975664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.4098975664
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2106175357
Short name T747
Test name
Test status
Simulation time 239051314013 ps
CPU time 720.58 seconds
Started Jun 27 07:18:25 PM PDT 24
Finished Jun 27 07:34:47 PM PDT 24
Peak memory 253656 kb
Host smart-25091c7e-eded-46ee-acbb-12ab63247011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106175357 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2106175357
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3401916895
Short name T261
Test name
Test status
Simulation time 3129476894 ps
CPU time 27.09 seconds
Started Jun 27 07:18:24 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 242112 kb
Host smart-18219f2b-81fb-4441-96b8-cc05402f20e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401916895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3401916895
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.3696543470
Short name T977
Test name
Test status
Simulation time 1423082390 ps
CPU time 3.79 seconds
Started Jun 27 07:27:05 PM PDT 24
Finished Jun 27 07:29:43 PM PDT 24
Peak memory 242064 kb
Host smart-d9c14ac6-e155-4b62-bb15-20bdd5d08002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696543470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.3696543470
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.4131535449
Short name T946
Test name
Test status
Simulation time 1224270150 ps
CPU time 9.41 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:27:39 PM PDT 24
Peak memory 241808 kb
Host smart-f9808ce7-9e56-4cf6-b702-6f1ab73bd9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131535449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.4131535449
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3647208814
Short name T325
Test name
Test status
Simulation time 147177703 ps
CPU time 3.89 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:27:42 PM PDT 24
Peak memory 241980 kb
Host smart-da279bcd-4a5c-4abe-b719-c6b63177aff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647208814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3647208814
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2530038248
Short name T434
Test name
Test status
Simulation time 464290823 ps
CPU time 12.91 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:45 PM PDT 24
Peak memory 241776 kb
Host smart-8e492769-e3e4-4b6f-8a72-f684a90e5859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530038248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2530038248
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1795585142
Short name T58
Test name
Test status
Simulation time 265123831 ps
CPU time 3.53 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:29:23 PM PDT 24
Peak memory 242044 kb
Host smart-df919943-798c-437f-8fa4-674847f415fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795585142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1795585142
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.331671272
Short name T600
Test name
Test status
Simulation time 207902225 ps
CPU time 4.07 seconds
Started Jun 27 07:26:46 PM PDT 24
Finished Jun 27 07:29:14 PM PDT 24
Peak memory 241792 kb
Host smart-5fe246e1-4b5b-47a7-b2db-1b787522edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331671272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.331671272
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.1183443232
Short name T711
Test name
Test status
Simulation time 125971050 ps
CPU time 3.85 seconds
Started Jun 27 07:27:48 PM PDT 24
Finished Jun 27 07:30:20 PM PDT 24
Peak memory 241996 kb
Host smart-b954f40f-a7fa-4bab-8afc-a962a6d67625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183443232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1183443232
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2154944122
Short name T588
Test name
Test status
Simulation time 4461524048 ps
CPU time 11.87 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:29:05 PM PDT 24
Peak memory 241712 kb
Host smart-4746d249-9bf4-4f6c-b606-086bb587758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154944122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2154944122
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2677399349
Short name T412
Test name
Test status
Simulation time 122334495 ps
CPU time 4.98 seconds
Started Jun 27 07:25:31 PM PDT 24
Finished Jun 27 07:27:56 PM PDT 24
Peak memory 242260 kb
Host smart-fc379b9d-2edf-495a-b482-f92b6641596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677399349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2677399349
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.2539294099
Short name T1034
Test name
Test status
Simulation time 273714899 ps
CPU time 10.22 seconds
Started Jun 27 07:26:53 PM PDT 24
Finished Jun 27 07:29:15 PM PDT 24
Peak memory 241936 kb
Host smart-a9b139f2-65ab-425f-bfb2-3db7ebd8458e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539294099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2539294099
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2264675927
Short name T589
Test name
Test status
Simulation time 300064404 ps
CPU time 2.89 seconds
Started Jun 27 07:27:05 PM PDT 24
Finished Jun 27 07:29:33 PM PDT 24
Peak memory 241872 kb
Host smart-85718046-3c7b-4e99-8f49-37cb6f120519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264675927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2264675927
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2572221205
Short name T556
Test name
Test status
Simulation time 295332890 ps
CPU time 6.34 seconds
Started Jun 27 07:25:32 PM PDT 24
Finished Jun 27 07:28:38 PM PDT 24
Peak memory 241952 kb
Host smart-d81a4acb-c09f-465c-a530-486d50e71063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572221205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2572221205
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.2670227106
Short name T788
Test name
Test status
Simulation time 2718972939 ps
CPU time 6.37 seconds
Started Jun 27 07:25:30 PM PDT 24
Finished Jun 27 07:28:41 PM PDT 24
Peak memory 242032 kb
Host smart-1b597846-2af6-478b-ad12-639d8246287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670227106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2670227106
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.1688337108
Short name T855
Test name
Test status
Simulation time 125052713 ps
CPU time 3.25 seconds
Started Jun 27 07:25:32 PM PDT 24
Finished Jun 27 07:28:12 PM PDT 24
Peak memory 242076 kb
Host smart-b85000e8-881c-4611-a927-318ce418798a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688337108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.1688337108
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.1101785150
Short name T578
Test name
Test status
Simulation time 293440360 ps
CPU time 3.23 seconds
Started Jun 27 07:25:32 PM PDT 24
Finished Jun 27 07:27:48 PM PDT 24
Peak memory 242220 kb
Host smart-48fec617-d97f-44d5-a232-d61d7c124d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101785150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.1101785150
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2484103259
Short name T230
Test name
Test status
Simulation time 250156092 ps
CPU time 3.01 seconds
Started Jun 27 07:25:28 PM PDT 24
Finished Jun 27 07:27:54 PM PDT 24
Peak memory 242144 kb
Host smart-6927cf8d-ca60-4c53-883b-b16f1e903ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484103259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2484103259
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.2843815115
Short name T998
Test name
Test status
Simulation time 162136026 ps
CPU time 1.63 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:21:24 PM PDT 24
Peak memory 240156 kb
Host smart-9aa6b850-a4c3-4bbb-aab7-4a7e9978cd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843815115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2843815115
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.3761210918
Short name T746
Test name
Test status
Simulation time 1098870771 ps
CPU time 31.3 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:21:20 PM PDT 24
Peak memory 242860 kb
Host smart-a5a36694-f42b-47f2-b2ad-364a0b808e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761210918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.3761210918
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.632689176
Short name T877
Test name
Test status
Simulation time 693568829 ps
CPU time 20.02 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:21:53 PM PDT 24
Peak memory 242468 kb
Host smart-3dc936c1-6426-49b3-a7cc-115569690ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632689176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.632689176
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.217631573
Short name T852
Test name
Test status
Simulation time 3073028566 ps
CPU time 21.69 seconds
Started Jun 27 07:18:40 PM PDT 24
Finished Jun 27 07:21:11 PM PDT 24
Peak memory 245584 kb
Host smart-3aea94df-29e6-468c-a12a-70c4eb073fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217631573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.217631573
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.4081319271
Short name T398
Test name
Test status
Simulation time 2631237813 ps
CPU time 29.5 seconds
Started Jun 27 07:18:49 PM PDT 24
Finished Jun 27 07:23:16 PM PDT 24
Peak memory 248828 kb
Host smart-a0fc9654-7a28-4a40-9fb7-90dff2d64245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081319271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.4081319271
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.757600462
Short name T177
Test name
Test status
Simulation time 436238941 ps
CPU time 12.19 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:21:45 PM PDT 24
Peak memory 242304 kb
Host smart-c25417e5-586b-41a7-8f8b-15c09b06dd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757600462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.757600462
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.2718007283
Short name T881
Test name
Test status
Simulation time 543924909 ps
CPU time 14.49 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:21 PM PDT 24
Peak memory 248728 kb
Host smart-c738ab33-2981-4232-a69c-dc863eaa8a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2718007283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2718007283
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.852003363
Short name T489
Test name
Test status
Simulation time 118569568 ps
CPU time 5.21 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 241772 kb
Host smart-f564d58a-610d-40c8-8a89-731b8ff8e0eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852003363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.852003363
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.1915339011
Short name T813
Test name
Test status
Simulation time 484238698 ps
CPU time 7.5 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:29 PM PDT 24
Peak memory 242072 kb
Host smart-6424bb9d-8ff3-442d-bbc2-3c61e0e3ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915339011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1915339011
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.169577158
Short name T175
Test name
Test status
Simulation time 6196078608 ps
CPU time 39.38 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:28 PM PDT 24
Peak memory 243256 kb
Host smart-d8d8227a-8941-408c-bc5d-8708934b1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169577158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.169577158
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3849233779
Short name T649
Test name
Test status
Simulation time 621334693 ps
CPU time 15.74 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:27:54 PM PDT 24
Peak memory 242268 kb
Host smart-38bcd7e7-e591-495d-a49a-763c0bdb1438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849233779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3849233779
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3286654812
Short name T463
Test name
Test status
Simulation time 464484156 ps
CPU time 3.75 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 242300 kb
Host smart-4bf769df-ebe4-49c0-befe-950f9c5d3c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286654812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3286654812
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2867121777
Short name T754
Test name
Test status
Simulation time 1155646841 ps
CPU time 7.1 seconds
Started Jun 27 07:26:46 PM PDT 24
Finished Jun 27 07:29:56 PM PDT 24
Peak memory 242060 kb
Host smart-e95d5a0f-ffd9-42aa-8790-dad2b9b0a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867121777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2867121777
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2101590135
Short name T896
Test name
Test status
Simulation time 170408351 ps
CPU time 3.34 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:28:14 PM PDT 24
Peak memory 242180 kb
Host smart-da3f903d-03d8-4932-97b9-da21f516e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101590135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2101590135
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2351549674
Short name T857
Test name
Test status
Simulation time 633979830 ps
CPU time 4.84 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:28:13 PM PDT 24
Peak memory 241920 kb
Host smart-6e16a49c-72c4-42de-8c0e-3ef3ac3f7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351549674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2351549674
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.3168673705
Short name T658
Test name
Test status
Simulation time 923466204 ps
CPU time 7.43 seconds
Started Jun 27 07:28:42 PM PDT 24
Finished Jun 27 07:30:43 PM PDT 24
Peak memory 241688 kb
Host smart-ecc172b1-486e-40ce-a86a-9bc9fa438bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168673705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3168673705
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.3800732307
Short name T289
Test name
Test status
Simulation time 443632181 ps
CPU time 4.07 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:57 PM PDT 24
Peak memory 242008 kb
Host smart-c8bc0e2a-a0e7-47e7-b875-1d6a8991dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800732307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3800732307
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.4106952219
Short name T890
Test name
Test status
Simulation time 241924506 ps
CPU time 5.79 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:59 PM PDT 24
Peak memory 241824 kb
Host smart-686ea759-4e4d-4dac-b608-127aeefc9776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106952219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.4106952219
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.677939059
Short name T662
Test name
Test status
Simulation time 494898516 ps
CPU time 3.64 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:56 PM PDT 24
Peak memory 242484 kb
Host smart-bb5fedb9-075e-43dc-abe7-a46606a93946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677939059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.677939059
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.852104507
Short name T204
Test name
Test status
Simulation time 1194005559 ps
CPU time 11.1 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:28:02 PM PDT 24
Peak memory 241892 kb
Host smart-32227cb8-dfea-4fd5-9460-2b32ce18e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852104507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.852104507
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1339410109
Short name T797
Test name
Test status
Simulation time 221983898 ps
CPU time 3.35 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:52 PM PDT 24
Peak memory 241964 kb
Host smart-35dd1371-3c76-43ab-8750-4f915fbc4b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339410109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1339410109
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.4081520090
Short name T568
Test name
Test status
Simulation time 234021680 ps
CPU time 7.47 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:58 PM PDT 24
Peak memory 241920 kb
Host smart-95b019ed-a399-4d75-8c7d-d6e515bb9c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081520090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.4081520090
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.642579857
Short name T453
Test name
Test status
Simulation time 484876872 ps
CPU time 3.43 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:48 PM PDT 24
Peak memory 241976 kb
Host smart-921f3060-4a10-4a8e-89df-4c3333026f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642579857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.642579857
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.2925325393
Short name T932
Test name
Test status
Simulation time 647492040 ps
CPU time 8.91 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:28:02 PM PDT 24
Peak memory 241996 kb
Host smart-9ab29f2a-29ed-4908-aef6-fa7cf5e9ff30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925325393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.2925325393
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.491525575
Short name T136
Test name
Test status
Simulation time 218186417 ps
CPU time 2.99 seconds
Started Jun 27 07:27:00 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242092 kb
Host smart-18589302-c668-4fb6-ad6c-c4b894d16d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491525575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.491525575
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.339801368
Short name T512
Test name
Test status
Simulation time 172409546 ps
CPU time 3.8 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:28:05 PM PDT 24
Peak memory 242036 kb
Host smart-09925668-6bb5-4012-a5ee-91984dd8f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339801368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.339801368
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.1373989300
Short name T651
Test name
Test status
Simulation time 2553578027 ps
CPU time 6.46 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:59 PM PDT 24
Peak memory 242148 kb
Host smart-619ae1c1-5b25-4b72-92b4-dded2921f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373989300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1373989300
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.3328813742
Short name T885
Test name
Test status
Simulation time 1474110004 ps
CPU time 13.63 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:59 PM PDT 24
Peak memory 241896 kb
Host smart-398b0992-7cad-401a-83df-ed4efd0d2c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328813742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3328813742
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.4115187110
Short name T623
Test name
Test status
Simulation time 914138774 ps
CPU time 3.38 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:45 PM PDT 24
Peak memory 240416 kb
Host smart-207614ba-46e0-4526-98f1-567e6ddb0b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115187110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.4115187110
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.2381915638
Short name T937
Test name
Test status
Simulation time 164536365 ps
CPU time 5.85 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 241936 kb
Host smart-efe61d11-545d-4d01-a2ab-b714ef7a0874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381915638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2381915638
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.1549704307
Short name T509
Test name
Test status
Simulation time 395559211 ps
CPU time 16.66 seconds
Started Jun 27 07:18:48 PM PDT 24
Finished Jun 27 07:21:23 PM PDT 24
Peak memory 241928 kb
Host smart-5d45ad9d-142d-4bdf-9129-d7b2781ffa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549704307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1549704307
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1274339883
Short name T442
Test name
Test status
Simulation time 217779854 ps
CPU time 5.49 seconds
Started Jun 27 07:18:40 PM PDT 24
Finished Jun 27 07:20:55 PM PDT 24
Peak memory 241952 kb
Host smart-5675500f-4aba-4c27-afcb-8297cb9a4008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274339883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1274339883
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.4008080045
Short name T143
Test name
Test status
Simulation time 493079104 ps
CPU time 5.31 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:35 PM PDT 24
Peak memory 242260 kb
Host smart-7d113fb8-9c42-410f-a1c3-bf9cb803e09f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008080045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.4008080045
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.1448879799
Short name T1047
Test name
Test status
Simulation time 1788936442 ps
CPU time 12.82 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:23:55 PM PDT 24
Peak memory 243140 kb
Host smart-08fbf056-f901-4497-a374-15d8a2fde21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448879799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1448879799
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1345212564
Short name T618
Test name
Test status
Simulation time 1591727186 ps
CPU time 5.21 seconds
Started Jun 27 07:18:43 PM PDT 24
Finished Jun 27 07:20:54 PM PDT 24
Peak memory 241728 kb
Host smart-4f5dd85d-1211-4db5-82b9-874901898234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345212564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1345212564
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3326873637
Short name T878
Test name
Test status
Simulation time 141531350 ps
CPU time 4.54 seconds
Started Jun 27 07:18:39 PM PDT 24
Finished Jun 27 07:21:13 PM PDT 24
Peak memory 242024 kb
Host smart-ec9c5a94-3d65-4922-ab50-e6ae28f47fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326873637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3326873637
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.3390407089
Short name T612
Test name
Test status
Simulation time 68497566505 ps
CPU time 245.16 seconds
Started Jun 27 07:18:35 PM PDT 24
Finished Jun 27 07:26:22 PM PDT 24
Peak memory 257040 kb
Host smart-61bbd60f-39fd-49e3-a664-4ccaa475edfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390407089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.3390407089
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.1495815100
Short name T1044
Test name
Test status
Simulation time 12218566403 ps
CPU time 22.78 seconds
Started Jun 27 07:18:41 PM PDT 24
Finished Jun 27 07:21:12 PM PDT 24
Peak memory 243268 kb
Host smart-e25194dc-ddb7-4826-bb96-99c51b3aa4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495815100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1495815100
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.847354454
Short name T677
Test name
Test status
Simulation time 2797744089 ps
CPU time 10.34 seconds
Started Jun 27 07:26:49 PM PDT 24
Finished Jun 27 07:29:05 PM PDT 24
Peak memory 242356 kb
Host smart-37ceca23-5230-4b26-98b6-98a9f272564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847354454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.847354454
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.2743466719
Short name T266
Test name
Test status
Simulation time 161858602 ps
CPU time 4.38 seconds
Started Jun 27 07:26:53 PM PDT 24
Finished Jun 27 07:29:14 PM PDT 24
Peak memory 242072 kb
Host smart-781e2665-1eec-4f2a-84bf-c1721d5c6563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743466719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2743466719
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2036294295
Short name T920
Test name
Test status
Simulation time 5848354040 ps
CPU time 12.72 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:28:04 PM PDT 24
Peak memory 242352 kb
Host smart-f72073a0-d4bd-4c2d-b6b8-44500d1fda05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036294295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2036294295
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2887884417
Short name T534
Test name
Test status
Simulation time 167245993 ps
CPU time 5.32 seconds
Started Jun 27 07:28:30 PM PDT 24
Finished Jun 27 07:30:47 PM PDT 24
Peak memory 242216 kb
Host smart-97b73dae-3878-476b-a0dd-93c82466b1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887884417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2887884417
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.920548290
Short name T120
Test name
Test status
Simulation time 1995485866 ps
CPU time 5.31 seconds
Started Jun 27 07:26:23 PM PDT 24
Finished Jun 27 07:28:42 PM PDT 24
Peak memory 241972 kb
Host smart-d19b27cb-c890-4f9d-ac6f-af6e148be1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920548290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.920548290
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1909150472
Short name T188
Test name
Test status
Simulation time 432596308 ps
CPU time 3.17 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:27:54 PM PDT 24
Peak memory 242168 kb
Host smart-ed4654ba-84f0-4a9e-b309-a476bb583cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909150472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1909150472
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.1125439216
Short name T572
Test name
Test status
Simulation time 547692716 ps
CPU time 6.63 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:27:58 PM PDT 24
Peak memory 242264 kb
Host smart-d9d5813f-121b-42e5-9073-bf7246b27de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125439216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1125439216
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.424862727
Short name T731
Test name
Test status
Simulation time 210410518 ps
CPU time 3.75 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:27:55 PM PDT 24
Peak memory 241792 kb
Host smart-6f05f895-c192-4f9f-9cf1-e49b9deb8d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424862727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.424862727
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.271017236
Short name T340
Test name
Test status
Simulation time 789385167 ps
CPU time 6.65 seconds
Started Jun 27 07:26:15 PM PDT 24
Finished Jun 27 07:28:38 PM PDT 24
Peak memory 242360 kb
Host smart-bcc2f93f-e5c6-40b8-9f65-66d71cdc23c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271017236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.271017236
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.571189694
Short name T636
Test name
Test status
Simulation time 330876604 ps
CPU time 3.56 seconds
Started Jun 27 07:28:50 PM PDT 24
Finished Jun 27 07:30:54 PM PDT 24
Peak memory 242052 kb
Host smart-836dbbaf-673e-4641-97ea-dab1b52d0cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571189694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.571189694
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.3937738345
Short name T539
Test name
Test status
Simulation time 843139764 ps
CPU time 19.74 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:28:11 PM PDT 24
Peak memory 241876 kb
Host smart-ed22d70b-6cdf-4322-be3a-08611eb678fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937738345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.3937738345
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.881230503
Short name T446
Test name
Test status
Simulation time 175238947 ps
CPU time 4.68 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242052 kb
Host smart-f066522a-89bb-42c6-b125-72f412ef2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881230503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.881230503
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.3559228815
Short name T749
Test name
Test status
Simulation time 110704774 ps
CPU time 4.81 seconds
Started Jun 27 07:26:15 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 241836 kb
Host smart-00a51bac-f16a-465f-9e4d-775c6ef869e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559228815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3559228815
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3961206226
Short name T161
Test name
Test status
Simulation time 504717815 ps
CPU time 5.02 seconds
Started Jun 27 07:25:57 PM PDT 24
Finished Jun 27 07:27:56 PM PDT 24
Peak memory 242080 kb
Host smart-a3efd765-751a-4595-97b6-0bc4910ed17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961206226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3961206226
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1066381490
Short name T425
Test name
Test status
Simulation time 6098604692 ps
CPU time 13.21 seconds
Started Jun 27 07:25:57 PM PDT 24
Finished Jun 27 07:28:05 PM PDT 24
Peak memory 242336 kb
Host smart-6c99c948-910e-429d-bf70-836bcee628ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066381490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1066381490
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.881128307
Short name T969
Test name
Test status
Simulation time 163011095 ps
CPU time 3.58 seconds
Started Jun 27 07:27:03 PM PDT 24
Finished Jun 27 07:29:53 PM PDT 24
Peak memory 242052 kb
Host smart-e84afbbe-38e4-4332-8ddb-6ead5d9c72ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881128307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.881128307
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2874903395
Short name T584
Test name
Test status
Simulation time 266793239 ps
CPU time 15.81 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:28:08 PM PDT 24
Peak memory 241764 kb
Host smart-247e0cfb-fdbc-4f5e-b9f2-ddefe704e279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874903395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2874903395
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.233363432
Short name T478
Test name
Test status
Simulation time 106825455 ps
CPU time 3.65 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:29:23 PM PDT 24
Peak memory 242044 kb
Host smart-1056fab9-db6f-45b4-81ed-e5583a147d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233363432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.233363432
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.1175508470
Short name T712
Test name
Test status
Simulation time 3795673022 ps
CPU time 10.93 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:47 PM PDT 24
Peak memory 242008 kb
Host smart-95be3877-aedc-4a74-9d76-d597b995d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175508470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1175508470
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.4085240981
Short name T420
Test name
Test status
Simulation time 167748531 ps
CPU time 2.13 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:19:10 PM PDT 24
Peak memory 240560 kb
Host smart-ccaa02eb-971b-4b94-991f-d8cff2232d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085240981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.4085240981
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.4274581690
Short name T146
Test name
Test status
Simulation time 3385320150 ps
CPU time 21.85 seconds
Started Jun 27 07:16:33 PM PDT 24
Finished Jun 27 07:19:02 PM PDT 24
Peak memory 242364 kb
Host smart-4ac3cd77-02fb-47e2-b6b7-fc8c9efeec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274581690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.4274581690
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1816013597
Short name T956
Test name
Test status
Simulation time 389399455 ps
CPU time 22.08 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:19:30 PM PDT 24
Peak memory 241888 kb
Host smart-02a34df9-94d3-4831-a1bb-caf74dd06927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816013597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1816013597
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.1095952576
Short name T1033
Test name
Test status
Simulation time 892008688 ps
CPU time 16.22 seconds
Started Jun 27 07:16:30 PM PDT 24
Finished Jun 27 07:18:54 PM PDT 24
Peak memory 242828 kb
Host smart-a7ec9766-af58-491b-a213-65dfe029feb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095952576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1095952576
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.665508168
Short name T156
Test name
Test status
Simulation time 205492460 ps
CPU time 3.13 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:43 PM PDT 24
Peak memory 242148 kb
Host smart-0dc923a5-de63-4c71-8a56-85944851894b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665508168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.665508168
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.2053495622
Short name T879
Test name
Test status
Simulation time 188836244 ps
CPU time 7.4 seconds
Started Jun 27 07:16:49 PM PDT 24
Finished Jun 27 07:19:18 PM PDT 24
Peak memory 242072 kb
Host smart-79b96052-a066-4b9d-a2f3-3f8efba7e235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053495622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2053495622
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2105358089
Short name T834
Test name
Test status
Simulation time 3833750674 ps
CPU time 21.11 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:31 PM PDT 24
Peak memory 242336 kb
Host smart-2d210bc2-2ddb-4be2-bd04-7877e791ff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105358089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2105358089
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.827331621
Short name T846
Test name
Test status
Simulation time 1707849349 ps
CPU time 6.15 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:45 PM PDT 24
Peak memory 242148 kb
Host smart-1cbcfdbf-ea83-431e-87f0-d71c3c6054c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827331621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.827331621
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.46230127
Short name T836
Test name
Test status
Simulation time 299800465 ps
CPU time 8.86 seconds
Started Jun 27 07:16:32 PM PDT 24
Finished Jun 27 07:18:48 PM PDT 24
Peak memory 248672 kb
Host smart-70fe626e-c1c8-4944-bd2a-447c435148d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46230127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.46230127
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.154286073
Short name T704
Test name
Test status
Simulation time 483392700 ps
CPU time 4.77 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:19:13 PM PDT 24
Peak memory 242324 kb
Host smart-61bf4249-7fea-442c-9baf-2a6b32a542a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154286073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.154286073
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.726410998
Short name T23
Test name
Test status
Simulation time 11328302557 ps
CPU time 189.88 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:22:16 PM PDT 24
Peak memory 278344 kb
Host smart-9a8675b9-6849-4846-a56f-808a1149c1bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726410998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.726410998
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1187784055
Short name T310
Test name
Test status
Simulation time 923083452 ps
CPU time 10.04 seconds
Started Jun 27 07:16:35 PM PDT 24
Finished Jun 27 07:19:02 PM PDT 24
Peak memory 242456 kb
Host smart-4d972dbb-118e-4701-a3ac-7fd52cc892e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187784055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1187784055
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.2864658680
Short name T733
Test name
Test status
Simulation time 9415538439 ps
CPU time 24.86 seconds
Started Jun 27 07:16:48 PM PDT 24
Finished Jun 27 07:19:35 PM PDT 24
Peak memory 242472 kb
Host smart-f9f24e87-1907-4885-8221-0d4936405fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864658680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2864658680
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3653440670
Short name T689
Test name
Test status
Simulation time 110814698 ps
CPU time 1.83 seconds
Started Jun 27 07:20:03 PM PDT 24
Finished Jun 27 07:22:40 PM PDT 24
Peak memory 239980 kb
Host smart-68261a13-318e-4290-9a98-71ec943576e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653440670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3653440670
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.3921052656
Short name T963
Test name
Test status
Simulation time 657183262 ps
CPU time 11.18 seconds
Started Jun 27 07:18:55 PM PDT 24
Finished Jun 27 07:21:17 PM PDT 24
Peak memory 242128 kb
Host smart-f9b9cbf5-590b-4616-b086-bf6a09221b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921052656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3921052656
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.1878224620
Short name T358
Test name
Test status
Simulation time 971484462 ps
CPU time 28.55 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:23:08 PM PDT 24
Peak memory 244508 kb
Host smart-24bb1c49-0ab9-43b3-88a4-99b9c1bce91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878224620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1878224620
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.1932998261
Short name T835
Test name
Test status
Simulation time 971850092 ps
CPU time 25.99 seconds
Started Jun 27 07:18:54 PM PDT 24
Finished Jun 27 07:21:33 PM PDT 24
Peak memory 242248 kb
Host smart-3c5f20b8-e32c-45fc-82e2-35101e6893ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932998261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.1932998261
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2561094899
Short name T317
Test name
Test status
Simulation time 362524195 ps
CPU time 3.83 seconds
Started Jun 27 07:18:40 PM PDT 24
Finished Jun 27 07:22:10 PM PDT 24
Peak memory 242072 kb
Host smart-78603db3-664b-4c96-952e-6039b5546bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561094899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2561094899
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.494072210
Short name T965
Test name
Test status
Simulation time 1020218882 ps
CPU time 7.13 seconds
Started Jun 27 07:20:03 PM PDT 24
Finished Jun 27 07:22:16 PM PDT 24
Peak memory 242580 kb
Host smart-38c4f490-be2d-46fb-8f64-9e82564d2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494072210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.494072210
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2278769385
Short name T887
Test name
Test status
Simulation time 566558717 ps
CPU time 16.32 seconds
Started Jun 27 07:19:00 PM PDT 24
Finished Jun 27 07:21:47 PM PDT 24
Peak memory 242040 kb
Host smart-4d2d7b98-b2e2-4858-ae77-c83470da0342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278769385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2278769385
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.1849923794
Short name T293
Test name
Test status
Simulation time 3949658995 ps
CPU time 11.5 seconds
Started Jun 27 07:18:42 PM PDT 24
Finished Jun 27 07:21:01 PM PDT 24
Peak memory 248724 kb
Host smart-5545217f-32d8-47ed-a3fe-9f064e5e3582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849923794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1849923794
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.2677988189
Short name T384
Test name
Test status
Simulation time 996518259 ps
CPU time 8.32 seconds
Started Jun 27 07:18:55 PM PDT 24
Finished Jun 27 07:21:41 PM PDT 24
Peak memory 242344 kb
Host smart-74fed605-b680-46ca-a8c8-ac13ef13b0fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677988189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2677988189
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.4152545419
Short name T928
Test name
Test status
Simulation time 2477510359 ps
CPU time 5.02 seconds
Started Jun 27 07:18:40 PM PDT 24
Finished Jun 27 07:23:34 PM PDT 24
Peak memory 242112 kb
Host smart-4860982b-399b-41fe-8ece-caeeb521c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152545419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.4152545419
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.4155353796
Short name T240
Test name
Test status
Simulation time 201979863736 ps
CPU time 601.54 seconds
Started Jun 27 07:18:54 PM PDT 24
Finished Jun 27 07:31:32 PM PDT 24
Peak memory 328012 kb
Host smart-00bb572f-6019-433d-828e-8b4f79189962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155353796 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.4155353796
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1177036192
Short name T403
Test name
Test status
Simulation time 5933865908 ps
CPU time 17.03 seconds
Started Jun 27 07:18:56 PM PDT 24
Finished Jun 27 07:21:15 PM PDT 24
Peak memory 242560 kb
Host smart-8e85fc34-bfd5-470b-aa8d-63fc1aae676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177036192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1177036192
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1886612964
Short name T465
Test name
Test status
Simulation time 321413516 ps
CPU time 4.18 seconds
Started Jun 27 07:26:25 PM PDT 24
Finished Jun 27 07:28:35 PM PDT 24
Peak memory 242088 kb
Host smart-a4e1d25d-8997-47cf-80d8-dd2ee608ca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886612964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1886612964
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.666179792
Short name T457
Test name
Test status
Simulation time 278233365 ps
CPU time 3.92 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:40 PM PDT 24
Peak memory 241792 kb
Host smart-3d9d49c3-cb84-4396-823c-dc695258fd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666179792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.666179792
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.1544280794
Short name T553
Test name
Test status
Simulation time 128048750 ps
CPU time 3.28 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:40 PM PDT 24
Peak memory 242128 kb
Host smart-01ed7de0-4c19-45dc-98df-9b718f4b2182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544280794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.1544280794
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.1127576065
Short name T726
Test name
Test status
Simulation time 191701826 ps
CPU time 4.26 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:41 PM PDT 24
Peak memory 242056 kb
Host smart-03410709-6154-431d-85ce-ee517f8158d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127576065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1127576065
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1954949074
Short name T666
Test name
Test status
Simulation time 2051964213 ps
CPU time 4.21 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:28 PM PDT 24
Peak memory 242008 kb
Host smart-f30ff158-e8c7-4629-a5cc-14b4427a8b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954949074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1954949074
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.2156714814
Short name T33
Test name
Test status
Simulation time 1521390552 ps
CPU time 5.59 seconds
Started Jun 27 07:26:25 PM PDT 24
Finished Jun 27 07:28:37 PM PDT 24
Peak memory 242392 kb
Host smart-3e8587fd-b021-4ae0-bba2-bb7a3b3a623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156714814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.2156714814
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.4220424280
Short name T43
Test name
Test status
Simulation time 177446126 ps
CPU time 4.01 seconds
Started Jun 27 07:26:26 PM PDT 24
Finished Jun 27 07:28:35 PM PDT 24
Peak memory 241924 kb
Host smart-2b380efe-cd21-46a1-9252-8562e755d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220424280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4220424280
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.4107007348
Short name T809
Test name
Test status
Simulation time 1728649002 ps
CPU time 5.24 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:42 PM PDT 24
Peak memory 242168 kb
Host smart-00c453c2-7717-4d70-88a8-4d3ad82d54ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107007348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.4107007348
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3531020736
Short name T496
Test name
Test status
Simulation time 1746839294 ps
CPU time 5.35 seconds
Started Jun 27 07:26:25 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 242224 kb
Host smart-037fc551-c50b-4b4d-aac9-aee9dd2a4d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531020736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3531020736
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.1267968573
Short name T537
Test name
Test status
Simulation time 429193773 ps
CPU time 3.18 seconds
Started Jun 27 07:20:23 PM PDT 24
Finished Jun 27 07:22:54 PM PDT 24
Peak memory 240368 kb
Host smart-0cbbba9b-68f3-4817-aba8-c7c9528c0529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267968573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.1267968573
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1925630346
Short name T848
Test name
Test status
Simulation time 272958020 ps
CPU time 6.1 seconds
Started Jun 27 07:20:04 PM PDT 24
Finished Jun 27 07:22:57 PM PDT 24
Peak memory 248992 kb
Host smart-cc100845-22ae-413c-a9ad-936473451ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925630346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1925630346
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.489011013
Short name T817
Test name
Test status
Simulation time 23892092347 ps
CPU time 35.12 seconds
Started Jun 27 07:18:54 PM PDT 24
Finished Jun 27 07:21:57 PM PDT 24
Peak memory 243496 kb
Host smart-f41f8689-c884-48b7-abe2-9a50be9bcb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489011013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.489011013
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.159402706
Short name T168
Test name
Test status
Simulation time 1620892615 ps
CPU time 4.09 seconds
Started Jun 27 07:20:00 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 242160 kb
Host smart-adc219fa-fbbf-4450-8362-23483c154964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159402706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.159402706
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2353010881
Short name T629
Test name
Test status
Simulation time 1071593430 ps
CPU time 11.7 seconds
Started Jun 27 07:21:41 PM PDT 24
Finished Jun 27 07:24:55 PM PDT 24
Peak memory 248752 kb
Host smart-ba1c118a-8dd7-4080-aae0-9f479733bfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353010881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2353010881
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.3178664573
Short name T979
Test name
Test status
Simulation time 1247950901 ps
CPU time 9.15 seconds
Started Jun 27 07:20:07 PM PDT 24
Finished Jun 27 07:23:08 PM PDT 24
Peak memory 241624 kb
Host smart-6341bca3-2e43-4712-b674-12723aa1e619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178664573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.3178664573
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.2022577793
Short name T1037
Test name
Test status
Simulation time 576959370 ps
CPU time 5.52 seconds
Started Jun 27 07:22:43 PM PDT 24
Finished Jun 27 07:24:43 PM PDT 24
Peak memory 242020 kb
Host smart-47c5e225-8c1e-4f81-aac7-9ec077b7afb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022577793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2022577793
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3997351027
Short name T934
Test name
Test status
Simulation time 2491211113 ps
CPU time 4.53 seconds
Started Jun 27 07:19:57 PM PDT 24
Finished Jun 27 07:23:12 PM PDT 24
Peak memory 242600 kb
Host smart-ba38c7dc-a58c-4c81-977c-39b9aa15b285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997351027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3997351027
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.2399786887
Short name T239
Test name
Test status
Simulation time 44886999984 ps
CPU time 231.87 seconds
Started Jun 27 07:19:17 PM PDT 24
Finished Jun 27 07:25:50 PM PDT 24
Peak memory 296276 kb
Host smart-9a74d267-a3ce-4652-8676-ebb0e1c94ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399786887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.2399786887
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.14286702
Short name T716
Test name
Test status
Simulation time 114778809963 ps
CPU time 986.65 seconds
Started Jun 27 07:21:30 PM PDT 24
Finished Jun 27 07:40:25 PM PDT 24
Peak memory 375928 kb
Host smart-a8946b54-bc87-4973-99c7-52c01c14579b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14286702 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.14286702
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.3408465227
Short name T1015
Test name
Test status
Simulation time 2041568872 ps
CPU time 5.31 seconds
Started Jun 27 07:19:10 PM PDT 24
Finished Jun 27 07:21:37 PM PDT 24
Peak memory 242060 kb
Host smart-45e23f44-a304-4082-bd1c-2ddfc2d62542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408465227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.3408465227
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1351264673
Short name T889
Test name
Test status
Simulation time 158689914 ps
CPU time 3.33 seconds
Started Jun 27 07:26:25 PM PDT 24
Finished Jun 27 07:28:34 PM PDT 24
Peak memory 241876 kb
Host smart-35e6f285-c7eb-46a6-9ab1-01a8a17bc952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351264673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1351264673
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.2632683351
Short name T715
Test name
Test status
Simulation time 491727005 ps
CPU time 5.35 seconds
Started Jun 27 07:26:24 PM PDT 24
Finished Jun 27 07:28:42 PM PDT 24
Peak memory 241844 kb
Host smart-0d1e3ae8-61a9-47be-a8bd-e00ba7c6652a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632683351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2632683351
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1870772347
Short name T450
Test name
Test status
Simulation time 446555105 ps
CPU time 3.38 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242416 kb
Host smart-6b43bb62-a688-4d73-be30-cf492147f99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870772347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1870772347
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3014472839
Short name T664
Test name
Test status
Simulation time 2102941114 ps
CPU time 5.67 seconds
Started Jun 27 07:26:37 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 242208 kb
Host smart-abda1aa7-fefc-4f9b-a30a-16e9b847cbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014472839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3014472839
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3595002179
Short name T1050
Test name
Test status
Simulation time 2021665990 ps
CPU time 5.83 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:52 PM PDT 24
Peak memory 241940 kb
Host smart-3edabe00-770f-4447-97f9-a2544ad4ffed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595002179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3595002179
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.150933887
Short name T533
Test name
Test status
Simulation time 120588575 ps
CPU time 3.8 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242080 kb
Host smart-31089163-2d94-46fe-9edd-e292e90beeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150933887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.150933887
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3000294370
Short name T1062
Test name
Test status
Simulation time 124374638 ps
CPU time 3.42 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242408 kb
Host smart-1ad6bd47-9bf9-469f-a442-bc27f34ec1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000294370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3000294370
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.3264409859
Short name T24
Test name
Test status
Simulation time 613038423 ps
CPU time 3.91 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 242052 kb
Host smart-c1349bcc-8527-400c-91b2-8b8ddcc417f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264409859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.3264409859
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.485922888
Short name T598
Test name
Test status
Simulation time 192146508 ps
CPU time 4 seconds
Started Jun 27 07:26:37 PM PDT 24
Finished Jun 27 07:28:48 PM PDT 24
Peak memory 241908 kb
Host smart-30a3aff3-c09f-4113-9454-5d8c383fe5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485922888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.485922888
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.3908603327
Short name T125
Test name
Test status
Simulation time 1111276721 ps
CPU time 23.27 seconds
Started Jun 27 07:19:25 PM PDT 24
Finished Jun 27 07:22:14 PM PDT 24
Peak memory 248760 kb
Host smart-91fd534e-051a-4b0d-af16-e11ae2aa809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908603327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3908603327
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.2799412877
Short name T549
Test name
Test status
Simulation time 270495558 ps
CPU time 14.42 seconds
Started Jun 27 07:19:19 PM PDT 24
Finished Jun 27 07:21:45 PM PDT 24
Peak memory 242332 kb
Host smart-50824efd-8c9d-4800-9a3e-ae3d3559609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799412877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2799412877
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.2533005177
Short name T986
Test name
Test status
Simulation time 276001129 ps
CPU time 5.32 seconds
Started Jun 27 07:19:25 PM PDT 24
Finished Jun 27 07:21:56 PM PDT 24
Peak memory 242004 kb
Host smart-98416cfa-3b2c-4c1e-9e74-bc21e4c2bb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533005177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2533005177
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3446308772
Short name T751
Test name
Test status
Simulation time 249679998 ps
CPU time 3.87 seconds
Started Jun 27 07:20:37 PM PDT 24
Finished Jun 27 07:23:10 PM PDT 24
Peak memory 242076 kb
Host smart-85a94294-c8be-4e18-ba76-089a400a874f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446308772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3446308772
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.1188409862
Short name T608
Test name
Test status
Simulation time 978134444 ps
CPU time 10.22 seconds
Started Jun 27 07:19:18 PM PDT 24
Finished Jun 27 07:21:41 PM PDT 24
Peak memory 248804 kb
Host smart-56da787f-d8a4-4b33-8d11-dd5c622d767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188409862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1188409862
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2286649920
Short name T333
Test name
Test status
Simulation time 112997567 ps
CPU time 3.05 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:23:02 PM PDT 24
Peak memory 241860 kb
Host smart-5cd5dd7c-7356-453e-bad9-40c09cba345f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286649920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2286649920
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.1271787177
Short name T411
Test name
Test status
Simulation time 736106970 ps
CPU time 7.26 seconds
Started Jun 27 07:20:20 PM PDT 24
Finished Jun 27 07:23:06 PM PDT 24
Peak memory 241920 kb
Host smart-74ef8cb5-93ca-4dd4-811f-570fbb39776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271787177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1271787177
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.3907537406
Short name T318
Test name
Test status
Simulation time 96252104861 ps
CPU time 250.91 seconds
Started Jun 27 07:19:19 PM PDT 24
Finished Jun 27 07:26:19 PM PDT 24
Peak memory 308272 kb
Host smart-38ed00dc-70b9-41f4-9c22-234bbd94ae84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907537406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.3907537406
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.49993203
Short name T211
Test name
Test status
Simulation time 117464189795 ps
CPU time 953.69 seconds
Started Jun 27 07:19:19 PM PDT 24
Finished Jun 27 07:37:24 PM PDT 24
Peak memory 417288 kb
Host smart-f4b2f3eb-aa19-4e6e-8e88-e4ec6c3ed6d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49993203 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.49993203
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3733682036
Short name T570
Test name
Test status
Simulation time 9863863637 ps
CPU time 16.78 seconds
Started Jun 27 07:19:19 PM PDT 24
Finished Jun 27 07:21:47 PM PDT 24
Peak memory 242492 kb
Host smart-f55317be-afcc-426b-952b-0528a59af028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733682036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3733682036
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1793547340
Short name T165
Test name
Test status
Simulation time 441512090 ps
CPU time 4.53 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242036 kb
Host smart-de898317-a0e8-4ec9-af71-5992e9580024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793547340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1793547340
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.2860382480
Short name T477
Test name
Test status
Simulation time 196385331 ps
CPU time 4.05 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 242076 kb
Host smart-9f788a3a-2e68-48c4-bb3b-090a48d43258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860382480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.2860382480
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2375328375
Short name T567
Test name
Test status
Simulation time 144267262 ps
CPU time 4.23 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242236 kb
Host smart-074addbf-dbd2-4180-9e53-02db36f833a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375328375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2375328375
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.3223624340
Short name T1017
Test name
Test status
Simulation time 153103213 ps
CPU time 3.73 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 241800 kb
Host smart-e3b42468-5bea-41e4-be2b-b291d4bda449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223624340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3223624340
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3299770217
Short name T625
Test name
Test status
Simulation time 192413859 ps
CPU time 3.65 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:48 PM PDT 24
Peak memory 241976 kb
Host smart-024b2d55-fd75-4427-a9de-9d3812c0d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299770217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3299770217
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1597251808
Short name T867
Test name
Test status
Simulation time 297977906 ps
CPU time 4.25 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:58 PM PDT 24
Peak memory 242020 kb
Host smart-9ee59be7-bdb0-4387-bd5c-fef47b5866c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597251808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1597251808
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.3277785749
Short name T591
Test name
Test status
Simulation time 1816736436 ps
CPU time 6.14 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:29:00 PM PDT 24
Peak memory 242016 kb
Host smart-e3c7d51e-c3cd-4a8e-a374-af6a85eced67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277785749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.3277785749
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.3711256873
Short name T868
Test name
Test status
Simulation time 103490385 ps
CPU time 3.8 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 241944 kb
Host smart-a84dc2f4-1161-4c58-a66a-96f1252050b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711256873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3711256873
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1124514727
Short name T821
Test name
Test status
Simulation time 364058709 ps
CPU time 3.44 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242056 kb
Host smart-394cf8fb-d208-42fa-8f7d-b48767f20e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124514727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1124514727
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.2337773082
Short name T709
Test name
Test status
Simulation time 127420009 ps
CPU time 3.25 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 242348 kb
Host smart-a4c92a23-9c6f-463e-88cb-e6d824c5782b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337773082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2337773082
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3292170760
Short name T1026
Test name
Test status
Simulation time 204778475 ps
CPU time 1.89 seconds
Started Jun 27 07:19:41 PM PDT 24
Finished Jun 27 07:22:10 PM PDT 24
Peak memory 240176 kb
Host smart-54f22838-6a36-4eec-938e-dc74a9c9fbba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292170760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3292170760
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3928075995
Short name T225
Test name
Test status
Simulation time 286396558 ps
CPU time 12.1 seconds
Started Jun 27 07:19:24 PM PDT 24
Finished Jun 27 07:22:22 PM PDT 24
Peak memory 242480 kb
Host smart-b7e90c59-6600-456a-8444-fb55a32ac763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928075995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3928075995
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.973756896
Short name T838
Test name
Test status
Simulation time 15058477932 ps
CPU time 35.89 seconds
Started Jun 27 07:19:18 PM PDT 24
Finished Jun 27 07:22:06 PM PDT 24
Peak memory 242536 kb
Host smart-b7c2e84d-5c5f-4d36-8d56-ea4ac52730b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973756896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.973756896
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.712693089
Short name T155
Test name
Test status
Simulation time 237580029 ps
CPU time 4.17 seconds
Started Jun 27 07:19:18 PM PDT 24
Finished Jun 27 07:21:35 PM PDT 24
Peak memory 242132 kb
Host smart-22acff5c-a47f-4f4d-9b92-b47a85fca68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712693089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.712693089
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3196863984
Short name T268
Test name
Test status
Simulation time 6885187739 ps
CPU time 15.52 seconds
Started Jun 27 07:19:18 PM PDT 24
Finished Jun 27 07:21:46 PM PDT 24
Peak memory 242312 kb
Host smart-deefe27d-5619-4cad-ad8a-9305c3039f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196863984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3196863984
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.1408532456
Short name T421
Test name
Test status
Simulation time 1340586833 ps
CPU time 13.21 seconds
Started Jun 27 07:19:18 PM PDT 24
Finished Jun 27 07:21:44 PM PDT 24
Peak memory 242088 kb
Host smart-93624488-0f95-4c6a-a1b9-d2e6563b03e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408532456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1408532456
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.3163596839
Short name T538
Test name
Test status
Simulation time 2762338956 ps
CPU time 14.26 seconds
Started Jun 27 07:19:24 PM PDT 24
Finished Jun 27 07:22:05 PM PDT 24
Peak memory 242224 kb
Host smart-53c2f674-4b1f-4615-8f62-effafc72ab60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163596839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.3163596839
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4070561265
Short name T503
Test name
Test status
Simulation time 309032998 ps
CPU time 9.67 seconds
Started Jun 27 07:19:20 PM PDT 24
Finished Jun 27 07:22:17 PM PDT 24
Peak memory 242176 kb
Host smart-445fb9dd-fd4c-4a4d-addb-c178f0a02200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070561265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4070561265
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.665261943
Short name T645
Test name
Test status
Simulation time 157099451 ps
CPU time 5.28 seconds
Started Jun 27 07:19:42 PM PDT 24
Finished Jun 27 07:21:56 PM PDT 24
Peak memory 242028 kb
Host smart-61342cfc-6dc6-4678-a613-ed5a72d793f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665261943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.665261943
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.1361538348
Short name T437
Test name
Test status
Simulation time 1051949022 ps
CPU time 7.72 seconds
Started Jun 27 07:19:20 PM PDT 24
Finished Jun 27 07:21:57 PM PDT 24
Peak memory 242040 kb
Host smart-b991db4f-4509-4c91-8b0d-0f819cfeeffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361538348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.1361538348
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.4073644457
Short name T810
Test name
Test status
Simulation time 4202299877 ps
CPU time 95.97 seconds
Started Jun 27 07:19:42 PM PDT 24
Finished Jun 27 07:23:27 PM PDT 24
Peak memory 256956 kb
Host smart-e79eb1ea-7350-4c95-9c97-52fec8b39ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073644457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.4073644457
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3063142679
Short name T344
Test name
Test status
Simulation time 189817688859 ps
CPU time 1511.51 seconds
Started Jun 27 07:19:43 PM PDT 24
Finished Jun 27 07:47:02 PM PDT 24
Peak memory 306088 kb
Host smart-5ff985c3-c168-45c9-9636-12601d999973
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063142679 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.3063142679
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3063920564
Short name T891
Test name
Test status
Simulation time 486904825 ps
CPU time 3.59 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 242096 kb
Host smart-2e2ed3b8-a87d-4e21-914c-4cbeddf3af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063920564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3063920564
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.1234135930
Short name T44
Test name
Test status
Simulation time 203733499 ps
CPU time 4.1 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242164 kb
Host smart-903ff77e-3d4f-48cf-8ee9-68ba6b90602c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234135930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.1234135930
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.2278666823
Short name T552
Test name
Test status
Simulation time 154812736 ps
CPU time 4.21 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 242076 kb
Host smart-9f3b0f87-d7ae-44ac-9be7-c5b6c896d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278666823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.2278666823
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2427587429
Short name T786
Test name
Test status
Simulation time 223302643 ps
CPU time 4.57 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 241868 kb
Host smart-eadfd599-bae2-4f2f-9c71-3770a1679809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427587429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2427587429
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1181010474
Short name T163
Test name
Test status
Simulation time 1487280651 ps
CPU time 4.71 seconds
Started Jun 27 07:26:43 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242204 kb
Host smart-90e73441-6457-4ca2-8184-5f48f08d0580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181010474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1181010474
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.3584976830
Short name T349
Test name
Test status
Simulation time 2843754555 ps
CPU time 6.59 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:29:00 PM PDT 24
Peak memory 242100 kb
Host smart-d6f17881-fff1-4d76-8012-25d4d3cc697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584976830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.3584976830
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.606145296
Short name T973
Test name
Test status
Simulation time 311844081 ps
CPU time 4.36 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 241832 kb
Host smart-f463836c-5f97-482a-a9cc-1b5cd64e3724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606145296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.606145296
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.2992337888
Short name T989
Test name
Test status
Simulation time 545258152 ps
CPU time 4.54 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242172 kb
Host smart-dfcd5e6c-9b59-44c1-a543-460bc1cd94ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992337888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2992337888
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2354430788
Short name T114
Test name
Test status
Simulation time 244095377 ps
CPU time 3.75 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242240 kb
Host smart-c756b689-6871-4275-91e1-d158220a31ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354430788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2354430788
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.3169353163
Short name T25
Test name
Test status
Simulation time 202467165 ps
CPU time 3.73 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 241916 kb
Host smart-1edfc047-db4c-4506-87d1-f4f95e5b764e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169353163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3169353163
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.1952112586
Short name T413
Test name
Test status
Simulation time 888829034 ps
CPU time 2.84 seconds
Started Jun 27 07:19:55 PM PDT 24
Finished Jun 27 07:22:12 PM PDT 24
Peak memory 240096 kb
Host smart-1597a070-5b86-4c68-a0f4-fd2723baedd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952112586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1952112586
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.1889923130
Short name T635
Test name
Test status
Simulation time 496395381 ps
CPU time 12.13 seconds
Started Jun 27 07:19:41 PM PDT 24
Finished Jun 27 07:22:03 PM PDT 24
Peak memory 242052 kb
Host smart-dd5e0a61-2234-4c90-a165-1062ccd3547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889923130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1889923130
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.622861083
Short name T674
Test name
Test status
Simulation time 763929939 ps
CPU time 4.86 seconds
Started Jun 27 07:19:40 PM PDT 24
Finished Jun 27 07:21:55 PM PDT 24
Peak memory 242124 kb
Host smart-8872d991-ed1b-48b5-8306-136c19e18ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622861083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.622861083
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.518062793
Short name T466
Test name
Test status
Simulation time 1813186288 ps
CPU time 5.8 seconds
Started Jun 27 07:19:41 PM PDT 24
Finished Jun 27 07:21:56 PM PDT 24
Peak memory 241932 kb
Host smart-aa2c6713-ff30-45aa-9cba-01fa09b2c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518062793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.518062793
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.3490458450
Short name T854
Test name
Test status
Simulation time 502076242 ps
CPU time 11.98 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:31 PM PDT 24
Peak memory 242380 kb
Host smart-cc276d51-44d0-4837-97ee-7b8f6b92220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490458450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.3490458450
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.199642288
Short name T805
Test name
Test status
Simulation time 892668131 ps
CPU time 22.03 seconds
Started Jun 27 07:19:55 PM PDT 24
Finished Jun 27 07:23:29 PM PDT 24
Peak memory 242224 kb
Host smart-4ad7d625-0b27-42da-a3d7-3cce3c80fd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199642288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.199642288
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.624499201
Short name T653
Test name
Test status
Simulation time 8510005368 ps
CPU time 14.13 seconds
Started Jun 27 07:19:41 PM PDT 24
Finished Jun 27 07:22:05 PM PDT 24
Peak memory 241956 kb
Host smart-85b831ce-9f9d-497d-b11f-a28617237d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624499201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.624499201
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2893039104
Short name T402
Test name
Test status
Simulation time 1432412992 ps
CPU time 22.46 seconds
Started Jun 27 07:19:40 PM PDT 24
Finished Jun 27 07:22:13 PM PDT 24
Peak memory 242000 kb
Host smart-5ed2f526-d26e-4438-a0e2-8d98dd34ec72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893039104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2893039104
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.3146156578
Short name T617
Test name
Test status
Simulation time 395102947 ps
CPU time 11.18 seconds
Started Jun 27 07:19:54 PM PDT 24
Finished Jun 27 07:22:50 PM PDT 24
Peak memory 242280 kb
Host smart-700e3ed5-2af6-4176-8588-f00c9f5a1b11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146156578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3146156578
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.2230793801
Short name T196
Test name
Test status
Simulation time 329178824 ps
CPU time 4.68 seconds
Started Jun 27 07:19:42 PM PDT 24
Finished Jun 27 07:21:55 PM PDT 24
Peak memory 241996 kb
Host smart-ee840635-4041-462f-b040-14530c444fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230793801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.2230793801
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.4043449370
Short name T958
Test name
Test status
Simulation time 286227669 ps
CPU time 2.07 seconds
Started Jun 27 07:19:54 PM PDT 24
Finished Jun 27 07:22:53 PM PDT 24
Peak memory 241392 kb
Host smart-4ed53248-0901-434a-a214-151b3813141d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043449370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.4043449370
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.2859234299
Short name T479
Test name
Test status
Simulation time 183661806 ps
CPU time 3.77 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242252 kb
Host smart-ef9e2955-e14b-4186-8340-907653a9c49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859234299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.2859234299
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.2316702007
Short name T729
Test name
Test status
Simulation time 242255191 ps
CPU time 3.51 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 241836 kb
Host smart-791b917c-0f04-4389-8ef7-44cba035cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316702007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2316702007
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2590519687
Short name T800
Test name
Test status
Simulation time 229044296 ps
CPU time 3.54 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242080 kb
Host smart-b21eea49-d5b8-44fb-bf05-d5361922fb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590519687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2590519687
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.685487111
Short name T1006
Test name
Test status
Simulation time 1907641510 ps
CPU time 5.64 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:52 PM PDT 24
Peak memory 242228 kb
Host smart-77ea769c-a511-49be-a5f6-d27ef45ffbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685487111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.685487111
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3562890391
Short name T1041
Test name
Test status
Simulation time 487147908 ps
CPU time 4.95 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:52 PM PDT 24
Peak memory 241844 kb
Host smart-d4dd55cc-fe2a-40ea-9524-a84fcdef0445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562890391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3562890391
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.510325778
Short name T199
Test name
Test status
Simulation time 135793862 ps
CPU time 3.6 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242008 kb
Host smart-dbdcce46-d9a0-4fcd-a286-b2a8220bb1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510325778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.510325778
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.291464149
Short name T468
Test name
Test status
Simulation time 637667049 ps
CPU time 3.74 seconds
Started Jun 27 07:26:44 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242692 kb
Host smart-495df183-182f-45e0-8957-3bd1f552279d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291464149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.291464149
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.2322496572
Short name T863
Test name
Test status
Simulation time 534831497 ps
CPU time 4.02 seconds
Started Jun 27 07:26:43 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242280 kb
Host smart-9b7cf0f7-8e78-4499-a8cb-7479876869e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322496572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.2322496572
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2646609468
Short name T983
Test name
Test status
Simulation time 543453004 ps
CPU time 3.34 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 241924 kb
Host smart-f4b720db-162a-49eb-86b6-578a32dc00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646609468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2646609468
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1392456137
Short name T415
Test name
Test status
Simulation time 183737669 ps
CPU time 4.12 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 242076 kb
Host smart-c76bd69c-f3f6-4d39-9bc5-26bdb24e781a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392456137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1392456137
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.2697387909
Short name T893
Test name
Test status
Simulation time 96437374 ps
CPU time 1.9 seconds
Started Jun 27 07:19:58 PM PDT 24
Finished Jun 27 07:22:10 PM PDT 24
Peak memory 240012 kb
Host smart-248a9f66-581a-4ce3-a984-3b819513f61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697387909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2697387909
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.3166793002
Short name T1058
Test name
Test status
Simulation time 4426872150 ps
CPU time 9.35 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:48 PM PDT 24
Peak memory 242572 kb
Host smart-6ea8d69b-1fc4-40bc-81f7-e013cf06de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166793002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.3166793002
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.826038025
Short name T245
Test name
Test status
Simulation time 2471025124 ps
CPU time 26.32 seconds
Started Jun 27 07:19:54 PM PDT 24
Finished Jun 27 07:23:17 PM PDT 24
Peak memory 242956 kb
Host smart-3ae05f84-0b38-4f1f-9d6b-1be7b8eaa542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826038025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.826038025
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.4038896169
Short name T678
Test name
Test status
Simulation time 150296270 ps
CPU time 4.51 seconds
Started Jun 27 07:19:54 PM PDT 24
Finished Jun 27 07:22:13 PM PDT 24
Peak memory 241924 kb
Host smart-94a8b0a8-8b2c-41f8-93d0-ff702cd4439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038896169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.4038896169
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.1926467088
Short name T366
Test name
Test status
Simulation time 3267807301 ps
CPU time 16.29 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:07 PM PDT 24
Peak memory 242260 kb
Host smart-221b7f24-14db-4ad4-b3b5-e0bfa8c49748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926467088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1926467088
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.1962509029
Short name T947
Test name
Test status
Simulation time 753133596 ps
CPU time 5.28 seconds
Started Jun 27 07:19:57 PM PDT 24
Finished Jun 27 07:22:14 PM PDT 24
Peak memory 242024 kb
Host smart-3f71905e-04f2-4a47-bf6e-5f8f12ca3845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962509029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.1962509029
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.3062034062
Short name T1010
Test name
Test status
Simulation time 2273941109 ps
CPU time 12.46 seconds
Started Jun 27 07:19:54 PM PDT 24
Finished Jun 27 07:22:21 PM PDT 24
Peak memory 242456 kb
Host smart-d8922ea6-0ca8-40b0-9a85-beec57bc84ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062034062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3062034062
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.2666890606
Short name T405
Test name
Test status
Simulation time 2808342181 ps
CPU time 32.07 seconds
Started Jun 27 07:19:55 PM PDT 24
Finished Jun 27 07:23:21 PM PDT 24
Peak memory 242764 kb
Host smart-fa2a4bd9-6e75-4bae-b643-48132d9773cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666890606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.2666890606
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2826142489
Short name T258
Test name
Test status
Simulation time 118727855933 ps
CPU time 856.72 seconds
Started Jun 27 07:19:56 PM PDT 24
Finished Jun 27 07:37:08 PM PDT 24
Peak memory 322208 kb
Host smart-ae80467f-03c3-4a69-8805-456d1882141b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826142489 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2826142489
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.4260957172
Short name T632
Test name
Test status
Simulation time 21061371578 ps
CPU time 160.08 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:25:09 PM PDT 24
Peak memory 242580 kb
Host smart-56e7621a-249a-4c5b-a364-e83d71e816ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260957172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.4260957172
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3431088319
Short name T158
Test name
Test status
Simulation time 469633253 ps
CPU time 3.11 seconds
Started Jun 27 07:26:38 PM PDT 24
Finished Jun 27 07:28:48 PM PDT 24
Peak memory 242260 kb
Host smart-a0e26244-d4bc-4c58-ab0a-d9c393ea7a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431088319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3431088319
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1866800540
Short name T630
Test name
Test status
Simulation time 1574412158 ps
CPU time 4.39 seconds
Started Jun 27 07:26:41 PM PDT 24
Finished Jun 27 07:28:51 PM PDT 24
Peak memory 242104 kb
Host smart-c6497c66-fb83-45fc-93f7-1dd36c2e37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866800540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1866800540
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.1282081794
Short name T919
Test name
Test status
Simulation time 399144853 ps
CPU time 3.38 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 241952 kb
Host smart-96777561-e885-495e-be79-691d5772ed8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282081794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1282081794
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.123417426
Short name T545
Test name
Test status
Simulation time 1809863276 ps
CPU time 4.61 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:58 PM PDT 24
Peak memory 242000 kb
Host smart-29dffa28-b5af-40e9-8e09-581ac6a28264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123417426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.123417426
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.1664876236
Short name T781
Test name
Test status
Simulation time 199192431 ps
CPU time 3.79 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242092 kb
Host smart-146cff4b-c99f-47d2-a698-20d15ae0699e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664876236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1664876236
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.2752194235
Short name T1036
Test name
Test status
Simulation time 99109448 ps
CPU time 3.08 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 242008 kb
Host smart-8db7784f-a3d8-4b62-ad85-f545f0876b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752194235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2752194235
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.718070524
Short name T825
Test name
Test status
Simulation time 2442400444 ps
CPU time 5.59 seconds
Started Jun 27 07:26:40 PM PDT 24
Finished Jun 27 07:28:52 PM PDT 24
Peak memory 242072 kb
Host smart-5e2f10fc-e42e-4cb7-9fb8-f5dd44f2eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718070524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.718070524
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2821584845
Short name T1053
Test name
Test status
Simulation time 295753237 ps
CPU time 3.62 seconds
Started Jun 27 07:26:39 PM PDT 24
Finished Jun 27 07:28:49 PM PDT 24
Peak memory 242148 kb
Host smart-1a4adc14-2969-42c5-915d-4aa5ece2a3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821584845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2821584845
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3804499664
Short name T134
Test name
Test status
Simulation time 578695649 ps
CPU time 4.75 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:57 PM PDT 24
Peak memory 242104 kb
Host smart-fd347d34-a1ea-4033-a589-edaad133849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804499664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3804499664
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2408367101
Short name T861
Test name
Test status
Simulation time 2791796864 ps
CPU time 7.7 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:29:00 PM PDT 24
Peak memory 241996 kb
Host smart-5a298583-da52-4f1d-bd51-78830de8ef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408367101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2408367101
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3493021622
Short name T996
Test name
Test status
Simulation time 104086071 ps
CPU time 1.75 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:50 PM PDT 24
Peak memory 240120 kb
Host smart-65db844d-9f14-46c0-b010-e844a6c2869b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493021622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3493021622
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.796312281
Short name T59
Test name
Test status
Simulation time 1037454749 ps
CPU time 23.11 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:01 PM PDT 24
Peak memory 242156 kb
Host smart-693b7420-d113-487b-ba53-11dd397669e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796312281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.796312281
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.2021432363
Short name T515
Test name
Test status
Simulation time 2698613049 ps
CPU time 37.24 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:46 PM PDT 24
Peak memory 250624 kb
Host smart-65740e33-fa0c-4860-9057-5b383e67a579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021432363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2021432363
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.1228771337
Short name T650
Test name
Test status
Simulation time 228334459 ps
CPU time 8.08 seconds
Started Jun 27 07:20:00 PM PDT 24
Finished Jun 27 07:22:26 PM PDT 24
Peak memory 242496 kb
Host smart-3661c214-ae96-44fa-9f83-45429e5fc8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228771337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1228771337
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1183756251
Short name T305
Test name
Test status
Simulation time 2938457773 ps
CPU time 16.12 seconds
Started Jun 27 07:19:58 PM PDT 24
Finished Jun 27 07:22:45 PM PDT 24
Peak memory 244560 kb
Host smart-cc6948b4-92f4-4999-a4a0-633eedf4d144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183756251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1183756251
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.2048763978
Short name T97
Test name
Test status
Simulation time 1236972411 ps
CPU time 24.31 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:37 PM PDT 24
Peak memory 242588 kb
Host smart-85ede362-1d54-4a70-ac56-0728dd3b3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048763978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2048763978
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.936022278
Short name T8
Test name
Test status
Simulation time 272855360 ps
CPU time 5.7 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:25 PM PDT 24
Peak memory 247560 kb
Host smart-dd402eda-31a4-41bb-a03c-da0fd74c334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936022278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.936022278
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.1899520053
Short name T392
Test name
Test status
Simulation time 346875586 ps
CPU time 8.67 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 242028 kb
Host smart-cdecf4fa-9ed8-4817-aedc-a12b1c98aa15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899520053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.1899520053
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1774855734
Short name T172
Test name
Test status
Simulation time 416150699 ps
CPU time 4.03 seconds
Started Jun 27 07:20:00 PM PDT 24
Finished Jun 27 07:22:52 PM PDT 24
Peak memory 242092 kb
Host smart-628fab45-773c-4a20-b7b4-8365481290aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774855734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1774855734
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.779929244
Short name T652
Test name
Test status
Simulation time 1191484648 ps
CPU time 9.02 seconds
Started Jun 27 07:19:57 PM PDT 24
Finished Jun 27 07:22:17 PM PDT 24
Peak memory 242032 kb
Host smart-79acca2b-54a7-4ed4-afa0-aee66136d4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779929244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.779929244
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.554456991
Short name T560
Test name
Test status
Simulation time 21355638344 ps
CPU time 130.48 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:26:09 PM PDT 24
Peak memory 257000 kb
Host smart-50ae37d0-9c51-41ae-a199-0d8b91714f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554456991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
554456991
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.3030879118
Short name T89
Test name
Test status
Simulation time 1933427030 ps
CPU time 20.51 seconds
Started Jun 27 07:27:14 PM PDT 24
Finished Jun 27 07:30:11 PM PDT 24
Peak memory 242184 kb
Host smart-3738f37b-d6ec-4acc-89e5-f8cc2f1304ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030879118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3030879118
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2199514372
Short name T36
Test name
Test status
Simulation time 258861350 ps
CPU time 3.71 seconds
Started Jun 27 07:26:42 PM PDT 24
Finished Jun 27 07:28:56 PM PDT 24
Peak memory 242116 kb
Host smart-9cb740b6-ac0c-4bbe-80dc-483934ed1a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199514372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2199514372
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.580846834
Short name T200
Test name
Test status
Simulation time 409060167 ps
CPU time 3.95 seconds
Started Jun 27 07:26:53 PM PDT 24
Finished Jun 27 07:29:42 PM PDT 24
Peak memory 242300 kb
Host smart-b3642ed4-5d77-4c82-a880-e00c2ad9451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580846834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.580846834
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.4212351381
Short name T714
Test name
Test status
Simulation time 120953752 ps
CPU time 3.11 seconds
Started Jun 27 07:26:57 PM PDT 24
Finished Jun 27 07:29:08 PM PDT 24
Peak memory 242428 kb
Host smart-af50f08d-f734-4988-8120-66c4194a3a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212351381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4212351381
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2131080434
Short name T845
Test name
Test status
Simulation time 259530103 ps
CPU time 4.4 seconds
Started Jun 27 07:26:56 PM PDT 24
Finished Jun 27 07:29:43 PM PDT 24
Peak memory 242088 kb
Host smart-f9a18995-bd36-43f2-a425-a0d77fbf6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131080434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2131080434
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.4207333089
Short name T554
Test name
Test status
Simulation time 358208297 ps
CPU time 4.35 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:30:20 PM PDT 24
Peak memory 241928 kb
Host smart-11f1ed49-7698-4c6f-b17b-4bb086dc38ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207333089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.4207333089
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.1232305771
Short name T917
Test name
Test status
Simulation time 1710277702 ps
CPU time 4.55 seconds
Started Jun 27 07:26:56 PM PDT 24
Finished Jun 27 07:29:35 PM PDT 24
Peak memory 242376 kb
Host smart-a99b4192-9973-4fda-8ede-d9d96bff3ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232305771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.1232305771
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.3734900904
Short name T456
Test name
Test status
Simulation time 1990651464 ps
CPU time 5.67 seconds
Started Jun 27 07:26:53 PM PDT 24
Finished Jun 27 07:30:07 PM PDT 24
Peak memory 242096 kb
Host smart-ca11e3e3-13b5-44a7-b866-9714e3c6cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734900904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3734900904
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1525676697
Short name T755
Test name
Test status
Simulation time 586837143 ps
CPU time 5.03 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:26 PM PDT 24
Peak memory 242056 kb
Host smart-99941e4c-9e31-4907-9d99-14573d8996af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525676697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1525676697
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.2621590886
Short name T874
Test name
Test status
Simulation time 373585141 ps
CPU time 3.9 seconds
Started Jun 27 07:26:56 PM PDT 24
Finished Jun 27 07:29:09 PM PDT 24
Peak memory 242020 kb
Host smart-d9e5b5e1-6014-43df-8929-6c9825c1fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621590886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2621590886
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.1279418023
Short name T864
Test name
Test status
Simulation time 499021929 ps
CPU time 4.64 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:30:05 PM PDT 24
Peak memory 241912 kb
Host smart-deb5babf-0d72-4123-a04d-ca246a8983d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279418023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1279418023
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1346181657
Short name T171
Test name
Test status
Simulation time 54964831 ps
CPU time 1.61 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:23:59 PM PDT 24
Peak memory 240324 kb
Host smart-cae7fe72-e261-4421-9801-55971dc3e425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346181657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1346181657
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1388751561
Short name T950
Test name
Test status
Simulation time 506896600 ps
CPU time 6.97 seconds
Started Jun 27 07:20:00 PM PDT 24
Finished Jun 27 07:22:37 PM PDT 24
Peak memory 248672 kb
Host smart-16bf8f34-cd3a-4589-8160-a4822480879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388751561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1388751561
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.3194826315
Short name T804
Test name
Test status
Simulation time 13605208076 ps
CPU time 35.99 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:27 PM PDT 24
Peak memory 245872 kb
Host smart-caf64c7d-29e7-41d5-bc6b-9e87dd7fc5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194826315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3194826315
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.988416365
Short name T524
Test name
Test status
Simulation time 1916784432 ps
CPU time 10.65 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:29 PM PDT 24
Peak memory 242092 kb
Host smart-a8bd5ffd-9629-4ecd-a9e2-dc22e8bb727d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988416365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.988416365
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3879587284
Short name T55
Test name
Test status
Simulation time 2071969712 ps
CPU time 3.72 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:13 PM PDT 24
Peak memory 241836 kb
Host smart-1aed7949-4276-4b2c-a069-6c73b4bddb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879587284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3879587284
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2937105949
Short name T187
Test name
Test status
Simulation time 640684490 ps
CPU time 19.63 seconds
Started Jun 27 07:19:58 PM PDT 24
Finished Jun 27 07:22:59 PM PDT 24
Peak memory 248772 kb
Host smart-c2c1a912-cf07-476f-9540-8f1389da127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937105949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2937105949
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2598596007
Short name T952
Test name
Test status
Simulation time 1711093142 ps
CPU time 33.38 seconds
Started Jun 27 07:20:00 PM PDT 24
Finished Jun 27 07:22:42 PM PDT 24
Peak memory 248732 kb
Host smart-5f8a6895-3713-4f8f-8374-3b54e55f140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598596007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2598596007
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.195798196
Short name T352
Test name
Test status
Simulation time 270096871 ps
CPU time 10.42 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:01 PM PDT 24
Peak memory 241888 kb
Host smart-7c5070f1-7da3-4b4a-8bc6-f6993a6d280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195798196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.195798196
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.3349180782
Short name T774
Test name
Test status
Simulation time 938944897 ps
CPU time 13.65 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:23:12 PM PDT 24
Peak memory 241952 kb
Host smart-1bdc17f4-660f-4c7f-9794-624f10b2f688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3349180782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.3349180782
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.1141310608
Short name T382
Test name
Test status
Simulation time 284101720 ps
CPU time 8.86 seconds
Started Jun 27 07:19:59 PM PDT 24
Finished Jun 27 07:22:59 PM PDT 24
Peak memory 242072 kb
Host smart-fce04507-d5d4-48fb-957f-921aeb3d1d34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141310608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.1141310608
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.3192089122
Short name T938
Test name
Test status
Simulation time 96534868551 ps
CPU time 1763.7 seconds
Started Jun 27 07:25:47 PM PDT 24
Finished Jun 27 07:57:17 PM PDT 24
Peak memory 351364 kb
Host smart-c00894f6-c154-4d68-8fee-c696bbcb4c50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192089122 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.3192089122
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.975034348
Short name T167
Test name
Test status
Simulation time 1857902312 ps
CPU time 4.89 seconds
Started Jun 27 07:26:56 PM PDT 24
Finished Jun 27 07:29:34 PM PDT 24
Peak memory 242136 kb
Host smart-26700b04-677c-4c5b-897e-a27bd554c048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975034348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.975034348
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.3665860946
Short name T115
Test name
Test status
Simulation time 126258565 ps
CPU time 3.47 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:13 PM PDT 24
Peak memory 242372 kb
Host smart-33c331c9-3cb9-4a7b-8b3b-e8b83f52dbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665860946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3665860946
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1685895613
Short name T1016
Test name
Test status
Simulation time 2026789552 ps
CPU time 7.5 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:12 PM PDT 24
Peak memory 242140 kb
Host smart-bfae2ba7-37b0-47ec-b469-ce49734ddf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685895613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1685895613
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.1458789769
Short name T671
Test name
Test status
Simulation time 2277130545 ps
CPU time 5.29 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:24 PM PDT 24
Peak memory 242420 kb
Host smart-127c24ce-0bb3-48ef-8a8a-3a93f1cbf590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458789769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.1458789769
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2937490121
Short name T866
Test name
Test status
Simulation time 692821605 ps
CPU time 4.34 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:55 PM PDT 24
Peak memory 242416 kb
Host smart-cc0e6d81-5e9a-4bc3-ba2d-dc67c2ce0266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937490121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2937490121
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1421011127
Short name T837
Test name
Test status
Simulation time 97165473 ps
CPU time 3.56 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:30:03 PM PDT 24
Peak memory 241868 kb
Host smart-062bf43d-197c-4094-95bb-1daf710e0b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421011127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1421011127
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1976649849
Short name T633
Test name
Test status
Simulation time 223761800 ps
CPU time 3.79 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:33 PM PDT 24
Peak memory 242072 kb
Host smart-9e8c6966-459c-4929-ae46-a35403e3cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976649849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1976649849
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3789785274
Short name T628
Test name
Test status
Simulation time 389378176 ps
CPU time 2.93 seconds
Started Jun 27 07:26:57 PM PDT 24
Finished Jun 27 07:29:08 PM PDT 24
Peak memory 242312 kb
Host smart-3935867b-2353-4f78-936e-2d05c5e61274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789785274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3789785274
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.739222407
Short name T164
Test name
Test status
Simulation time 211635272 ps
CPU time 3.47 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:53 PM PDT 24
Peak memory 241928 kb
Host smart-83b35bed-567a-4c07-8334-fb1129e0cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739222407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.739222407
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3571656016
Short name T1004
Test name
Test status
Simulation time 43410899 ps
CPU time 1.54 seconds
Started Jun 27 07:20:26 PM PDT 24
Finished Jun 27 07:22:53 PM PDT 24
Peak memory 240020 kb
Host smart-b8941fc9-c91c-45f4-b81b-aa36fd5f0791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571656016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3571656016
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2461687402
Short name T357
Test name
Test status
Simulation time 558278299 ps
CPU time 12.29 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:22:50 PM PDT 24
Peak memory 241916 kb
Host smart-40533e2d-79c0-4d1a-9b9b-671f360cdd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461687402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2461687402
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.1333588411
Short name T583
Test name
Test status
Simulation time 1725251257 ps
CPU time 29.49 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:23:18 PM PDT 24
Peak memory 242768 kb
Host smart-afb53744-7f21-4ab6-b642-b735a814be80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333588411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1333588411
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.1179337781
Short name T961
Test name
Test status
Simulation time 547341083 ps
CPU time 4.37 seconds
Started Jun 27 07:22:43 PM PDT 24
Finished Jun 27 07:25:40 PM PDT 24
Peak memory 242088 kb
Host smart-ffd1e2bc-a283-43a7-8dd0-a5b2bfa8fc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179337781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.1179337781
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2339997086
Short name T185
Test name
Test status
Simulation time 447919847 ps
CPU time 5.26 seconds
Started Jun 27 07:21:25 PM PDT 24
Finished Jun 27 07:24:30 PM PDT 24
Peak memory 242652 kb
Host smart-54237134-e56c-4e64-9103-e6662762625f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339997086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2339997086
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3761088342
Short name T926
Test name
Test status
Simulation time 355134496 ps
CPU time 9.23 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:22:18 PM PDT 24
Peak memory 242672 kb
Host smart-3f0ca89a-f185-4b9e-8532-399c45cb0ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761088342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3761088342
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1777684051
Short name T659
Test name
Test status
Simulation time 113357205 ps
CPU time 2.7 seconds
Started Jun 27 07:24:32 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 241972 kb
Host smart-ba996955-c479-490f-bede-2aaa83064de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777684051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1777684051
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.2567051410
Short name T270
Test name
Test status
Simulation time 1347527333 ps
CPU time 13.94 seconds
Started Jun 27 07:21:42 PM PDT 24
Finished Jun 27 07:24:29 PM PDT 24
Peak memory 241908 kb
Host smart-50135f88-c64c-4c0f-85e7-2ae3905ef3bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2567051410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2567051410
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.1244064818
Short name T103
Test name
Test status
Simulation time 1711685690 ps
CPU time 4.68 seconds
Started Jun 27 07:26:10 PM PDT 24
Finished Jun 27 07:28:38 PM PDT 24
Peak memory 241812 kb
Host smart-e19c1746-63e1-45c8-87c2-a0c975f06282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244064818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1244064818
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.4160608572
Short name T481
Test name
Test status
Simulation time 969305708 ps
CPU time 9.57 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:22:57 PM PDT 24
Peak memory 241980 kb
Host smart-5fe5ec93-cd00-4b36-8008-36d5abd7fb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160608572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.4160608572
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.3225614603
Short name T607
Test name
Test status
Simulation time 20572200503 ps
CPU time 121.18 seconds
Started Jun 27 07:26:11 PM PDT 24
Finished Jun 27 07:30:12 PM PDT 24
Peak memory 245144 kb
Host smart-caac2d63-5a59-4f66-ac39-9327df6c6e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225614603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.3225614603
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2607805286
Short name T1052
Test name
Test status
Simulation time 353388370747 ps
CPU time 1981.77 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:55:41 PM PDT 24
Peak memory 301440 kb
Host smart-896f43b2-41e3-497b-9078-a4abbed9dea0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607805286 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2607805286
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.2907719214
Short name T1054
Test name
Test status
Simulation time 831399056 ps
CPU time 18.14 seconds
Started Jun 27 07:20:07 PM PDT 24
Finished Jun 27 07:22:55 PM PDT 24
Peak memory 242136 kb
Host smart-5746ae4b-b2a5-4d83-a3f2-20e3844202a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907719214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2907719214
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.1143609913
Short name T34
Test name
Test status
Simulation time 2345077356 ps
CPU time 4.88 seconds
Started Jun 27 07:26:57 PM PDT 24
Finished Jun 27 07:29:55 PM PDT 24
Peak memory 242156 kb
Host smart-5d1ca44d-91f2-474e-b762-b7a571549821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143609913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1143609913
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.2157033796
Short name T862
Test name
Test status
Simulation time 156685125 ps
CPU time 3.98 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:09 PM PDT 24
Peak memory 242180 kb
Host smart-b42703ca-d0e7-4b36-b8e5-2284fe2a9bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157033796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2157033796
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2728564818
Short name T769
Test name
Test status
Simulation time 527404788 ps
CPU time 3.65 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:32 PM PDT 24
Peak memory 242396 kb
Host smart-3e9d0474-0ef3-43aa-943f-19dee6b0567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728564818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2728564818
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.4015175140
Short name T687
Test name
Test status
Simulation time 133969226 ps
CPU time 4.32 seconds
Started Jun 27 07:26:55 PM PDT 24
Finished Jun 27 07:29:08 PM PDT 24
Peak memory 242404 kb
Host smart-f9662910-dc97-490c-a055-eaa890609d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015175140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.4015175140
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.269554895
Short name T844
Test name
Test status
Simulation time 171238882 ps
CPU time 4.36 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 241904 kb
Host smart-559bd161-624a-4339-a7ef-9ed2eb9d310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269554895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.269554895
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.2074920275
Short name T1007
Test name
Test status
Simulation time 111460362 ps
CPU time 3.74 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:26 PM PDT 24
Peak memory 242076 kb
Host smart-6c292add-2584-4460-a9da-23f50a82e488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074920275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2074920275
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.658150567
Short name T898
Test name
Test status
Simulation time 177916148 ps
CPU time 3.99 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242204 kb
Host smart-348edeb4-5585-423b-adef-b356c7a519ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658150567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.658150567
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2704930194
Short name T433
Test name
Test status
Simulation time 1640708346 ps
CPU time 5.67 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:29:35 PM PDT 24
Peak memory 241904 kb
Host smart-1f685d2c-8355-453f-bd6e-fe8755414cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704930194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2704930194
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.104401748
Short name T521
Test name
Test status
Simulation time 227093631 ps
CPU time 2.93 seconds
Started Jun 27 07:28:13 PM PDT 24
Finished Jun 27 07:30:27 PM PDT 24
Peak memory 241936 kb
Host smart-e3ca9af7-6ad7-4cbb-a907-6abcb492cb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104401748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.104401748
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1280928220
Short name T192
Test name
Test status
Simulation time 326854159 ps
CPU time 3.43 seconds
Started Jun 27 07:27:10 PM PDT 24
Finished Jun 27 07:29:24 PM PDT 24
Peak memory 242032 kb
Host smart-0b0268e3-9689-4905-8b48-00fb20f6da55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280928220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1280928220
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2422174837
Short name T287
Test name
Test status
Simulation time 716906092 ps
CPU time 1.8 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:22:40 PM PDT 24
Peak memory 240172 kb
Host smart-28a7b6f7-bde8-4147-a30f-21a8d9a5f134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422174837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2422174837
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.1273391556
Short name T130
Test name
Test status
Simulation time 2214663927 ps
CPU time 10.82 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:23:09 PM PDT 24
Peak memory 242368 kb
Host smart-e4ea36b2-cfc5-4d66-acd8-1094252d1ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273391556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1273391556
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.257608589
Short name T203
Test name
Test status
Simulation time 419769207 ps
CPU time 11.34 seconds
Started Jun 27 07:21:51 PM PDT 24
Finished Jun 27 07:24:26 PM PDT 24
Peak memory 241936 kb
Host smart-ded3920a-d0ee-4ff5-9e02-ec9273e58952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257608589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.257608589
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.1266819557
Short name T888
Test name
Test status
Simulation time 2314326938 ps
CPU time 22.41 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:23:21 PM PDT 24
Peak memory 242376 kb
Host smart-6b09ff22-df46-4586-9026-e21676f4d40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266819557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1266819557
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3727964227
Short name T631
Test name
Test status
Simulation time 294321176 ps
CPU time 4.35 seconds
Started Jun 27 07:21:30 PM PDT 24
Finished Jun 27 07:25:01 PM PDT 24
Peak memory 242040 kb
Host smart-34784867-31fb-4db2-ac01-3b83750d9de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727964227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3727964227
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.3072855556
Short name T975
Test name
Test status
Simulation time 1319807329 ps
CPU time 7.39 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:22:48 PM PDT 24
Peak memory 242324 kb
Host smart-5edf904c-4e34-4da5-9f79-3ac74e4fb8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072855556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3072855556
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.922373077
Short name T430
Test name
Test status
Simulation time 177417525 ps
CPU time 3.89 seconds
Started Jun 27 07:20:26 PM PDT 24
Finished Jun 27 07:23:22 PM PDT 24
Peak memory 241980 kb
Host smart-a069dae7-4475-4b43-98db-083c6a63c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922373077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.922373077
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.370040983
Short name T761
Test name
Test status
Simulation time 419286118 ps
CPU time 9.4 seconds
Started Jun 27 07:20:26 PM PDT 24
Finished Jun 27 07:23:16 PM PDT 24
Peak memory 241880 kb
Host smart-41e9c0a8-90ff-4213-8e2e-8713d5c0712d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370040983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.370040983
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.3899106170
Short name T527
Test name
Test status
Simulation time 2797823029 ps
CPU time 27.02 seconds
Started Jun 27 07:25:58 PM PDT 24
Finished Jun 27 07:28:18 PM PDT 24
Peak memory 242416 kb
Host smart-4e91d2e8-5328-4b55-b451-9c7b6eeea218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899106170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.3899106170
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2962877799
Short name T386
Test name
Test status
Simulation time 992903880 ps
CPU time 7.64 seconds
Started Jun 27 07:23:38 PM PDT 24
Finished Jun 27 07:26:08 PM PDT 24
Peak memory 242364 kb
Host smart-e0916b1a-de04-447e-803c-f33d8e752d26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2962877799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2962877799
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1754320943
Short name T483
Test name
Test status
Simulation time 565547555 ps
CPU time 4.11 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:22:13 PM PDT 24
Peak memory 242064 kb
Host smart-b72baf64-be3a-44f3-b1f8-d42393bc5383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754320943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1754320943
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1327557396
Short name T540
Test name
Test status
Simulation time 4307577811 ps
CPU time 45.1 seconds
Started Jun 27 07:20:10 PM PDT 24
Finished Jun 27 07:23:32 PM PDT 24
Peak memory 243172 kb
Host smart-2f6662ad-5172-4c5c-aaee-5b3611dccfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327557396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1327557396
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2066110508
Short name T702
Test name
Test status
Simulation time 195973797 ps
CPU time 4.63 seconds
Started Jun 27 07:28:25 PM PDT 24
Finished Jun 27 07:30:35 PM PDT 24
Peak memory 242332 kb
Host smart-462f90f1-2196-49bb-ba00-c3b75e01e5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066110508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2066110508
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.1791687036
Short name T162
Test name
Test status
Simulation time 140430333 ps
CPU time 3.81 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:30:05 PM PDT 24
Peak memory 242084 kb
Host smart-11e8670b-38f0-4416-b353-39587f1daa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791687036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.1791687036
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.183080459
Short name T52
Test name
Test status
Simulation time 281707290 ps
CPU time 3.5 seconds
Started Jun 27 07:27:10 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 242252 kb
Host smart-bf91f767-1014-4caf-af80-833d5b1aa14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183080459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.183080459
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1763242376
Short name T551
Test name
Test status
Simulation time 2039755476 ps
CPU time 6.42 seconds
Started Jun 27 07:28:38 PM PDT 24
Finished Jun 27 07:30:37 PM PDT 24
Peak memory 242108 kb
Host smart-fba7902a-bc7b-46a4-9db7-01b9ed8f056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763242376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1763242376
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3735101702
Short name T190
Test name
Test status
Simulation time 120684620 ps
CPU time 3.26 seconds
Started Jun 27 07:28:22 PM PDT 24
Finished Jun 27 07:30:39 PM PDT 24
Peak memory 241928 kb
Host smart-950aa820-daaf-4af5-b49a-ce0969c1dc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735101702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3735101702
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.2653406375
Short name T148
Test name
Test status
Simulation time 153351637 ps
CPU time 3.8 seconds
Started Jun 27 07:28:14 PM PDT 24
Finished Jun 27 07:30:20 PM PDT 24
Peak memory 241820 kb
Host smart-1a1439ff-a222-4d6b-af39-39c8b7d166cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653406375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2653406375
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.3380490156
Short name T85
Test name
Test status
Simulation time 569056038 ps
CPU time 4.19 seconds
Started Jun 27 07:27:17 PM PDT 24
Finished Jun 27 07:29:47 PM PDT 24
Peak memory 242160 kb
Host smart-40ddc670-8624-4aee-9dec-8db4e8213510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380490156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3380490156
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.1540866944
Short name T1056
Test name
Test status
Simulation time 1419048643 ps
CPU time 3.86 seconds
Started Jun 27 07:27:17 PM PDT 24
Finished Jun 27 07:29:43 PM PDT 24
Peak memory 241848 kb
Host smart-bf7d0913-a2b5-4d8e-9fd7-49fd83aefabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540866944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1540866944
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.19066513
Short name T945
Test name
Test status
Simulation time 224849457 ps
CPU time 3.02 seconds
Started Jun 27 07:28:23 PM PDT 24
Finished Jun 27 07:31:04 PM PDT 24
Peak memory 241932 kb
Host smart-184e1ac4-49e1-46d9-a803-aa1daba4821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19066513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.19066513
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.3094088373
Short name T484
Test name
Test status
Simulation time 53978050 ps
CPU time 1.74 seconds
Started Jun 27 07:16:48 PM PDT 24
Finished Jun 27 07:19:12 PM PDT 24
Peak memory 240180 kb
Host smart-c9466900-436a-4481-ab97-6ba4afe3c3b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094088373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3094088373
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3955665924
Short name T680
Test name
Test status
Simulation time 1158948358 ps
CPU time 18.17 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:19:24 PM PDT 24
Peak memory 242240 kb
Host smart-743a23f9-499b-4de4-8753-4b3d8fa994d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955665924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3955665924
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.3814325755
Short name T528
Test name
Test status
Simulation time 432809468 ps
CPU time 7.77 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:19:14 PM PDT 24
Peak memory 242088 kb
Host smart-b2fbecd6-237d-4c41-b10d-c6a917f34892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814325755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.3814325755
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.319999558
Short name T670
Test name
Test status
Simulation time 344207082 ps
CPU time 8.72 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:19:15 PM PDT 24
Peak memory 242220 kb
Host smart-4d2399e6-d376-4691-ba8a-18aeea20aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319999558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.319999558
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.617600916
Short name T756
Test name
Test status
Simulation time 2744543560 ps
CPU time 27.14 seconds
Started Jun 27 07:16:49 PM PDT 24
Finished Jun 27 07:19:38 PM PDT 24
Peak memory 242144 kb
Host smart-428aa761-6941-4fd7-bce1-1e49f18a6739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617600916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.617600916
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.4004322912
Short name T563
Test name
Test status
Simulation time 1891528825 ps
CPU time 6.59 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:17 PM PDT 24
Peak memory 241820 kb
Host smart-a514d805-14fe-413b-96f2-3f0e2c344966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004322912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.4004322912
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.2936138542
Short name T705
Test name
Test status
Simulation time 1414377113 ps
CPU time 33.29 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:43 PM PDT 24
Peak memory 259592 kb
Host smart-cc83803a-b8de-46df-bc36-528e995ca4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936138542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.2936138542
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1691650307
Short name T970
Test name
Test status
Simulation time 10048444370 ps
CPU time 20.68 seconds
Started Jun 27 07:18:29 PM PDT 24
Finished Jun 27 07:21:10 PM PDT 24
Peak memory 248792 kb
Host smart-ca6385d2-78ec-4fee-a052-3c66d55a30d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691650307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1691650307
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2838008744
Short name T900
Test name
Test status
Simulation time 1267407757 ps
CPU time 4.61 seconds
Started Jun 27 07:16:46 PM PDT 24
Finished Jun 27 07:19:15 PM PDT 24
Peak memory 241872 kb
Host smart-4ca59f1d-3c52-412f-9d82-a869d41c0c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838008744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2838008744
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1472158455
Short name T1027
Test name
Test status
Simulation time 726579256 ps
CPU time 19.9 seconds
Started Jun 27 07:16:46 PM PDT 24
Finished Jun 27 07:20:06 PM PDT 24
Peak memory 241528 kb
Host smart-aa6a3d01-22ff-4e7f-8fa9-eb2f6cb64791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1472158455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1472158455
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.472012241
Short name T257
Test name
Test status
Simulation time 271988525 ps
CPU time 6.52 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:16 PM PDT 24
Peak memory 242028 kb
Host smart-d56a9a8a-0774-4ad0-abc3-431e9a8696b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472012241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.472012241
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.564169426
Short name T227
Test name
Test status
Simulation time 24945077251 ps
CPU time 189.75 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:22:18 PM PDT 24
Peak memory 278444 kb
Host smart-af7f31c8-a3cd-45bb-bc11-304c2b68b60c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564169426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.564169426
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.200759519
Short name T439
Test name
Test status
Simulation time 1429692621 ps
CPU time 9.19 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:19 PM PDT 24
Peak memory 241840 kb
Host smart-652c4a09-2132-4d48-a998-cf60f2be3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200759519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.200759519
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3150307604
Short name T19
Test name
Test status
Simulation time 93927306618 ps
CPU time 1305.51 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:40:53 PM PDT 24
Peak memory 266144 kb
Host smart-7dffc4a1-8fef-4d96-81cb-80d10826e84b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150307604 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3150307604
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.947290843
Short name T526
Test name
Test status
Simulation time 161378623 ps
CPU time 3.56 seconds
Started Jun 27 07:16:43 PM PDT 24
Finished Jun 27 07:19:09 PM PDT 24
Peak memory 242252 kb
Host smart-4431683e-7f79-4fee-96d9-71a61ec528d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947290843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.947290843
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3120432124
Short name T660
Test name
Test status
Simulation time 154795947 ps
CPU time 2.63 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:23:20 PM PDT 24
Peak memory 240484 kb
Host smart-e0eb9c49-5966-46ca-842d-a61fce537344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120432124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3120432124
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2902986190
Short name T780
Test name
Test status
Simulation time 644678200 ps
CPU time 15.93 seconds
Started Jun 27 07:21:38 PM PDT 24
Finished Jun 27 07:24:29 PM PDT 24
Peak memory 242080 kb
Host smart-d606a061-ceb1-4af9-861c-2115794c9b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902986190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2902986190
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.2753048083
Short name T642
Test name
Test status
Simulation time 1164533160 ps
CPU time 20.62 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:25:47 PM PDT 24
Peak memory 242472 kb
Host smart-3e9e2293-63d7-44f9-820c-56b768147f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753048083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2753048083
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.2305078795
Short name T197
Test name
Test status
Simulation time 376682685 ps
CPU time 4.54 seconds
Started Jun 27 07:23:29 PM PDT 24
Finished Jun 27 07:26:26 PM PDT 24
Peak memory 242120 kb
Host smart-d29175f6-e443-479e-b966-2e0c53b28d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305078795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2305078795
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2040887921
Short name T853
Test name
Test status
Simulation time 652858360 ps
CPU time 16.11 seconds
Started Jun 27 07:21:24 PM PDT 24
Finished Jun 27 07:24:18 PM PDT 24
Peak memory 245648 kb
Host smart-230cb319-98bb-4a89-8d2d-1e9e6596bf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040887921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2040887921
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.654312317
Short name T514
Test name
Test status
Simulation time 776262447 ps
CPU time 4.97 seconds
Started Jun 27 07:20:21 PM PDT 24
Finished Jun 27 07:22:52 PM PDT 24
Peak memory 242312 kb
Host smart-faeefd19-63ca-4d6a-8972-f2838393a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654312317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.654312317
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1135132602
Short name T269
Test name
Test status
Simulation time 1838947037 ps
CPU time 4.18 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:15 PM PDT 24
Peak memory 242116 kb
Host smart-3f6dabe8-bf2b-45fe-a776-56b9a1124cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135132602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1135132602
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2264509068
Short name T596
Test name
Test status
Simulation time 273803364 ps
CPU time 3.95 seconds
Started Jun 27 07:20:09 PM PDT 24
Finished Jun 27 07:22:13 PM PDT 24
Peak memory 242256 kb
Host smart-3537cf8e-0928-4f50-b7cf-2412a99fc300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264509068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2264509068
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.1128263118
Short name T573
Test name
Test status
Simulation time 9899352323 ps
CPU time 65.12 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:26:32 PM PDT 24
Peak memory 248804 kb
Host smart-fb7d7cd4-7634-4c6d-b29a-3396078b8685
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128263118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.1128263118
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.761154300
Short name T1008
Test name
Test status
Simulation time 13256527416 ps
CPU time 37.58 seconds
Started Jun 27 07:21:37 PM PDT 24
Finished Jun 27 07:24:51 PM PDT 24
Peak memory 242488 kb
Host smart-fca8abec-84e5-4aa4-93f4-b3fa58a731d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761154300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.761154300
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.2075118978
Short name T997
Test name
Test status
Simulation time 181558395 ps
CPU time 1.6 seconds
Started Jun 27 07:23:44 PM PDT 24
Finished Jun 27 07:26:14 PM PDT 24
Peak memory 240184 kb
Host smart-f0f9fd5e-6c6f-445f-8cde-a139e8fed00a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075118978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2075118978
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.2138431591
Short name T669
Test name
Test status
Simulation time 20218369991 ps
CPU time 35.14 seconds
Started Jun 27 07:21:38 PM PDT 24
Finished Jun 27 07:24:58 PM PDT 24
Peak memory 242848 kb
Host smart-caa8bbec-7344-465d-9d83-6ef5a87a6339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138431591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.2138431591
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.234783748
Short name T766
Test name
Test status
Simulation time 267621184 ps
CPU time 5.2 seconds
Started Jun 27 07:20:20 PM PDT 24
Finished Jun 27 07:23:04 PM PDT 24
Peak memory 242044 kb
Host smart-024852a3-9d62-40aa-8334-4dcfc2216a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234783748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.234783748
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.2757102734
Short name T843
Test name
Test status
Simulation time 354107861 ps
CPU time 5.53 seconds
Started Jun 27 07:20:37 PM PDT 24
Finished Jun 27 07:22:57 PM PDT 24
Peak memory 242060 kb
Host smart-87da11d7-e932-4dda-8d81-ee948cee0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757102734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.2757102734
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2849212818
Short name T707
Test name
Test status
Simulation time 1692386436 ps
CPU time 16.71 seconds
Started Jun 27 07:20:35 PM PDT 24
Finished Jun 27 07:23:08 PM PDT 24
Peak memory 242304 kb
Host smart-46810a5d-6bc9-4280-9a99-34608bf1dca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849212818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2849212818
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.4100429233
Short name T740
Test name
Test status
Simulation time 177868059 ps
CPU time 3.69 seconds
Started Jun 27 07:24:26 PM PDT 24
Finished Jun 27 07:26:58 PM PDT 24
Peak memory 242368 kb
Host smart-415138ac-fc47-4948-9ffb-0558fdc1428c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100429233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.4100429233
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.2492111743
Short name T561
Test name
Test status
Simulation time 2488386290 ps
CPU time 5.97 seconds
Started Jun 27 07:21:51 PM PDT 24
Finished Jun 27 07:24:31 PM PDT 24
Peak memory 242060 kb
Host smart-6eab1942-a808-4f51-845f-7fb7954a6a84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2492111743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2492111743
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.1801003424
Short name T525
Test name
Test status
Simulation time 427449046 ps
CPU time 5.07 seconds
Started Jun 27 07:20:32 PM PDT 24
Finished Jun 27 07:24:03 PM PDT 24
Peak memory 242076 kb
Host smart-b96fd530-54ec-498c-8ad3-99e777f1e1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801003424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1801003424
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2180078252
Short name T345
Test name
Test status
Simulation time 368375315436 ps
CPU time 1189.61 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:44:09 PM PDT 24
Peak memory 326200 kb
Host smart-1b0871cd-18a0-489e-805c-a482363617cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180078252 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.2180078252
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.749178409
Short name T174
Test name
Test status
Simulation time 17142989891 ps
CPU time 39.03 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:24:05 PM PDT 24
Peak memory 243132 kb
Host smart-4015de37-ae56-4033-9ec3-69af0a5da164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749178409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.749178409
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2266730905
Short name T802
Test name
Test status
Simulation time 1046372390 ps
CPU time 1.96 seconds
Started Jun 27 07:22:19 PM PDT 24
Finished Jun 27 07:24:35 PM PDT 24
Peak memory 240480 kb
Host smart-a8fa6f06-58bd-44be-a6a9-c2b2074385f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266730905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2266730905
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.3616917628
Short name T1018
Test name
Test status
Simulation time 22793094929 ps
CPU time 34.46 seconds
Started Jun 27 07:20:51 PM PDT 24
Finished Jun 27 07:24:49 PM PDT 24
Peak memory 248856 kb
Host smart-0222fb49-06b8-4ca7-8386-51c9bf8f24af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616917628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3616917628
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.817781449
Short name T873
Test name
Test status
Simulation time 1022907956 ps
CPU time 30.88 seconds
Started Jun 27 07:20:44 PM PDT 24
Finished Jun 27 07:23:37 PM PDT 24
Peak memory 246648 kb
Host smart-e12da5ff-4a8c-4e20-9593-22d3d25f4a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817781449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.817781449
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1835752656
Short name T105
Test name
Test status
Simulation time 352751163 ps
CPU time 11.15 seconds
Started Jun 27 07:20:43 PM PDT 24
Finished Jun 27 07:23:02 PM PDT 24
Peak memory 241956 kb
Host smart-949d471b-8619-40f3-8983-f663c68e200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835752656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1835752656
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.2964423438
Short name T38
Test name
Test status
Simulation time 302330565 ps
CPU time 4.48 seconds
Started Jun 27 07:21:52 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 242116 kb
Host smart-a3274a01-ed0a-4a00-af58-d9c620f1ae77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964423438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2964423438
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.3306702000
Short name T776
Test name
Test status
Simulation time 510809558 ps
CPU time 12.61 seconds
Started Jun 27 07:22:09 PM PDT 24
Finished Jun 27 07:24:54 PM PDT 24
Peak memory 242220 kb
Host smart-493018bf-b5f2-4a95-a974-b52a8810c14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306702000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3306702000
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.3614345578
Short name T535
Test name
Test status
Simulation time 2137307312 ps
CPU time 7.23 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:25:01 PM PDT 24
Peak memory 241916 kb
Host smart-339e44b0-1a69-4750-b036-93fac72edbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614345578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.3614345578
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.1394086213
Short name T995
Test name
Test status
Simulation time 257857741 ps
CPU time 5.45 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:24:38 PM PDT 24
Peak memory 242272 kb
Host smart-0ada6d46-78a8-41fb-9e04-ab320825f223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394086213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.1394086213
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.323384499
Short name T9
Test name
Test status
Simulation time 2137259251 ps
CPU time 4.28 seconds
Started Jun 27 07:20:37 PM PDT 24
Finished Jun 27 07:22:55 PM PDT 24
Peak memory 242164 kb
Host smart-c1004e5a-10e1-4988-b4e0-84c38a496276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323384499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.323384499
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.3048453296
Short name T248
Test name
Test status
Simulation time 45361748248 ps
CPU time 118.05 seconds
Started Jun 27 07:20:43 PM PDT 24
Finished Jun 27 07:25:59 PM PDT 24
Peak memory 248812 kb
Host smart-b1d7ea39-2d0a-4c66-ba98-ca45fc98ec50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048453296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.3048453296
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2626966500
Short name T827
Test name
Test status
Simulation time 41062354116 ps
CPU time 475.11 seconds
Started Jun 27 07:20:37 PM PDT 24
Finished Jun 27 07:32:20 PM PDT 24
Peak memory 257100 kb
Host smart-f6a013f7-62a1-444f-9d40-59f262914e6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626966500 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2626966500
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1002310674
Short name T499
Test name
Test status
Simulation time 473508089 ps
CPU time 10.88 seconds
Started Jun 27 07:21:43 PM PDT 24
Finished Jun 27 07:24:13 PM PDT 24
Peak memory 248804 kb
Host smart-cbf32a3d-be3a-4dcd-86ca-bae89cc07238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002310674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1002310674
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.3165443653
Short name T1039
Test name
Test status
Simulation time 92013768 ps
CPU time 1.61 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:24:00 PM PDT 24
Peak memory 240640 kb
Host smart-c43ff6f4-df15-45cd-bd25-b17be9bcec1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165443653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3165443653
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.1692646080
Short name T750
Test name
Test status
Simulation time 16188373232 ps
CPU time 20.52 seconds
Started Jun 27 07:22:18 PM PDT 24
Finished Jun 27 07:24:53 PM PDT 24
Peak memory 248812 kb
Host smart-b090db61-ec36-4131-b2b7-ab751fa09713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692646080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.1692646080
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.665636689
Short name T1057
Test name
Test status
Simulation time 726386317 ps
CPU time 7.3 seconds
Started Jun 27 07:22:19 PM PDT 24
Finished Jun 27 07:25:00 PM PDT 24
Peak memory 242248 kb
Host smart-8b7f348d-140d-4b8c-adcf-3125c993df18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665636689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.665636689
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.1441401586
Short name T137
Test name
Test status
Simulation time 870167029 ps
CPU time 16.54 seconds
Started Jun 27 07:20:37 PM PDT 24
Finished Jun 27 07:23:08 PM PDT 24
Peak memory 242684 kb
Host smart-6952a77a-8553-44d0-8f20-b3caec4e8228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441401586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.1441401586
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3832417519
Short name T935
Test name
Test status
Simulation time 3271278172 ps
CPU time 12.91 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:23:20 PM PDT 24
Peak memory 242432 kb
Host smart-e55aab55-3178-44c5-a25b-8dd78625dd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832417519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3832417519
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.584402877
Short name T981
Test name
Test status
Simulation time 1862829723 ps
CPU time 4.38 seconds
Started Jun 27 07:22:03 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 242200 kb
Host smart-2840d9aa-46f9-4900-8c3f-faf5aab781f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584402877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.584402877
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.217585407
Short name T951
Test name
Test status
Simulation time 4408898574 ps
CPU time 12.11 seconds
Started Jun 27 07:20:36 PM PDT 24
Finished Jun 27 07:23:12 PM PDT 24
Peak memory 242028 kb
Host smart-fc1d9515-7ff5-4135-a0ef-82f3cf75e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217585407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.217585407
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.4239344499
Short name T627
Test name
Test status
Simulation time 25966194414 ps
CPU time 475.35 seconds
Started Jun 27 07:24:25 PM PDT 24
Finished Jun 27 07:35:23 PM PDT 24
Peak memory 257096 kb
Host smart-1faf977f-70a1-4a6f-972f-859918aa3af9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239344499 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.4239344499
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2088067451
Short name T1002
Test name
Test status
Simulation time 1074765284 ps
CPU time 18.82 seconds
Started Jun 27 07:23:38 PM PDT 24
Finished Jun 27 07:27:07 PM PDT 24
Peak memory 242504 kb
Host smart-7587b028-236a-4ab5-ac53-264c58db46d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088067451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2088067451
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.3450685082
Short name T414
Test name
Test status
Simulation time 122581650 ps
CPU time 1.87 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:23:59 PM PDT 24
Peak memory 240152 kb
Host smart-75d55262-abed-4bb9-ac7b-63c6b4882e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450685082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3450685082
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.3090858893
Short name T960
Test name
Test status
Simulation time 129428617 ps
CPU time 3.52 seconds
Started Jun 27 07:20:51 PM PDT 24
Finished Jun 27 07:23:17 PM PDT 24
Peak memory 248764 kb
Host smart-2a2861e8-1b17-4fb2-9cfc-73697f4dbe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090858893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.3090858893
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.143051843
Short name T657
Test name
Test status
Simulation time 5602100138 ps
CPU time 22.84 seconds
Started Jun 27 07:27:28 PM PDT 24
Finished Jun 27 07:30:12 PM PDT 24
Peak memory 242116 kb
Host smart-332403f1-2c68-497c-ba33-6d3f46cdc1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143051843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.143051843
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.994181294
Short name T646
Test name
Test status
Simulation time 532589761 ps
CPU time 3.74 seconds
Started Jun 27 07:22:03 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 242356 kb
Host smart-e103e75c-45a7-4963-9684-641c8bc16cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994181294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.994181294
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.1281222895
Short name T1029
Test name
Test status
Simulation time 9592634994 ps
CPU time 25.28 seconds
Started Jun 27 07:20:52 PM PDT 24
Finished Jun 27 07:23:39 PM PDT 24
Peak memory 245440 kb
Host smart-86d05887-d26f-4710-aa80-c53779167be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281222895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1281222895
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.1715239265
Short name T1005
Test name
Test status
Simulation time 1121560458 ps
CPU time 14.21 seconds
Started Jun 27 07:20:50 PM PDT 24
Finished Jun 27 07:24:52 PM PDT 24
Peak memory 242176 kb
Host smart-a4cdf662-c44e-4161-8f28-7d4170201d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715239265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1715239265
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3737794896
Short name T569
Test name
Test status
Simulation time 1482036526 ps
CPU time 23.19 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 07:27:28 PM PDT 24
Peak memory 242356 kb
Host smart-91852bae-e8e5-48a4-8781-8dc20cec92a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737794896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3737794896
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.858088713
Short name T594
Test name
Test status
Simulation time 3776085598 ps
CPU time 9.27 seconds
Started Jun 27 07:22:28 PM PDT 24
Finished Jun 27 07:24:41 PM PDT 24
Peak memory 242152 kb
Host smart-0ea1a98b-bd82-4678-af3d-e02f62bc18cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=858088713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.858088713
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3131821754
Short name T290
Test name
Test status
Simulation time 15431257902 ps
CPU time 190.86 seconds
Started Jun 27 07:23:18 PM PDT 24
Finished Jun 27 07:30:02 PM PDT 24
Peak memory 257096 kb
Host smart-4b5f916d-5b1e-4d5e-b6b3-e1c1b02b2930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131821754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3131821754
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.3731885452
Short name T343
Test name
Test status
Simulation time 83190332737 ps
CPU time 1140.19 seconds
Started Jun 27 07:20:53 PM PDT 24
Finished Jun 27 07:42:18 PM PDT 24
Peak memory 466004 kb
Host smart-12c5b117-20dd-4212-948f-69547c0b6e2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731885452 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.3731885452
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2578851365
Short name T831
Test name
Test status
Simulation time 146844854 ps
CPU time 1.53 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:23:28 PM PDT 24
Peak memory 240180 kb
Host smart-508239b1-6485-431f-88dd-9cf890d63092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578851365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2578851365
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1164859029
Short name T400
Test name
Test status
Simulation time 11551233169 ps
CPU time 23.33 seconds
Started Jun 27 07:21:01 PM PDT 24
Finished Jun 27 07:23:31 PM PDT 24
Peak memory 248884 kb
Host smart-c089fc68-2a62-40b9-b471-c24d37fd7d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164859029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1164859029
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2397692499
Short name T104
Test name
Test status
Simulation time 4971482477 ps
CPU time 33.88 seconds
Started Jun 27 07:21:03 PM PDT 24
Finished Jun 27 07:23:41 PM PDT 24
Peak memory 242240 kb
Host smart-0afafb10-08c6-4fff-93a0-b385423817df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397692499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2397692499
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1328452119
Short name T416
Test name
Test status
Simulation time 484552583 ps
CPU time 4.45 seconds
Started Jun 27 07:21:02 PM PDT 24
Finished Jun 27 07:23:12 PM PDT 24
Peak memory 241900 kb
Host smart-e4217bbe-77aa-4c62-8912-99a3ce596e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328452119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1328452119
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3316869005
Short name T321
Test name
Test status
Simulation time 858171123 ps
CPU time 6.67 seconds
Started Jun 27 07:21:10 PM PDT 24
Finished Jun 27 07:24:40 PM PDT 24
Peak memory 248716 kb
Host smart-8cdf059a-0dc6-40f7-984a-a72055fc68a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316869005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3316869005
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3346502642
Short name T149
Test name
Test status
Simulation time 419221959 ps
CPU time 4.72 seconds
Started Jun 27 07:21:07 PM PDT 24
Finished Jun 27 07:24:07 PM PDT 24
Peak memory 241880 kb
Host smart-bfda6258-fd2d-40db-a7e4-c06aee77135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346502642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3346502642
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.80852204
Short name T309
Test name
Test status
Simulation time 296597447 ps
CPU time 5.48 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:25:29 PM PDT 24
Peak memory 242048 kb
Host smart-206dd34a-e94c-4c61-9379-dc377d6a9615
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80852204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.80852204
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.575684766
Short name T381
Test name
Test status
Simulation time 250494942 ps
CPU time 8.69 seconds
Started Jun 27 07:21:02 PM PDT 24
Finished Jun 27 07:23:16 PM PDT 24
Peak memory 242036 kb
Host smart-f4bbe248-be04-43c6-ba71-ff05b2b416e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=575684766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.575684766
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.851490311
Short name T2
Test name
Test status
Simulation time 4551241908 ps
CPU time 7.45 seconds
Started Jun 27 07:21:10 PM PDT 24
Finished Jun 27 07:23:26 PM PDT 24
Peak memory 242680 kb
Host smart-082d0815-95a8-4dfb-a742-d69486abf64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851490311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.851490311
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3522349937
Short name T785
Test name
Test status
Simulation time 92269989087 ps
CPU time 1426.71 seconds
Started Jun 27 07:22:15 PM PDT 24
Finished Jun 27 07:48:20 PM PDT 24
Peak memory 310216 kb
Host smart-17f6f643-fb61-4e82-b5aa-f0912c1f347e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522349937 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.3522349937
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.3565144485
Short name T597
Test name
Test status
Simulation time 142451618 ps
CPU time 2.04 seconds
Started Jun 27 07:21:15 PM PDT 24
Finished Jun 27 07:24:04 PM PDT 24
Peak memory 240156 kb
Host smart-551f1304-b6ad-443d-88e3-145bbb676427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565144485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.3565144485
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.66198977
Short name T987
Test name
Test status
Simulation time 854788073 ps
CPU time 5.64 seconds
Started Jun 27 07:27:17 PM PDT 24
Finished Jun 27 07:29:58 PM PDT 24
Peak memory 248720 kb
Host smart-6c2ab85c-5ce4-4d1d-9580-955762cde9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66198977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.66198977
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.660371498
Short name T1045
Test name
Test status
Simulation time 1774593996 ps
CPU time 23.74 seconds
Started Jun 27 07:21:01 PM PDT 24
Finished Jun 27 07:23:42 PM PDT 24
Peak memory 242128 kb
Host smart-3a244dcc-afb1-4a68-a472-ec77c3acd0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660371498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.660371498
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.2033385027
Short name T529
Test name
Test status
Simulation time 678836516 ps
CPU time 12.58 seconds
Started Jun 27 07:21:07 PM PDT 24
Finished Jun 27 07:24:10 PM PDT 24
Peak memory 242292 kb
Host smart-7f244f00-6122-435a-b9d2-e906e825bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033385027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2033385027
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2485666895
Short name T807
Test name
Test status
Simulation time 2916507592 ps
CPU time 5.9 seconds
Started Jun 27 07:21:10 PM PDT 24
Finished Jun 27 07:23:24 PM PDT 24
Peak memory 242748 kb
Host smart-321d5f65-053f-4a36-b94e-e9df3cce23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485666895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2485666895
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.1655610732
Short name T734
Test name
Test status
Simulation time 13694582731 ps
CPU time 25.79 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:24:23 PM PDT 24
Peak memory 248872 kb
Host smart-dcb5002f-f285-45ad-8e50-bb41704a0498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655610732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.1655610732
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.4281244712
Short name T790
Test name
Test status
Simulation time 711434662 ps
CPU time 17.15 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:23:35 PM PDT 24
Peak memory 242408 kb
Host smart-a6400094-83ad-418f-b5f3-cc042b67bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281244712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.4281244712
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2760906436
Short name T244
Test name
Test status
Simulation time 381443761 ps
CPU time 9.69 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:24:23 PM PDT 24
Peak memory 241816 kb
Host smart-9b2192c2-b9cf-4bdd-af5c-7124f6911cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760906436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2760906436
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3225935975
Short name T1011
Test name
Test status
Simulation time 1042302874 ps
CPU time 13.98 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:26:27 PM PDT 24
Peak memory 241992 kb
Host smart-73bd0969-fff2-4f16-9140-f3e15938e3de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225935975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3225935975
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3984288305
Short name T985
Test name
Test status
Simulation time 503799219 ps
CPU time 9.71 seconds
Started Jun 27 07:21:09 PM PDT 24
Finished Jun 27 07:24:35 PM PDT 24
Peak memory 242244 kb
Host smart-648e8fe2-fe09-485b-83ab-ae05dffc762a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984288305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3984288305
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.3796501442
Short name T236
Test name
Test status
Simulation time 50625891234 ps
CPU time 209.7 seconds
Started Jun 27 07:21:15 PM PDT 24
Finished Jun 27 07:26:44 PM PDT 24
Peak memory 256936 kb
Host smart-7be21368-a94d-49ff-8269-7bbcd293a6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796501442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.3796501442
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1173421224
Short name T395
Test name
Test status
Simulation time 20197040523 ps
CPU time 476.42 seconds
Started Jun 27 07:21:29 PM PDT 24
Finished Jun 27 07:31:54 PM PDT 24
Peak memory 257096 kb
Host smart-3bb599da-01f3-4acc-bd01-8c3ae6689092
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173421224 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1173421224
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.1601182851
Short name T391
Test name
Test status
Simulation time 5109171792 ps
CPU time 11.19 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:23:38 PM PDT 24
Peak memory 242548 kb
Host smart-1949a647-27a1-48b4-baf2-6f8c7465ebb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601182851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1601182851
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.855318712
Short name T933
Test name
Test status
Simulation time 610299526 ps
CPU time 2.08 seconds
Started Jun 27 07:21:24 PM PDT 24
Finished Jun 27 07:24:03 PM PDT 24
Peak memory 240168 kb
Host smart-e12dc57f-5b6a-478b-864e-2f37e8ebd6c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855318712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.855318712
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3920823200
Short name T1049
Test name
Test status
Simulation time 1804572979 ps
CPU time 16.03 seconds
Started Jun 27 07:21:17 PM PDT 24
Finished Jun 27 07:24:14 PM PDT 24
Peak memory 241888 kb
Host smart-a37772ae-0d7e-451d-8de3-321e8b72961d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920823200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3920823200
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.3378836520
Short name T459
Test name
Test status
Simulation time 3196994834 ps
CPU time 38.41 seconds
Started Jun 27 07:30:03 PM PDT 24
Finished Jun 27 07:33:05 PM PDT 24
Peak memory 242140 kb
Host smart-28b66baa-1d1e-4426-bca9-36c9ca051c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378836520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3378836520
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.4058110213
Short name T773
Test name
Test status
Simulation time 264922463 ps
CPU time 3.69 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:24:17 PM PDT 24
Peak memory 242476 kb
Host smart-8e08c0fd-9826-40eb-b36b-7c43a95816cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058110213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.4058110213
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.3621816065
Short name T931
Test name
Test status
Simulation time 15713119935 ps
CPU time 23.81 seconds
Started Jun 27 07:21:22 PM PDT 24
Finished Jun 27 07:24:09 PM PDT 24
Peak memory 248496 kb
Host smart-5053890f-8c56-47a4-8349-a6fe3a494fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621816065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3621816065
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.2436544781
Short name T517
Test name
Test status
Simulation time 660404927 ps
CPU time 7.74 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:23:33 PM PDT 24
Peak memory 241860 kb
Host smart-52d9d040-3e05-4d20-9e7f-72d17607f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436544781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2436544781
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.2827928780
Short name T745
Test name
Test status
Simulation time 495589883 ps
CPU time 8.4 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:24:10 PM PDT 24
Peak memory 241940 kb
Host smart-d788ba47-ffb8-4879-b382-e9c13e1e5f77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827928780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.2827928780
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1733425892
Short name T452
Test name
Test status
Simulation time 459751402 ps
CPU time 12.42 seconds
Started Jun 27 07:26:10 PM PDT 24
Finished Jun 27 07:29:06 PM PDT 24
Peak memory 242312 kb
Host smart-30989b6e-04d1-448f-b0c2-07b98a21cf49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1733425892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1733425892
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.103353672
Short name T574
Test name
Test status
Simulation time 2414657653 ps
CPU time 8.28 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:24:10 PM PDT 24
Peak memory 242540 kb
Host smart-109690c8-0c44-4908-ae0a-19a9d2417df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103353672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.103353672
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.3370626838
Short name T886
Test name
Test status
Simulation time 8281357268 ps
CPU time 102.39 seconds
Started Jun 27 07:21:38 PM PDT 24
Finished Jun 27 07:26:05 PM PDT 24
Peak memory 248156 kb
Host smart-92a89891-167c-4009-9e7f-3049bf59c2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370626838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.3370626838
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3830692047
Short name T940
Test name
Test status
Simulation time 1951973740 ps
CPU time 17.29 seconds
Started Jun 27 07:22:38 PM PDT 24
Finished Jun 27 07:26:06 PM PDT 24
Peak memory 242412 kb
Host smart-97edd33b-e374-4423-bce6-03a948c51d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830692047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3830692047
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.404928101
Short name T1019
Test name
Test status
Simulation time 773703557 ps
CPU time 2.2 seconds
Started Jun 27 07:21:15 PM PDT 24
Finished Jun 27 07:24:05 PM PDT 24
Peak memory 240048 kb
Host smart-8a5bd4f5-e6b9-4314-9629-9a4cff1bc6e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404928101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.404928101
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3875209554
Short name T112
Test name
Test status
Simulation time 11799500270 ps
CPU time 21.81 seconds
Started Jun 27 07:21:52 PM PDT 24
Finished Jun 27 07:24:55 PM PDT 24
Peak memory 243272 kb
Host smart-895769db-6130-4080-87dd-483e0cb83a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875209554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3875209554
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.2386006243
Short name T62
Test name
Test status
Simulation time 502650936 ps
CPU time 5.16 seconds
Started Jun 27 07:21:22 PM PDT 24
Finished Jun 27 07:24:07 PM PDT 24
Peak memory 242240 kb
Host smart-d9b9d8cf-5c01-48ad-a154-210a5cf04414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386006243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.2386006243
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1861372160
Short name T718
Test name
Test status
Simulation time 681070200 ps
CPU time 18.71 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:24:20 PM PDT 24
Peak memory 242716 kb
Host smart-77023f96-9507-4090-bbf0-45c5bedbf54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861372160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1861372160
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.942001052
Short name T98
Test name
Test status
Simulation time 1112404286 ps
CPU time 10.94 seconds
Started Jun 27 07:24:18 PM PDT 24
Finished Jun 27 07:26:43 PM PDT 24
Peak memory 242120 kb
Host smart-12fdd5a1-3608-4c95-9fca-544da1ca9783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942001052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.942001052
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3201039176
Short name T656
Test name
Test status
Simulation time 110047103 ps
CPU time 3.52 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:24:05 PM PDT 24
Peak memory 241572 kb
Host smart-de2d4fa2-65bd-43f2-ba8b-9ed410472ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201039176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3201039176
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.1440465403
Short name T307
Test name
Test status
Simulation time 285771030 ps
CPU time 8.2 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:23:42 PM PDT 24
Peak memory 242048 kb
Host smart-cf20847a-6098-443c-bf98-134113b4d1e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1440465403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.1440465403
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3975212276
Short name T291
Test name
Test status
Simulation time 172963989 ps
CPU time 4.21 seconds
Started Jun 27 07:21:20 PM PDT 24
Finished Jun 27 07:24:04 PM PDT 24
Peak memory 242472 kb
Host smart-39840cc7-8b09-4d80-8931-52c2567b8a86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3975212276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3975212276
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.2110609975
Short name T615
Test name
Test status
Simulation time 195627146 ps
CPU time 4.86 seconds
Started Jun 27 07:21:17 PM PDT 24
Finished Jun 27 07:23:31 PM PDT 24
Peak memory 242164 kb
Host smart-60963c6c-8867-4d1f-84a7-a683d0200665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110609975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2110609975
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3266223938
Short name T579
Test name
Test status
Simulation time 18712711292 ps
CPU time 182.32 seconds
Started Jun 27 07:21:22 PM PDT 24
Finished Jun 27 07:27:15 PM PDT 24
Peak memory 245840 kb
Host smart-eb3fa327-fa3b-4f8c-9887-b9fd62d7b427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266223938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3266223938
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.559833721
Short name T276
Test name
Test status
Simulation time 192711119702 ps
CPU time 2661.97 seconds
Started Jun 27 07:21:15 PM PDT 24
Finished Jun 27 08:08:45 PM PDT 24
Peak memory 283864 kb
Host smart-c74f15b2-6a72-4757-8f46-957efdee4205
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559833721 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.559833721
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3634472943
Short name T763
Test name
Test status
Simulation time 1070990418 ps
CPU time 10.11 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:24:08 PM PDT 24
Peak memory 242316 kb
Host smart-8d9e9b81-b2fa-4b4c-84ec-1ecca1041e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634472943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3634472943
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.3084593365
Short name T262
Test name
Test status
Simulation time 122558279 ps
CPU time 1.75 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:25:24 PM PDT 24
Peak memory 240180 kb
Host smart-a398f327-224e-4a90-9292-dcc1e72a1c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084593365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3084593365
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.1819577733
Short name T394
Test name
Test status
Simulation time 269433496 ps
CPU time 9.92 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:23:28 PM PDT 24
Peak memory 242636 kb
Host smart-34a0b15c-854b-4c96-9d8b-aace7047e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819577733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1819577733
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1200982896
Short name T675
Test name
Test status
Simulation time 2126639729 ps
CPU time 14.7 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:27:33 PM PDT 24
Peak memory 242368 kb
Host smart-6685ccfa-5c64-481c-a078-7ff89b3d853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200982896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1200982896
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.882542123
Short name T404
Test name
Test status
Simulation time 337223492 ps
CPU time 10.99 seconds
Started Jun 27 07:24:31 PM PDT 24
Finished Jun 27 07:27:16 PM PDT 24
Peak memory 242332 kb
Host smart-f4218b67-9d2f-4ee8-96e1-a6f20af78de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882542123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.882542123
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.1410231989
Short name T122
Test name
Test status
Simulation time 555724465 ps
CPU time 3.99 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:24:24 PM PDT 24
Peak memory 242136 kb
Host smart-81e6bc6a-9e3d-4d75-9321-1de950f7346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410231989 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1410231989
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.842821450
Short name T820
Test name
Test status
Simulation time 974506178 ps
CPU time 14.11 seconds
Started Jun 27 07:21:21 PM PDT 24
Finished Jun 27 07:24:27 PM PDT 24
Peak memory 243888 kb
Host smart-7295571f-17da-47d7-9b6d-6418ec1332c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842821450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.842821450
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2868855283
Short name T581
Test name
Test status
Simulation time 268864402 ps
CPU time 9.93 seconds
Started Jun 27 07:21:18 PM PDT 24
Finished Jun 27 07:23:28 PM PDT 24
Peak memory 242296 kb
Host smart-ee71c7eb-e465-4772-ad4e-5d70020ee52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868855283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2868855283
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3749953716
Short name T1014
Test name
Test status
Simulation time 303564194 ps
CPU time 4.84 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:24:03 PM PDT 24
Peak memory 242312 kb
Host smart-b01d8d99-aa5c-4e89-bcc5-67c1baa21387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749953716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3749953716
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1376383607
Short name T473
Test name
Test status
Simulation time 246788920 ps
CPU time 7.39 seconds
Started Jun 27 07:21:52 PM PDT 24
Finished Jun 27 07:24:33 PM PDT 24
Peak memory 241920 kb
Host smart-cf0eb62d-8f4e-4ca7-8208-30632437d8e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1376383607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1376383607
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.963163195
Short name T753
Test name
Test status
Simulation time 136408891 ps
CPU time 5.15 seconds
Started Jun 27 07:21:19 PM PDT 24
Finished Jun 27 07:24:02 PM PDT 24
Peak memory 242316 kb
Host smart-98e1ef5c-a3ef-4c9b-a67e-0dae56760fe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=963163195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.963163195
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.2522834014
Short name T410
Test name
Test status
Simulation time 200035116 ps
CPU time 4.33 seconds
Started Jun 27 07:21:21 PM PDT 24
Finished Jun 27 07:24:30 PM PDT 24
Peak memory 241872 kb
Host smart-afd0cd73-03cb-450a-8ad3-e914bdaeff13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522834014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.2522834014
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2478725648
Short name T929
Test name
Test status
Simulation time 59354763598 ps
CPU time 458.59 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:34:18 PM PDT 24
Peak memory 259164 kb
Host smart-b15785ab-6f53-475f-adf9-cb9c7759ffd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478725648 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2478725648
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.644683012
Short name T277
Test name
Test status
Simulation time 2296166540 ps
CPU time 19.01 seconds
Started Jun 27 07:21:14 PM PDT 24
Finished Jun 27 07:24:21 PM PDT 24
Peak memory 242280 kb
Host smart-3067b0ee-bd86-4e58-9e2b-49820f7b0437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644683012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.644683012
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2937410277
Short name T407
Test name
Test status
Simulation time 97734085 ps
CPU time 1.71 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:19 PM PDT 24
Peak memory 240172 kb
Host smart-4d4e5d4d-10f8-442f-ac82-c1ebe2dd0524
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937410277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2937410277
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.4130697267
Short name T1025
Test name
Test status
Simulation time 1234005374 ps
CPU time 22.06 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:32 PM PDT 24
Peak memory 248776 kb
Host smart-ad9dbd4a-0d45-4664-8c76-c799f0179eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130697267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.4130697267
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.693884559
Short name T209
Test name
Test status
Simulation time 426897401 ps
CPU time 11.93 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:19:20 PM PDT 24
Peak memory 241948 kb
Host smart-51ee144a-3f0d-445a-8ef2-563a99475ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693884559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.693884559
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1329209595
Short name T178
Test name
Test status
Simulation time 2459096737 ps
CPU time 7.53 seconds
Started Jun 27 07:16:43 PM PDT 24
Finished Jun 27 07:19:13 PM PDT 24
Peak memory 242552 kb
Host smart-62a50383-7e07-4f60-a96f-b04319b6ed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329209595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1329209595
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3990055619
Short name T189
Test name
Test status
Simulation time 2144744092 ps
CPU time 5.86 seconds
Started Jun 27 07:17:21 PM PDT 24
Finished Jun 27 07:20:24 PM PDT 24
Peak memory 241788 kb
Host smart-5648e461-5e24-45bc-add7-fd5a6c2941ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990055619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3990055619
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.3049998394
Short name T485
Test name
Test status
Simulation time 693653209 ps
CPU time 5.22 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:23 PM PDT 24
Peak memory 242404 kb
Host smart-23f8b266-9128-49cf-b713-491cf24f6f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049998394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.3049998394
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.1625825788
Short name T544
Test name
Test status
Simulation time 1153248948 ps
CPU time 7.26 seconds
Started Jun 27 07:16:44 PM PDT 24
Finished Jun 27 07:19:14 PM PDT 24
Peak memory 242208 kb
Host smart-ceeaeba5-0f56-48a0-9b4f-741eae56fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625825788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1625825788
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.620179582
Short name T150
Test name
Test status
Simulation time 2234061459 ps
CPU time 16.15 seconds
Started Jun 27 07:16:47 PM PDT 24
Finished Jun 27 07:19:26 PM PDT 24
Peak memory 248728 kb
Host smart-3f55bf86-0f9f-49b1-be96-eadd562bbfa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=620179582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.620179582
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.4163596074
Short name T643
Test name
Test status
Simulation time 1176625762 ps
CPU time 9.21 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:27 PM PDT 24
Peak memory 242088 kb
Host smart-9c0569e1-2249-4842-9693-57d56da9bf82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163596074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.4163596074
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.932746133
Short name T22
Test name
Test status
Simulation time 11833912349 ps
CPU time 202.36 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:22:40 PM PDT 24
Peak memory 278020 kb
Host smart-a8808f47-7666-40b8-a3a3-f08cb884b786
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932746133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.932746133
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.2448054312
Short name T823
Test name
Test status
Simulation time 518629536 ps
CPU time 5.18 seconds
Started Jun 27 07:16:45 PM PDT 24
Finished Jun 27 07:19:13 PM PDT 24
Peak memory 242012 kb
Host smart-d2a9f6bf-9efa-4973-bd65-6f89390056ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448054312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.2448054312
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1269981958
Short name T90
Test name
Test status
Simulation time 313960829 ps
CPU time 11.15 seconds
Started Jun 27 07:16:58 PM PDT 24
Finished Jun 27 07:19:29 PM PDT 24
Peak memory 242488 kb
Host smart-ce064c3c-bf9c-4605-915f-823562ac7ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269981958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1269981958
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2002146420
Short name T959
Test name
Test status
Simulation time 65455411 ps
CPU time 1.86 seconds
Started Jun 27 07:27:04 PM PDT 24
Finished Jun 27 07:29:11 PM PDT 24
Peak memory 240176 kb
Host smart-75061d51-8a1a-4d84-b4b8-6bc274ad04ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002146420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2002146420
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1983483284
Short name T231
Test name
Test status
Simulation time 268173948 ps
CPU time 5.27 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:18 PM PDT 24
Peak memory 242080 kb
Host smart-392f3adc-d036-4e9f-9652-222f54e0a265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983483284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1983483284
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.3894138246
Short name T7
Test name
Test status
Simulation time 5389910401 ps
CPU time 21.13 seconds
Started Jun 27 07:21:29 PM PDT 24
Finished Jun 27 07:24:42 PM PDT 24
Peak memory 241992 kb
Host smart-bcc91335-9379-48b4-b2a3-174272fdc995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894138246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3894138246
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.25519880
Short name T980
Test name
Test status
Simulation time 2492972403 ps
CPU time 12.7 seconds
Started Jun 27 07:22:58 PM PDT 24
Finished Jun 27 07:26:02 PM PDT 24
Peak memory 242104 kb
Host smart-8fb118db-8d37-4413-be9f-5a6fee568803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25519880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.25519880
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.2685400323
Short name T724
Test name
Test status
Simulation time 152139972 ps
CPU time 3.71 seconds
Started Jun 27 07:22:43 PM PDT 24
Finished Jun 27 07:25:26 PM PDT 24
Peak memory 242148 kb
Host smart-bc133118-ba5a-4599-b031-224753179c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685400323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2685400323
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.2841979698
Short name T909
Test name
Test status
Simulation time 7876747864 ps
CPU time 35.94 seconds
Started Jun 27 07:21:38 PM PDT 24
Finished Jun 27 07:25:09 PM PDT 24
Peak memory 248752 kb
Host smart-c90e8bb0-4d71-41af-afef-fd6cc0c3b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841979698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2841979698
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3418103651
Short name T728
Test name
Test status
Simulation time 1568249536 ps
CPU time 14.78 seconds
Started Jun 27 07:23:17 PM PDT 24
Finished Jun 27 07:25:30 PM PDT 24
Peak memory 248776 kb
Host smart-cf3a6b3b-d57f-4a0b-8ce1-7b4c5f8267bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418103651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3418103651
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2881833032
Short name T828
Test name
Test status
Simulation time 462957353 ps
CPU time 5.5 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:07 PM PDT 24
Peak memory 241740 kb
Host smart-33a81f23-bc82-436c-9a12-451040899166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881833032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2881833032
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.4282266413
Short name T798
Test name
Test status
Simulation time 301299608 ps
CPU time 9.83 seconds
Started Jun 27 07:26:11 PM PDT 24
Finished Jun 27 07:28:21 PM PDT 24
Peak memory 248724 kb
Host smart-305c5a76-c027-47d0-9c74-dc266738ec5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282266413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.4282266413
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1730251255
Short name T902
Test name
Test status
Simulation time 267724172 ps
CPU time 5.41 seconds
Started Jun 27 07:21:42 PM PDT 24
Finished Jun 27 07:24:31 PM PDT 24
Peak memory 242004 kb
Host smart-78d91bc2-b3e6-453f-b8ab-387a4a8e6761
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730251255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1730251255
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1910091784
Short name T109
Test name
Test status
Simulation time 588856366 ps
CPU time 7.53 seconds
Started Jun 27 07:21:42 PM PDT 24
Finished Jun 27 07:24:45 PM PDT 24
Peak memory 248484 kb
Host smart-dedd4f2d-96e3-42a0-971f-a28a0621bd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910091784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1910091784
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3647151805
Short name T692
Test name
Test status
Simulation time 167758001263 ps
CPU time 1170.56 seconds
Started Jun 27 07:23:17 PM PDT 24
Finished Jun 27 07:44:46 PM PDT 24
Peak memory 372724 kb
Host smart-66ce66fd-9199-4c9a-985b-6fa6042dc029
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647151805 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3647151805
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2104073779
Short name T532
Test name
Test status
Simulation time 927201214 ps
CPU time 15.69 seconds
Started Jun 27 07:21:48 PM PDT 24
Finished Jun 27 07:24:40 PM PDT 24
Peak memory 242496 kb
Host smart-58ad460e-213f-42c1-814d-3ba9089183c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104073779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2104073779
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3281774026
Short name T611
Test name
Test status
Simulation time 72488304 ps
CPU time 2.17 seconds
Started Jun 27 07:31:41 PM PDT 24
Finished Jun 27 07:33:35 PM PDT 24
Peak memory 240048 kb
Host smart-95bdcabf-b88c-45db-8897-1c149c644404
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281774026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3281774026
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.2139986327
Short name T464
Test name
Test status
Simulation time 311057949 ps
CPU time 16.85 seconds
Started Jun 27 07:21:39 PM PDT 24
Finished Jun 27 07:24:30 PM PDT 24
Peak memory 242036 kb
Host smart-4ff388d7-3955-4913-89e9-c1b723fe6a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139986327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.2139986327
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2720385529
Short name T1023
Test name
Test status
Simulation time 639474766 ps
CPU time 15.27 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:09 PM PDT 24
Peak memory 242372 kb
Host smart-8be0e4c9-dafd-49fa-91fa-c642ce00df68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720385529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2720385529
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.3642168699
Short name T224
Test name
Test status
Simulation time 14029260677 ps
CPU time 30.59 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:26:04 PM PDT 24
Peak memory 247236 kb
Host smart-1fca1fa6-e0f0-43bf-b8bd-6dc6dd3d936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642168699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.3642168699
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.4033564457
Short name T1055
Test name
Test status
Simulation time 7067672837 ps
CPU time 26.78 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:45 PM PDT 24
Peak memory 242880 kb
Host smart-d8f7344f-305f-462f-a8a4-de49b142812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033564457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.4033564457
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.4156412459
Short name T713
Test name
Test status
Simulation time 3164014177 ps
CPU time 7.27 seconds
Started Jun 27 07:22:44 PM PDT 24
Finished Jun 27 07:25:41 PM PDT 24
Peak memory 241932 kb
Host smart-77c26ce2-efa1-45a9-b28c-70abb50eac5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156412459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.4156412459
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.50661708
Short name T613
Test name
Test status
Simulation time 1211597897 ps
CPU time 22 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:25:44 PM PDT 24
Peak memory 242000 kb
Host smart-5c210130-f504-4b93-a955-2d0808569549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50661708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.50661708
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.4095721944
Short name T351
Test name
Test status
Simulation time 4350700019 ps
CPU time 14.37 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:25:37 PM PDT 24
Peak memory 242180 kb
Host smart-e5e6eb23-fbae-4167-882a-5cfc5cdf0a60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4095721944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.4095721944
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.856390898
Short name T1046
Test name
Test status
Simulation time 315325006 ps
CPU time 2.99 seconds
Started Jun 27 07:24:10 PM PDT 24
Finished Jun 27 07:27:08 PM PDT 24
Peak memory 242000 kb
Host smart-dd5fc9e3-2386-4df6-a95a-fa47060ae108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856390898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.856390898
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1500056093
Short name T911
Test name
Test status
Simulation time 6979177094 ps
CPU time 111.1 seconds
Started Jun 27 07:22:01 PM PDT 24
Finished Jun 27 07:26:16 PM PDT 24
Peak memory 246252 kb
Host smart-cdb6a7b7-5b31-4537-be56-c8323e55ca7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500056093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1500056093
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2895063781
Short name T882
Test name
Test status
Simulation time 81987444712 ps
CPU time 445.12 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:32:59 PM PDT 24
Peak memory 265340 kb
Host smart-0484ae32-8afe-43c2-b353-cdbdd97faf87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895063781 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2895063781
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.3741807222
Short name T676
Test name
Test status
Simulation time 1544032257 ps
CPU time 14.19 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:26:48 PM PDT 24
Peak memory 242228 kb
Host smart-0e065ce8-1ac4-4a4a-8045-80fbf2fcba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741807222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3741807222
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.920615490
Short name T819
Test name
Test status
Simulation time 50083094 ps
CPU time 1.6 seconds
Started Jun 27 07:25:55 PM PDT 24
Finished Jun 27 07:27:53 PM PDT 24
Peak memory 240160 kb
Host smart-442b979c-426b-49c3-8e7a-2b1936d4910f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920615490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.920615490
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.1359991124
Short name T557
Test name
Test status
Simulation time 5241769083 ps
CPU time 38.77 seconds
Started Jun 27 07:21:59 PM PDT 24
Finished Jun 27 07:25:12 PM PDT 24
Peak memory 248624 kb
Host smart-01b71097-e3d1-493d-ac2b-4eff133f1772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359991124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.1359991124
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.587135731
Short name T562
Test name
Test status
Simulation time 11765793042 ps
CPU time 16.5 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:24:49 PM PDT 24
Peak memory 242608 kb
Host smart-ecc3a8e2-edd1-4bd2-9986-45a5daa633a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587135731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.587135731
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4086690404
Short name T140
Test name
Test status
Simulation time 154577870 ps
CPU time 4.13 seconds
Started Jun 27 07:22:20 PM PDT 24
Finished Jun 27 07:25:19 PM PDT 24
Peak memory 241936 kb
Host smart-14501e0c-a3f0-4ea9-88ed-275d6868f9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086690404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4086690404
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1822759355
Short name T369
Test name
Test status
Simulation time 544642121 ps
CPU time 9.82 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:24:43 PM PDT 24
Peak memory 242660 kb
Host smart-8040463b-48ca-4cf8-a870-5092d9b078af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822759355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1822759355
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2013147020
Short name T39
Test name
Test status
Simulation time 1352105287 ps
CPU time 15.74 seconds
Started Jun 27 07:21:59 PM PDT 24
Finished Jun 27 07:24:41 PM PDT 24
Peak memory 248792 kb
Host smart-7060d643-c6cd-46e8-92a4-d29482f514de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013147020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2013147020
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.3562682511
Short name T566
Test name
Test status
Simulation time 435842662 ps
CPU time 11.41 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:24:44 PM PDT 24
Peak memory 241876 kb
Host smart-a8c9775b-eb0d-4a0c-92de-0cf0b1c43de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562682511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3562682511
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.3225661624
Short name T107
Test name
Test status
Simulation time 7770689799 ps
CPU time 17.79 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:24:33 PM PDT 24
Peak memory 242104 kb
Host smart-bd6b44d0-830c-40fe-aa00-970884428862
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225661624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.3225661624
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3632475221
Short name T383
Test name
Test status
Simulation time 724367009 ps
CPU time 6.99 seconds
Started Jun 27 07:22:01 PM PDT 24
Finished Jun 27 07:24:45 PM PDT 24
Peak memory 241980 kb
Host smart-f0f34289-ceb7-4326-b2be-8aafd18dc978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632475221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3632475221
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.1204425288
Short name T418
Test name
Test status
Simulation time 8112846225 ps
CPU time 18.98 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:26:06 PM PDT 24
Peak memory 242236 kb
Host smart-9425f24d-57a6-4836-81f9-a2faba5d3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204425288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1204425288
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2263450913
Short name T840
Test name
Test status
Simulation time 18695346713 ps
CPU time 145.35 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:27:03 PM PDT 24
Peak memory 249524 kb
Host smart-6fc6e330-9b1f-427e-b31c-abc57b8d7f6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263450913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2263450913
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3070079908
Short name T637
Test name
Test status
Simulation time 196406766085 ps
CPU time 1456.97 seconds
Started Jun 27 07:22:04 PM PDT 24
Finished Jun 27 07:48:42 PM PDT 24
Peak memory 263828 kb
Host smart-6deb06a6-e0a1-4920-8e85-fd42cb442026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070079908 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3070079908
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2537633345
Short name T451
Test name
Test status
Simulation time 3196568736 ps
CPU time 27.09 seconds
Started Jun 27 07:22:01 PM PDT 24
Finished Jun 27 07:24:52 PM PDT 24
Peak memory 242308 kb
Host smart-417363d9-bf62-4a95-826f-c363350f7f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537633345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2537633345
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.3705346507
Short name T226
Test name
Test status
Simulation time 64374450 ps
CPU time 1.75 seconds
Started Jun 27 07:23:53 PM PDT 24
Finished Jun 27 07:26:31 PM PDT 24
Peak memory 239980 kb
Host smart-ecd80d73-b069-4263-be9e-b167cc4bbbe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705346507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3705346507
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.200959292
Short name T30
Test name
Test status
Simulation time 15320545545 ps
CPU time 58.11 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:25:31 PM PDT 24
Peak memory 245388 kb
Host smart-a889ec3f-0187-4e89-b6bb-e594d94b5d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200959292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.200959292
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3092648439
Short name T700
Test name
Test status
Simulation time 961372011 ps
CPU time 25.65 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:24:58 PM PDT 24
Peak memory 242124 kb
Host smart-09d910eb-5c0b-41bc-9900-b9276a0b5185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092648439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3092648439
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.2000230944
Short name T916
Test name
Test status
Simulation time 798742063 ps
CPU time 16.29 seconds
Started Jun 27 07:22:19 PM PDT 24
Finished Jun 27 07:24:49 PM PDT 24
Peak memory 242080 kb
Host smart-07b5bdc3-0207-406f-826f-50b401d57f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000230944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2000230944
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.792514411
Short name T426
Test name
Test status
Simulation time 1567391451 ps
CPU time 4.6 seconds
Started Jun 27 07:21:58 PM PDT 24
Finished Jun 27 07:24:38 PM PDT 24
Peak memory 241876 kb
Host smart-c620233c-68a8-4515-ba86-01490d83c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792514411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.792514411
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1267081766
Short name T851
Test name
Test status
Simulation time 10763107479 ps
CPU time 27.77 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:25:00 PM PDT 24
Peak memory 248768 kb
Host smart-73ba11e4-f049-4a84-9208-d5976b0422d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267081766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1267081766
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.195897735
Short name T907
Test name
Test status
Simulation time 948375184 ps
CPU time 10.41 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:24:26 PM PDT 24
Peak memory 242132 kb
Host smart-42fb2e90-e363-495d-8ce8-d36a9d48eb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195897735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.195897735
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.892165945
Short name T953
Test name
Test status
Simulation time 358610824 ps
CPU time 7.58 seconds
Started Jun 27 07:21:59 PM PDT 24
Finished Jun 27 07:24:41 PM PDT 24
Peak memory 242112 kb
Host smart-f27ee80e-be0d-4191-adc7-f534ec88b9f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=892165945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.892165945
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.758250022
Short name T850
Test name
Test status
Simulation time 366828782 ps
CPU time 10.19 seconds
Started Jun 27 07:25:22 PM PDT 24
Finished Jun 27 07:27:40 PM PDT 24
Peak memory 242080 kb
Host smart-55a287f7-8849-4b9b-9d22-af71da947905
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758250022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.758250022
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2237611170
Short name T419
Test name
Test status
Simulation time 2529111297 ps
CPU time 10.81 seconds
Started Jun 27 07:22:00 PM PDT 24
Finished Jun 27 07:24:36 PM PDT 24
Peak memory 242448 kb
Host smart-a64ee002-593b-46e1-a0da-8d5d89c38a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237611170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2237611170
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.4225852782
Short name T15
Test name
Test status
Simulation time 6255471523 ps
CPU time 36.74 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:24:57 PM PDT 24
Peak memory 242320 kb
Host smart-b6454847-0df2-45e2-9ed5-495c39015111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225852782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.4225852782
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.4183190145
Short name T282
Test name
Test status
Simulation time 158990281984 ps
CPU time 1469.94 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:50:43 PM PDT 24
Peak memory 352004 kb
Host smart-c3ef2a3d-b219-4473-bf4b-76791fb6ee19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183190145 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.4183190145
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.371887160
Short name T280
Test name
Test status
Simulation time 2145827124 ps
CPU time 16.28 seconds
Started Jun 27 07:30:21 PM PDT 24
Finished Jun 27 07:32:25 PM PDT 24
Peak memory 242244 kb
Host smart-4a9df810-979d-4551-909e-a1b7a81a282b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371887160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.371887160
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3031147580
Short name T742
Test name
Test status
Simulation time 206178173 ps
CPU time 1.82 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:25:26 PM PDT 24
Peak memory 240176 kb
Host smart-c2acd109-28be-4625-9ca0-c22b60467f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031147580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3031147580
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.3844747073
Short name T759
Test name
Test status
Simulation time 499796043 ps
CPU time 13.45 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:25:38 PM PDT 24
Peak memory 241980 kb
Host smart-e4371570-7cff-4cee-8254-a892d06ddd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844747073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.3844747073
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.2357809002
Short name T186
Test name
Test status
Simulation time 16943325513 ps
CPU time 33.77 seconds
Started Jun 27 07:22:18 PM PDT 24
Finished Jun 27 07:25:44 PM PDT 24
Peak memory 245648 kb
Host smart-d01e846b-259e-446c-9c17-e1deeadcb9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357809002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2357809002
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2491829500
Short name T493
Test name
Test status
Simulation time 3543578950 ps
CPU time 23.33 seconds
Started Jun 27 07:22:15 PM PDT 24
Finished Jun 27 07:25:05 PM PDT 24
Peak memory 243316 kb
Host smart-9a614734-75be-48c9-8dfd-e8fe918b0e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491829500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2491829500
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3767411666
Short name T91
Test name
Test status
Simulation time 8865700958 ps
CPU time 23.55 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:26:00 PM PDT 24
Peak memory 242300 kb
Host smart-8623ee12-ceb8-4d1e-91c1-46d63119c10d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767411666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3767411666
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.535045221
Short name T11
Test name
Test status
Simulation time 803584027 ps
CPU time 10.08 seconds
Started Jun 27 07:22:14 PM PDT 24
Finished Jun 27 07:26:11 PM PDT 24
Peak memory 241964 kb
Host smart-0e23323c-cba7-49d7-93fa-913138610c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535045221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.535045221
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.877422719
Short name T431
Test name
Test status
Simulation time 492495313 ps
CPU time 8.7 seconds
Started Jun 27 07:23:38 PM PDT 24
Finished Jun 27 07:26:22 PM PDT 24
Peak memory 242116 kb
Host smart-69406cd5-c019-4796-a28b-28b23baa224e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877422719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.877422719
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.1723519907
Short name T949
Test name
Test status
Simulation time 2775635227 ps
CPU time 17.05 seconds
Started Jun 27 07:25:22 PM PDT 24
Finished Jun 27 07:28:48 PM PDT 24
Peak memory 241616 kb
Host smart-1c9586f6-cbf4-44b0-b243-2409a4870012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723519907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.1723519907
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2984753157
Short name T233
Test name
Test status
Simulation time 101998904192 ps
CPU time 742.16 seconds
Started Jun 27 07:22:28 PM PDT 24
Finished Jun 27 07:36:54 PM PDT 24
Peak memory 296744 kb
Host smart-3eb0cdbb-86d4-4701-a5aa-c662060bb2f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984753157 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2984753157
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.367178166
Short name T730
Test name
Test status
Simulation time 15064946367 ps
CPU time 41.3 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:26:42 PM PDT 24
Peak memory 242272 kb
Host smart-242a32b9-e42a-4980-9b32-f3b501f39903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367178166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.367178166
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3185627013
Short name T497
Test name
Test status
Simulation time 222446589 ps
CPU time 2.16 seconds
Started Jun 27 07:22:17 PM PDT 24
Finished Jun 27 07:27:05 PM PDT 24
Peak memory 240124 kb
Host smart-6daf8d49-f3ee-42b7-9623-dfc450fad595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185627013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3185627013
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.771258465
Short name T53
Test name
Test status
Simulation time 1033579282 ps
CPU time 20.91 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:27:09 PM PDT 24
Peak memory 243324 kb
Host smart-ad5a474e-558c-4358-9c48-23f01e84486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771258465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.771258465
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1176404121
Short name T908
Test name
Test status
Simulation time 25587220851 ps
CPU time 32.9 seconds
Started Jun 27 07:22:17 PM PDT 24
Finished Jun 27 07:24:53 PM PDT 24
Peak memory 242460 kb
Host smart-75bbba1b-a159-4a20-b585-4b88ea378608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176404121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1176404121
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.3211225373
Short name T501
Test name
Test status
Simulation time 149820445 ps
CPU time 3.6 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:24:36 PM PDT 24
Peak memory 241928 kb
Host smart-1b0fde8a-fb82-4257-86c1-3cbe8907a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211225373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.3211225373
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.3969741009
Short name T142
Test name
Test status
Simulation time 1063850912 ps
CPU time 14.34 seconds
Started Jun 27 07:22:17 PM PDT 24
Finished Jun 27 07:24:47 PM PDT 24
Peak memory 242336 kb
Host smart-b6d3a9f6-9686-4882-a4ee-c8cd4c63bd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969741009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3969741009
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.375289111
Short name T436
Test name
Test status
Simulation time 430672779 ps
CPU time 5 seconds
Started Jun 27 07:22:15 PM PDT 24
Finished Jun 27 07:24:43 PM PDT 24
Peak memory 241720 kb
Host smart-407137c0-e6dd-435b-9d93-9f5df8eb30dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375289111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.375289111
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.2486272238
Short name T727
Test name
Test status
Simulation time 394642147 ps
CPU time 5.72 seconds
Started Jun 27 07:23:37 PM PDT 24
Finished Jun 27 07:26:44 PM PDT 24
Peak memory 247712 kb
Host smart-c50a3996-b832-4607-81a5-e275c6456b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486272238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.2486272238
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2845686951
Short name T794
Test name
Test status
Simulation time 534811419 ps
CPU time 11.24 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:26:28 PM PDT 24
Peak memory 242348 kb
Host smart-a10a95cb-acff-4502-ac30-987fb723839b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845686951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2845686951
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2572853329
Short name T462
Test name
Test status
Simulation time 892539004 ps
CPU time 9.36 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:25:45 PM PDT 24
Peak memory 242224 kb
Host smart-ab35cad7-71f5-49e1-a0f8-1ebdddc10a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572853329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2572853329
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1444193241
Short name T993
Test name
Test status
Simulation time 2014240642 ps
CPU time 38.03 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:24:58 PM PDT 24
Peak memory 242392 kb
Host smart-6a4e4d9d-2558-4e6d-bd02-a3a37c30f6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444193241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1444193241
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.1135653275
Short name T449
Test name
Test status
Simulation time 71145742 ps
CPU time 1.96 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:26:23 PM PDT 24
Peak memory 240096 kb
Host smart-4825bf29-441e-43af-91d2-a5e969cb3d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135653275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1135653275
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.3944522098
Short name T139
Test name
Test status
Simulation time 697949656 ps
CPU time 8.39 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:27:25 PM PDT 24
Peak memory 242172 kb
Host smart-ffa6c828-351a-4655-bfbd-462aefa2ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944522098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3944522098
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2304628639
Short name T202
Test name
Test status
Simulation time 1889876870 ps
CPU time 13.21 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:25:48 PM PDT 24
Peak memory 248912 kb
Host smart-3c7957ab-4d15-4560-a451-35ac33fdd9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304628639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2304628639
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.375871680
Short name T108
Test name
Test status
Simulation time 14814830382 ps
CPU time 21.13 seconds
Started Jun 27 07:23:24 PM PDT 24
Finished Jun 27 07:26:48 PM PDT 24
Peak memory 243456 kb
Host smart-3f26d032-c098-4fe6-b9b9-6821fdf835d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375871680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.375871680
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.154461083
Short name T1021
Test name
Test status
Simulation time 341614285 ps
CPU time 4.51 seconds
Started Jun 27 07:22:23 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 241924 kb
Host smart-d1e05be9-5c94-431f-935f-37ed73581450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154461083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.154461083
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3060290525
Short name T368
Test name
Test status
Simulation time 1509821376 ps
CPU time 21.49 seconds
Started Jun 27 07:23:47 PM PDT 24
Finished Jun 27 07:26:35 PM PDT 24
Peak memory 242716 kb
Host smart-39e90c6a-4799-4401-8369-83e7dbb94d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060290525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3060290525
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.907802036
Short name T474
Test name
Test status
Simulation time 315753955 ps
CPU time 8.42 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:25:21 PM PDT 24
Peak memory 241788 kb
Host smart-dec6d87e-0263-45a3-98fc-3599aaead7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907802036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.907802036
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1890516149
Short name T575
Test name
Test status
Simulation time 2186493116 ps
CPU time 15.95 seconds
Started Jun 27 07:22:17 PM PDT 24
Finished Jun 27 07:25:01 PM PDT 24
Peak memory 242172 kb
Host smart-6bfb0660-236f-4cdb-97f4-5719797223e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890516149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1890516149
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.4019448030
Short name T795
Test name
Test status
Simulation time 16268096577 ps
CPU time 44.91 seconds
Started Jun 27 07:26:54 PM PDT 24
Finished Jun 27 07:30:37 PM PDT 24
Peak memory 245264 kb
Host smart-71430d53-e54d-4ab7-9cd2-4baca9cf8fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019448030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.4019448030
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2869320103
Short name T1030
Test name
Test status
Simulation time 8949730577 ps
CPU time 240 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:30:36 PM PDT 24
Peak memory 257140 kb
Host smart-5cd6c403-07e8-4492-b577-89c2cd151dfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869320103 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.2869320103
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.1072604303
Short name T927
Test name
Test status
Simulation time 762024781 ps
CPU time 30.97 seconds
Started Jun 27 07:22:15 PM PDT 24
Finished Jun 27 07:25:04 PM PDT 24
Peak memory 242432 kb
Host smart-c5dbee75-f47d-49e0-8a73-2dbf7bbb4584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072604303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1072604303
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.1477944894
Short name T621
Test name
Test status
Simulation time 639482496 ps
CPU time 1.63 seconds
Started Jun 27 07:27:09 PM PDT 24
Finished Jun 27 07:29:31 PM PDT 24
Peak memory 240244 kb
Host smart-b0313d31-8e0e-4f19-868f-c3329f973d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477944894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1477944894
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.3170626209
Short name T826
Test name
Test status
Simulation time 310053297 ps
CPU time 7.28 seconds
Started Jun 27 07:22:21 PM PDT 24
Finished Jun 27 07:24:40 PM PDT 24
Peak memory 242060 kb
Host smart-d09dda92-d840-4a8f-a88e-5ccd726516eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170626209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.3170626209
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.4063467301
Short name T991
Test name
Test status
Simulation time 1138114325 ps
CPU time 21 seconds
Started Jun 27 07:23:37 PM PDT 24
Finished Jun 27 07:27:13 PM PDT 24
Peak memory 242340 kb
Host smart-f6c06605-959f-4744-9bf2-84c4f0c49b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063467301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.4063467301
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.767402954
Short name T783
Test name
Test status
Simulation time 1850196082 ps
CPU time 4.91 seconds
Started Jun 27 07:22:15 PM PDT 24
Finished Jun 27 07:24:38 PM PDT 24
Peak memory 242052 kb
Host smart-ee8d31ef-75ec-4863-8345-752fa5eddb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767402954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.767402954
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2830992586
Short name T789
Test name
Test status
Simulation time 369393993 ps
CPU time 7.32 seconds
Started Jun 27 07:25:34 PM PDT 24
Finished Jun 27 07:27:52 PM PDT 24
Peak memory 242008 kb
Host smart-89c5d096-0f66-422c-a642-19f4a82d25bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830992586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2830992586
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.927136020
Short name T116
Test name
Test status
Simulation time 3005942801 ps
CPU time 30.63 seconds
Started Jun 27 07:23:24 PM PDT 24
Finished Jun 27 07:26:20 PM PDT 24
Peak memory 242664 kb
Host smart-adfea81d-c08f-42f1-a534-d4c52b416cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927136020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.927136020
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.1000097167
Short name T397
Test name
Test status
Simulation time 612578769 ps
CPU time 11.19 seconds
Started Jun 27 07:22:16 PM PDT 24
Finished Jun 27 07:24:49 PM PDT 24
Peak memory 241972 kb
Host smart-6c45579c-6045-4ca4-9edf-ed1032f1a3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000097167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.1000097167
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.869612917
Short name T435
Test name
Test status
Simulation time 348598728 ps
CPU time 6.12 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:26:19 PM PDT 24
Peak memory 242168 kb
Host smart-5f6881f3-16e5-4b78-8838-66bb98b92d38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869612917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.869612917
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.435673600
Short name T955
Test name
Test status
Simulation time 260290206 ps
CPU time 8.55 seconds
Started Jun 27 07:22:21 PM PDT 24
Finished Jun 27 07:24:41 PM PDT 24
Peak memory 242400 kb
Host smart-9ce2598f-533f-48c8-8a37-48e95a15b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435673600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.435673600
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.64355717
Short name T278
Test name
Test status
Simulation time 28101228625 ps
CPU time 189.15 seconds
Started Jun 27 07:22:31 PM PDT 24
Finished Jun 27 07:28:58 PM PDT 24
Peak memory 249812 kb
Host smart-117877c8-3ef7-4e49-927c-353063e9397c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64355717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.64355717
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3450153145
Short name T260
Test name
Test status
Simulation time 361555016043 ps
CPU time 2060.23 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 08:01:24 PM PDT 24
Peak memory 367668 kb
Host smart-b6fa9cb1-759b-4b23-bb4d-591e178e84b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450153145 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.3450153145
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2923642213
Short name T472
Test name
Test status
Simulation time 198046449 ps
CPU time 1.85 seconds
Started Jun 27 07:27:01 PM PDT 24
Finished Jun 27 07:29:07 PM PDT 24
Peak memory 240204 kb
Host smart-cddb7513-faac-430f-b9d9-5934aa68063d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923642213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2923642213
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2191951176
Short name T681
Test name
Test status
Simulation time 235857793 ps
CPU time 8.8 seconds
Started Jun 27 07:22:28 PM PDT 24
Finished Jun 27 07:24:41 PM PDT 24
Peak memory 242120 kb
Host smart-d8248aa9-aa19-46df-af42-f2581b65d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191951176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2191951176
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.2487831083
Short name T859
Test name
Test status
Simulation time 818705289 ps
CPU time 14.57 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:25:51 PM PDT 24
Peak memory 242624 kb
Host smart-78e04a86-733c-4e4b-b43c-4046b57be0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487831083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.2487831083
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2455020640
Short name T447
Test name
Test status
Simulation time 111521106 ps
CPU time 3.87 seconds
Started Jun 27 07:24:06 PM PDT 24
Finished Jun 27 07:26:58 PM PDT 24
Peak memory 241980 kb
Host smart-981b37c1-5529-4d9f-9123-52e6d01ea5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455020640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2455020640
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1375725676
Short name T396
Test name
Test status
Simulation time 10447953371 ps
CPU time 31.27 seconds
Started Jun 27 07:22:38 PM PDT 24
Finished Jun 27 07:26:07 PM PDT 24
Peak memory 248804 kb
Host smart-c22ddf9d-5e79-4300-b444-29bb1288a020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375725676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1375725676
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.2003447313
Short name T523
Test name
Test status
Simulation time 329428110 ps
CPU time 7.63 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:25:44 PM PDT 24
Peak memory 242088 kb
Host smart-944c6478-336b-4b76-9652-427c117d8b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003447313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2003447313
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3880314231
Short name T279
Test name
Test status
Simulation time 137100976010 ps
CPU time 1255.26 seconds
Started Jun 27 07:22:30 PM PDT 24
Finished Jun 27 07:45:36 PM PDT 24
Peak memory 462628 kb
Host smart-77398558-8480-4a8e-9ead-a87e798e9e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880314231 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3880314231
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.1407661403
Short name T306
Test name
Test status
Simulation time 2699031880 ps
CPU time 19.25 seconds
Started Jun 27 07:22:30 PM PDT 24
Finished Jun 27 07:25:55 PM PDT 24
Peak memory 242416 kb
Host smart-748a9217-135d-44b2-a946-48176679bbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407661403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1407661403
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.4032885248
Short name T616
Test name
Test status
Simulation time 755559603 ps
CPU time 1.71 seconds
Started Jun 27 07:23:53 PM PDT 24
Finished Jun 27 07:26:56 PM PDT 24
Peak memory 240156 kb
Host smart-ee6ff230-aa97-4420-9d38-ac2e73f7109c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032885248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4032885248
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.2854402971
Short name T764
Test name
Test status
Simulation time 987642164 ps
CPU time 20.62 seconds
Started Jun 27 07:22:32 PM PDT 24
Finished Jun 27 07:24:58 PM PDT 24
Peak memory 242508 kb
Host smart-64117915-b6be-42c1-b5a8-6b18302dd6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854402971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2854402971
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.2045315358
Short name T1059
Test name
Test status
Simulation time 312657996 ps
CPU time 7.19 seconds
Started Jun 27 07:26:15 PM PDT 24
Finished Jun 27 07:28:38 PM PDT 24
Peak memory 242688 kb
Host smart-4535719f-a009-4778-815c-90f1512948fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045315358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2045315358
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.1290270783
Short name T460
Test name
Test status
Simulation time 16140921531 ps
CPU time 25.63 seconds
Started Jun 27 07:22:28 PM PDT 24
Finished Jun 27 07:25:59 PM PDT 24
Peak memory 242484 kb
Host smart-c5b8daea-9e26-46b1-98f9-bddf3544fe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290270783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1290270783
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1040224464
Short name T693
Test name
Test status
Simulation time 1661550219 ps
CPU time 15.11 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:25:25 PM PDT 24
Peak memory 248748 kb
Host smart-b715591e-12dd-4cbf-8188-eb1248c15e9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040224464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1040224464
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.1409249742
Short name T924
Test name
Test status
Simulation time 128278134 ps
CPU time 4.01 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:24:37 PM PDT 24
Peak memory 242184 kb
Host smart-5b53d23a-f8e6-4bb5-a3c9-50ec145b0896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409249742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.1409249742
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2476019729
Short name T906
Test name
Test status
Simulation time 4020564098 ps
CPU time 7.55 seconds
Started Jun 27 07:22:30 PM PDT 24
Finished Jun 27 07:24:53 PM PDT 24
Peak memory 242488 kb
Host smart-112b23af-d1c6-4edb-8af9-8f53e526c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476019729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2476019729
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.1002279397
Short name T833
Test name
Test status
Simulation time 9248870514 ps
CPU time 87.81 seconds
Started Jun 27 07:25:54 PM PDT 24
Finished Jun 27 07:29:12 PM PDT 24
Peak memory 248796 kb
Host smart-4c98ad80-fd33-45c8-85f9-b7b4b1aaff32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002279397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all
.1002279397
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1892001562
Short name T487
Test name
Test status
Simulation time 236570698 ps
CPU time 2.19 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:20 PM PDT 24
Peak memory 240208 kb
Host smart-5e34a4c2-035f-43a6-8f5c-0db429d8b844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892001562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1892001562
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.2222703111
Short name T124
Test name
Test status
Simulation time 6932753552 ps
CPU time 14.44 seconds
Started Jun 27 07:17:06 PM PDT 24
Finished Jun 27 07:19:42 PM PDT 24
Peak memory 248724 kb
Host smart-9eabdf8b-6cb0-4ebb-81bd-3ba3e729eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222703111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2222703111
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2682107626
Short name T80
Test name
Test status
Simulation time 549565598 ps
CPU time 15.44 seconds
Started Jun 27 07:16:59 PM PDT 24
Finished Jun 27 07:19:37 PM PDT 24
Peak memory 248808 kb
Host smart-11b614d4-8285-48d3-9288-a295248be38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682107626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2682107626
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.954073082
Short name T870
Test name
Test status
Simulation time 7545468974 ps
CPU time 16.15 seconds
Started Jun 27 07:16:59 PM PDT 24
Finished Jun 27 07:19:39 PM PDT 24
Peak memory 242248 kb
Host smart-241a8efa-ff09-4c8d-a641-2bca0293838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954073082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.954073082
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3826483400
Short name T166
Test name
Test status
Simulation time 1729176436 ps
CPU time 5.66 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:23 PM PDT 24
Peak memory 242040 kb
Host smart-6be24e17-c80a-4118-9433-69e94f9c54de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826483400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3826483400
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2583382373
Short name T830
Test name
Test status
Simulation time 942933501 ps
CPU time 12.79 seconds
Started Jun 27 07:17:05 PM PDT 24
Finished Jun 27 07:19:40 PM PDT 24
Peak memory 248816 kb
Host smart-1b080435-4828-4eb1-ab01-de1112af4cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583382373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2583382373
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.614961884
Short name T229
Test name
Test status
Simulation time 745912467 ps
CPU time 14.94 seconds
Started Jun 27 07:16:58 PM PDT 24
Finished Jun 27 07:19:33 PM PDT 24
Peak memory 248772 kb
Host smart-2b177d00-14ce-40f9-8572-860a748d3adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614961884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.614961884
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.2087732611
Short name T73
Test name
Test status
Simulation time 1155247858 ps
CPU time 7.12 seconds
Started Jun 27 07:17:06 PM PDT 24
Finished Jun 27 07:19:34 PM PDT 24
Peak memory 242032 kb
Host smart-2f13ae79-460e-451f-b4bd-a966e8c05a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087732611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2087732611
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1025719377
Short name T350
Test name
Test status
Simulation time 2141257684 ps
CPU time 5.41 seconds
Started Jun 27 07:16:59 PM PDT 24
Finished Jun 27 07:19:23 PM PDT 24
Peak memory 242140 kb
Host smart-bbf42ebb-22a4-4ecd-affc-7d928e9d96ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1025719377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1025719377
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.980006829
Short name T964
Test name
Test status
Simulation time 289590642 ps
CPU time 7.94 seconds
Started Jun 27 07:16:58 PM PDT 24
Finished Jun 27 07:19:26 PM PDT 24
Peak memory 242056 kb
Host smart-b06fd56a-446b-4ac0-abaa-b9dca99a9f64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=980006829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.980006829
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3926453863
Short name T546
Test name
Test status
Simulation time 407426454 ps
CPU time 10.83 seconds
Started Jun 27 07:16:59 PM PDT 24
Finished Jun 27 07:19:33 PM PDT 24
Peak memory 248684 kb
Host smart-8a061f21-7f80-4e68-a1de-bf58dead6a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926453863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3926453863
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.2829861166
Short name T696
Test name
Test status
Simulation time 184125451028 ps
CPU time 481.7 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:27:19 PM PDT 24
Peak memory 258664 kb
Host smart-a3db2a1d-9995-488f-8764-de6ac128ab37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829861166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.
2829861166
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.265881786
Short name T892
Test name
Test status
Simulation time 383408094 ps
CPU time 6.93 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:25 PM PDT 24
Peak memory 248764 kb
Host smart-7860309d-61c7-4d9b-9e8b-6123d377ade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265881786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.265881786
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2686185074
Short name T247
Test name
Test status
Simulation time 304591753 ps
CPU time 6.79 seconds
Started Jun 27 07:22:39 PM PDT 24
Finished Jun 27 07:24:44 PM PDT 24
Peak memory 241936 kb
Host smart-1a0fca85-4e0a-4de9-be3c-f7466bb69ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686185074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2686185074
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.4215842327
Short name T913
Test name
Test status
Simulation time 536246768 ps
CPU time 4.63 seconds
Started Jun 27 07:22:47 PM PDT 24
Finished Jun 27 07:25:52 PM PDT 24
Peak memory 241824 kb
Host smart-56fe6d67-30b7-4ad7-b71d-6ad7ef711171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215842327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.4215842327
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.3305647501
Short name T461
Test name
Test status
Simulation time 155515439 ps
CPU time 3.18 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:24:36 PM PDT 24
Peak memory 241848 kb
Host smart-cb342cb9-5893-4e3b-9914-47441b9ec34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305647501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3305647501
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.186881836
Short name T20
Test name
Test status
Simulation time 226859457270 ps
CPU time 2074.31 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:59:07 PM PDT 24
Peak memory 278636 kb
Host smart-6f441791-a424-4c4c-9a48-8ccd785afeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186881836 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.186881836
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.4241978930
Short name T1042
Test name
Test status
Simulation time 180983409 ps
CPU time 4 seconds
Started Jun 27 07:22:29 PM PDT 24
Finished Jun 27 07:24:42 PM PDT 24
Peak memory 242148 kb
Host smart-4179f798-8191-46ca-8197-5c82ff703abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241978930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.4241978930
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3341289872
Short name T65
Test name
Test status
Simulation time 133156385979 ps
CPU time 2064.44 seconds
Started Jun 27 07:23:56 PM PDT 24
Finished Jun 27 08:00:38 PM PDT 24
Peak memory 328916 kb
Host smart-e901f5f9-29a4-4c43-a64b-5e5e66853926
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341289872 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3341289872
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3847238914
Short name T982
Test name
Test status
Simulation time 55819548174 ps
CPU time 464.2 seconds
Started Jun 27 07:22:57 PM PDT 24
Finished Jun 27 07:32:59 PM PDT 24
Peak memory 289884 kb
Host smart-7b71e10f-545f-4507-8999-a64fb223fd44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847238914 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3847238914
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3119369851
Short name T735
Test name
Test status
Simulation time 309643811 ps
CPU time 3.58 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:26:33 PM PDT 24
Peak memory 241896 kb
Host smart-1e93e2d5-2a82-4b1c-ab03-af514b4879cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119369851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3119369851
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.3289013775
Short name T500
Test name
Test status
Simulation time 312392244 ps
CPU time 5.11 seconds
Started Jun 27 07:22:48 PM PDT 24
Finished Jun 27 07:25:26 PM PDT 24
Peak memory 242416 kb
Host smart-3f0c2e3d-a6f1-4e99-bd81-129183b5e360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289013775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3289013775
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.698872806
Short name T736
Test name
Test status
Simulation time 104720081250 ps
CPU time 833.71 seconds
Started Jun 27 07:25:13 PM PDT 24
Finished Jun 27 07:41:13 PM PDT 24
Peak memory 257928 kb
Host smart-20e65cc8-61ee-4361-b265-d353db90b4c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698872806 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.698872806
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.2148459580
Short name T408
Test name
Test status
Simulation time 162022391 ps
CPU time 4.49 seconds
Started Jun 27 07:27:15 PM PDT 24
Finished Jun 27 07:30:06 PM PDT 24
Peak memory 242092 kb
Host smart-2e41b8a4-bdc4-4a88-9a30-6545c3ddd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148459580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2148459580
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1678941806
Short name T661
Test name
Test status
Simulation time 3274578082 ps
CPU time 7.38 seconds
Started Jun 27 07:22:44 PM PDT 24
Finished Jun 27 07:24:48 PM PDT 24
Peak memory 242284 kb
Host smart-8d16bbef-367f-4f52-8ed0-fbbf1be3c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678941806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1678941806
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2514271163
Short name T647
Test name
Test status
Simulation time 581269622 ps
CPU time 4.78 seconds
Started Jun 27 07:23:52 PM PDT 24
Finished Jun 27 07:26:57 PM PDT 24
Peak memory 241728 kb
Host smart-4dbdb0e0-aefd-4d65-b5fb-28e351aea8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514271163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2514271163
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.2698985852
Short name T17
Test name
Test status
Simulation time 157227876404 ps
CPU time 685.61 seconds
Started Jun 27 07:27:11 PM PDT 24
Finished Jun 27 07:40:35 PM PDT 24
Peak memory 310608 kb
Host smart-9721e4d6-92e7-4f5e-a43e-d06a8b890c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698985852 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.2698985852
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.4200713345
Short name T502
Test name
Test status
Simulation time 2250651234 ps
CPU time 6.17 seconds
Started Jun 27 07:22:58 PM PDT 24
Finished Jun 27 07:25:56 PM PDT 24
Peak memory 241824 kb
Host smart-7d4b6aa7-0cdf-4502-abe9-7f2c10e954a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200713345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.4200713345
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1248322045
Short name T346
Test name
Test status
Simulation time 79538573861 ps
CPU time 390.05 seconds
Started Jun 27 07:23:56 PM PDT 24
Finished Jun 27 07:32:30 PM PDT 24
Peak memory 320936 kb
Host smart-ef3f0719-a110-49e4-8edf-1eb231d077fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248322045 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1248322045
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.1330929102
Short name T170
Test name
Test status
Simulation time 173724562 ps
CPU time 1.66 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:19 PM PDT 24
Peak memory 240160 kb
Host smart-a2c78a59-9c8e-4711-86c3-15b9a025b39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330929102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.1330929102
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2802620953
Short name T974
Test name
Test status
Simulation time 6064888884 ps
CPU time 46.95 seconds
Started Jun 27 07:17:00 PM PDT 24
Finished Jun 27 07:20:08 PM PDT 24
Peak memory 243924 kb
Host smart-7f4e028e-e5ad-400f-97d3-8da597402a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802620953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2802620953
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1345366023
Short name T839
Test name
Test status
Simulation time 2632749789 ps
CPU time 22.59 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:40 PM PDT 24
Peak memory 241932 kb
Host smart-a5598110-1f15-4a23-98ff-e79efa28db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345366023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1345366023
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.2357698170
Short name T990
Test name
Test status
Simulation time 2375266889 ps
CPU time 26.24 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:44 PM PDT 24
Peak memory 248860 kb
Host smart-355a1c32-b532-4a33-92d2-5524bd99584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357698170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2357698170
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.1920729210
Short name T779
Test name
Test status
Simulation time 1618238200 ps
CPU time 34.01 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:52 PM PDT 24
Peak memory 248672 kb
Host smart-7a9c59cc-b09d-43fa-828c-7a5fb4285f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920729210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1920729210
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.2756260347
Short name T939
Test name
Test status
Simulation time 276134691 ps
CPU time 5.5 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:23 PM PDT 24
Peak memory 242084 kb
Host smart-dcfe14a7-b2fb-417f-b74f-cc5db6c3697e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2756260347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2756260347
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.85430036
Short name T292
Test name
Test status
Simulation time 4221456195 ps
CPU time 10.75 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:28 PM PDT 24
Peak memory 242120 kb
Host smart-63a2df85-c30a-422c-bbba-ac3cf1c37add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85430036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.85430036
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.2969571299
Short name T602
Test name
Test status
Simulation time 357743606 ps
CPU time 18.03 seconds
Started Jun 27 07:16:56 PM PDT 24
Finished Jun 27 07:19:36 PM PDT 24
Peak memory 248696 kb
Host smart-2c8bd49b-f8c6-4083-8d3e-e39143ae6896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969571299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.
2969571299
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1895928607
Short name T359
Test name
Test status
Simulation time 108666427801 ps
CPU time 1439.7 seconds
Started Jun 27 07:16:59 PM PDT 24
Finished Jun 27 07:43:21 PM PDT 24
Peak memory 277012 kb
Host smart-09e2c535-4fa0-4a37-8576-7faa4167e919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895928607 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1895928607
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.963040033
Short name T126
Test name
Test status
Simulation time 320781630 ps
CPU time 8.17 seconds
Started Jun 27 07:16:57 PM PDT 24
Finished Jun 27 07:19:26 PM PDT 24
Peak memory 242188 kb
Host smart-1e267627-e3f2-4e9a-b73e-78339e7bb611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963040033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.963040033
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.3779701335
Short name T263
Test name
Test status
Simulation time 307228416 ps
CPU time 5 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:41 PM PDT 24
Peak memory 241928 kb
Host smart-e5054cfd-76d5-4895-a17e-96f92490cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779701335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.3779701335
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.915175725
Short name T605
Test name
Test status
Simulation time 304492752016 ps
CPU time 649.76 seconds
Started Jun 27 07:24:06 PM PDT 24
Finished Jun 27 07:37:43 PM PDT 24
Peak memory 392168 kb
Host smart-57d51d46-2304-4fd4-bd26-792367de1c94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915175725 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.915175725
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.3228646421
Short name T151
Test name
Test status
Simulation time 231623388 ps
CPU time 4.15 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:27:57 PM PDT 24
Peak memory 242188 kb
Host smart-4529ce3c-2865-45cf-8151-6a89cc511a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228646421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3228646421
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.3569354356
Short name T606
Test name
Test status
Simulation time 194872556 ps
CPU time 5.21 seconds
Started Jun 27 07:22:58 PM PDT 24
Finished Jun 27 07:25:07 PM PDT 24
Peak memory 241648 kb
Host smart-7c1b0bb6-ea75-4081-8806-f0b9458b3095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569354356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3569354356
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2698391724
Short name T531
Test name
Test status
Simulation time 97827465335 ps
CPU time 818.86 seconds
Started Jun 27 07:23:59 PM PDT 24
Finished Jun 27 07:39:59 PM PDT 24
Peak memory 301220 kb
Host smart-f1c2cd1f-510e-48dc-b9e5-c4275f15d1ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698391724 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2698391724
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1684242600
Short name T1040
Test name
Test status
Simulation time 144877464 ps
CPU time 4.62 seconds
Started Jun 27 07:24:17 PM PDT 24
Finished Jun 27 07:26:18 PM PDT 24
Peak memory 241996 kb
Host smart-65792295-2512-40c5-a0bd-36ad1aeb6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684242600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1684242600
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.1614056779
Short name T1032
Test name
Test status
Simulation time 461566408 ps
CPU time 6.04 seconds
Started Jun 27 07:26:12 PM PDT 24
Finished Jun 27 07:28:17 PM PDT 24
Peak memory 241872 kb
Host smart-030570bb-31cb-4ca1-b0fa-d5c56ae51c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614056779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1614056779
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1747825394
Short name T648
Test name
Test status
Simulation time 20349887537 ps
CPU time 486.72 seconds
Started Jun 27 07:22:57 PM PDT 24
Finished Jun 27 07:34:08 PM PDT 24
Peak memory 338848 kb
Host smart-0dbce4bb-07e2-4b2f-afc3-177f5512b718
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747825394 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.1747825394
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3329051388
Short name T871
Test name
Test status
Simulation time 282711808 ps
CPU time 3.73 seconds
Started Jun 27 07:23:09 PM PDT 24
Finished Jun 27 07:25:28 PM PDT 24
Peak memory 242016 kb
Host smart-5ebf68c9-d976-4528-ae41-2d48f0a34c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329051388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3329051388
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.751729567
Short name T778
Test name
Test status
Simulation time 165645651 ps
CPU time 3.95 seconds
Started Jun 27 07:23:16 PM PDT 24
Finished Jun 27 07:27:20 PM PDT 24
Peak memory 241732 kb
Host smart-d0539cf3-9b08-4d48-bfcd-47ef8031b2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751729567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.751729567
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1856650233
Short name T547
Test name
Test status
Simulation time 145921634 ps
CPU time 5.02 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:40 PM PDT 24
Peak memory 242048 kb
Host smart-cec8d21f-fc2d-4fbe-b403-146787380a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856650233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1856650233
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.789561269
Short name T550
Test name
Test status
Simulation time 379645987 ps
CPU time 8.32 seconds
Started Jun 27 07:23:08 PM PDT 24
Finished Jun 27 07:25:21 PM PDT 24
Peak memory 241936 kb
Host smart-e9081691-d445-4e8e-8285-45d1489b03ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789561269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.789561269
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3153542176
Short name T695
Test name
Test status
Simulation time 124038582665 ps
CPU time 305.04 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:32:21 PM PDT 24
Peak memory 257116 kb
Host smart-3193a0a0-1530-4f96-8d2e-1ef22e701282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153542176 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3153542176
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.644202949
Short name T622
Test name
Test status
Simulation time 2847302710 ps
CPU time 5.35 seconds
Started Jun 27 07:24:18 PM PDT 24
Finished Jun 27 07:26:38 PM PDT 24
Peak memory 242436 kb
Host smart-6c9b9d69-8a0d-496b-806f-f6628be4860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644202949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.644202949
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.3161518845
Short name T744
Test name
Test status
Simulation time 1547287008 ps
CPU time 5.02 seconds
Started Jun 27 07:26:52 PM PDT 24
Finished Jun 27 07:29:54 PM PDT 24
Peak memory 241940 kb
Host smart-2d8f9bf8-b5e2-41ca-81d4-68180cb4bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161518845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3161518845
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1420041427
Short name T685
Test name
Test status
Simulation time 87919696391 ps
CPU time 1561.58 seconds
Started Jun 27 07:25:29 PM PDT 24
Finished Jun 27 07:54:34 PM PDT 24
Peak memory 439856 kb
Host smart-6d1ce16a-5666-46dc-806f-ea9f3e1cb4dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420041427 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1420041427
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2403487799
Short name T941
Test name
Test status
Simulation time 166900610 ps
CPU time 4.26 seconds
Started Jun 27 07:27:16 PM PDT 24
Finished Jun 27 07:29:33 PM PDT 24
Peak memory 241884 kb
Host smart-1df8c51a-cede-4b93-ad5a-ed59d24cff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403487799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2403487799
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.1781457352
Short name T710
Test name
Test status
Simulation time 270214000 ps
CPU time 5.91 seconds
Started Jun 27 07:23:09 PM PDT 24
Finished Jun 27 07:25:42 PM PDT 24
Peak memory 241948 kb
Host smart-a97b00ab-cdc6-4b3c-9ac7-ad0fa45a287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781457352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.1781457352
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1834534496
Short name T1000
Test name
Test status
Simulation time 142124298771 ps
CPU time 1734.27 seconds
Started Jun 27 07:24:06 PM PDT 24
Finished Jun 27 07:56:13 PM PDT 24
Peak memory 470900 kb
Host smart-2658957d-e48f-482e-88d0-f5ae17b1ef67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834534496 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.1834534496
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.979374057
Short name T492
Test name
Test status
Simulation time 602910674 ps
CPU time 4.06 seconds
Started Jun 27 07:22:59 PM PDT 24
Finished Jun 27 07:25:29 PM PDT 24
Peak memory 242264 kb
Host smart-3f68e8d3-eab9-4a7a-9b17-ed1c4c706245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979374057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.979374057
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2652100351
Short name T216
Test name
Test status
Simulation time 1280492618 ps
CPU time 4.4 seconds
Started Jun 27 07:26:16 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 242192 kb
Host smart-2b6ed161-5121-477e-a258-ab742590d2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652100351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2652100351
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2965115212
Short name T793
Test name
Test status
Simulation time 501016171 ps
CPU time 3.26 seconds
Started Jun 27 07:25:33 PM PDT 24
Finished Jun 27 07:28:35 PM PDT 24
Peak memory 242104 kb
Host smart-d941818a-0af2-4f1a-a0c7-632a9d978be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965115212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2965115212
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.366551163
Short name T587
Test name
Test status
Simulation time 147707347 ps
CPU time 6.56 seconds
Started Jun 27 07:23:05 PM PDT 24
Finished Jun 27 07:25:17 PM PDT 24
Peak memory 241752 kb
Host smart-fe517034-34de-4902-baf0-24ce805fa964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366551163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.366551163
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1770847374
Short name T49
Test name
Test status
Simulation time 1655661426 ps
CPU time 4.15 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:25:31 PM PDT 24
Peak memory 242088 kb
Host smart-a818442a-7884-47db-b468-86a6e50802f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770847374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1770847374
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1419719348
Short name T14
Test name
Test status
Simulation time 64430169069 ps
CPU time 623.24 seconds
Started Jun 27 07:23:18 PM PDT 24
Finished Jun 27 07:37:11 PM PDT 24
Peak memory 308752 kb
Host smart-34d165b9-3eb3-4473-ab90-fa17b13a8031
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419719348 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.1419719348
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.854275615
Short name T508
Test name
Test status
Simulation time 138271928 ps
CPU time 1.73 seconds
Started Jun 27 07:17:15 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 240520 kb
Host smart-9216ef63-1198-46ac-9056-643fa26273a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854275615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.854275615
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3934601313
Short name T586
Test name
Test status
Simulation time 23003174199 ps
CPU time 56.47 seconds
Started Jun 27 07:17:14 PM PDT 24
Finished Jun 27 07:21:15 PM PDT 24
Peak memory 243488 kb
Host smart-40aaa227-254b-4c87-9ea1-464f61498dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934601313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3934601313
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.567523107
Short name T738
Test name
Test status
Simulation time 746021899 ps
CPU time 8.66 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:21:35 PM PDT 24
Peak memory 242296 kb
Host smart-69299a56-6304-4fe9-a51d-c3a3199ad8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567523107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.567523107
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3849613849
Short name T792
Test name
Test status
Simulation time 621769052 ps
CPU time 16.43 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:20:35 PM PDT 24
Peak memory 242244 kb
Host smart-f07415ae-4c0c-4442-bb07-5ab25c4b90de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849613849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3849613849
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1656193442
Short name T624
Test name
Test status
Simulation time 177532696 ps
CPU time 4.05 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:20:22 PM PDT 24
Peak memory 242388 kb
Host smart-6cb1cbd4-6325-4ca1-8c75-704c2b629b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656193442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1656193442
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1413356726
Short name T691
Test name
Test status
Simulation time 1344442845 ps
CPU time 17.18 seconds
Started Jun 27 07:17:10 PM PDT 24
Finished Jun 27 07:20:12 PM PDT 24
Peak memory 242608 kb
Host smart-3485981a-6988-4393-bd05-f5e153bb2ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413356726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1413356726
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.1937160892
Short name T812
Test name
Test status
Simulation time 522563754 ps
CPU time 5.65 seconds
Started Jun 27 07:17:10 PM PDT 24
Finished Jun 27 07:20:21 PM PDT 24
Peak memory 241896 kb
Host smart-61760b76-d3a3-43a7-aa1a-8e8d8cd7261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937160892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1937160892
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2029280230
Short name T265
Test name
Test status
Simulation time 416090660 ps
CPU time 11.15 seconds
Started Jun 27 07:17:15 PM PDT 24
Finished Jun 27 07:20:29 PM PDT 24
Peak memory 242148 kb
Host smart-41acd54d-7ce5-4c21-b887-b675febd9a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029280230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2029280230
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.3823276514
Short name T944
Test name
Test status
Simulation time 106605497 ps
CPU time 3.15 seconds
Started Jun 27 07:17:15 PM PDT 24
Finished Jun 27 07:20:21 PM PDT 24
Peak memory 242244 kb
Host smart-36a85d6a-5485-4f81-9f4a-668e38c5e112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823276514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3823276514
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.1331714418
Short name T498
Test name
Test status
Simulation time 181344696 ps
CPU time 4.19 seconds
Started Jun 27 07:17:05 PM PDT 24
Finished Jun 27 07:19:32 PM PDT 24
Peak memory 241952 kb
Host smart-9d7fb276-a775-4ca7-8f49-aa69eae787a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331714418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1331714418
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.1371375197
Short name T548
Test name
Test status
Simulation time 2501060949 ps
CPU time 9.36 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:26:36 PM PDT 24
Peak memory 241772 kb
Host smart-f5962e32-146d-401f-8635-d25a40ee0f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371375197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1371375197
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.3826280949
Short name T842
Test name
Test status
Simulation time 154064624 ps
CPU time 6.01 seconds
Started Jun 27 07:23:14 PM PDT 24
Finished Jun 27 07:26:12 PM PDT 24
Peak memory 241948 kb
Host smart-67283732-606c-40ed-ac83-c63dd5eba082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826280949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.3826280949
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.366137799
Short name T342
Test name
Test status
Simulation time 22655516340 ps
CPU time 199.33 seconds
Started Jun 27 07:23:23 PM PDT 24
Finished Jun 27 07:28:46 PM PDT 24
Peak memory 255424 kb
Host smart-aec79334-acf2-4602-b383-aae92546d3bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366137799 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.366137799
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3350199966
Short name T663
Test name
Test status
Simulation time 1654852350 ps
CPU time 5.52 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:25:32 PM PDT 24
Peak memory 242064 kb
Host smart-141b7445-48a9-45c8-8de6-4863742012db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350199966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3350199966
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1482247144
Short name T698
Test name
Test status
Simulation time 2663632067 ps
CPU time 4.8 seconds
Started Jun 27 07:23:18 PM PDT 24
Finished Jun 27 07:25:20 PM PDT 24
Peak memory 242104 kb
Host smart-443dd388-7bef-41b6-9041-9b5259de2d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482247144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1482247144
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.3451204813
Short name T323
Test name
Test status
Simulation time 3647624724 ps
CPU time 7.27 seconds
Started Jun 27 07:24:42 PM PDT 24
Finished Jun 27 07:26:48 PM PDT 24
Peak memory 241964 kb
Host smart-f6958526-f6d5-44e3-91c3-88a7c9a0bf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451204813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.3451204813
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.3384812115
Short name T76
Test name
Test status
Simulation time 106518679 ps
CPU time 3.69 seconds
Started Jun 27 07:23:24 PM PDT 24
Finished Jun 27 07:26:32 PM PDT 24
Peak memory 242060 kb
Host smart-a072085a-da7e-4d8a-af4d-668b90c578d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384812115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3384812115
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2757412021
Short name T641
Test name
Test status
Simulation time 287503240 ps
CPU time 3.77 seconds
Started Jun 27 07:26:58 PM PDT 24
Finished Jun 27 07:29:35 PM PDT 24
Peak memory 241904 kb
Host smart-20e128d2-0102-48de-b7a8-c9251df7d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757412021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2757412021
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.1859989319
Short name T719
Test name
Test status
Simulation time 1097135465 ps
CPU time 7.04 seconds
Started Jun 27 07:23:18 PM PDT 24
Finished Jun 27 07:25:22 PM PDT 24
Peak memory 242212 kb
Host smart-87cf0d2f-2ac2-436d-9cdb-6074db548802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859989319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1859989319
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.923117987
Short name T841
Test name
Test status
Simulation time 445864931 ps
CPU time 5.95 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:26:12 PM PDT 24
Peak memory 241876 kb
Host smart-b630624a-e992-45e4-bf4f-45f7c5c8703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923117987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.923117987
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.1143893494
Short name T767
Test name
Test status
Simulation time 2392915753 ps
CPU time 5.59 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 07:26:55 PM PDT 24
Peak memory 242076 kb
Host smart-3c05bcc2-1ca8-4d10-97e1-93debc37044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143893494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.1143893494
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.3315067060
Short name T339
Test name
Test status
Simulation time 317021737 ps
CPU time 4.56 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 07:26:18 PM PDT 24
Peak memory 241760 kb
Host smart-a851a776-88ca-4d9f-aa94-cd23703eff33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315067060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3315067060
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.3280721383
Short name T699
Test name
Test status
Simulation time 98880497 ps
CPU time 3.96 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:26:34 PM PDT 24
Peak memory 241900 kb
Host smart-78a08445-19c0-4cef-8171-df1227b3922b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280721383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.3280721383
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2320962827
Short name T1035
Test name
Test status
Simulation time 185032124 ps
CPU time 3.56 seconds
Started Jun 27 07:23:31 PM PDT 24
Finished Jun 27 07:25:55 PM PDT 24
Peak memory 242072 kb
Host smart-0c4bdf9b-49ae-4bb2-8a17-4342ad74a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320962827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2320962827
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3590566308
Short name T319
Test name
Test status
Simulation time 874579848 ps
CPU time 7.2 seconds
Started Jun 27 07:23:32 PM PDT 24
Finished Jun 27 07:25:58 PM PDT 24
Peak memory 242128 kb
Host smart-744cab01-247a-4d01-9c96-805ff648863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590566308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3590566308
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2456515732
Short name T644
Test name
Test status
Simulation time 1310749250004 ps
CPU time 3470.77 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 08:23:18 PM PDT 24
Peak memory 572576 kb
Host smart-c738e38d-91e5-4ac8-90c5-2af2ac18d057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456515732 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.2456515732
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3774680024
Short name T506
Test name
Test status
Simulation time 152434392 ps
CPU time 2.12 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:11 PM PDT 24
Peak memory 240180 kb
Host smart-a0d4c71e-4751-4897-857c-728f019ff6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774680024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3774680024
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.862273250
Short name T966
Test name
Test status
Simulation time 469748492 ps
CPU time 8.89 seconds
Started Jun 27 07:17:15 PM PDT 24
Finished Jun 27 07:20:27 PM PDT 24
Peak memory 242060 kb
Host smart-ea9ec88c-b5c0-402a-8a4f-be22f47ca285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862273250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.862273250
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.244852586
Short name T32
Test name
Test status
Simulation time 2848125918 ps
CPU time 19.5 seconds
Started Jun 27 07:17:15 PM PDT 24
Finished Jun 27 07:20:38 PM PDT 24
Peak memory 242620 kb
Host smart-c06ac457-e745-42cc-a9c5-54f0404001b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244852586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.244852586
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.2917868730
Short name T246
Test name
Test status
Simulation time 411488109 ps
CPU time 4.98 seconds
Started Jun 27 07:17:14 PM PDT 24
Finished Jun 27 07:20:23 PM PDT 24
Peak memory 241860 kb
Host smart-b089776b-3d13-45d5-9188-d3176d122dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917868730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2917868730
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2380970962
Short name T829
Test name
Test status
Simulation time 150664908 ps
CPU time 3.91 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:20:22 PM PDT 24
Peak memory 241932 kb
Host smart-9288df8d-f752-42e3-94db-79a08a0479ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380970962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2380970962
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3808290641
Short name T994
Test name
Test status
Simulation time 15588640043 ps
CPU time 27.05 seconds
Started Jun 27 07:17:12 PM PDT 24
Finished Jun 27 07:20:13 PM PDT 24
Peak memory 249052 kb
Host smart-e5e0ccc7-68ae-4be0-86ce-01078b9dddb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808290641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3808290641
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.3700485277
Short name T482
Test name
Test status
Simulation time 857471747 ps
CPU time 24.26 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:20:43 PM PDT 24
Peak memory 242292 kb
Host smart-6d82ffac-4a9d-4b50-ab1f-dbaa6036a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700485277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3700485277
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.1531313617
Short name T564
Test name
Test status
Simulation time 2270859295 ps
CPU time 27.68 seconds
Started Jun 27 07:17:14 PM PDT 24
Finished Jun 27 07:20:46 PM PDT 24
Peak memory 242160 kb
Host smart-6926f88d-bcee-4c19-a947-3a4901ff5533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531313617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.1531313617
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.127820315
Short name T494
Test name
Test status
Simulation time 480343322 ps
CPU time 6.75 seconds
Started Jun 27 07:17:08 PM PDT 24
Finished Jun 27 07:20:02 PM PDT 24
Peak memory 242012 kb
Host smart-d1a94988-3ca3-4d30-8a15-fe3aae13e5a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=127820315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.127820315
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3065926946
Short name T895
Test name
Test status
Simulation time 5582976552 ps
CPU time 13.2 seconds
Started Jun 27 07:17:10 PM PDT 24
Finished Jun 27 07:20:29 PM PDT 24
Peak memory 242088 kb
Host smart-a38c9d0a-8ae6-4cfa-813e-ca205bd4648a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065926946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3065926946
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.1785897535
Short name T281
Test name
Test status
Simulation time 3017376553 ps
CPU time 83.71 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:21:33 PM PDT 24
Peak memory 248748 kb
Host smart-65188f1e-5ee8-44d4-92af-8a3ab07f61f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785897535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
1785897535
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2343158521
Short name T320
Test name
Test status
Simulation time 265924489822 ps
CPU time 746.66 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:33:39 PM PDT 24
Peak memory 339968 kb
Host smart-73931345-41c7-474f-969c-508a1f0207ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343158521 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.2343158521
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1969090858
Short name T683
Test name
Test status
Simulation time 2396927764 ps
CPU time 10.46 seconds
Started Jun 27 07:17:13 PM PDT 24
Finished Jun 27 07:20:29 PM PDT 24
Peak memory 242236 kb
Host smart-b514f761-e929-432a-9725-29e47892f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969090858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1969090858
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.1529803073
Short name T79
Test name
Test status
Simulation time 269681915 ps
CPU time 3.69 seconds
Started Jun 27 07:23:32 PM PDT 24
Finished Jun 27 07:25:55 PM PDT 24
Peak memory 242164 kb
Host smart-532cd425-4685-4616-b777-931dc5556b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529803073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1529803073
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2104438683
Short name T912
Test name
Test status
Simulation time 1872526073 ps
CPU time 15.32 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:26:07 PM PDT 24
Peak memory 241884 kb
Host smart-9e2e676e-077c-460d-96be-84c44b50cf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104438683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2104438683
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1837137919
Short name T777
Test name
Test status
Simulation time 126477909 ps
CPU time 3.49 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:26:33 PM PDT 24
Peak memory 242128 kb
Host smart-98022517-7d70-406a-858a-34dd9a4cb4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837137919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1837137919
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.888624641
Short name T910
Test name
Test status
Simulation time 6563752405 ps
CPU time 11.7 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:26:03 PM PDT 24
Peak memory 242352 kb
Host smart-f1e8f9e8-a4c6-4c95-a5e7-d5eef596b2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888624641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.888624641
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.325866269
Short name T145
Test name
Test status
Simulation time 126596670 ps
CPU time 4.04 seconds
Started Jun 27 07:23:32 PM PDT 24
Finished Jun 27 07:26:17 PM PDT 24
Peak memory 242400 kb
Host smart-e9566250-cc2b-4c0e-bdd6-7f567d62d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325866269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.325866269
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.1572487244
Short name T173
Test name
Test status
Simulation time 4168222271 ps
CPU time 8.87 seconds
Started Jun 27 07:23:42 PM PDT 24
Finished Jun 27 07:27:16 PM PDT 24
Peak memory 242212 kb
Host smart-471a7895-e8bd-4893-b629-e3edacdb86ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572487244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1572487244
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2570950683
Short name T370
Test name
Test status
Simulation time 635172873910 ps
CPU time 1230.02 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:45:57 PM PDT 24
Peak memory 355452 kb
Host smart-484f10a8-e09d-4d29-82ab-7be04f95b46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570950683 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.2570950683
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.1461509785
Short name T201
Test name
Test status
Simulation time 523468374 ps
CPU time 4.19 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:25:31 PM PDT 24
Peak memory 242184 kb
Host smart-a5706ec0-073b-4746-b4bf-5363b7e4ad47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461509785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.1461509785
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.878948873
Short name T1020
Test name
Test status
Simulation time 181802901 ps
CPU time 3.01 seconds
Started Jun 27 07:23:30 PM PDT 24
Finished Jun 27 07:26:32 PM PDT 24
Peak memory 241900 kb
Host smart-e4fd7a92-aa14-4791-8fa6-c1944abb5787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878948873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.878948873
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.1917721394
Short name T884
Test name
Test status
Simulation time 36429002246 ps
CPU time 1036.89 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:44:05 PM PDT 24
Peak memory 265360 kb
Host smart-1f2b70e6-38d4-4fe5-8f13-b135404c5be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917721394 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.1917721394
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.1251390196
Short name T495
Test name
Test status
Simulation time 298173201 ps
CPU time 3.83 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:26:38 PM PDT 24
Peak memory 241936 kb
Host smart-8e465b35-5749-4705-8776-2022054859d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251390196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.1251390196
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1176572303
Short name T223
Test name
Test status
Simulation time 3310191084 ps
CPU time 11.71 seconds
Started Jun 27 07:23:27 PM PDT 24
Finished Jun 27 07:26:28 PM PDT 24
Peak memory 241896 kb
Host smart-5d425da5-0a45-4861-9071-3bbc6eb662db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176572303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1176572303
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.146085470
Short name T259
Test name
Test status
Simulation time 32744349041 ps
CPU time 893.02 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:40:44 PM PDT 24
Peak memory 258736 kb
Host smart-4188079f-840b-4726-a9b0-20715c93c577
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146085470 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.146085470
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.3267367560
Short name T117
Test name
Test status
Simulation time 130339524 ps
CPU time 3.18 seconds
Started Jun 27 07:23:26 PM PDT 24
Finished Jun 27 07:26:32 PM PDT 24
Peak memory 242064 kb
Host smart-60177ccc-262f-4094-a4ec-8a63a3377dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267367560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.3267367560
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.2822354402
Short name T101
Test name
Test status
Simulation time 260922448 ps
CPU time 5.67 seconds
Started Jun 27 07:23:39 PM PDT 24
Finished Jun 27 07:26:12 PM PDT 24
Peak memory 241756 kb
Host smart-d7e0ab5b-520d-40fa-8a8d-e06a9b7d9b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822354402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2822354402
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.763586092
Short name T943
Test name
Test status
Simulation time 126357840626 ps
CPU time 685.8 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:37:39 PM PDT 24
Peak memory 309232 kb
Host smart-e174db0b-63ad-4684-b2f7-802aa2b4b237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763586092 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.763586092
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.1947917359
Short name T48
Test name
Test status
Simulation time 451007824 ps
CPU time 3.7 seconds
Started Jun 27 07:23:40 PM PDT 24
Finished Jun 27 07:26:25 PM PDT 24
Peak memory 242040 kb
Host smart-c0df23b6-406d-4c48-94dc-16349c03ac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947917359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1947917359
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2654533909
Short name T427
Test name
Test status
Simulation time 269211488 ps
CPU time 5.32 seconds
Started Jun 27 07:23:41 PM PDT 24
Finished Jun 27 07:27:11 PM PDT 24
Peak memory 241928 kb
Host smart-26ace4cc-54aa-4a51-b9a0-c40c301eb29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654533909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2654533909
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.748330883
Short name T51
Test name
Test status
Simulation time 104361166 ps
CPU time 3.18 seconds
Started Jun 27 07:23:41 PM PDT 24
Finished Jun 27 07:26:03 PM PDT 24
Peak memory 241892 kb
Host smart-ee4134a3-8f07-46f0-b923-7cf30a4b5670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748330883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.748330883
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.3880610467
Short name T806
Test name
Test status
Simulation time 1790457806 ps
CPU time 16.94 seconds
Started Jun 27 07:23:44 PM PDT 24
Finished Jun 27 07:26:49 PM PDT 24
Peak memory 241772 kb
Host smart-22a08698-8631-4b84-9d25-3343da5d5e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880610467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.3880610467
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.3161156010
Short name T737
Test name
Test status
Simulation time 205197328 ps
CPU time 3.79 seconds
Started Jun 27 07:23:41 PM PDT 24
Finished Jun 27 07:26:16 PM PDT 24
Peak memory 241960 kb
Host smart-d3241ef5-d266-4bc0-9f42-6ebfd2771f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161156010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.3161156010
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.126067607
Short name T347
Test name
Test status
Simulation time 1209200866 ps
CPU time 9.73 seconds
Started Jun 27 07:23:43 PM PDT 24
Finished Jun 27 07:26:23 PM PDT 24
Peak memory 241768 kb
Host smart-10fc4cdd-3c19-45b8-b964-17dea68898c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126067607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.126067607
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2440296869
Short name T335
Test name
Test status
Simulation time 277215312429 ps
CPU time 1685.04 seconds
Started Jun 27 07:23:41 PM PDT 24
Finished Jun 27 07:54:44 PM PDT 24
Peak memory 431728 kb
Host smart-6bf2c2c2-7df7-4ab6-8653-d550dab8bccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440296869 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2440296869
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.831086152
Short name T543
Test name
Test status
Simulation time 48780616 ps
CPU time 1.64 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:11 PM PDT 24
Peak memory 240324 kb
Host smart-76a5f00c-326b-44d8-900d-b7203d1336c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831086152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.831086152
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.2869247531
Short name T595
Test name
Test status
Simulation time 2259459112 ps
CPU time 22.89 seconds
Started Jun 27 07:17:30 PM PDT 24
Finished Jun 27 07:20:38 PM PDT 24
Peak memory 242344 kb
Host smart-2858b513-9a67-4984-9f0f-180510ccde9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869247531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.2869247531
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.554906145
Short name T739
Test name
Test status
Simulation time 1958494443 ps
CPU time 19.57 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:35 PM PDT 24
Peak memory 243152 kb
Host smart-c2e7be81-c9d7-4ccb-86a0-27a803d54d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554906145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.554906145
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.870382115
Short name T360
Test name
Test status
Simulation time 324908952 ps
CPU time 17.7 seconds
Started Jun 27 07:17:28 PM PDT 24
Finished Jun 27 07:20:27 PM PDT 24
Peak memory 242356 kb
Host smart-92ba3db5-fdb5-47a8-a185-1f49ed5bfc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870382115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.870382115
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.3926036590
Short name T923
Test name
Test status
Simulation time 1158159806 ps
CPU time 11.43 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:21 PM PDT 24
Peak memory 242024 kb
Host smart-51abf453-bfaa-43e2-9209-4d1599e9ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926036590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.3926036590
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1753867025
Short name T444
Test name
Test status
Simulation time 1476868461 ps
CPU time 4.21 seconds
Started Jun 27 07:17:32 PM PDT 24
Finished Jun 27 07:20:20 PM PDT 24
Peak memory 241896 kb
Host smart-b701a18c-67e5-496d-85e3-b1ce8dff24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753867025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1753867025
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1957130783
Short name T604
Test name
Test status
Simulation time 235971987 ps
CPU time 8.87 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:18 PM PDT 24
Peak memory 242096 kb
Host smart-5705fd41-b62d-4e95-824b-2e4cbe21f568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957130783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1957130783
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.638711663
Short name T897
Test name
Test status
Simulation time 217543390 ps
CPU time 3.71 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:20:19 PM PDT 24
Peak memory 241876 kb
Host smart-e7f1e930-e745-4bf6-87e9-52c9c4578d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638711663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.638711663
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.3088858469
Short name T471
Test name
Test status
Simulation time 651954766 ps
CPU time 15.7 seconds
Started Jun 27 07:17:30 PM PDT 24
Finished Jun 27 07:20:25 PM PDT 24
Peak memory 241884 kb
Host smart-93f65f7d-42fe-4f55-ae48-28ca705ae86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3088858469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3088858469
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.750746403
Short name T957
Test name
Test status
Simulation time 530310688 ps
CPU time 8.88 seconds
Started Jun 27 07:17:29 PM PDT 24
Finished Jun 27 07:21:25 PM PDT 24
Peak memory 241968 kb
Host smart-39ced098-52c7-45c4-9c02-a523d107dc4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750746403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.750746403
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3507634123
Short name T469
Test name
Test status
Simulation time 1002142793 ps
CPU time 10.01 seconds
Started Jun 27 07:17:42 PM PDT 24
Finished Jun 27 07:20:25 PM PDT 24
Peak memory 242100 kb
Host smart-d9b939e6-6883-42f6-8a36-c9472989aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507634123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3507634123
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3889788564
Short name T772
Test name
Test status
Simulation time 37019579303 ps
CPU time 546.26 seconds
Started Jun 27 07:17:30 PM PDT 24
Finished Jun 27 07:29:22 PM PDT 24
Peak memory 265104 kb
Host smart-b23e8553-82ff-4fc0-b1bb-2ef9b9b3449b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889788564 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.3889788564
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.4204854222
Short name T808
Test name
Test status
Simulation time 1853665497 ps
CPU time 14.14 seconds
Started Jun 27 07:17:31 PM PDT 24
Finished Jun 27 07:20:30 PM PDT 24
Peak memory 242420 kb
Host smart-f530443c-3766-4e8a-a768-09f233dfb35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204854222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.4204854222
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.1843464257
Short name T688
Test name
Test status
Simulation time 118673831 ps
CPU time 3.03 seconds
Started Jun 27 07:26:33 PM PDT 24
Finished Jun 27 07:28:50 PM PDT 24
Peak memory 242000 kb
Host smart-e5b8eabd-bd16-49e2-8532-414817355792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843464257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1843464257
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.4182867158
Short name T585
Test name
Test status
Simulation time 185719367 ps
CPU time 4.98 seconds
Started Jun 27 07:25:08 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 241884 kb
Host smart-1c597273-c3c4-4581-9044-5130c723ec6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182867158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.4182867158
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.99996374
Short name T399
Test name
Test status
Simulation time 99432382424 ps
CPU time 721.55 seconds
Started Jun 27 07:25:08 PM PDT 24
Finished Jun 27 07:39:21 PM PDT 24
Peak memory 256724 kb
Host smart-53c30b26-86e1-4d4f-b5ca-7417308889ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99996374 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.99996374
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3379790416
Short name T721
Test name
Test status
Simulation time 123993065 ps
CPU time 3.74 seconds
Started Jun 27 07:25:22 PM PDT 24
Finished Jun 27 07:28:36 PM PDT 24
Peak memory 242308 kb
Host smart-d948b0d8-e81d-4a6e-a2bd-bed272d43ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379790416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3379790416
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.2361886701
Short name T723
Test name
Test status
Simulation time 419989140 ps
CPU time 4.73 seconds
Started Jun 27 07:25:19 PM PDT 24
Finished Jun 27 07:28:06 PM PDT 24
Peak memory 242056 kb
Host smart-872c611b-fa75-4db8-aec6-a865def6af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361886701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.2361886701
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2219116440
Short name T356
Test name
Test status
Simulation time 1084326492339 ps
CPU time 2759.12 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 08:12:48 PM PDT 24
Peak memory 434008 kb
Host smart-ffbc9cc3-132a-4c2e-b616-7320c5867ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219116440 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2219116440
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.2169766576
Short name T128
Test name
Test status
Simulation time 308157395 ps
CPU time 4.45 seconds
Started Jun 27 07:25:38 PM PDT 24
Finished Jun 27 07:27:56 PM PDT 24
Peak memory 241852 kb
Host smart-959b2b1e-8c78-4ac7-a2fa-7ad188837ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169766576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.2169766576
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.1593084357
Short name T1024
Test name
Test status
Simulation time 4255838520 ps
CPU time 14.86 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:28:07 PM PDT 24
Peak memory 242248 kb
Host smart-1c41019a-1560-4f4e-8c2d-5c10c5a4fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593084357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.1593084357
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1421646124
Short name T341
Test name
Test status
Simulation time 498229565911 ps
CPU time 897.23 seconds
Started Jun 27 07:27:23 PM PDT 24
Finished Jun 27 07:44:27 PM PDT 24
Peak memory 486664 kb
Host smart-43686b6f-f196-4ab2-b621-be00723a8a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421646124 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1421646124
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1115712871
Short name T875
Test name
Test status
Simulation time 1768258833 ps
CPU time 4.59 seconds
Started Jun 27 07:27:03 PM PDT 24
Finished Jun 27 07:29:33 PM PDT 24
Peak memory 242028 kb
Host smart-a2aa864f-635f-497e-bfc6-c214ddb0aa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115712871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1115712871
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.11924390
Short name T971
Test name
Test status
Simulation time 250376684 ps
CPU time 6.21 seconds
Started Jun 27 07:25:10 PM PDT 24
Finished Jun 27 07:27:59 PM PDT 24
Peak memory 241892 kb
Host smart-2a116600-4fc3-4be7-99c2-87d792255346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11924390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.11924390
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1465721422
Short name T334
Test name
Test status
Simulation time 107252092700 ps
CPU time 577.94 seconds
Started Jun 27 07:25:44 PM PDT 24
Finished Jun 27 07:37:23 PM PDT 24
Peak memory 273716 kb
Host smart-e4075666-596a-4454-bd39-ca44a38b0367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465721422 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1465721422
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.1405200445
Short name T799
Test name
Test status
Simulation time 214414314 ps
CPU time 3.93 seconds
Started Jun 27 07:25:12 PM PDT 24
Finished Jun 27 07:27:57 PM PDT 24
Peak memory 242104 kb
Host smart-ddec8b4f-29fe-4cc9-bc57-dec5cb29bcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405200445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.1405200445
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.4122647057
Short name T99
Test name
Test status
Simulation time 423295395 ps
CPU time 5.61 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:27:25 PM PDT 24
Peak memory 241872 kb
Host smart-23a10705-4363-4476-b4ce-b709d7788a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122647057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.4122647057
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2088160628
Short name T822
Test name
Test status
Simulation time 3411439326 ps
CPU time 97.57 seconds
Started Jun 27 07:24:05 PM PDT 24
Finished Jun 27 07:28:27 PM PDT 24
Peak memory 248956 kb
Host smart-259850de-268f-4aca-b70a-641bb4b31033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088160628 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2088160628
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.15632319
Short name T720
Test name
Test status
Simulation time 1922828809 ps
CPU time 3.75 seconds
Started Jun 27 07:25:34 PM PDT 24
Finished Jun 27 07:28:26 PM PDT 24
Peak memory 241948 kb
Host smart-98317adc-cd7d-44c3-8e6e-bdb955d41812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15632319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.15632319
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.2236390848
Short name T242
Test name
Test status
Simulation time 130485286 ps
CPU time 5.21 seconds
Started Jun 27 07:25:10 PM PDT 24
Finished Jun 27 07:27:42 PM PDT 24
Peak memory 242092 kb
Host smart-d3f86e7b-0211-473a-88d7-931a7baa8fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236390848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2236390848
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1205967780
Short name T942
Test name
Test status
Simulation time 202262210929 ps
CPU time 1991.62 seconds
Started Jun 27 07:25:13 PM PDT 24
Finished Jun 27 08:00:42 PM PDT 24
Peak memory 513036 kb
Host smart-f3da1d2a-6ee8-43da-824a-dc854ac379e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205967780 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1205967780
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.1934827860
Short name T536
Test name
Test status
Simulation time 1966621829 ps
CPU time 4.84 seconds
Started Jun 27 07:26:58 PM PDT 24
Finished Jun 27 07:29:09 PM PDT 24
Peak memory 241856 kb
Host smart-2b03f309-e3f2-456c-a137-292788c5cf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934827860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1934827860
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3904854339
Short name T214
Test name
Test status
Simulation time 7646533687 ps
CPU time 14.09 seconds
Started Jun 27 07:27:12 PM PDT 24
Finished Jun 27 07:29:24 PM PDT 24
Peak memory 241924 kb
Host smart-e21284a9-47a0-4bf8-a21e-4bde5a8e748b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904854339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3904854339
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.639487035
Short name T362
Test name
Test status
Simulation time 80881021837 ps
CPU time 339.94 seconds
Started Jun 27 07:25:14 PM PDT 24
Finished Jun 27 07:33:31 PM PDT 24
Peak memory 271040 kb
Host smart-1a884b6d-474c-4b2a-8b97-ff56c9d3074f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639487035 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.639487035
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3929365479
Short name T454
Test name
Test status
Simulation time 1870983726 ps
CPU time 5.69 seconds
Started Jun 27 07:25:40 PM PDT 24
Finished Jun 27 07:27:58 PM PDT 24
Peak memory 242140 kb
Host smart-691a0739-838e-4dd1-9d53-62e655994b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929365479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3929365479
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.1079143975
Short name T824
Test name
Test status
Simulation time 184507864 ps
CPU time 3.21 seconds
Started Jun 27 07:25:22 PM PDT 24
Finished Jun 27 07:27:41 PM PDT 24
Peak memory 241952 kb
Host smart-53db88c6-e6b2-422e-a88a-37ad5db65760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079143975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1079143975
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1748466229
Short name T193
Test name
Test status
Simulation time 199051668 ps
CPU time 3.83 seconds
Started Jun 27 07:25:15 PM PDT 24
Finished Jun 27 07:27:34 PM PDT 24
Peak memory 241840 kb
Host smart-c87568ab-72c8-4f62-9e2d-2eac864caaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748466229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1748466229
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.3435292838
Short name T169
Test name
Test status
Simulation time 482429704 ps
CPU time 5.73 seconds
Started Jun 27 07:25:04 PM PDT 24
Finished Jun 27 07:27:13 PM PDT 24
Peak memory 241712 kb
Host smart-0ad3ba2c-5edb-46c8-aeba-4d8ae4b5b233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435292838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3435292838
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.1271310312
Short name T801
Test name
Test status
Simulation time 396391981 ps
CPU time 4.61 seconds
Started Jun 27 07:25:08 PM PDT 24
Finished Jun 27 07:27:49 PM PDT 24
Peak memory 241932 kb
Host smart-4d1a5d65-ad78-4a45-853a-aab3fe604f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271310312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.1271310312
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3741166279
Short name T722
Test name
Test status
Simulation time 583971351 ps
CPU time 9.61 seconds
Started Jun 27 07:28:38 PM PDT 24
Finished Jun 27 07:31:28 PM PDT 24
Peak memory 241940 kb
Host smart-70577af3-2065-4b54-89a1-41ddc117047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741166279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3741166279
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1229187111
Short name T872
Test name
Test status
Simulation time 55003399787 ps
CPU time 506.54 seconds
Started Jun 27 07:25:45 PM PDT 24
Finished Jun 27 07:36:18 PM PDT 24
Peak memory 248912 kb
Host smart-b6aab4f1-f105-4636-9696-57291d46c4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229187111 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1229187111
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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