Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_1_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_1_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_1_req_during_sram_0_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_1_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11646

1

T3

49

T4

22

T5

10

auto[1]

616

1

T3

1

T111

3

T101

4

---

Summary for Variable sram_1_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11572

1

T3

35

T4

22

T5

10

auto[1]

690

1

T3

15

T111

2

T101

11

---

Summary for Variable sram_1_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_1_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

12226

1

T3

50

T4

22

T5

10

lc_esc_on

36

1

T212

1

T220

1

T14

1

---

Summary for Variable sram_1_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11747

1

T3

49

T4

22

T5

10

auto[1]

515

1

T3

1

T12

4

T101

5

---

Summary for Variable sram_1_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1708

1

T3

25

T6

19

T25

8

auto[1]

10554

1

T3

25

T4

22

T5

10

---

Summary for Variable sram_1_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12182

1

T3

42

T4

22

T5

10

auto[1]

80

1

T3

8

T211

1

T212

1