Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.56	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	12	60	83.33

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	12	60	83.33	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	50270	1			T4	54		T6	53		T105	34
access_err	58864	1			T4	113		T5	7		T8	349
write_blank_err	439	1			T12	4		T13	3		T120	1
ecc_uncorr_err	62738	1			T5	51		T108	235		T12	840
ecc_corr_err	1168	1			T5	3		T10	5		T108	12
no_err	87642	1			T4	308		T5	18		T8	277

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	875	1			T12	12		T13	19		T14	1
secret2	23745	1			T4	33		T5	4		T8	71
secret1	29490	1			T4	90		T5	1		T8	53
secret0	32794	1			T4	30		T5	18		T8	54
hw_cfg1	34648	1			T4	51		T5	15		T8	60
hw_cfg0	25198	1			T4	25		T5	6		T8	54
rot_creator_auth_state	19807	1			T4	51		T5	20		T8	43
rot_creator_auth_codesign	21266	1			T4	67		T5	5		T8	75
owner_sw_cfg	20187	1			T4	46		T5	4		T8	86
creator_sw_cfg	20555	1			T4	47		T5	3		T8	55
vendor_test	32556	1			T4	35		T5	3		T8	75

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	12	60	83.33	12
Automatically Generated Cross Bins	72	12	60	83.33	12
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	life_cycle	155	1			T386	155		-	-		-	-
fsm_err	secret2	4153	1			T163	480		T387	172		T242	2
fsm_err	secret1	5361	1			T4	54		T119	70		T212	197
fsm_err	secret0	2811	1			T149	161		T388	267		T140	78
fsm_err	hw_cfg1	4276	1			T161	101		T14	184		T154	78
fsm_err	hw_cfg0	3884	1			T96	186		T97	251		T151	84
fsm_err	rot_creator_auth_state	2423	1			T389	588		T140	211		T243	30
fsm_err	rot_creator_auth_codesign	4117	1			T105	34		T135	54		T176	75
fsm_err	owner_sw_cfg	4011	1			T6	53		T13	340		T213	135
fsm_err	creator_sw_cfg	3667	1			T108	11		T390	61		T391	113
fsm_err	vendor_test	15412	1			T109	460		T110	295		T167	56
access_err	life_cycle	720	1			T12	12		T13	19		T14	1
access_err	secret2	10383	1			T4	6		T5	4		T8	57
access_err	secret1	5820	1			T8	45		T25	4		T7	2
access_err	secret0	4696	1			T4	2		T5	1		T8	28
access_err	hw_cfg1	1216	1			T4	2		T8	5		T9	1
access_err	hw_cfg0	2102	1			T8	13		T25	2		T12	13
access_err	rot_creator_auth_state	5717	1			T4	33		T8	26		T25	3
access_err	rot_creator_auth_codesign	7459	1			T4	29		T5	2		T8	51
access_err	owner_sw_cfg	6221	1			T4	14		T8	30		T6	1
access_err	creator_sw_cfg	7140	1			T4	19		T8	46		T6	1
access_err	vendor_test	7390	1			T4	8		T8	48		T6	2
write_blank_err	secret2	11	1			T216	1		T392	1		T393	1
write_blank_err	secret1	22	1			T69	1		T296	1		T143	1
write_blank_err	secret0	44	1			T12	2		T13	1		T120	1
write_blank_err	hw_cfg1	71	1			T12	1		T13	1		T14	1
write_blank_err	hw_cfg0	21	1			T13	1		T16	1		T379	1
write_blank_err	rot_creator_auth_state	149	1			T12	1		T69	3		T216	4
write_blank_err	rot_creator_auth_codesign	67	1			T69	1		T392	3		T300	2
write_blank_err	owner_sw_cfg	20	1			T14	1		T379	1		T143	1
write_blank_err	creator_sw_cfg	9	1			T144	1		T394	1		T395	1
write_blank_err	vendor_test	25	1			T14	1		T154	1		T392	1
ecc_uncorr_err	secret2	3862	1			T216	270		T392	682		T396	37
ecc_uncorr_err	secret1	9599	1			T167	111		T99	53		T69	588
ecc_uncorr_err	secret0	16922	1			T5	17		T108	31		T12	511
ecc_uncorr_err	hw_cfg1	18365	1			T5	15		T108	27		T12	329
ecc_uncorr_err	hw_cfg0	7407	1			T108	27		T167	52		T99	66
ecc_uncorr_err	rot_creator_auth_state	3416	1			T5	19		T108	21		T167	108
ecc_uncorr_err	rot_creator_auth_codesign	916	1			T108	52		T123	15		T99	59
ecc_uncorr_err	owner_sw_cfg	810	1			T108	77		T397	45		T398	39
ecc_uncorr_err	creator_sw_cfg	1441	1			T167	57		T397	23		T224	7
ecc_corr_err	secret2	55	1			T108	2		T99	1		T43	2
ecc_corr_err	secret1	122	1			T5	1		T108	2		T167	1
ecc_corr_err	secret0	95	1			T108	3		T50	6		T43	2
ecc_corr_err	hw_cfg1	234	1			T167	1		T50	19		T43	9
ecc_corr_err	hw_cfg0	211	1			T5	1		T108	1		T13	2
ecc_corr_err	rot_creator_auth_state	131	1			T10	1		T50	4		T43	4
ecc_corr_err	rot_creator_auth_codesign	86	1			T10	2		T50	2		T398	1
ecc_corr_err	owner_sw_cfg	146	1			T5	1		T108	4		T167	3
ecc_corr_err	creator_sw_cfg	88	1			T10	2		T50	1		T43	6
no_err	secret2	5281	1			T4	27		T8	14		T6	2
no_err	secret1	8566	1			T4	36		T8	8		T9	3
no_err	secret0	8226	1			T4	28		T8	26		T10	1
no_err	hw_cfg1	10486	1			T4	49		T8	55		T9	3
no_err	hw_cfg0	11573	1			T4	25		T5	5		T8	41
no_err	rot_creator_auth_state	7971	1			T4	18		T5	1		T8	17
no_err	rot_creator_auth_codesign	8621	1			T4	38		T5	3		T8	24
no_err	owner_sw_cfg	8979	1			T4	32		T5	3		T8	56
no_err	creator_sw_cfg	8210	1			T4	28		T5	3		T8	9
no_err	vendor_test	9729	1			T4	27		T5	3		T8	27

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded