Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1550 |
1 |
|
|
T5 |
1 |
|
T10 |
3 |
|
T7 |
33 |
auto[1] |
1020 |
1 |
|
|
T100 |
11 |
|
T216 |
20 |
|
T217 |
18 |
Summary for Variable sram_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for sram_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
64 |
1 |
|
|
T154 |
3 |
|
T219 |
4 |
|
T429 |
1 |
sram_key[0x1] |
823 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T7 |
12 |
sram_key[0x2] |
844 |
1 |
|
|
T10 |
1 |
|
T7 |
9 |
|
T100 |
4 |
sram_key[0x3] |
839 |
1 |
|
|
T10 |
1 |
|
T7 |
12 |
|
T100 |
6 |
Summary for Cross sram_req_lock_cross
Samples crossed: sram_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for sram_req_lock_cross
Bins
sram_index | secret1_lock | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sram_key[0x0] |
auto[0] |
38 |
1 |
|
|
T154 |
3 |
|
T219 |
1 |
|
T143 |
2 |
sram_key[0x0] |
auto[1] |
26 |
1 |
|
|
T219 |
3 |
|
T429 |
1 |
|
T143 |
3 |
sram_key[0x1] |
auto[0] |
495 |
1 |
|
|
T5 |
1 |
|
T10 |
1 |
|
T7 |
12 |
sram_key[0x1] |
auto[1] |
328 |
1 |
|
|
T100 |
1 |
|
T216 |
6 |
|
T217 |
6 |
sram_key[0x2] |
auto[0] |
504 |
1 |
|
|
T10 |
1 |
|
T7 |
9 |
|
T14 |
2 |
sram_key[0x2] |
auto[1] |
340 |
1 |
|
|
T100 |
4 |
|
T216 |
7 |
|
T217 |
6 |
sram_key[0x3] |
auto[0] |
513 |
1 |
|
|
T10 |
1 |
|
T7 |
12 |
|
T14 |
4 |
sram_key[0x3] |
auto[1] |
326 |
1 |
|
|
T100 |
6 |
|
T216 |
7 |
|
T217 |
6 |