Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
854 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T216 |
7 |
all_values[1] |
854 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T216 |
7 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
915 |
1 |
|
|
T13 |
5 |
|
T14 |
6 |
|
T216 |
12 |
auto[1] |
793 |
1 |
|
|
T13 |
3 |
|
T14 |
2 |
|
T216 |
2 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
680 |
1 |
|
|
T13 |
1 |
|
T14 |
2 |
|
T216 |
8 |
auto[1] |
1028 |
1 |
|
|
T13 |
7 |
|
T14 |
6 |
|
T216 |
6 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
1010 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T216 |
10 |
auto[1] |
698 |
1 |
|
|
T13 |
4 |
|
T14 |
4 |
|
T216 |
4 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
12 |
0 |
12 |
100.00 |
|
Automatically Generated Cross Bins |
12 |
0 |
12 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
174 |
1 |
|
|
T14 |
1 |
|
T216 |
2 |
|
T15 |
5 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
74 |
1 |
|
|
T13 |
2 |
|
T216 |
1 |
|
T295 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
166 |
1 |
|
|
T15 |
7 |
|
T16 |
4 |
|
T383 |
5 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
91 |
1 |
|
|
T14 |
1 |
|
T216 |
1 |
|
T295 |
1 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
205 |
1 |
|
|
T13 |
2 |
|
T14 |
1 |
|
T216 |
2 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
144 |
1 |
|
|
T14 |
1 |
|
T216 |
1 |
|
T15 |
3 |
all_values[1] |
auto[0] |
auto[0] |
auto[0] |
197 |
1 |
|
|
T14 |
1 |
|
T216 |
6 |
|
T295 |
3 |
all_values[1] |
auto[0] |
auto[0] |
auto[1] |
76 |
1 |
|
|
T14 |
1 |
|
T15 |
3 |
|
T16 |
2 |
all_values[1] |
auto[0] |
auto[1] |
auto[0] |
143 |
1 |
|
|
T13 |
1 |
|
T154 |
2 |
|
T15 |
1 |
all_values[1] |
auto[0] |
auto[1] |
auto[1] |
89 |
1 |
|
|
T13 |
1 |
|
T383 |
1 |
|
T140 |
1 |
all_values[1] |
auto[1] |
auto[0] |
auto[1] |
189 |
1 |
|
|
T13 |
1 |
|
T14 |
2 |
|
T216 |
1 |
all_values[1] |
auto[1] |
auto[1] |
auto[1] |
160 |
1 |
|
|
T13 |
1 |
|
T154 |
1 |
|
T15 |
3 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |