Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

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Summary for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::otbn_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
otbn_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
otbn_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
otbn_req_during_lc_esc	2	0	2	100.00	100	1	1	0
otbn_req_during_otp_idle	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
otbn_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable otbn_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12244

1

T1

4

T3

4

T4

22

auto[1]

978

1

T7

5

T43

3

T102

3

---

Summary for Variable otbn_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12257

1

T1

4

T3

4

T4

22

auto[1]

965

1

T7

8

T43

3

T102

8

---

Summary for Variable otbn_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for otbn_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

13185

1

T1

4

T3

4

T4

22

lc_esc_on

37

1

T100

1

T137

1

T113

1

---

Summary for Variable otbn_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2528

1

T4

1

T6

3

T100

1

auto[1]

10694

1

T1

4

T3

4

T4

21

---

Summary for Variable otbn_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12319

1

T1

4

T3

4

T4

22

auto[1]

903

1

T7

5

T43

1

T102

8

---

Summary for Variable otbn_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12776

1

T1

4

T3

4

T4

22

auto[1]

446

1

T102

1

T103

2

T31

2