SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
84.44 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 18 | 1 | 17 | 94.44 |
Crosses | 72 | 13 | 59 | 81.94 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
err_code_vals | 7 | 1 | 6 | 85.71 | 100 | 1 | 1 | 0 | |
partition | 11 | 0 | 11 | 100.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
dai_err_code_for_all_partitions | 72 | 13 | 59 | 81.94 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 7 | 1 | 6 | 85.71 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
macro_err | 0 | 1 | 1 |
NAME | COUNT | STATUS |
illegal_err | 0 | Illegal |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | 49656 | 1 | T9 | 64 | T6 | 340 | T98 | 43 | ||||
access_err | 60007 | 1 | T3 | 4 | T5 | 42 | T4 | 2 | ||||
write_blank_err | 405 | 1 | T5 | 1 | T6 | 14 | T7 | 6 | ||||
ecc_uncorr_err | 66990 | 1 | T5 | 110 | T4 | 359 | T6 | 1285 | ||||
ecc_corr_err | 1260 | 1 | T3 | 4 | T4 | 1 | T6 | 3 | ||||
no_err | 87680 | 1 | T1 | 35 | T3 | 22 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 11 | 0 | 11 | 100.00 |
NAME | COUNT | STATUS |
illegal_idx | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
life_cycle | 665 | 1 | T5 | 11 | T6 | 17 | T7 | 16 | ||||
secret2 | 23568 | 1 | T1 | 6 | T3 | 2 | T5 | 5 | ||||
secret1 | 28709 | 1 | T1 | 1 | T3 | 1 | T5 | 126 | ||||
secret0 | 34858 | 1 | T1 | 6 | T3 | 3 | T5 | 3 | ||||
hw_cfg1 | 41572 | 1 | T1 | 2 | T3 | 2 | T12 | 1 | ||||
hw_cfg0 | 24485 | 1 | T1 | 3 | T3 | 2 | T9 | 65 | ||||
rot_creator_auth_state | 21017 | 1 | T1 | 4 | T3 | 7 | T5 | 8 | ||||
rot_creator_auth_codesign | 21486 | 1 | T3 | 3 | T5 | 15 | T4 | 41 | ||||
owner_sw_cfg | 20568 | 1 | T1 | 3 | T3 | 1 | T5 | 11 | ||||
creator_sw_cfg | 19590 | 1 | T1 | 7 | T3 | 7 | T5 | 9 | ||||
vendor_test | 29480 | 1 | T1 | 3 | T3 | 2 | T5 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 72 | 13 | 59 | 81.94 | 13 |
Automatically Generated Cross Bins | 72 | 13 | 59 | 81.94 | 13 |
User Defined Cross Bins | 0 | 0 | 0 |
err_code_vals | partition | COUNT | AT LEAST | NUMBER | STATUS |
[fsm_err] | [life_cycle] | 0 | 1 | 1 | |
[ecc_corr_err] | [vendor_test] | 0 | 1 | 1 | |
[macro_err] | [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] | -- | -- | 10 | |
[no_err] | [life_cycle] | 0 | 1 | 1 |
err_code_vals | partition | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
fsm_err | secret2 | 4763 | 1 | T6 | 1 | T21 | 188 | T22 | 336 | ||||
fsm_err | secret1 | 4061 | 1 | T156 | 78 | T159 | 66 | T355 | 16 | ||||
fsm_err | secret0 | 6227 | 1 | T6 | 339 | T137 | 60 | T154 | 558 | ||||
fsm_err | hw_cfg1 | 3734 | 1 | T100 | 74 | T253 | 51 | T356 | 42 | ||||
fsm_err | hw_cfg0 | 4155 | 1 | T9 | 64 | T357 | 205 | T157 | 31 | ||||
fsm_err | rot_creator_auth_state | 2994 | 1 | T110 | 154 | T113 | 257 | T209 | 3 | ||||
fsm_err | rot_creator_auth_codesign | 4594 | 1 | T175 | 34 | T186 | 23 | T260 | 462 | ||||
fsm_err | owner_sw_cfg | 4005 | 1 | T101 | 83 | T21 | 139 | T297 | 121 | ||||
fsm_err | creator_sw_cfg | 2725 | 1 | T168 | 185 | T284 | 102 | T118 | 115 | ||||
fsm_err | vendor_test | 12398 | 1 | T98 | 43 | T121 | 295 | T73 | 26 | ||||
access_err | life_cycle | 665 | 1 | T5 | 11 | T6 | 17 | T7 | 16 | ||||
access_err | secret2 | 10608 | 1 | T5 | 5 | T4 | 2 | T6 | 24 | ||||
access_err | secret1 | 5576 | 1 | T17 | 18 | T119 | 20 | T19 | 69 | ||||
access_err | secret0 | 4662 | 1 | T3 | 1 | T6 | 1 | T17 | 12 | ||||
access_err | hw_cfg1 | 1261 | 1 | T6 | 5 | T32 | 1 | T119 | 4 | ||||
access_err | hw_cfg0 | 2156 | 1 | T17 | 10 | T19 | 12 | T7 | 12 | ||||
access_err | rot_creator_auth_state | 5820 | 1 | T5 | 2 | T6 | 14 | T17 | 9 | ||||
access_err | rot_creator_auth_codesign | 7835 | 1 | T3 | 3 | T5 | 8 | T6 | 10 | ||||
access_err | owner_sw_cfg | 6801 | 1 | T5 | 6 | T6 | 5 | T17 | 14 | ||||
access_err | creator_sw_cfg | 7384 | 1 | T5 | 2 | T6 | 9 | T17 | 14 | ||||
access_err | vendor_test | 7239 | 1 | T5 | 8 | T6 | 22 | T17 | 22 | ||||
write_blank_err | secret2 | 9 | 1 | T109 | 1 | T358 | 1 | T342 | 1 | ||||
write_blank_err | secret1 | 21 | 1 | T5 | 1 | T21 | 1 | T359 | 1 | ||||
write_blank_err | secret0 | 39 | 1 | T6 | 1 | T7 | 2 | T102 | 1 | ||||
write_blank_err | hw_cfg1 | 80 | 1 | T6 | 4 | T113 | 1 | T174 | 1 | ||||
write_blank_err | hw_cfg0 | 16 | 1 | T6 | 1 | T102 | 1 | T20 | 1 | ||||
write_blank_err | rot_creator_auth_state | 122 | 1 | T6 | 5 | T7 | 4 | T113 | 4 | ||||
write_blank_err | rot_creator_auth_codesign | 49 | 1 | T20 | 1 | T360 | 1 | T361 | 3 | ||||
write_blank_err | owner_sw_cfg | 27 | 1 | T6 | 2 | T157 | 5 | T131 | 1 | ||||
write_blank_err | creator_sw_cfg | 13 | 1 | T142 | 2 | T265 | 1 | T362 | 1 | ||||
write_blank_err | vendor_test | 29 | 1 | T6 | 1 | T174 | 1 | T360 | 1 | ||||
ecc_uncorr_err | secret2 | 3039 | 1 | T175 | 35 | T186 | 25 | T109 | 247 | ||||
ecc_uncorr_err | secret1 | 10274 | 1 | T5 | 110 | T4 | 137 | T98 | 72 | ||||
ecc_uncorr_err | secret0 | 15525 | 1 | T4 | 81 | T6 | 234 | T98 | 44 | ||||
ecc_uncorr_err | hw_cfg1 | 25845 | 1 | T4 | 52 | T6 | 1051 | T113 | 557 | ||||
ecc_uncorr_err | hw_cfg0 | 5791 | 1 | T98 | 34 | T175 | 70 | T109 | 229 | ||||
ecc_uncorr_err | rot_creator_auth_state | 3970 | 1 | T4 | 48 | T14 | 495 | T175 | 35 | ||||
ecc_uncorr_err | rot_creator_auth_codesign | 654 | 1 | T4 | 41 | T209 | 8 | T363 | 69 | ||||
ecc_uncorr_err | owner_sw_cfg | 756 | 1 | T175 | 77 | T211 | 66 | T257 | 78 | ||||
ecc_uncorr_err | creator_sw_cfg | 1136 | 1 | T186 | 50 | T183 | 11 | T211 | 66 | ||||
ecc_corr_err | secret2 | 64 | 1 | T98 | 1 | T44 | 1 | T76 | 1 | ||||
ecc_corr_err | secret1 | 122 | 1 | T98 | 1 | T75 | 2 | T44 | 2 | ||||
ecc_corr_err | secret0 | 124 | 1 | T75 | 4 | T175 | 1 | T76 | 4 | ||||
ecc_corr_err | hw_cfg1 | 263 | 1 | T3 | 1 | T6 | 1 | T98 | 1 | ||||
ecc_corr_err | hw_cfg0 | 221 | 1 | T6 | 2 | T75 | 6 | T44 | 7 | ||||
ecc_corr_err | rot_creator_auth_state | 104 | 1 | T3 | 3 | T98 | 1 | T75 | 2 | ||||
ecc_corr_err | rot_creator_auth_codesign | 138 | 1 | T98 | 1 | T44 | 1 | T175 | 2 | ||||
ecc_corr_err | owner_sw_cfg | 83 | 1 | T75 | 1 | T44 | 3 | T175 | 1 | ||||
ecc_corr_err | creator_sw_cfg | 141 | 1 | T4 | 1 | T75 | 1 | T44 | 2 | ||||
no_err | secret2 | 5085 | 1 | T1 | 6 | T3 | 2 | T6 | 27 | ||||
no_err | secret1 | 8655 | 1 | T1 | 1 | T3 | 1 | T5 | 15 | ||||
no_err | secret0 | 8281 | 1 | T1 | 6 | T3 | 2 | T5 | 3 | ||||
no_err | hw_cfg1 | 10389 | 1 | T1 | 2 | T3 | 1 | T12 | 1 | ||||
no_err | hw_cfg0 | 12146 | 1 | T1 | 3 | T3 | 2 | T9 | 1 | ||||
no_err | rot_creator_auth_state | 8007 | 1 | T1 | 4 | T3 | 4 | T5 | 6 | ||||
no_err | rot_creator_auth_codesign | 8216 | 1 | T5 | 7 | T6 | 24 | T48 | 4 | ||||
no_err | owner_sw_cfg | 8896 | 1 | T1 | 3 | T3 | 1 | T5 | 5 | ||||
no_err | creator_sw_cfg | 8191 | 1 | T1 | 7 | T3 | 7 | T5 | 7 | ||||
no_err | vendor_test | 9814 | 1 | T1 | 3 | T3 | 2 | T5 | 4 |
NAME | COUNT | STATUS |
vendor_test_ecc_uncorrectable_err | 0 | Illegal |
life_cycle_ignore | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |