Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.09 93.86 96.62 96.14 92.12 97.29 96.34 93.28


Total test records in report: 1321
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T1266 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1585248584 Jun 29 07:24:44 PM PDT 24 Jun 29 07:24:48 PM PDT 24 132487533 ps
T365 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2818129704 Jun 29 07:24:38 PM PDT 24 Jun 29 07:25:01 PM PDT 24 2062152769 ps
T1267 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1480485829 Jun 29 07:25:11 PM PDT 24 Jun 29 07:25:14 PM PDT 24 528754804 ps
T1268 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3313471799 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:17 PM PDT 24 38879824 ps
T1269 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1906512153 Jun 29 07:24:38 PM PDT 24 Jun 29 07:24:40 PM PDT 24 41535438 ps
T1270 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.4191680598 Jun 29 07:24:48 PM PDT 24 Jun 29 07:24:51 PM PDT 24 38975266 ps
T1271 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3428492067 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:19 PM PDT 24 578306346 ps
T315 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3767916689 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:49 PM PDT 24 105986744 ps
T316 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1803015776 Jun 29 07:25:11 PM PDT 24 Jun 29 07:25:13 PM PDT 24 40358149 ps
T1272 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4208935318 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:19 PM PDT 24 564117396 ps
T1273 /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2462376117 Jun 29 07:24:56 PM PDT 24 Jun 29 07:24:59 PM PDT 24 133169536 ps
T1274 /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.653223018 Jun 29 07:24:52 PM PDT 24 Jun 29 07:24:55 PM PDT 24 96488383 ps
T1275 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2452351352 Jun 29 07:24:36 PM PDT 24 Jun 29 07:24:39 PM PDT 24 76203077 ps
T1276 /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.501842816 Jun 29 07:24:54 PM PDT 24 Jun 29 07:24:56 PM PDT 24 37563910 ps
T329 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4121777420 Jun 29 07:25:08 PM PDT 24 Jun 29 07:25:11 PM PDT 24 65177436 ps
T1277 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.81886295 Jun 29 07:24:36 PM PDT 24 Jun 29 07:24:42 PM PDT 24 1333311056 ps
T1278 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.216152602 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:48 PM PDT 24 99685651 ps
T1279 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3917312998 Jun 29 07:25:12 PM PDT 24 Jun 29 07:25:17 PM PDT 24 1542373735 ps
T1280 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.453266394 Jun 29 07:25:16 PM PDT 24 Jun 29 07:25:19 PM PDT 24 44105300 ps
T1281 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.617545074 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:19 PM PDT 24 37769676 ps
T371 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1695706429 Jun 29 07:24:39 PM PDT 24 Jun 29 07:24:59 PM PDT 24 1389594020 ps
T1282 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2553460095 Jun 29 07:25:07 PM PDT 24 Jun 29 07:25:09 PM PDT 24 92367934 ps
T1283 /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.631034473 Jun 29 07:25:00 PM PDT 24 Jun 29 07:25:03 PM PDT 24 789285479 ps
T1284 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3693279597 Jun 29 07:24:59 PM PDT 24 Jun 29 07:25:02 PM PDT 24 106913976 ps
T366 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1744948837 Jun 29 07:25:10 PM PDT 24 Jun 29 07:25:21 PM PDT 24 779639130 ps
T317 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.946136604 Jun 29 07:24:47 PM PDT 24 Jun 29 07:24:50 PM PDT 24 157751334 ps
T1285 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3401694208 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:49 PM PDT 24 201939402 ps
T1286 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4168124512 Jun 29 07:24:43 PM PDT 24 Jun 29 07:24:52 PM PDT 24 481329359 ps
T330 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1297422796 Jun 29 07:24:35 PM PDT 24 Jun 29 07:24:37 PM PDT 24 88267964 ps
T376 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2715961133 Jun 29 07:24:47 PM PDT 24 Jun 29 07:24:59 PM PDT 24 813354447 ps
T1287 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2296746780 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:18 PM PDT 24 508648181 ps
T1288 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1119107428 Jun 29 07:24:44 PM PDT 24 Jun 29 07:24:52 PM PDT 24 268691370 ps
T369 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2905803837 Jun 29 07:24:48 PM PDT 24 Jun 29 07:25:07 PM PDT 24 1254946791 ps
T1289 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2120665466 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:51 PM PDT 24 100797366 ps
T1290 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2009467831 Jun 29 07:25:13 PM PDT 24 Jun 29 07:25:17 PM PDT 24 204225312 ps
T1291 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2271853697 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:49 PM PDT 24 136140470 ps
T1292 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1625961715 Jun 29 07:25:16 PM PDT 24 Jun 29 07:25:19 PM PDT 24 72336767 ps
T1293 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.123622362 Jun 29 07:24:39 PM PDT 24 Jun 29 07:24:41 PM PDT 24 144720533 ps
T1294 /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.122309268 Jun 29 07:25:18 PM PDT 24 Jun 29 07:25:20 PM PDT 24 148133117 ps
T1295 /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3709469953 Jun 29 07:25:14 PM PDT 24 Jun 29 07:25:17 PM PDT 24 81288097 ps
T318 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3535415012 Jun 29 07:24:49 PM PDT 24 Jun 29 07:24:52 PM PDT 24 103690953 ps
T1296 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2457559101 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:49 PM PDT 24 55325727 ps
T1297 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3044972185 Jun 29 07:25:16 PM PDT 24 Jun 29 07:25:19 PM PDT 24 46463445 ps
T1298 /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4280968108 Jun 29 07:25:09 PM PDT 24 Jun 29 07:25:14 PM PDT 24 213244517 ps
T331 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2868158084 Jun 29 07:24:39 PM PDT 24 Jun 29 07:24:42 PM PDT 24 90795184 ps
T1299 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3614113802 Jun 29 07:24:35 PM PDT 24 Jun 29 07:24:38 PM PDT 24 76184816 ps
T1300 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3799190521 Jun 29 07:25:15 PM PDT 24 Jun 29 07:25:17 PM PDT 24 42560282 ps
T1301 /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3443032739 Jun 29 07:24:58 PM PDT 24 Jun 29 07:25:01 PM PDT 24 74623600 ps
T1302 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3154754432 Jun 29 07:25:12 PM PDT 24 Jun 29 07:25:14 PM PDT 24 171588681 ps
T1303 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4172221374 Jun 29 07:24:52 PM PDT 24 Jun 29 07:25:03 PM PDT 24 1244516903 ps
T1304 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2716841717 Jun 29 07:25:01 PM PDT 24 Jun 29 07:25:06 PM PDT 24 401424494 ps
T1305 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1442965163 Jun 29 07:25:11 PM PDT 24 Jun 29 07:25:15 PM PDT 24 427002877 ps
T1306 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2985872813 Jun 29 07:24:53 PM PDT 24 Jun 29 07:24:58 PM PDT 24 134549585 ps
T1307 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1816132650 Jun 29 07:25:02 PM PDT 24 Jun 29 07:25:05 PM PDT 24 41013228 ps
T1308 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3186441093 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:51 PM PDT 24 227911700 ps
T1309 /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2452141307 Jun 29 07:24:53 PM PDT 24 Jun 29 07:24:57 PM PDT 24 161777109 ps
T1310 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3874410775 Jun 29 07:25:14 PM PDT 24 Jun 29 07:25:17 PM PDT 24 121115001 ps
T1311 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.428930631 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:52 PM PDT 24 199546156 ps
T1312 /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3574678335 Jun 29 07:25:00 PM PDT 24 Jun 29 07:25:04 PM PDT 24 290471501 ps
T1313 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2936172356 Jun 29 07:25:00 PM PDT 24 Jun 29 07:25:12 PM PDT 24 640973581 ps
T1314 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2350654618 Jun 29 07:25:17 PM PDT 24 Jun 29 07:25:20 PM PDT 24 39906791 ps
T1315 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2143070618 Jun 29 07:24:36 PM PDT 24 Jun 29 07:24:42 PM PDT 24 863123172 ps
T1316 /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1168164720 Jun 29 07:24:45 PM PDT 24 Jun 29 07:24:52 PM PDT 24 1662706170 ps
T1317 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2210142811 Jun 29 07:25:02 PM PDT 24 Jun 29 07:25:07 PM PDT 24 77423224 ps
T319 /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.962595897 Jun 29 07:24:53 PM PDT 24 Jun 29 07:24:55 PM PDT 24 79202285 ps
T1318 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.624513539 Jun 29 07:24:39 PM PDT 24 Jun 29 07:24:41 PM PDT 24 36401677 ps
T1319 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2253385421 Jun 29 07:25:14 PM PDT 24 Jun 29 07:25:17 PM PDT 24 138139242 ps
T1320 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1103845085 Jun 29 07:24:49 PM PDT 24 Jun 29 07:24:59 PM PDT 24 703818218 ps
T332 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2894368194 Jun 29 07:25:09 PM PDT 24 Jun 29 07:25:12 PM PDT 24 117470009 ps
T1321 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.973744846 Jun 29 07:25:09 PM PDT 24 Jun 29 07:25:14 PM PDT 24 108874689 ps
T320 /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3661732105 Jun 29 07:24:53 PM PDT 24 Jun 29 07:24:56 PM PDT 24 43229937 ps

Test location /workspace/coverage/default/46.otp_ctrl_regwen.1405610706
Short name T1
Test name
Test status
Simulation time 471449805 ps
CPU time 8.04 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 242476 kb
Host smart-2670ff25-c071-407c-98b3-8be5341ab145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405610706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.1405610706
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2843278677
Short name T7
Test name
Test status
Simulation time 42877445082 ps
CPU time 220.3 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:29:55 PM PDT 24
Peak memory 266372 kb
Host smart-597e793e-9460-4fe6-81f2-430398d45151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843278677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2843278677
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.396260613
Short name T6
Test name
Test status
Simulation time 1133548277170 ps
CPU time 2874.57 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 08:16:11 PM PDT 24
Peak memory 445688 kb
Host smart-bd0b1e5f-c021-4aef-a9c9-ad3757c9e7ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396260613 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.396260613
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2524165678
Short name T102
Test name
Test status
Simulation time 32019540205 ps
CPU time 255.98 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:31:08 PM PDT 24
Peak memory 262552 kb
Host smart-9f9d3b83-6b33-484a-bb9b-fbf2c73f7477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524165678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2524165678
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.925689093
Short name T24
Test name
Test status
Simulation time 10888591587 ps
CPU time 178.9 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:28:26 PM PDT 24
Peak memory 278372 kb
Host smart-8cebb144-967b-4d86-8ef6-aebd9d07bb52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925689093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.925689093
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.164011374
Short name T177
Test name
Test status
Simulation time 112418021 ps
CPU time 3.14 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 242148 kb
Host smart-022cabdf-f2e9-4ec3-b107-d37382c84f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164011374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.164011374
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.218476415
Short name T157
Test name
Test status
Simulation time 146350418891 ps
CPU time 267.48 seconds
Started Jun 29 07:26:06 PM PDT 24
Finished Jun 29 07:30:35 PM PDT 24
Peak memory 273376 kb
Host smart-93129e6f-a6a8-486d-9a29-af1e24bc8241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218476415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.
218476415
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3907272710
Short name T39
Test name
Test status
Simulation time 191072729 ps
CPU time 4.21 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241932 kb
Host smart-e654f13e-a445-4d51-aa0c-7c096ffdc5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907272710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3907272710
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.3140908305
Short name T121
Test name
Test status
Simulation time 919028750 ps
CPU time 13.4 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:59 PM PDT 24
Peak memory 241844 kb
Host smart-1cc2393f-6f9f-4dfc-82c0-e62eea2bfc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140908305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3140908305
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.4026368284
Short name T44
Test name
Test status
Simulation time 2498473588 ps
CPU time 25.68 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:28:03 PM PDT 24
Peak memory 242696 kb
Host smart-848ac3b0-4dba-4427-9aa7-daba3113332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026368284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.4026368284
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.2315434382
Short name T21
Test name
Test status
Simulation time 1371759496467 ps
CPU time 2185.81 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 08:01:52 PM PDT 24
Peak memory 371932 kb
Host smart-67f696e1-6548-41b2-a44e-1ceffe3450a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315434382 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.2315434382
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3468134871
Short name T276
Test name
Test status
Simulation time 4991247976 ps
CPU time 21.36 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:25:15 PM PDT 24
Peak memory 239412 kb
Host smart-a9730084-b344-4921-b6ee-083afbce2aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468134871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3468134871
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.1027446086
Short name T109
Test name
Test status
Simulation time 17463779334 ps
CPU time 223.4 seconds
Started Jun 29 07:26:12 PM PDT 24
Finished Jun 29 07:29:56 PM PDT 24
Peak memory 256996 kb
Host smart-efdf332c-2d32-42f1-b1d3-6f2f8dd94e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027446086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.1027446086
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3501999140
Short name T10
Test name
Test status
Simulation time 118528005 ps
CPU time 4.51 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:25:37 PM PDT 24
Peak memory 242044 kb
Host smart-d4387083-eecf-4745-a848-f457ed32aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501999140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3501999140
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.13530908
Short name T53
Test name
Test status
Simulation time 115595770 ps
CPU time 3.93 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:26 PM PDT 24
Peak memory 242264 kb
Host smart-bb0c0146-f5fa-4a9e-bbd5-50125a638a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13530908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.13530908
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.530090983
Short name T22
Test name
Test status
Simulation time 256783402225 ps
CPU time 2151.42 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 08:02:27 PM PDT 24
Peak memory 410716 kb
Host smart-8fb87c9c-3187-49ec-8455-dcf188ceb9d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530090983 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.530090983
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.409903993
Short name T27
Test name
Test status
Simulation time 706041306 ps
CPU time 5.52 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:08 PM PDT 24
Peak memory 242252 kb
Host smart-b577beea-512f-4574-9f47-97f76b8ebedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409903993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.409903993
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.3790908117
Short name T170
Test name
Test status
Simulation time 26588038288 ps
CPU time 54.38 seconds
Started Jun 29 07:26:08 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 257084 kb
Host smart-d01148de-4955-48cb-a234-c3072a1994a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790908117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3790908117
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.4128843960
Short name T8
Test name
Test status
Simulation time 119404779 ps
CPU time 4.72 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 242084 kb
Host smart-a7f988f9-7630-48fc-9008-251fd636f4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128843960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.4128843960
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.2615511853
Short name T16
Test name
Test status
Simulation time 34856535422 ps
CPU time 272.49 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:32:05 PM PDT 24
Peak memory 264996 kb
Host smart-4227bcda-0199-4388-be66-216e0a33de08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615511853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.2615511853
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.2411823154
Short name T392
Test name
Test status
Simulation time 20855174008 ps
CPU time 209.05 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:29:58 PM PDT 24
Peak memory 265300 kb
Host smart-20cc7f83-1677-48f6-9f5a-8326428b82e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411823154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.2411823154
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.97498188
Short name T87
Test name
Test status
Simulation time 643145037 ps
CPU time 4.17 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:29 PM PDT 24
Peak memory 242172 kb
Host smart-d0c28b8f-6d3f-4806-8223-1a6f030d91c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97498188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.97498188
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1737995964
Short name T81
Test name
Test status
Simulation time 672106631 ps
CPU time 4.87 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:01 PM PDT 24
Peak memory 241916 kb
Host smart-78e75ce4-eda2-4caf-a90a-ab9eafdc1641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737995964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1737995964
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.1553354227
Short name T181
Test name
Test status
Simulation time 311813378 ps
CPU time 4.03 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 242072 kb
Host smart-007b7522-4a51-44f5-8f85-f8ac6c113d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553354227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.1553354227
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.3579151033
Short name T67
Test name
Test status
Simulation time 10235939056 ps
CPU time 17.96 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:57 PM PDT 24
Peak memory 242916 kb
Host smart-783c8cba-1d99-4ec3-8742-a1b3d768e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579151033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3579151033
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2550751153
Short name T312
Test name
Test status
Simulation time 553227656 ps
CPU time 2.18 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:06 PM PDT 24
Peak memory 241360 kb
Host smart-d2f19471-89a3-4706-b2fe-943581969018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550751153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2550751153
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.838466296
Short name T23
Test name
Test status
Simulation time 75834864958 ps
CPU time 2300.12 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 08:06:07 PM PDT 24
Peak memory 591984 kb
Host smart-c730161d-d07c-4a64-850f-3b0dfce7b258
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838466296 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.838466296
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.1644779588
Short name T11
Test name
Test status
Simulation time 189855961 ps
CPU time 4.6 seconds
Started Jun 29 07:28:17 PM PDT 24
Finished Jun 29 07:28:22 PM PDT 24
Peak memory 242412 kb
Host smart-cdb13e73-0c30-45a7-9158-28c4bd419365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644779588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1644779588
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.1610602150
Short name T205
Test name
Test status
Simulation time 130992770 ps
CPU time 4.14 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 242064 kb
Host smart-ae9a26ee-9450-40b7-aa93-567230f5ba04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610602150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1610602150
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.2655555348
Short name T57
Test name
Test status
Simulation time 243769096 ps
CPU time 4.39 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 242392 kb
Host smart-2104f465-f776-4181-9940-1cd48a0218f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655555348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.2655555348
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.1226984873
Short name T36
Test name
Test status
Simulation time 245308274 ps
CPU time 5.7 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:03 PM PDT 24
Peak memory 241932 kb
Host smart-dcae8e77-28cd-470f-8a70-ad9c366bd289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226984873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1226984873
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.1563168851
Short name T72
Test name
Test status
Simulation time 205428564 ps
CPU time 5.22 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 242080 kb
Host smart-879b971a-d077-47e9-8f7a-55f895acade2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563168851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1563168851
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.970156663
Short name T152
Test name
Test status
Simulation time 28747051031 ps
CPU time 179.55 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 258432 kb
Host smart-4614f32f-0f26-48bf-90c0-25e0e09a69d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970156663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.970156663
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.1938869367
Short name T63
Test name
Test status
Simulation time 1296293685 ps
CPU time 29.32 seconds
Started Jun 29 07:27:29 PM PDT 24
Finished Jun 29 07:27:59 PM PDT 24
Peak memory 248780 kb
Host smart-a37ee2dd-3dad-4558-aa1b-60fffcf96bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938869367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1938869367
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.4282656167
Short name T222
Test name
Test status
Simulation time 3846708813 ps
CPU time 24.43 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:26 PM PDT 24
Peak memory 248860 kb
Host smart-cbeadc3a-7275-43bf-9200-3a1b84d5a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282656167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.4282656167
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.1295011252
Short name T131
Test name
Test status
Simulation time 140162826246 ps
CPU time 228 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:30:27 PM PDT 24
Peak memory 283020 kb
Host smart-60d4a79b-9ba8-4f44-ba0e-6319b9a8bf6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295011252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.1295011252
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.980231665
Short name T144
Test name
Test status
Simulation time 2444159857 ps
CPU time 31.13 seconds
Started Jun 29 07:26:54 PM PDT 24
Finished Jun 29 07:27:25 PM PDT 24
Peak memory 249612 kb
Host smart-4ef6b9a4-8cf9-49af-8af4-cdda91f1912f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980231665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.980231665
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.2361822767
Short name T733
Test name
Test status
Simulation time 156916042031 ps
CPU time 1750.44 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:57:27 PM PDT 24
Peak memory 461716 kb
Host smart-ccea6e3a-4485-4496-80fb-4b915f7bbf6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361822767 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.2361822767
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.4289245754
Short name T18
Test name
Test status
Simulation time 87976627 ps
CPU time 2.02 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:25:52 PM PDT 24
Peak memory 240096 kb
Host smart-32750dc6-661f-4e7b-bb55-48a03746f62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289245754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.4289245754
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.604816074
Short name T164
Test name
Test status
Simulation time 372034792 ps
CPU time 8.68 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:18 PM PDT 24
Peak memory 241896 kb
Host smart-2cc96e67-c0cc-4bc3-af89-18029bb15eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604816074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.604816074
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2193660311
Short name T77
Test name
Test status
Simulation time 12526683387 ps
CPU time 43.8 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 244256 kb
Host smart-14901d9c-a27e-46d9-b98a-381f1fb0a2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193660311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2193660311
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.1563283782
Short name T34
Test name
Test status
Simulation time 1526419344 ps
CPU time 22.32 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:52 PM PDT 24
Peak memory 242080 kb
Host smart-a9ff82b1-3794-487f-b399-475199162bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563283782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.1563283782
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2070200432
Short name T149
Test name
Test status
Simulation time 267389389 ps
CPU time 5.06 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 242076 kb
Host smart-6c91f121-eb6e-4788-abbe-6d690e3a5f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070200432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2070200432
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.917237635
Short name T407
Test name
Test status
Simulation time 695659573335 ps
CPU time 2273.35 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 08:03:52 PM PDT 24
Peak memory 358452 kb
Host smart-f51520d4-207a-4214-b890-2160245bef54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917237635 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.917237635
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.886435608
Short name T138
Test name
Test status
Simulation time 162847300 ps
CPU time 3.74 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 242496 kb
Host smart-fa03c391-0647-4bce-b425-d3665fd3c2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886435608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.886435608
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.162401916
Short name T66
Test name
Test status
Simulation time 200042431 ps
CPU time 3.53 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242076 kb
Host smart-69a74699-eb79-4078-a390-39811b9540b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162401916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.162401916
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1056536876
Short name T75
Test name
Test status
Simulation time 417055239 ps
CPU time 11.51 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:14 PM PDT 24
Peak memory 242768 kb
Host smart-e28ed450-5cc0-4f99-923a-4646a8b12a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056536876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1056536876
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2083276884
Short name T534
Test name
Test status
Simulation time 3682990445 ps
CPU time 11.89 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 248844 kb
Host smart-2e3f6329-e05a-42de-a0a9-0a2998d40472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083276884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2083276884
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.3383310187
Short name T69
Test name
Test status
Simulation time 1196175415 ps
CPU time 28.72 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 242188 kb
Host smart-5809b60a-385c-4375-9e28-6dfd2b1dee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383310187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.3383310187
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.4112227135
Short name T261
Test name
Test status
Simulation time 1810334345 ps
CPU time 12.36 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241888 kb
Host smart-71b3aa7d-ead4-4ad8-96ec-32a8a1ac4d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112227135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4112227135
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.2419602904
Short name T211
Test name
Test status
Simulation time 13252387293 ps
CPU time 34.41 seconds
Started Jun 29 07:27:16 PM PDT 24
Finished Jun 29 07:27:51 PM PDT 24
Peak memory 246116 kb
Host smart-3c25f71f-b651-42b3-81aa-f774198a28f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419602904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.2419602904
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3749721320
Short name T141
Test name
Test status
Simulation time 139564582 ps
CPU time 3.04 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:33 PM PDT 24
Peak memory 242248 kb
Host smart-6ebc674e-8515-40b6-b77d-693652a82105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749721320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3749721320
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.231033090
Short name T150
Test name
Test status
Simulation time 596556123 ps
CPU time 4.15 seconds
Started Jun 29 07:28:23 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 242144 kb
Host smart-944808ff-78fd-4d3b-9d45-74e6130446b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231033090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.231033090
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.3206975104
Short name T156
Test name
Test status
Simulation time 311946988 ps
CPU time 7.04 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 242364 kb
Host smart-db825d75-b1eb-4a7e-be6f-25deaf875443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206975104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.3206975104
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.2363072786
Short name T128
Test name
Test status
Simulation time 863661822 ps
CPU time 5.92 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 241756 kb
Host smart-b6c1afa8-0ea0-4ae2-81e7-1a114eb24efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363072786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2363072786
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.2128392380
Short name T79
Test name
Test status
Simulation time 2526324579 ps
CPU time 11.83 seconds
Started Jun 29 07:29:06 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 241932 kb
Host smart-9a67935e-4085-49ba-ae97-cacadae00324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128392380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2128392380
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.1773559376
Short name T139
Test name
Test status
Simulation time 35156732322 ps
CPU time 284.42 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:32:07 PM PDT 24
Peak memory 266576 kb
Host smart-19cf664c-af9f-42c3-b980-8bb86cf9eccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773559376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.1773559376
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.1683800540
Short name T74
Test name
Test status
Simulation time 273647486 ps
CPU time 13.77 seconds
Started Jun 29 07:27:21 PM PDT 24
Finished Jun 29 07:27:36 PM PDT 24
Peak memory 241960 kb
Host smart-90f23852-848b-4247-93f7-959bd96fcf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683800540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.1683800540
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.462136483
Short name T140
Test name
Test status
Simulation time 5088909678 ps
CPU time 24.76 seconds
Started Jun 29 07:27:54 PM PDT 24
Finished Jun 29 07:28:19 PM PDT 24
Peak memory 241856 kb
Host smart-601b1613-0c0a-40a3-ad03-6f2fa6e41880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462136483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.462136483
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.3651768271
Short name T167
Test name
Test status
Simulation time 1993699628 ps
CPU time 18.62 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:41 PM PDT 24
Peak memory 241856 kb
Host smart-ca222004-dbb6-4015-93c2-ab00e9d5e608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651768271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.3651768271
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.1580697932
Short name T387
Test name
Test status
Simulation time 545326617 ps
CPU time 8.48 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 242208 kb
Host smart-07d06b88-2196-4d29-a094-e6d29f8c8fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1580697932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1580697932
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2359066952
Short name T54
Test name
Test status
Simulation time 1445023570 ps
CPU time 23.35 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:38 PM PDT 24
Peak memory 248788 kb
Host smart-9cce2bf0-1188-4c82-84d2-4b80bbda4f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359066952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2359066952
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.1002220760
Short name T362
Test name
Test status
Simulation time 15782970102 ps
CPU time 333.57 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:32:49 PM PDT 24
Peak memory 265208 kb
Host smart-f4ed2e59-f358-48a1-bf00-47fb6b720ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002220760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.1002220760
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3500502710
Short name T364
Test name
Test status
Simulation time 1297501786 ps
CPU time 18.93 seconds
Started Jun 29 07:24:29 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 244284 kb
Host smart-f26abc8e-006c-432c-b675-872704cdefcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500502710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3500502710
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1695706429
Short name T371
Test name
Test status
Simulation time 1389594020 ps
CPU time 18.41 seconds
Started Jun 29 07:24:39 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 244284 kb
Host smart-c32e17ea-af9e-48c1-b510-6d7684f466de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695706429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.1695706429
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.2016138300
Short name T284
Test name
Test status
Simulation time 3813422675 ps
CPU time 7.76 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 242104 kb
Host smart-327966e3-b540-47d4-9a6c-d03c37eeb572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016138300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.2016138300
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.3448898994
Short name T30
Test name
Test status
Simulation time 2460046695 ps
CPU time 6.12 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 242056 kb
Host smart-e6d53b8b-95c2-482b-b12d-0860b0bafc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448898994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3448898994
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3273125914
Short name T354
Test name
Test status
Simulation time 104860860356 ps
CPU time 179.02 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:28:47 PM PDT 24
Peak memory 246404 kb
Host smart-5672d36b-f7e1-4606-87ee-23c7e31e7bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273125914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3273125914
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.184606764
Short name T272
Test name
Test status
Simulation time 550197119 ps
CPU time 4.35 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 241800 kb
Host smart-3d114934-81d1-4255-930e-dd34da402655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184606764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.184606764
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.2995030925
Short name T92
Test name
Test status
Simulation time 7762221486 ps
CPU time 16.61 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:26:36 PM PDT 24
Peak memory 244640 kb
Host smart-8ac7532d-e4c9-4332-b1e9-f0024622251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995030925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2995030925
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2413527266
Short name T575
Test name
Test status
Simulation time 7101644359 ps
CPU time 72.28 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 246828 kb
Host smart-599d9c2f-7fe3-436d-afec-8b84dbd4d130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413527266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2413527266
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.1650041418
Short name T176
Test name
Test status
Simulation time 1590623397 ps
CPU time 4.11 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:29 PM PDT 24
Peak memory 242388 kb
Host smart-0d258b77-465e-4a9b-8ec9-a97ee496c44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650041418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1650041418
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.919495368
Short name T135
Test name
Test status
Simulation time 127985818 ps
CPU time 4.29 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 241808 kb
Host smart-2d99c613-c446-4d13-bd65-877814a92411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919495368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.919495368
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.3002653324
Short name T207
Test name
Test status
Simulation time 259732244 ps
CPU time 3.68 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:03 PM PDT 24
Peak memory 241832 kb
Host smart-b1c01fef-0892-4af9-8f60-3b2c2e905124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002653324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.3002653324
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.4252174078
Short name T591
Test name
Test status
Simulation time 112040441914 ps
CPU time 1468.17 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:51:12 PM PDT 24
Peak memory 313232 kb
Host smart-944aea82-f9bd-4cc7-8330-831f58785bb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252174078 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.4252174078
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2717538007
Short name T278
Test name
Test status
Simulation time 3225446541 ps
CPU time 21.55 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:24 PM PDT 24
Peak memory 239368 kb
Host smart-c7615858-1a72-4cda-9471-e02fb88fd7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717538007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2717538007
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2905803837
Short name T369
Test name
Test status
Simulation time 1254946791 ps
CPU time 17.83 seconds
Started Jun 29 07:24:48 PM PDT 24
Finished Jun 29 07:25:07 PM PDT 24
Peak memory 245436 kb
Host smart-9d644d39-3412-4483-9227-e3a00d654173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905803837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_in
tg_err.2905803837
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.4267646028
Short name T1042
Test name
Test status
Simulation time 4233475386 ps
CPU time 15.45 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:25:42 PM PDT 24
Peak memory 248800 kb
Host smart-962e8f9c-4b8c-46e7-bf70-f37ee15b2341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4267646028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.4267646028
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.4011941962
Short name T860
Test name
Test status
Simulation time 1695461733 ps
CPU time 12.15 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 242372 kb
Host smart-d70f585f-2d4c-4058-b477-eacb24449fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011941962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.4011941962
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.2788737282
Short name T410
Test name
Test status
Simulation time 109910131738 ps
CPU time 824.88 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:41:49 PM PDT 24
Peak memory 351992 kb
Host smart-bb2c9f60-1390-4f8e-ad8f-3cbf3077ecfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788737282 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.2788737282
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2006191257
Short name T281
Test name
Test status
Simulation time 397099963 ps
CPU time 2.66 seconds
Started Jun 29 07:24:38 PM PDT 24
Finished Jun 29 07:24:41 PM PDT 24
Peak memory 241236 kb
Host smart-89f00fa6-cb62-45f6-8ea3-51d39550e19d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006191257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2006191257
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.1170297838
Short name T335
Test name
Test status
Simulation time 54481889 ps
CPU time 1.87 seconds
Started Jun 29 07:24:37 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 239172 kb
Host smart-ac03d813-7170-44e3-b2b2-35ae3ff14a24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170297838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.1170297838
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.2077157803
Short name T271
Test name
Test status
Simulation time 122571860 ps
CPU time 4.37 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 241844 kb
Host smart-b010865f-1ac0-45aa-aed8-e22516db7630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077157803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2077157803
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.2983832503
Short name T173
Test name
Test status
Simulation time 85945967 ps
CPU time 1.71 seconds
Started Jun 29 07:25:17 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 240260 kb
Host smart-0e73a064-3dd1-4737-a2e8-33e870d4f781
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2983832503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2983832503
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.3801168407
Short name T49
Test name
Test status
Simulation time 2067642463 ps
CPU time 4.79 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 242176 kb
Host smart-b3c0a4af-3a0a-4dd0-b8b6-f1a9dec198c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801168407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3801168407
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3621112225
Short name T266
Test name
Test status
Simulation time 53568741625 ps
CPU time 1504.63 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:52:38 PM PDT 24
Peak memory 349880 kb
Host smart-e8060613-3666-4dd1-845d-6a680d90e988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621112225 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3621112225
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.2760147413
Short name T928
Test name
Test status
Simulation time 162653685 ps
CPU time 5.32 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242108 kb
Host smart-6210d29e-c227-4892-9461-a21c0899625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760147413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.2760147413
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3439458422
Short name T43
Test name
Test status
Simulation time 892492428 ps
CPU time 16.92 seconds
Started Jun 29 07:26:34 PM PDT 24
Finished Jun 29 07:26:52 PM PDT 24
Peak memory 248804 kb
Host smart-d671339e-8ef2-4954-af8b-0a42bb521d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439458422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3439458422
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.911895185
Short name T251
Test name
Test status
Simulation time 11549833516 ps
CPU time 196.19 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 274264 kb
Host smart-629009b1-3c11-497b-8791-63cc5f15244c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911895185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.911895185
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1809522978
Short name T108
Test name
Test status
Simulation time 2686589831 ps
CPU time 14.64 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 242444 kb
Host smart-7fecba6f-134e-4c1a-82f5-f46a67e0481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809522978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1809522978
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2019376663
Short name T592
Test name
Test status
Simulation time 2588372262 ps
CPU time 20.64 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:02 PM PDT 24
Peak memory 242088 kb
Host smart-c024cc8d-5833-4f09-afce-f5014fca02a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2019376663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2019376663
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.968941027
Short name T1194
Test name
Test status
Simulation time 109299599 ps
CPU time 3.05 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 241540 kb
Host smart-9172d006-2368-43a5-a258-51b1c32e64e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968941027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.968941027
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2143070618
Short name T1315
Test name
Test status
Simulation time 863123172 ps
CPU time 6.12 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:42 PM PDT 24
Peak memory 239256 kb
Host smart-d52d271c-8bef-4468-8532-94fcf57926c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143070618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2143070618
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3614113802
Short name T1299
Test name
Test status
Simulation time 76184816 ps
CPU time 2.18 seconds
Started Jun 29 07:24:35 PM PDT 24
Finished Jun 29 07:24:38 PM PDT 24
Peak memory 245480 kb
Host smart-7365524e-4106-49a0-839c-9a759ac92390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614113802 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3614113802
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.1297422796
Short name T330
Test name
Test status
Simulation time 88267964 ps
CPU time 1.79 seconds
Started Jun 29 07:24:35 PM PDT 24
Finished Jun 29 07:24:37 PM PDT 24
Peak memory 241436 kb
Host smart-eef29593-e5a6-4fe2-befe-331f1cd6efd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297422796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.1297422796
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.30804842
Short name T1214
Test name
Test status
Simulation time 112594540 ps
CPU time 1.54 seconds
Started Jun 29 07:24:37 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 231072 kb
Host smart-a21fd25c-5f0b-484c-ad26-e9b825749ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30804842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.30804842
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1906512153
Short name T1269
Test name
Test status
Simulation time 41535438 ps
CPU time 1.43 seconds
Started Jun 29 07:24:38 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 230612 kb
Host smart-680247a3-c742-4830-9375-cbdf0a2f1ce1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906512153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.1906512153
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.624513539
Short name T1318
Test name
Test status
Simulation time 36401677 ps
CPU time 1.3 seconds
Started Jun 29 07:24:39 PM PDT 24
Finished Jun 29 07:24:41 PM PDT 24
Peak memory 230964 kb
Host smart-8ddcc48e-cc5f-4fdf-a51c-1582ada5e10a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624513539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.
624513539
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.929176686
Short name T1252
Test name
Test status
Simulation time 317170244 ps
CPU time 2.78 seconds
Started Jun 29 07:24:37 PM PDT 24
Finished Jun 29 07:24:41 PM PDT 24
Peak memory 242328 kb
Host smart-eb9e9fe1-2103-410e-b88e-21fd62bdc363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929176686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_same_csr_outstanding.929176686
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.697797032
Short name T1217
Test name
Test status
Simulation time 100485991 ps
CPU time 3.61 seconds
Started Jun 29 07:24:30 PM PDT 24
Finished Jun 29 07:24:35 PM PDT 24
Peak memory 246272 kb
Host smart-b9ef5bea-6bb7-487b-bc10-5f8696fad4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697797032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.697797032
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.619481391
Short name T313
Test name
Test status
Simulation time 123191355 ps
CPU time 4.85 seconds
Started Jun 29 07:24:37 PM PDT 24
Finished Jun 29 07:24:42 PM PDT 24
Peak memory 239200 kb
Host smart-cc35f878-2074-4039-aa73-f1ff661f7ed9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619481391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.619481391
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1668556851
Short name T1198
Test name
Test status
Simulation time 344591168 ps
CPU time 8.26 seconds
Started Jun 29 07:24:34 PM PDT 24
Finished Jun 29 07:24:43 PM PDT 24
Peak memory 239232 kb
Host smart-00651f68-dbe3-44aa-9681-100245fd158c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668556851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.1668556851
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2868158084
Short name T331
Test name
Test status
Simulation time 90795184 ps
CPU time 2.38 seconds
Started Jun 29 07:24:39 PM PDT 24
Finished Jun 29 07:24:42 PM PDT 24
Peak memory 239280 kb
Host smart-b431f7fe-a568-482e-969d-0ea38bb7854e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868158084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.2868158084
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2024921983
Short name T1240
Test name
Test status
Simulation time 74404777 ps
CPU time 2.13 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 244572 kb
Host smart-b27ded46-d2da-41d4-802e-9b832195f475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024921983 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2024921983
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.999473859
Short name T1254
Test name
Test status
Simulation time 44119922 ps
CPU time 1.53 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:38 PM PDT 24
Peak memory 240524 kb
Host smart-c6bb1377-8261-4144-8f62-a21b3b07db68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999473859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.999473859
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.3106198293
Short name T1190
Test name
Test status
Simulation time 93971760 ps
CPU time 1.44 seconds
Started Jun 29 07:24:38 PM PDT 24
Finished Jun 29 07:24:40 PM PDT 24
Peak memory 230324 kb
Host smart-5bb367f2-8d21-4868-a3e3-8608619cfec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106198293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3106198293
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3537975171
Short name T1243
Test name
Test status
Simulation time 516514282 ps
CPU time 1.63 seconds
Started Jun 29 07:24:41 PM PDT 24
Finished Jun 29 07:24:43 PM PDT 24
Peak memory 229896 kb
Host smart-bbbc2c58-0707-4a6c-849c-7a0108bdb54f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537975171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.3537975171
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.123622362
Short name T1293
Test name
Test status
Simulation time 144720533 ps
CPU time 1.44 seconds
Started Jun 29 07:24:39 PM PDT 24
Finished Jun 29 07:24:41 PM PDT 24
Peak memory 230128 kb
Host smart-b31b7ded-d70c-470d-9284-ad728e85126b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123622362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.
123622362
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.81886295
Short name T1277
Test name
Test status
Simulation time 1333311056 ps
CPU time 4.82 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:42 PM PDT 24
Peak memory 247056 kb
Host smart-0ddb1a71-1ca8-4cbc-b122-4a9206b82b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81886295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.81886295
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3693279597
Short name T1284
Test name
Test status
Simulation time 106913976 ps
CPU time 2.54 seconds
Started Jun 29 07:24:59 PM PDT 24
Finished Jun 29 07:25:02 PM PDT 24
Peak memory 246028 kb
Host smart-da3ffce5-17f6-48d0-9495-6c41acb21da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693279597 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3693279597
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.417084293
Short name T333
Test name
Test status
Simulation time 41006137 ps
CPU time 1.49 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 239172 kb
Host smart-3c63393b-437d-4afb-a4f5-280ef68d2373
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417084293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.417084293
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1960966968
Short name T1211
Test name
Test status
Simulation time 555275318 ps
CPU time 1.61 seconds
Started Jun 29 07:24:51 PM PDT 24
Finished Jun 29 07:24:54 PM PDT 24
Peak memory 230268 kb
Host smart-825ea41f-dd30-4f60-887c-e11b5e658f88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960966968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1960966968
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1520338379
Short name T340
Test name
Test status
Simulation time 153371160 ps
CPU time 2.18 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:06 PM PDT 24
Peak memory 239228 kb
Host smart-2f6d3aff-fd26-441b-86c6-070397a68167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520338379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1520338379
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3359306442
Short name T1263
Test name
Test status
Simulation time 317356173 ps
CPU time 6.58 seconds
Started Jun 29 07:24:55 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 246868 kb
Host smart-a1d2f614-9694-48e9-8161-0048dfbb2011
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359306442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3359306442
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2689447528
Short name T370
Test name
Test status
Simulation time 2590364805 ps
CPU time 13.04 seconds
Started Jun 29 07:24:55 PM PDT 24
Finished Jun 29 07:25:09 PM PDT 24
Peak memory 244268 kb
Host smart-6fed1781-1de5-48bb-be85-a8d3fea39be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689447528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.2689447528
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2251043256
Short name T1203
Test name
Test status
Simulation time 313950734 ps
CPU time 2.9 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 247036 kb
Host smart-bb57ada8-e865-4aca-8bd5-085f5b1e59da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251043256 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2251043256
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1816132650
Short name T1307
Test name
Test status
Simulation time 41013228 ps
CPU time 1.62 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 239292 kb
Host smart-9a67b5fa-58c1-4b2d-8b75-b7c9649b6991
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816132650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1816132650
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.1290003543
Short name T1210
Test name
Test status
Simulation time 138422736 ps
CPU time 1.56 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 230260 kb
Host smart-cd0dcafd-bf60-4c16-9fbf-c4cd3c9e8948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290003543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.1290003543
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.3574678335
Short name T1312
Test name
Test status
Simulation time 290471501 ps
CPU time 3.8 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:04 PM PDT 24
Peak memory 239160 kb
Host smart-834fb8f6-4d49-4266-b93a-1a93d6801526
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574678335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.3574678335
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.2716841717
Short name T1304
Test name
Test status
Simulation time 401424494 ps
CPU time 4.27 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:06 PM PDT 24
Peak memory 246104 kb
Host smart-91d7a0f0-0a84-442e-87b9-bc81e1bdfc10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716841717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.2716841717
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.843574427
Short name T1213
Test name
Test status
Simulation time 98990880 ps
CPU time 3.48 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 247456 kb
Host smart-113a8128-0a70-4585-a597-be7576a553a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843574427 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.843574427
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.3984956516
Short name T1226
Test name
Test status
Simulation time 42917603 ps
CPU time 1.63 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 241140 kb
Host smart-98dfa9d5-1e6b-4d38-b7b3-469ccc56e02d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984956516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.3984956516
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3772202727
Short name T1264
Test name
Test status
Simulation time 590139402 ps
CPU time 1.59 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 230268 kb
Host smart-48cdad66-530a-4612-9849-35f6ddb30d0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772202727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3772202727
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.774788502
Short name T280
Test name
Test status
Simulation time 175662933 ps
CPU time 2.5 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 239184 kb
Host smart-091e692d-1dc9-4c5f-85d5-3cee4ad1af89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774788502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c
trl_same_csr_outstanding.774788502
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3566019110
Short name T1221
Test name
Test status
Simulation time 290274522 ps
CPU time 5.08 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:07 PM PDT 24
Peak memory 246292 kb
Host smart-c44680da-2a73-4f9f-9d44-49e1ddd69f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566019110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3566019110
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.133852423
Short name T373
Test name
Test status
Simulation time 1723389443 ps
CPU time 10.89 seconds
Started Jun 29 07:25:04 PM PDT 24
Finished Jun 29 07:25:15 PM PDT 24
Peak memory 239508 kb
Host smart-31e9d445-c79a-4b5d-8c55-f47fcaa50db7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133852423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_in
tg_err.133852423
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3870203932
Short name T1204
Test name
Test status
Simulation time 252875490 ps
CPU time 3.02 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 247256 kb
Host smart-c395dc5f-7820-4285-a3d3-c02dfe8cfbb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870203932 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3870203932
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3304428858
Short name T1219
Test name
Test status
Simulation time 142212115 ps
CPU time 1.5 seconds
Started Jun 29 07:24:59 PM PDT 24
Finished Jun 29 07:25:01 PM PDT 24
Peak memory 230596 kb
Host smart-8a7b1101-ff01-4cfd-986c-0c14527dfdaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304428858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3304428858
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.631034473
Short name T1283
Test name
Test status
Simulation time 789285479 ps
CPU time 2.84 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 239112 kb
Host smart-6145addb-0d83-475f-8690-5a48356d704a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631034473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_same_csr_outstanding.631034473
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.223434178
Short name T1207
Test name
Test status
Simulation time 199881957 ps
CPU time 3.32 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 246412 kb
Host smart-996a73e2-1501-40f9-a188-7274e27a9141
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223434178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.223434178
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.267469596
Short name T375
Test name
Test status
Simulation time 4819619619 ps
CPU time 21.36 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:22 PM PDT 24
Peak memory 244968 kb
Host smart-8cde8922-45dc-4cbb-92ea-db5b391c9ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267469596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.267469596
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.2210142811
Short name T1317
Test name
Test status
Simulation time 77423224 ps
CPU time 3.28 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:07 PM PDT 24
Peak memory 247436 kb
Host smart-7bbe1b35-2e40-4df2-a5ab-74e1f4136ca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210142811 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.2210142811
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.4293126802
Short name T314
Test name
Test status
Simulation time 561777319 ps
CPU time 2.16 seconds
Started Jun 29 07:25:02 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 241016 kb
Host smart-764398d0-cdf2-4a16-9b44-2c35eac0ecfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293126802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.4293126802
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3525653153
Short name T1223
Test name
Test status
Simulation time 135011347 ps
CPU time 1.43 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 230276 kb
Host smart-3e293e2d-caf8-41fd-9e18-9758885e05be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525653153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3525653153
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.414298595
Short name T1236
Test name
Test status
Simulation time 110431440 ps
CPU time 2.57 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:04 PM PDT 24
Peak memory 239256 kb
Host smart-1ac9f02f-18d5-49a8-b476-f938929de1fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414298595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_same_csr_outstanding.414298595
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2249003355
Short name T1224
Test name
Test status
Simulation time 438223176 ps
CPU time 3.67 seconds
Started Jun 29 07:25:01 PM PDT 24
Finished Jun 29 07:25:05 PM PDT 24
Peak memory 246500 kb
Host smart-b0d74f71-ef2b-49c7-bff3-469a64e8676d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249003355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2249003355
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.2936172356
Short name T1313
Test name
Test status
Simulation time 640973581 ps
CPU time 10.46 seconds
Started Jun 29 07:25:00 PM PDT 24
Finished Jun 29 07:25:12 PM PDT 24
Peak memory 239172 kb
Host smart-fb7faf88-2a66-4e73-b2f9-e1dff60c4782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936172356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.2936172356
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.1763036010
Short name T1201
Test name
Test status
Simulation time 144753248 ps
CPU time 2.56 seconds
Started Jun 29 07:25:08 PM PDT 24
Finished Jun 29 07:25:11 PM PDT 24
Peak memory 246676 kb
Host smart-d63e5c1a-dd93-4535-b2d3-2f02a5ab6430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763036010 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.1763036010
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1803015776
Short name T316
Test name
Test status
Simulation time 40358149 ps
CPU time 1.6 seconds
Started Jun 29 07:25:11 PM PDT 24
Finished Jun 29 07:25:13 PM PDT 24
Peak memory 240824 kb
Host smart-5698af08-b90e-4c4d-8127-8102aada063d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803015776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1803015776
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4024080314
Short name T1246
Test name
Test status
Simulation time 39193007 ps
CPU time 1.44 seconds
Started Jun 29 07:25:10 PM PDT 24
Finished Jun 29 07:25:12 PM PDT 24
Peak memory 230372 kb
Host smart-725b14b2-9fb5-4e16-8297-0a118a36b521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024080314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.4024080314
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.624326874
Short name T339
Test name
Test status
Simulation time 829388586 ps
CPU time 2.89 seconds
Started Jun 29 07:25:10 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 239220 kb
Host smart-9c0ad6a3-aba2-4c3a-9b6c-2273b1efe74a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624326874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_same_csr_outstanding.624326874
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2009467831
Short name T1290
Test name
Test status
Simulation time 204225312 ps
CPU time 3.27 seconds
Started Jun 29 07:25:13 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 246176 kb
Host smart-34ffe081-4f4e-43e6-b28f-80199a2cf1fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009467831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2009467831
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.1112697602
Short name T372
Test name
Test status
Simulation time 1358348081 ps
CPU time 11.24 seconds
Started Jun 29 07:25:13 PM PDT 24
Finished Jun 29 07:25:25 PM PDT 24
Peak memory 239224 kb
Host smart-1e9d8985-ae87-43c8-af8e-6719a8af6304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112697602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.1112697602
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1442965163
Short name T1305
Test name
Test status
Simulation time 427002877 ps
CPU time 2.94 seconds
Started Jun 29 07:25:11 PM PDT 24
Finished Jun 29 07:25:15 PM PDT 24
Peak memory 247460 kb
Host smart-bad8765b-266f-4441-b3e8-7881f97b1f5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442965163 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1442965163
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.2949688201
Short name T338
Test name
Test status
Simulation time 46456552 ps
CPU time 1.79 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:11 PM PDT 24
Peak memory 240912 kb
Host smart-21a9e8d7-b08a-4ebb-bc33-ea43db742760
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949688201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.2949688201
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.2498974764
Short name T1218
Test name
Test status
Simulation time 537615370 ps
CPU time 1.97 seconds
Started Jun 29 07:25:08 PM PDT 24
Finished Jun 29 07:25:11 PM PDT 24
Peak memory 230600 kb
Host smart-a85ae379-5242-4661-8992-3c183ec81f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498974764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.2498974764
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.972885263
Short name T334
Test name
Test status
Simulation time 357577270 ps
CPU time 3.43 seconds
Started Jun 29 07:25:07 PM PDT 24
Finished Jun 29 07:25:11 PM PDT 24
Peak memory 239104 kb
Host smart-ed3451e2-2a87-45d9-a3d4-0b4a54d278f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972885263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_same_csr_outstanding.972885263
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.973744846
Short name T1321
Test name
Test status
Simulation time 108874689 ps
CPU time 4.39 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 246300 kb
Host smart-cf8f9bec-9658-4cc5-8fc1-a3d8aa9658ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973744846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.973744846
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.384196967
Short name T367
Test name
Test status
Simulation time 10243390942 ps
CPU time 11.97 seconds
Started Jun 29 07:25:08 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 244796 kb
Host smart-f98d81e3-9058-4cee-9774-c4eea6ac0578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384196967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_in
tg_err.384196967
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.875583861
Short name T1237
Test name
Test status
Simulation time 142343769 ps
CPU time 2.85 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:13 PM PDT 24
Peak memory 247412 kb
Host smart-fb2fde68-6cf9-4dec-be4f-6a1337bcb3b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875583861 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.875583861
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.3154754432
Short name T1302
Test name
Test status
Simulation time 171588681 ps
CPU time 1.66 seconds
Started Jun 29 07:25:12 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 241664 kb
Host smart-d6366671-ea47-49b8-a70c-fa51c5a9897b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154754432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.3154754432
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2315042699
Short name T1241
Test name
Test status
Simulation time 137227833 ps
CPU time 1.51 seconds
Started Jun 29 07:25:11 PM PDT 24
Finished Jun 29 07:25:13 PM PDT 24
Peak memory 231084 kb
Host smart-9dd5e1c9-3601-4725-9ef6-71c49d46f9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315042699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2315042699
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.1446066772
Short name T336
Test name
Test status
Simulation time 1021152919 ps
CPU time 2.76 seconds
Started Jun 29 07:25:07 PM PDT 24
Finished Jun 29 07:25:10 PM PDT 24
Peak memory 239216 kb
Host smart-b6da5899-c72e-452d-8f8e-c762dee1e98b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446066772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_
ctrl_same_csr_outstanding.1446066772
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3917312998
Short name T1279
Test name
Test status
Simulation time 1542373735 ps
CPU time 4.46 seconds
Started Jun 29 07:25:12 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 246324 kb
Host smart-f37f7cef-c99e-46a9-ba72-11473f435d7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917312998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3917312998
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2609488162
Short name T374
Test name
Test status
Simulation time 4801650904 ps
CPU time 21.06 seconds
Started Jun 29 07:25:13 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 239308 kb
Host smart-27409bdc-e248-4551-93d3-1dc5eaee4f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609488162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2609488162
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1183909623
Short name T1259
Test name
Test status
Simulation time 231873719 ps
CPU time 3 seconds
Started Jun 29 07:25:12 PM PDT 24
Finished Jun 29 07:25:16 PM PDT 24
Peak memory 246664 kb
Host smart-26449c3b-bdfa-49ad-9973-47e046baa07c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183909623 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.1183909623
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.4121777420
Short name T329
Test name
Test status
Simulation time 65177436 ps
CPU time 1.86 seconds
Started Jun 29 07:25:08 PM PDT 24
Finished Jun 29 07:25:11 PM PDT 24
Peak memory 241424 kb
Host smart-d0aef43a-004e-4021-a0c0-3cb87ed6f972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121777420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.4121777420
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2553460095
Short name T1282
Test name
Test status
Simulation time 92367934 ps
CPU time 1.37 seconds
Started Jun 29 07:25:07 PM PDT 24
Finished Jun 29 07:25:09 PM PDT 24
Peak memory 230276 kb
Host smart-e5ef175b-cf71-4315-a353-0a4971646e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553460095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2553460095
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.3248523290
Short name T1231
Test name
Test status
Simulation time 245217606 ps
CPU time 2.35 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:12 PM PDT 24
Peak memory 242352 kb
Host smart-3529221e-7b2a-4584-879a-fb10687dc590
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248523290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.3248523290
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.4280968108
Short name T1298
Test name
Test status
Simulation time 213244517 ps
CPU time 4.18 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 246384 kb
Host smart-79fed808-4c8e-4193-bea9-52256c45c173
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280968108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.4280968108
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1744948837
Short name T366
Test name
Test status
Simulation time 779639130 ps
CPU time 11.23 seconds
Started Jun 29 07:25:10 PM PDT 24
Finished Jun 29 07:25:21 PM PDT 24
Peak memory 239196 kb
Host smart-dc82d657-ecf3-4b78-8634-e5645741db0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744948837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.1744948837
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3893913883
Short name T1255
Test name
Test status
Simulation time 1647888898 ps
CPU time 5.09 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:22 PM PDT 24
Peak memory 247392 kb
Host smart-b5d5f4e3-abda-4d34-a9f7-581ae349619f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893913883 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3893913883
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2894368194
Short name T332
Test name
Test status
Simulation time 117470009 ps
CPU time 1.68 seconds
Started Jun 29 07:25:09 PM PDT 24
Finished Jun 29 07:25:12 PM PDT 24
Peak memory 241044 kb
Host smart-737b6a79-d200-43f1-8a57-9156f6b1b4d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894368194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2894368194
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.1480485829
Short name T1267
Test name
Test status
Simulation time 528754804 ps
CPU time 1.95 seconds
Started Jun 29 07:25:11 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 230248 kb
Host smart-8263a30a-87ec-416c-8d3c-a97946daef9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480485829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1480485829
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1232228765
Short name T1248
Test name
Test status
Simulation time 61520217 ps
CPU time 2.59 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 242480 kb
Host smart-a59926ec-0181-482c-abe9-78afd6cf632d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232228765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.1232228765
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1558548241
Short name T1234
Test name
Test status
Simulation time 1602917579 ps
CPU time 4.89 seconds
Started Jun 29 07:25:08 PM PDT 24
Finished Jun 29 07:25:14 PM PDT 24
Peak memory 247200 kb
Host smart-2655ab90-3f30-4177-ad1c-91930a27120d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558548241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1558548241
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2308208839
Short name T277
Test name
Test status
Simulation time 1212246013 ps
CPU time 18.41 seconds
Started Jun 29 07:25:06 PM PDT 24
Finished Jun 29 07:25:25 PM PDT 24
Peak memory 244428 kb
Host smart-8f32c09e-1c7a-4366-bfa4-c7f94e634d4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308208839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2308208839
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2120665466
Short name T1289
Test name
Test status
Simulation time 100797366 ps
CPU time 3.76 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:51 PM PDT 24
Peak memory 239168 kb
Host smart-75af2717-3290-4747-93d7-bd31e02c3284
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120665466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2120665466
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.428930631
Short name T1311
Test name
Test status
Simulation time 199546156 ps
CPU time 4.93 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 231064 kb
Host smart-a39e947e-2f3b-4bb2-a728-a9aea3f2d30a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428930631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.428930631
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3967429307
Short name T309
Test name
Test status
Simulation time 69160828 ps
CPU time 1.79 seconds
Started Jun 29 07:24:47 PM PDT 24
Finished Jun 29 07:24:50 PM PDT 24
Peak memory 240916 kb
Host smart-4e818908-e228-4ecf-a61b-788cea74a6fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967429307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.3967429307
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3301996924
Short name T1242
Test name
Test status
Simulation time 104601366 ps
CPU time 2.92 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 247456 kb
Host smart-bb3bfbf5-e423-498b-bc0f-6cd4aa0cac63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301996924 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3301996924
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2694252178
Short name T1245
Test name
Test status
Simulation time 39196434 ps
CPU time 1.49 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 241084 kb
Host smart-80773cd5-7e07-4ced-a54a-c0bf3bad108d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694252178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2694252178
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4162470388
Short name T1232
Test name
Test status
Simulation time 565647627 ps
CPU time 1.65 seconds
Started Jun 29 07:24:35 PM PDT 24
Finished Jun 29 07:24:38 PM PDT 24
Peak memory 230564 kb
Host smart-36dd02a6-1a74-41ce-84a8-c3a274178d08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162470388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4162470388
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.850274536
Short name T1262
Test name
Test status
Simulation time 561162261 ps
CPU time 1.44 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 230676 kb
Host smart-eecc2567-2931-4844-addd-2a43f5fbc6be
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850274536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl
_mem_partial_access.850274536
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2452351352
Short name T1275
Test name
Test status
Simulation time 76203077 ps
CPU time 1.43 seconds
Started Jun 29 07:24:36 PM PDT 24
Finished Jun 29 07:24:39 PM PDT 24
Peak memory 229960 kb
Host smart-934d8276-3cd6-482f-8892-28b0aebcf505
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452351352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.2452351352
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3401694208
Short name T1285
Test name
Test status
Simulation time 201939402 ps
CPU time 2.43 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 239208 kb
Host smart-040a75f3-48a6-445d-8e2b-3fca58f1395e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401694208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3401694208
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2519255875
Short name T1258
Test name
Test status
Simulation time 387387298 ps
CPU time 3.69 seconds
Started Jun 29 07:24:39 PM PDT 24
Finished Jun 29 07:24:43 PM PDT 24
Peak memory 246124 kb
Host smart-790e5a95-132f-4dd8-a58d-032fe39a92ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519255875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2519255875
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2818129704
Short name T365
Test name
Test status
Simulation time 2062152769 ps
CPU time 22.64 seconds
Started Jun 29 07:24:38 PM PDT 24
Finished Jun 29 07:25:01 PM PDT 24
Peak memory 239156 kb
Host smart-aaf31b9f-9942-4377-8303-f1890c43830e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818129704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2818129704
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3313471799
Short name T1268
Test name
Test status
Simulation time 38879824 ps
CPU time 1.41 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 230284 kb
Host smart-c640a5b8-6277-41f1-bc1d-9cdaaccef4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313471799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3313471799
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.122309268
Short name T1294
Test name
Test status
Simulation time 148133117 ps
CPU time 1.44 seconds
Started Jun 29 07:25:18 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 231064 kb
Host smart-8852b133-39fc-4615-97e1-d4a847dc8c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122309268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.122309268
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2413965423
Short name T1220
Test name
Test status
Simulation time 146775127 ps
CPU time 1.47 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:18 PM PDT 24
Peak memory 231068 kb
Host smart-9608360d-2784-441e-a2e6-160ff4a2932a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413965423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2413965423
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1416945562
Short name T1202
Test name
Test status
Simulation time 41603502 ps
CPU time 1.4 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 231032 kb
Host smart-098993b8-f9d5-4f8c-a498-72af78719074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416945562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1416945562
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3709469953
Short name T1295
Test name
Test status
Simulation time 81288097 ps
CPU time 1.47 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 230524 kb
Host smart-37b55a4c-b22b-493b-91b4-532c62017159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709469953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3709469953
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.466771644
Short name T1244
Test name
Test status
Simulation time 81442918 ps
CPU time 1.4 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230276 kb
Host smart-fef560c2-7d1e-44cc-a3c0-971d9d620b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466771644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.466771644
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.1392216925
Short name T1256
Test name
Test status
Simulation time 71754974 ps
CPU time 1.4 seconds
Started Jun 29 07:25:19 PM PDT 24
Finished Jun 29 07:25:21 PM PDT 24
Peak memory 230328 kb
Host smart-d93cb30d-b5b0-4f81-9bd9-776ea59589af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392216925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1392216925
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.1625961715
Short name T1292
Test name
Test status
Simulation time 72336767 ps
CPU time 1.51 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230668 kb
Host smart-09718698-53e1-43ff-b1b3-4bc15aea72c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625961715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1625961715
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.1175643234
Short name T1222
Test name
Test status
Simulation time 552379329 ps
CPU time 1.59 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230560 kb
Host smart-99803cba-de39-46ea-abee-621e7d812798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175643234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1175643234
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2296746780
Short name T1287
Test name
Test status
Simulation time 508648181 ps
CPU time 2.08 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:18 PM PDT 24
Peak memory 230252 kb
Host smart-eb2effe7-72db-4a69-82ad-3c631a3321e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296746780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2296746780
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.4049059103
Short name T1195
Test name
Test status
Simulation time 1925886698 ps
CPU time 4.59 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 239228 kb
Host smart-829fe02e-65e4-4462-b754-6516cdfc19ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049059103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.4049059103
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.4168124512
Short name T1286
Test name
Test status
Simulation time 481329359 ps
CPU time 7.16 seconds
Started Jun 29 07:24:43 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 239232 kb
Host smart-88f7aa9d-c739-469c-b6c1-e2278f5f5841
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168124512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.4168124512
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3767916689
Short name T315
Test name
Test status
Simulation time 105986744 ps
CPU time 2.39 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 241368 kb
Host smart-129cb033-a768-463e-afb2-c4b8bd0ec4f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767916689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3767916689
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.2715595637
Short name T1261
Test name
Test status
Simulation time 169866848 ps
CPU time 2.14 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 244512 kb
Host smart-e22fb90b-bece-4e6d-af80-cf1d365e3055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715595637 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.2715595637
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.221212624
Short name T310
Test name
Test status
Simulation time 62245772 ps
CPU time 1.52 seconds
Started Jun 29 07:24:48 PM PDT 24
Finished Jun 29 07:24:50 PM PDT 24
Peak memory 241100 kb
Host smart-9888b447-75d0-4cd3-8995-3545d9dcef82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221212624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.221212624
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.1732480605
Short name T1230
Test name
Test status
Simulation time 135411566 ps
CPU time 1.57 seconds
Started Jun 29 07:24:46 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 230456 kb
Host smart-b0bcc61d-28d2-4a45-8a39-b0f5f8c5045f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732480605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1732480605
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.216152602
Short name T1278
Test name
Test status
Simulation time 99685651 ps
CPU time 1.37 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 230140 kb
Host smart-7edf8c10-77e5-42dd-9c91-7d1cb33503e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216152602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.216152602
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3638209092
Short name T1260
Test name
Test status
Simulation time 522133431 ps
CPU time 1.46 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:47 PM PDT 24
Peak memory 230384 kb
Host smart-46ffe69c-4d4d-4c9a-acd4-851c42bbb677
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638209092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.3638209092
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2746349026
Short name T279
Test name
Test status
Simulation time 357870160 ps
CPU time 3.1 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 239228 kb
Host smart-879a1f30-fb70-4f79-8181-2c3a3ded91a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746349026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2746349026
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.419153067
Short name T1200
Test name
Test status
Simulation time 622713171 ps
CPU time 6.35 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:53 PM PDT 24
Peak memory 246468 kb
Host smart-d8f32425-ab78-479f-81ce-1ab50bf71396
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419153067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.419153067
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1103845085
Short name T1320
Test name
Test status
Simulation time 703818218 ps
CPU time 9.57 seconds
Started Jun 29 07:24:49 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 239336 kb
Host smart-9c5cd66f-6543-4c54-9937-c8923bbbdf0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103845085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.1103845085
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.996068313
Short name T1216
Test name
Test status
Simulation time 532034608 ps
CPU time 1.78 seconds
Started Jun 29 07:25:20 PM PDT 24
Finished Jun 29 07:25:22 PM PDT 24
Peak memory 230576 kb
Host smart-71dfcffc-d2f1-4c4d-bf6c-9decd8fd9f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996068313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.996068313
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.3874410775
Short name T1310
Test name
Test status
Simulation time 121115001 ps
CPU time 1.5 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 230320 kb
Host smart-f034050a-2985-4111-a60a-f084f24fcbdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874410775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.3874410775
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1450206125
Short name T1250
Test name
Test status
Simulation time 39930870 ps
CPU time 1.53 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230352 kb
Host smart-35782a36-6752-457f-ab91-06bd4d6867b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450206125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1450206125
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.4208935318
Short name T1272
Test name
Test status
Simulation time 564117396 ps
CPU time 1.55 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 231072 kb
Host smart-3ff4183e-a399-4942-9917-2d531fc8725f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208935318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.4208935318
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.269429791
Short name T1249
Test name
Test status
Simulation time 52986378 ps
CPU time 1.5 seconds
Started Jun 29 07:25:20 PM PDT 24
Finished Jun 29 07:25:22 PM PDT 24
Peak memory 231032 kb
Host smart-7bfd2971-07ea-4bd3-ae7b-cd1d7282b680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269429791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.269429791
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.2350654618
Short name T1314
Test name
Test status
Simulation time 39906791 ps
CPU time 1.44 seconds
Started Jun 29 07:25:17 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 230304 kb
Host smart-2ffe3637-e276-4078-b2ad-b84047dea85c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350654618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.2350654618
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3044972185
Short name T1297
Test name
Test status
Simulation time 46463445 ps
CPU time 1.4 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230276 kb
Host smart-e977ddb3-43c8-46a1-87b3-5d2f71a92f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044972185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3044972185
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.786154604
Short name T1209
Test name
Test status
Simulation time 36445472 ps
CPU time 1.32 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:16 PM PDT 24
Peak memory 230252 kb
Host smart-6f4800a2-4462-4646-801f-ec917b5e8576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786154604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.786154604
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.3292155188
Short name T1191
Test name
Test status
Simulation time 78710157 ps
CPU time 1.44 seconds
Started Jun 29 07:25:17 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 231056 kb
Host smart-12ecc7ed-9601-49e9-bbb5-eb238654ef20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292155188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.3292155188
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2253385421
Short name T1319
Test name
Test status
Simulation time 138139242 ps
CPU time 1.51 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 231076 kb
Host smart-254c4dd9-a5cf-4aaf-80b8-919bc37a3828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253385421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2253385421
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3186441093
Short name T1308
Test name
Test status
Simulation time 227911700 ps
CPU time 3.98 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:51 PM PDT 24
Peak memory 239220 kb
Host smart-c6519b90-0861-4dea-96de-fcf298395a7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186441093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.3186441093
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1119107428
Short name T1288
Test name
Test status
Simulation time 268691370 ps
CPU time 6.31 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 239228 kb
Host smart-34729215-70b9-475c-ba8a-59129c0d6c56
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119107428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.1119107428
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3535415012
Short name T318
Test name
Test status
Simulation time 103690953 ps
CPU time 2.31 seconds
Started Jun 29 07:24:49 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 241280 kb
Host smart-5225e1b2-0400-49d1-bb27-60388086de1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535415012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3535415012
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.3738589024
Short name T1193
Test name
Test status
Simulation time 142591729 ps
CPU time 2.28 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 246168 kb
Host smart-afc79b76-1535-4a49-a98f-e5f9f7d31723
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738589024 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.3738589024
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2232636407
Short name T311
Test name
Test status
Simulation time 86946150 ps
CPU time 1.88 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 241168 kb
Host smart-28536d40-47ca-45b3-be36-53ab865984b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232636407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2232636407
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.4191680598
Short name T1270
Test name
Test status
Simulation time 38975266 ps
CPU time 1.4 seconds
Started Jun 29 07:24:48 PM PDT 24
Finished Jun 29 07:24:51 PM PDT 24
Peak memory 230308 kb
Host smart-98e2c1f7-99f3-4885-a81c-86d8a49dac29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191680598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.4191680598
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1585248584
Short name T1266
Test name
Test status
Simulation time 132487533 ps
CPU time 1.47 seconds
Started Jun 29 07:24:44 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 230728 kb
Host smart-afe9f7c6-8115-4748-ae87-af9fa1d1c315
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585248584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.1585248584
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2422385172
Short name T1199
Test name
Test status
Simulation time 36384523 ps
CPU time 1.29 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:48 PM PDT 24
Peak memory 230216 kb
Host smart-e9d4cf27-eb41-4565-a5d3-7a0c47fdd1a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422385172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2422385172
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2271853697
Short name T1291
Test name
Test status
Simulation time 136140470 ps
CPU time 2.47 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 239160 kb
Host smart-8198c5a4-c2b6-4d84-88c0-065da2feffaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271853697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.2271853697
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.2457559101
Short name T1296
Test name
Test status
Simulation time 55325727 ps
CPU time 2.91 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:49 PM PDT 24
Peak memory 246216 kb
Host smart-0c4ef30f-81cb-42bf-8f0f-20b25e84af5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457559101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.2457559101
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.1034971425
Short name T1227
Test name
Test status
Simulation time 38243607 ps
CPU time 1.44 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230204 kb
Host smart-c17cb7c8-48fc-4142-964f-a4de44f889b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034971425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1034971425
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3799190521
Short name T1300
Test name
Test status
Simulation time 42560282 ps
CPU time 1.47 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:17 PM PDT 24
Peak memory 230384 kb
Host smart-738c5f00-bf18-46fc-bcda-8b38caf19dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799190521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3799190521
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.3374925448
Short name T1197
Test name
Test status
Simulation time 140640182 ps
CPU time 1.59 seconds
Started Jun 29 07:25:18 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 230348 kb
Host smart-91a8c197-feb6-411d-98d5-82db7f998915
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374925448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3374925448
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.3683766340
Short name T1208
Test name
Test status
Simulation time 515884249 ps
CPU time 1.66 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 230640 kb
Host smart-39bf67fb-8fc3-4e0b-9da6-d7576f672508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683766340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.3683766340
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.3428492067
Short name T1271
Test name
Test status
Simulation time 578306346 ps
CPU time 1.84 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230304 kb
Host smart-d20c71e2-489a-4971-958c-8568c7ce47d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428492067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3428492067
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.617545074
Short name T1281
Test name
Test status
Simulation time 37769676 ps
CPU time 1.41 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230344 kb
Host smart-cf462c11-9a0e-419a-ab76-b73a6df9d961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617545074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.617545074
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.694343007
Short name T1251
Test name
Test status
Simulation time 47888231 ps
CPU time 1.44 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 231032 kb
Host smart-9aa87344-21e7-42a1-ba80-1c3d9533d7e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694343007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.694343007
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.453266394
Short name T1280
Test name
Test status
Simulation time 44105300 ps
CPU time 1.57 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230308 kb
Host smart-6e6da336-d844-4675-a2fe-c299ff6eff48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453266394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.453266394
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.1693788308
Short name T1265
Test name
Test status
Simulation time 94507635 ps
CPU time 1.42 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:16 PM PDT 24
Peak memory 231024 kb
Host smart-55e83bbb-5e2a-445f-b484-d1e2f8cb933a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693788308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1693788308
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.4262692866
Short name T1192
Test name
Test status
Simulation time 45197874 ps
CPU time 1.53 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:19 PM PDT 24
Peak memory 230376 kb
Host smart-3081045f-86b1-433a-9667-16549e9c18e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262692866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.4262692866
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3517243054
Short name T1205
Test name
Test status
Simulation time 142400115 ps
CPU time 2.98 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:24:56 PM PDT 24
Peak memory 247504 kb
Host smart-b95ed3e4-d398-451c-950f-b7434b3998c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517243054 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.3517243054
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.946136604
Short name T317
Test name
Test status
Simulation time 157751334 ps
CPU time 1.77 seconds
Started Jun 29 07:24:47 PM PDT 24
Finished Jun 29 07:24:50 PM PDT 24
Peak memory 239240 kb
Host smart-7dbfea70-d87f-4f13-8a8b-00660ad8d4ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946136604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.946136604
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.155881854
Short name T1257
Test name
Test status
Simulation time 38076505 ps
CPU time 1.51 seconds
Started Jun 29 07:24:47 PM PDT 24
Finished Jun 29 07:24:50 PM PDT 24
Peak memory 230332 kb
Host smart-f271c2b1-f1a1-46ab-b5aa-df7e0f61adf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155881854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.155881854
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1168164720
Short name T1316
Test name
Test status
Simulation time 1662706170 ps
CPU time 5.16 seconds
Started Jun 29 07:24:45 PM PDT 24
Finished Jun 29 07:24:52 PM PDT 24
Peak memory 242400 kb
Host smart-8458b902-9cc6-4e84-853d-8b2dcadc0f46
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168164720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.1168164720
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1926283712
Short name T1239
Test name
Test status
Simulation time 283362799 ps
CPU time 5.99 seconds
Started Jun 29 07:24:43 PM PDT 24
Finished Jun 29 07:24:51 PM PDT 24
Peak memory 246304 kb
Host smart-77ff2487-a6ed-4dc8-8344-64a68ef1cea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926283712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1926283712
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2715961133
Short name T376
Test name
Test status
Simulation time 813354447 ps
CPU time 10.4 seconds
Started Jun 29 07:24:47 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 239344 kb
Host smart-4bdd8971-5ea0-406c-8af1-92ffdc011a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715961133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.2715961133
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2397212067
Short name T1229
Test name
Test status
Simulation time 198821929 ps
CPU time 2.63 seconds
Started Jun 29 07:24:56 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 246448 kb
Host smart-62d4bd0d-cd3f-40f2-994d-5b442adb50dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397212067 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2397212067
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.2704787597
Short name T1212
Test name
Test status
Simulation time 43632662 ps
CPU time 1.59 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:24:54 PM PDT 24
Peak memory 239176 kb
Host smart-f36c383b-2a38-4aab-ad24-63fe81c8ddb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704787597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.2704787597
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.548229041
Short name T1238
Test name
Test status
Simulation time 583557816 ps
CPU time 1.92 seconds
Started Jun 29 07:24:56 PM PDT 24
Finished Jun 29 07:24:58 PM PDT 24
Peak memory 231068 kb
Host smart-efd58f8d-dcb6-42d6-b2bf-fc3b6399a19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548229041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.548229041
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3443032739
Short name T1301
Test name
Test status
Simulation time 74623600 ps
CPU time 2.2 seconds
Started Jun 29 07:24:58 PM PDT 24
Finished Jun 29 07:25:01 PM PDT 24
Peak memory 239256 kb
Host smart-56395a46-d296-4ab4-8213-041ca3a0075f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443032739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.3443032739
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.352318087
Short name T1233
Test name
Test status
Simulation time 243048432 ps
CPU time 3.52 seconds
Started Jun 29 07:24:54 PM PDT 24
Finished Jun 29 07:24:58 PM PDT 24
Peak memory 246436 kb
Host smart-3b017a9a-1d73-4462-b133-74c579fbd13b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352318087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.352318087
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3347589717
Short name T1228
Test name
Test status
Simulation time 883447110 ps
CPU time 10.02 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:25:04 PM PDT 24
Peak memory 244032 kb
Host smart-9fc62739-6137-4c4f-8847-a3eb396b7f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347589717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.3347589717
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.944593156
Short name T1235
Test name
Test status
Simulation time 1088474510 ps
CPU time 3.02 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:57 PM PDT 24
Peak memory 239332 kb
Host smart-53a924fd-db9b-4451-96ec-517b737746ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944593156 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.944593156
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3661732105
Short name T320
Test name
Test status
Simulation time 43229937 ps
CPU time 1.52 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:56 PM PDT 24
Peak memory 239204 kb
Host smart-d89252d1-6528-4e99-9d91-dae4fe89d4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661732105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3661732105
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.3169133218
Short name T1247
Test name
Test status
Simulation time 74866755 ps
CPU time 1.43 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:24:55 PM PDT 24
Peak memory 230248 kb
Host smart-7155d406-907e-47f3-b220-ff1a79be6315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169133218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3169133218
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.2452141307
Short name T1309
Test name
Test status
Simulation time 161777109 ps
CPU time 2.96 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:57 PM PDT 24
Peak memory 242380 kb
Host smart-e8547caf-7ba1-46b1-827d-a5f4613e0dce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452141307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.2452141307
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.2985872813
Short name T1306
Test name
Test status
Simulation time 134549585 ps
CPU time 3.73 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:58 PM PDT 24
Peak memory 246932 kb
Host smart-04f36ddb-1e22-4558-8114-787ffad00c98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985872813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2985872813
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1818460282
Short name T1215
Test name
Test status
Simulation time 135116072 ps
CPU time 2.36 seconds
Started Jun 29 07:24:56 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 246104 kb
Host smart-811de37b-eee6-4135-b3a0-8feca6e6d2c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818460282 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.1818460282
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.962595897
Short name T319
Test name
Test status
Simulation time 79202285 ps
CPU time 1.56 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:55 PM PDT 24
Peak memory 240984 kb
Host smart-f4e128a8-8135-4d12-9824-57cb5ead5a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962595897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.962595897
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.653223018
Short name T1274
Test name
Test status
Simulation time 96488383 ps
CPU time 1.39 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:24:55 PM PDT 24
Peak memory 230624 kb
Host smart-dd537dac-0928-4bb7-b454-23f2366af3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653223018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.653223018
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.2462376117
Short name T1273
Test name
Test status
Simulation time 133169536 ps
CPU time 2.21 seconds
Started Jun 29 07:24:56 PM PDT 24
Finished Jun 29 07:24:59 PM PDT 24
Peak memory 242184 kb
Host smart-bc2a01bb-b5fa-41b1-9a06-b306a0a9a9e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462376117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.2462376117
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.1823329959
Short name T1206
Test name
Test status
Simulation time 93344064 ps
CPU time 3.38 seconds
Started Jun 29 07:24:54 PM PDT 24
Finished Jun 29 07:24:58 PM PDT 24
Peak memory 246580 kb
Host smart-0399fa38-2feb-4164-b5be-2b7ee174197d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823329959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.1823329959
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1388317430
Short name T368
Test name
Test status
Simulation time 1007507956 ps
CPU time 12.71 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:25:06 PM PDT 24
Peak memory 243860 kb
Host smart-4f065b16-2326-4775-881e-2c842a74a679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388317430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.1388317430
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.4268444157
Short name T1225
Test name
Test status
Simulation time 117839279 ps
CPU time 2.54 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:24:56 PM PDT 24
Peak memory 239252 kb
Host smart-ab1b4532-1fae-4e54-9231-c3e6206f4cdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268444157 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.4268444157
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.662739466
Short name T1196
Test name
Test status
Simulation time 87166915 ps
CPU time 1.73 seconds
Started Jun 29 07:24:55 PM PDT 24
Finished Jun 29 07:24:58 PM PDT 24
Peak memory 239240 kb
Host smart-3aeb3305-485d-4d13-b01a-212a3874d193
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662739466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.662739466
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.501842816
Short name T1276
Test name
Test status
Simulation time 37563910 ps
CPU time 1.42 seconds
Started Jun 29 07:24:54 PM PDT 24
Finished Jun 29 07:24:56 PM PDT 24
Peak memory 230548 kb
Host smart-b7f86ddf-c937-4e60-937c-6ba3adda572e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501842816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.501842816
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.977212785
Short name T337
Test name
Test status
Simulation time 62013410 ps
CPU time 2.19 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:24:55 PM PDT 24
Peak memory 242300 kb
Host smart-a3ad2275-c0af-434e-81d3-71d75880924d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977212785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_same_csr_outstanding.977212785
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2975805801
Short name T1253
Test name
Test status
Simulation time 322394958 ps
CPU time 6.26 seconds
Started Jun 29 07:24:53 PM PDT 24
Finished Jun 29 07:25:00 PM PDT 24
Peak memory 246652 kb
Host smart-49935ca9-ff5f-4ed0-8f25-692ef278edae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975805801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2975805801
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.4172221374
Short name T1303
Test name
Test status
Simulation time 1244516903 ps
CPU time 10.7 seconds
Started Jun 29 07:24:52 PM PDT 24
Finished Jun 29 07:25:03 PM PDT 24
Peak memory 239340 kb
Host smart-59319401-dbba-4ab4-9bcf-55f0dbec0234
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172221374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.4172221374
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1959749431
Short name T775
Test name
Test status
Simulation time 114076788 ps
CPU time 1.97 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:30 PM PDT 24
Peak memory 240256 kb
Host smart-202363bf-ad00-47a7-a4a0-e85d765134a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959749431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1959749431
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3036083825
Short name T1101
Test name
Test status
Simulation time 3189037981 ps
CPU time 5.32 seconds
Started Jun 29 07:25:15 PM PDT 24
Finished Jun 29 07:25:21 PM PDT 24
Peak memory 248760 kb
Host smart-4736fd59-04a5-4af7-8a36-c4e876e1e3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036083825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3036083825
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3292476464
Short name T45
Test name
Test status
Simulation time 2666008324 ps
CPU time 21.59 seconds
Started Jun 29 07:25:18 PM PDT 24
Finished Jun 29 07:25:41 PM PDT 24
Peak memory 248872 kb
Host smart-d63de026-64e4-4234-ac0a-84dc943a669e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292476464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3292476464
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.3326752614
Short name T429
Test name
Test status
Simulation time 680157793 ps
CPU time 24.1 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:42 PM PDT 24
Peak memory 241856 kb
Host smart-f1bb9674-58c8-461c-9245-04a0aef2ea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326752614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3326752614
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3231990209
Short name T724
Test name
Test status
Simulation time 27006528819 ps
CPU time 45.41 seconds
Started Jun 29 07:25:18 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242396 kb
Host smart-dc5547ff-605f-4edb-9732-f4ff4be7f5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231990209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3231990209
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2201984882
Short name T757
Test name
Test status
Simulation time 3051910153 ps
CPU time 12.09 seconds
Started Jun 29 07:25:14 PM PDT 24
Finished Jun 29 07:25:27 PM PDT 24
Peak memory 241608 kb
Host smart-89abcdb0-714c-43de-9108-7e9e5d273fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201984882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2201984882
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.2191144858
Short name T937
Test name
Test status
Simulation time 1476372912 ps
CPU time 14.48 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:25:38 PM PDT 24
Peak memory 242192 kb
Host smart-b6b899a7-25e8-4728-807d-b649c5de1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191144858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2191144858
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1188502281
Short name T1067
Test name
Test status
Simulation time 2216795847 ps
CPU time 40.9 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 242292 kb
Host smart-34dd86bb-f5ad-4a68-9f18-dfc787b107c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188502281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1188502281
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.1052394376
Short name T735
Test name
Test status
Simulation time 861136204 ps
CPU time 21.06 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:39 PM PDT 24
Peak memory 241836 kb
Host smart-95bbe16b-e142-4fcf-9321-9b9d3ed561be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052394376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.1052394376
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.2937615458
Short name T298
Test name
Test status
Simulation time 1533102328 ps
CPU time 12 seconds
Started Jun 29 07:25:17 PM PDT 24
Finished Jun 29 07:25:30 PM PDT 24
Peak memory 242344 kb
Host smart-6283881b-696f-4f5a-96dc-1e38a90cd4ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2937615458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2937615458
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.3639490891
Short name T640
Test name
Test status
Simulation time 793426609 ps
CPU time 22.13 seconds
Started Jun 29 07:25:20 PM PDT 24
Finished Jun 29 07:25:43 PM PDT 24
Peak memory 241452 kb
Host smart-18cb5ab7-ff08-4e6f-b083-8a4b96c89700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639490891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3639490891
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.1855456089
Short name T226
Test name
Test status
Simulation time 550618063 ps
CPU time 11.48 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:38 PM PDT 24
Peak memory 242376 kb
Host smart-fdf9dcda-86b5-428c-a0ec-3030b2bbc7fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855456089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1855456089
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.2763307413
Short name T599
Test name
Test status
Simulation time 85382278 ps
CPU time 2.65 seconds
Started Jun 29 07:25:16 PM PDT 24
Finished Jun 29 07:25:20 PM PDT 24
Peak memory 241884 kb
Host smart-687bbd28-9d6d-42c1-91f9-5f6a3a19799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763307413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2763307413
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.1997188042
Short name T1108
Test name
Test status
Simulation time 8954430292 ps
CPU time 149.79 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 247096 kb
Host smart-dee9e7dd-40fd-4c97-8670-ecd0e323c457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997188042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
1997188042
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2724649715
Short name T15
Test name
Test status
Simulation time 144578974263 ps
CPU time 784.56 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:38:31 PM PDT 24
Peak memory 265340 kb
Host smart-3e916555-2f48-4159-9100-3156b4007cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724649715 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2724649715
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2910836390
Short name T498
Test name
Test status
Simulation time 1155564124 ps
CPU time 9 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:37 PM PDT 24
Peak memory 242644 kb
Host smart-23a12be6-a770-4df3-b63c-87e206c1cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910836390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2910836390
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.1011751903
Short name T303
Test name
Test status
Simulation time 103796331 ps
CPU time 2.17 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:29 PM PDT 24
Peak memory 240096 kb
Host smart-c3b0018f-b3ac-4b8f-ae7e-7d07b4a030a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011751903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.1011751903
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.1739477259
Short name T631
Test name
Test status
Simulation time 1396354378 ps
CPU time 25.91 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:52 PM PDT 24
Peak memory 242240 kb
Host smart-bab5c303-0fa3-40e4-955e-06ba44fa7ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739477259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1739477259
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.2153928563
Short name T197
Test name
Test status
Simulation time 362206903 ps
CPU time 5.8 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:32 PM PDT 24
Peak memory 248784 kb
Host smart-25582c25-f806-46ba-875c-5b3db4319791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153928563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2153928563
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.3813064110
Short name T876
Test name
Test status
Simulation time 699812468 ps
CPU time 10.89 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:25:34 PM PDT 24
Peak memory 241968 kb
Host smart-92f7df11-5bb0-495e-9f58-1dba2a105bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813064110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3813064110
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.542737035
Short name T957
Test name
Test status
Simulation time 23388505515 ps
CPU time 34.05 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:26:00 PM PDT 24
Peak memory 248860 kb
Host smart-0ba193f0-57c7-4eeb-b5e7-62469cf9383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542737035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.542737035
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.1513424206
Short name T883
Test name
Test status
Simulation time 300505557 ps
CPU time 7.72 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:36 PM PDT 24
Peak memory 243592 kb
Host smart-7c5c987c-da51-4c88-bce3-47066bfe9e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513424206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.1513424206
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3819314476
Short name T515
Test name
Test status
Simulation time 2706415293 ps
CPU time 54.55 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:26:22 PM PDT 24
Peak memory 243432 kb
Host smart-a2ec2218-96dc-4d42-935b-635556f63102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819314476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3819314476
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.3644786440
Short name T439
Test name
Test status
Simulation time 1062606364 ps
CPU time 17.46 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:25:44 PM PDT 24
Peak memory 241904 kb
Host smart-7f58df9b-00af-495b-b89d-7bfcd7e146b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644786440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3644786440
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.688990681
Short name T1073
Test name
Test status
Simulation time 6526650840 ps
CPU time 20.86 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:46 PM PDT 24
Peak memory 248776 kb
Host smart-fe269313-d1f0-4be9-a0c7-2ba2f96b2554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688990681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.688990681
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3932214546
Short name T727
Test name
Test status
Simulation time 772604810 ps
CPU time 10.78 seconds
Started Jun 29 07:25:28 PM PDT 24
Finished Jun 29 07:25:40 PM PDT 24
Peak memory 242540 kb
Host smart-fc78a6dd-0708-4603-9fe6-a3bb15309a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932214546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3932214546
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.445391905
Short name T203
Test name
Test status
Simulation time 9876907387 ps
CPU time 113.95 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 245420 kb
Host smart-eed5f556-c972-4abf-ac8c-6cf2957860dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445391905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.445391905
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2290886739
Short name T861
Test name
Test status
Simulation time 47586664277 ps
CPU time 625.75 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:35:50 PM PDT 24
Peak memory 268700 kb
Host smart-85a0855e-5318-4ecf-aca7-3371fc289916
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290886739 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2290886739
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.1553355766
Short name T1028
Test name
Test status
Simulation time 794611392 ps
CPU time 17.19 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:42 PM PDT 24
Peak memory 248764 kb
Host smart-46d5613f-69bd-4251-8ace-fa8dcdf79995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553355766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.1553355766
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.4199844286
Short name T895
Test name
Test status
Simulation time 153395292 ps
CPU time 1.7 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:25:50 PM PDT 24
Peak memory 240100 kb
Host smart-02344e4d-1976-4fdc-a186-ee3fc8801ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199844286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.4199844286
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.1103373633
Short name T1121
Test name
Test status
Simulation time 531189292 ps
CPU time 6.57 seconds
Started Jun 29 07:25:47 PM PDT 24
Finished Jun 29 07:25:54 PM PDT 24
Peak memory 248792 kb
Host smart-99c4923d-406b-4170-98ab-28feef37201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103373633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.1103373633
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.65491372
Short name T962
Test name
Test status
Simulation time 13882697477 ps
CPU time 38.37 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 248636 kb
Host smart-7a95576f-46fc-47f1-801c-ead73c617cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65491372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.65491372
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.65484225
Short name T1182
Test name
Test status
Simulation time 1553761957 ps
CPU time 26.46 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 242396 kb
Host smart-4445b2d9-8c5b-41b5-b479-6c4e50cc321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65484225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.65484225
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3054016188
Short name T1167
Test name
Test status
Simulation time 663102616 ps
CPU time 4.85 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:47 PM PDT 24
Peak memory 242084 kb
Host smart-9de57a8f-ef91-4233-bc8b-de2cdf3dba25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054016188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3054016188
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.4237027064
Short name T1052
Test name
Test status
Simulation time 2511176398 ps
CPU time 34.99 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:26:24 PM PDT 24
Peak memory 249476 kb
Host smart-dcb5c9a9-193b-419e-b4f6-f525acf7326c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237027064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.4237027064
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.1120881876
Short name T1005
Test name
Test status
Simulation time 1157667916 ps
CPU time 21.77 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 242188 kb
Host smart-f086329d-9be7-4042-8942-1286537bb3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120881876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.1120881876
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.966831576
Short name T855
Test name
Test status
Simulation time 2559405705 ps
CPU time 5.44 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 241788 kb
Host smart-caeab484-0a73-4db0-993f-48a9f6f42f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966831576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.966831576
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2590478622
Short name T117
Test name
Test status
Simulation time 1042437428 ps
CPU time 7.79 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:25:57 PM PDT 24
Peak memory 242240 kb
Host smart-45ea3206-9c56-4959-a8aa-dac52a82b288
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590478622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2590478622
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.2614521772
Short name T48
Test name
Test status
Simulation time 1807727972 ps
CPU time 6.02 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:25:59 PM PDT 24
Peak memory 241760 kb
Host smart-970173bb-2111-40ca-980b-c54d9e7004c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614521772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2614521772
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.2061917089
Short name T425
Test name
Test status
Simulation time 157238269 ps
CPU time 5.67 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 241896 kb
Host smart-1781dadd-5e5a-4691-8730-46a62c4510a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061917089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2061917089
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.3204414637
Short name T292
Test name
Test status
Simulation time 7190126668 ps
CPU time 106.15 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:27:38 PM PDT 24
Peak memory 247460 kb
Host smart-5a61cfe6-1433-4362-b208-a03c83d8784d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204414637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.3204414637
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.1177995403
Short name T1174
Test name
Test status
Simulation time 530739233 ps
CPU time 4.55 seconds
Started Jun 29 07:28:23 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 242036 kb
Host smart-e2b173b9-7515-404b-9db8-59db5e0a1518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177995403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.1177995403
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.1570456895
Short name T740
Test name
Test status
Simulation time 395348274 ps
CPU time 5.01 seconds
Started Jun 29 07:28:25 PM PDT 24
Finished Jun 29 07:28:31 PM PDT 24
Peak memory 242088 kb
Host smart-a716ee2b-b909-49cb-a62d-65e0113ba884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570456895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.1570456895
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1023191538
Short name T659
Test name
Test status
Simulation time 566355803 ps
CPU time 4.49 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:27 PM PDT 24
Peak memory 242252 kb
Host smart-5b0ce87a-8ad1-4ebf-8921-fabe81aebc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023191538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1023191538
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.1715373807
Short name T218
Test name
Test status
Simulation time 884805675 ps
CPU time 20.9 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 241736 kb
Host smart-fea492f4-7799-460a-a534-97a3733b3335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715373807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1715373807
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.1304871031
Short name T746
Test name
Test status
Simulation time 282245811 ps
CPU time 4.77 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 242044 kb
Host smart-5782fa36-818d-4d5b-b75d-0f278478abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304871031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1304871031
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2614265447
Short name T713
Test name
Test status
Simulation time 544813738 ps
CPU time 6.97 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 241764 kb
Host smart-f3c58dd5-b5ab-44e2-9b19-5912a5644368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614265447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2614265447
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.443272813
Short name T229
Test name
Test status
Simulation time 133826141 ps
CPU time 4.1 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:29 PM PDT 24
Peak memory 241836 kb
Host smart-e463ac2e-2791-4e91-92c1-f16268cb4b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443272813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.443272813
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.4050064667
Short name T647
Test name
Test status
Simulation time 2941537257 ps
CPU time 13.02 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 241904 kb
Host smart-008e848a-5de0-43d9-81ba-027256e87d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050064667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.4050064667
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.2238748967
Short name T328
Test name
Test status
Simulation time 2530696404 ps
CPU time 5.14 seconds
Started Jun 29 07:28:23 PM PDT 24
Finished Jun 29 07:28:29 PM PDT 24
Peak memory 242224 kb
Host smart-ef8807dc-dc20-40fe-aa68-0338d1fdcc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238748967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2238748967
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.4034550921
Short name T1088
Test name
Test status
Simulation time 594851758 ps
CPU time 13.41 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242288 kb
Host smart-39155e45-62b3-4c38-bf22-e2989cadcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034550921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.4034550921
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.2956272447
Short name T926
Test name
Test status
Simulation time 182539674 ps
CPU time 5.07 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 241920 kb
Host smart-e1929329-e697-4a0c-87eb-02107f9f8d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956272447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.2956272447
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.4019536428
Short name T668
Test name
Test status
Simulation time 1852784150 ps
CPU time 4.1 seconds
Started Jun 29 07:28:25 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 242468 kb
Host smart-2bfe717e-f6db-4307-80f9-1cade6deb3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019536428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.4019536428
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3896243673
Short name T1107
Test name
Test status
Simulation time 143199541 ps
CPU time 6.9 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:32 PM PDT 24
Peak memory 241964 kb
Host smart-423de7db-27c9-4dac-9902-a77d7a6167dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896243673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3896243673
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3801589607
Short name T1156
Test name
Test status
Simulation time 398228550 ps
CPU time 4.6 seconds
Started Jun 29 07:28:25 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 241960 kb
Host smart-d826800c-776a-4b64-beaa-da77a51278d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801589607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3801589607
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3894424396
Short name T190
Test name
Test status
Simulation time 3998393669 ps
CPU time 10.89 seconds
Started Jun 29 07:28:23 PM PDT 24
Finished Jun 29 07:28:35 PM PDT 24
Peak memory 241892 kb
Host smart-2cc89b7a-8f5a-481d-afab-953123d514ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894424396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3894424396
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.2279762289
Short name T781
Test name
Test status
Simulation time 250115783 ps
CPU time 4.63 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:29 PM PDT 24
Peak memory 242084 kb
Host smart-dc83746a-3d02-4fac-86b6-60aa236ec990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279762289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2279762289
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.6872686
Short name T638
Test name
Test status
Simulation time 322990088 ps
CPU time 3.28 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 242152 kb
Host smart-0cc044e4-cc90-4be8-9393-d0efdbe4f90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6872686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.6872686
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.3310421309
Short name T91
Test name
Test status
Simulation time 590793108 ps
CPU time 11 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242612 kb
Host smart-828d58f7-7d90-437f-8f78-efd4ff864034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310421309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3310421309
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.3679633827
Short name T986
Test name
Test status
Simulation time 8960513973 ps
CPU time 24.72 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 242448 kb
Host smart-f7246d57-b56c-4d17-9fc7-39568a71a45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679633827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3679633827
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.1457977944
Short name T324
Test name
Test status
Simulation time 5930571844 ps
CPU time 19.03 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 243408 kb
Host smart-b4ebb627-6a50-429f-ac33-f1211e24cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457977944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.1457977944
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1121659424
Short name T521
Test name
Test status
Simulation time 124126061 ps
CPU time 3.38 seconds
Started Jun 29 07:26:00 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242084 kb
Host smart-4da9503f-16dc-45a0-bafc-d960bd167278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121659424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1121659424
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.2533748034
Short name T792
Test name
Test status
Simulation time 4237746955 ps
CPU time 27.93 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:28 PM PDT 24
Peak memory 257092 kb
Host smart-2b8db0de-db6b-4267-b273-2b057884477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533748034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2533748034
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2989968639
Short name T105
Test name
Test status
Simulation time 1540201478 ps
CPU time 15.27 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:26:08 PM PDT 24
Peak memory 242376 kb
Host smart-bb94bc17-00c6-4d29-88dc-3362511e1151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989968639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2989968639
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.300565928
Short name T274
Test name
Test status
Simulation time 222575264 ps
CPU time 9.62 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 242324 kb
Host smart-94b210ec-d07b-4cba-87e5-57db6ca7d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300565928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.300565928
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.944019079
Short name T1066
Test name
Test status
Simulation time 2480782765 ps
CPU time 23.02 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:13 PM PDT 24
Peak memory 242080 kb
Host smart-4514ea9b-6287-4a77-a80d-658d93b585f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=944019079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.944019079
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.3979019507
Short name T1106
Test name
Test status
Simulation time 256106346 ps
CPU time 9.19 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:26:02 PM PDT 24
Peak memory 248692 kb
Host smart-50ea4323-4141-469a-a570-dbcaa9eb8c1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979019507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3979019507
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2057943330
Short name T846
Test name
Test status
Simulation time 677849417 ps
CPU time 10.47 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:26:02 PM PDT 24
Peak memory 248748 kb
Host smart-e39a720b-463c-4f3c-9093-2e86521a4059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057943330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2057943330
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.1738016163
Short name T732
Test name
Test status
Simulation time 55693641334 ps
CPU time 99.02 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:27:29 PM PDT 24
Peak memory 257036 kb
Host smart-32f0c7e1-474d-4e2c-8fac-5e9c04505cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738016163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.1738016163
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1122033814
Short name T345
Test name
Test status
Simulation time 220015895344 ps
CPU time 878.9 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:40:29 PM PDT 24
Peak memory 362868 kb
Host smart-d2a2af72-c6bd-471d-96c7-3fe1436abf5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122033814 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.1122033814
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.176845436
Short name T872
Test name
Test status
Simulation time 5163557358 ps
CPU time 14.71 seconds
Started Jun 29 07:25:53 PM PDT 24
Finished Jun 29 07:26:08 PM PDT 24
Peak memory 242728 kb
Host smart-4c2212c4-f812-4dcc-8b3a-f76f9815bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176845436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.176845436
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3129296673
Short name T815
Test name
Test status
Simulation time 206080512 ps
CPU time 5.48 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 241888 kb
Host smart-5944a008-aca4-41d5-a06d-4208184aa201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129296673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3129296673
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1888851077
Short name T1124
Test name
Test status
Simulation time 622621942 ps
CPU time 5.08 seconds
Started Jun 29 07:28:32 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 242060 kb
Host smart-9fa7fc37-940e-4808-a043-493bc7fa336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888851077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1888851077
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.933748162
Short name T816
Test name
Test status
Simulation time 1767639290 ps
CPU time 4.87 seconds
Started Jun 29 07:28:32 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 242168 kb
Host smart-4bad16fd-dfcc-4ef5-9d38-2b5597376a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933748162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.933748162
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.1149111105
Short name T1139
Test name
Test status
Simulation time 3193669186 ps
CPU time 7.38 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:40 PM PDT 24
Peak memory 241904 kb
Host smart-7fe647ae-e55d-4b67-8b5f-5015e99c6023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149111105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1149111105
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.1457002585
Short name T182
Test name
Test status
Simulation time 429677450 ps
CPU time 4.47 seconds
Started Jun 29 07:28:28 PM PDT 24
Finished Jun 29 07:28:33 PM PDT 24
Peak memory 242068 kb
Host smart-c00db6a6-7a98-4f67-be18-95ad185f5762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457002585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1457002585
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2718698536
Short name T596
Test name
Test status
Simulation time 1208551923 ps
CPU time 3.91 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:35 PM PDT 24
Peak memory 242048 kb
Host smart-1cfceab3-58e9-4671-911e-2b3fcda293c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718698536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2718698536
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.3186574054
Short name T212
Test name
Test status
Simulation time 286614197 ps
CPU time 4.24 seconds
Started Jun 29 07:28:29 PM PDT 24
Finished Jun 29 07:28:34 PM PDT 24
Peak memory 242084 kb
Host smart-3a5634a0-173a-4f6b-8f04-44dac5bb3683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186574054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3186574054
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2212254359
Short name T262
Test name
Test status
Simulation time 273448160 ps
CPU time 4.05 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:34 PM PDT 24
Peak memory 241964 kb
Host smart-3b9919a5-299d-4fb3-9fdd-f419368b1d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212254359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2212254359
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.2055122071
Short name T1057
Test name
Test status
Simulation time 213673349 ps
CPU time 4.13 seconds
Started Jun 29 07:28:32 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 242104 kb
Host smart-5e7b001a-3c42-4a40-95a8-561fa5a9dd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055122071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2055122071
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.4013050961
Short name T1120
Test name
Test status
Simulation time 144649050 ps
CPU time 3.62 seconds
Started Jun 29 07:28:34 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 242008 kb
Host smart-9741bd2d-0fea-470f-858b-cfd817969969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013050961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.4013050961
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.4253245460
Short name T198
Test name
Test status
Simulation time 279836285 ps
CPU time 7.59 seconds
Started Jun 29 07:28:29 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 241972 kb
Host smart-8608e0e9-b1c0-4d65-930d-772c19d41a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253245460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.4253245460
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2385238000
Short name T1010
Test name
Test status
Simulation time 454480001 ps
CPU time 3.8 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242164 kb
Host smart-62a9f8f3-9030-4b6b-a20c-ed1e327d639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385238000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2385238000
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3382851606
Short name T168
Test name
Test status
Simulation time 1107148517 ps
CPU time 13.54 seconds
Started Jun 29 07:28:28 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 241896 kb
Host smart-ae0dfc69-f1c8-4fb8-96a7-1ef34af2a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382851606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3382851606
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.3053284345
Short name T739
Test name
Test status
Simulation time 1614520252 ps
CPU time 5.18 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 241824 kb
Host smart-539d7617-0341-418a-a5a5-a405768e178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053284345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.3053284345
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.4215448872
Short name T878
Test name
Test status
Simulation time 522017407 ps
CPU time 5.9 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 242240 kb
Host smart-8c6f5149-ec3a-4c35-87ef-3f5bfe854591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215448872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.4215448872
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.4182756674
Short name T602
Test name
Test status
Simulation time 292709704 ps
CPU time 4.47 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 241820 kb
Host smart-e9ded833-4546-4e07-8ccb-0a52be3117c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182756674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.4182756674
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.944736534
Short name T415
Test name
Test status
Simulation time 151549677 ps
CPU time 3.44 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:35 PM PDT 24
Peak memory 241924 kb
Host smart-ffe65d11-b75c-4269-93da-a5bb7b2f6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944736534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.944736534
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.453780901
Short name T1022
Test name
Test status
Simulation time 160269770 ps
CPU time 2.1 seconds
Started Jun 29 07:25:52 PM PDT 24
Finished Jun 29 07:25:55 PM PDT 24
Peak memory 240392 kb
Host smart-15d5ebdc-849c-4d74-977e-5ee34726e58c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453780901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.453780901
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.1987332894
Short name T196
Test name
Test status
Simulation time 435797305 ps
CPU time 19.41 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 242216 kb
Host smart-dcc9a905-e726-44d6-9b59-667eb3b9fe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987332894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1987332894
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.2817732774
Short name T119
Test name
Test status
Simulation time 834393050 ps
CPU time 16.65 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 248776 kb
Host smart-7e9daa30-3fc5-42a4-8bad-f572d1ce042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817732774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.2817732774
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.1481016739
Short name T1036
Test name
Test status
Simulation time 535614161 ps
CPU time 4.02 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:25:55 PM PDT 24
Peak memory 241948 kb
Host smart-437be4ef-1dac-4226-9342-71315fa1fcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481016739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1481016739
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.1139352296
Short name T363
Test name
Test status
Simulation time 4593237895 ps
CPU time 52.97 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:26:42 PM PDT 24
Peak memory 251596 kb
Host smart-c827c719-a155-48eb-ad18-723621cdab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139352296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.1139352296
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1769013092
Short name T691
Test name
Test status
Simulation time 115488180 ps
CPU time 3.61 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:25:53 PM PDT 24
Peak memory 242100 kb
Host smart-fb1c9e93-4fb5-4749-9875-31e9f0d7c70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769013092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1769013092
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.1206628890
Short name T282
Test name
Test status
Simulation time 1421404641 ps
CPU time 5.5 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:25:55 PM PDT 24
Peak memory 241824 kb
Host smart-ab2409e2-edd5-479d-a9e2-2d41d0b45c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206628890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1206628890
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.3912236146
Short name T765
Test name
Test status
Simulation time 7064284658 ps
CPU time 15.25 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 242304 kb
Host smart-12e3cd18-6412-40b6-b451-2d8eb54b7f40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912236146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.3912236146
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.1781814334
Short name T983
Test name
Test status
Simulation time 571436311 ps
CPU time 11.74 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242072 kb
Host smart-1adc07f5-34db-4fb7-9341-6ed0cd2eb847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781814334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1781814334
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.2116895674
Short name T862
Test name
Test status
Simulation time 829760844 ps
CPU time 6.48 seconds
Started Jun 29 07:25:53 PM PDT 24
Finished Jun 29 07:26:00 PM PDT 24
Peak memory 242468 kb
Host smart-b2156d00-3ee3-4dda-bac4-bf9a8f11d1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116895674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.2116895674
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.2590060012
Short name T1090
Test name
Test status
Simulation time 2740279580 ps
CPU time 21.46 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:26:13 PM PDT 24
Peak memory 248868 kb
Host smart-8b98f8b1-6835-4d20-ab79-98f5aece0e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590060012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2590060012
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.2672205723
Short name T978
Test name
Test status
Simulation time 105749798 ps
CPU time 4.8 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242100 kb
Host smart-4e222de8-d73e-4a2c-97f7-b97544b79f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672205723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2672205723
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.4070698721
Short name T9
Test name
Test status
Simulation time 945943423 ps
CPU time 6.32 seconds
Started Jun 29 07:28:29 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242180 kb
Host smart-af44eb74-128e-43f7-9305-2c0d79a0d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070698721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.4070698721
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.210821435
Short name T1098
Test name
Test status
Simulation time 175657406 ps
CPU time 3.35 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242176 kb
Host smart-e2428913-73eb-4c6f-b5e0-5dd683ef5020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210821435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.210821435
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.2377844259
Short name T132
Test name
Test status
Simulation time 1030226540 ps
CPU time 7.82 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:40 PM PDT 24
Peak memory 241976 kb
Host smart-a0367cb5-b16e-4600-b942-bbd492927de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377844259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2377844259
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.2169502652
Short name T1006
Test name
Test status
Simulation time 259734398 ps
CPU time 4.04 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:35 PM PDT 24
Peak memory 241936 kb
Host smart-37b68057-81fb-4546-9508-edd223a852e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169502652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.2169502652
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.2836902018
Short name T269
Test name
Test status
Simulation time 144043687 ps
CPU time 3.17 seconds
Started Jun 29 07:28:32 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 241964 kb
Host smart-75489fb7-b273-44d1-9669-bf6f451396b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836902018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.2836902018
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3563127422
Short name T679
Test name
Test status
Simulation time 270943889 ps
CPU time 4.11 seconds
Started Jun 29 07:28:29 PM PDT 24
Finished Jun 29 07:28:34 PM PDT 24
Peak memory 242076 kb
Host smart-65fe97bc-7dbc-4b7e-b313-0b1d18e16002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563127422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3563127422
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.2523369540
Short name T1130
Test name
Test status
Simulation time 1919174670 ps
CPU time 5.97 seconds
Started Jun 29 07:28:32 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 242312 kb
Host smart-46c2f17d-a948-413b-9c91-751e16cb7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523369540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2523369540
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.505993459
Short name T910
Test name
Test status
Simulation time 183472449 ps
CPU time 3.57 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242080 kb
Host smart-cf30dd26-db0d-41d0-9fe4-561ed56e3a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505993459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.505993459
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.3129765090
Short name T1064
Test name
Test status
Simulation time 103003113 ps
CPU time 4.08 seconds
Started Jun 29 07:28:33 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 241956 kb
Host smart-e5bc7f2e-aa02-4428-9940-fe21557ed8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129765090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3129765090
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.1843326468
Short name T256
Test name
Test status
Simulation time 185196357 ps
CPU time 4.2 seconds
Started Jun 29 07:28:28 PM PDT 24
Finished Jun 29 07:28:33 PM PDT 24
Peak memory 242340 kb
Host smart-964c6885-4df6-4265-8d2b-1a93aec0ee3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843326468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1843326468
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1670662103
Short name T1149
Test name
Test status
Simulation time 4204598524 ps
CPU time 18.05 seconds
Started Jun 29 07:28:33 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 241916 kb
Host smart-997d4ccf-2db7-454d-9eff-8eb62f77e692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670662103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1670662103
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.2006911962
Short name T917
Test name
Test status
Simulation time 211597907 ps
CPU time 4.88 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 242184 kb
Host smart-38e6172f-71b6-4841-b2dc-0573a3c710fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006911962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.2006911962
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.2949815441
Short name T558
Test name
Test status
Simulation time 219044687 ps
CPU time 4.15 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:35 PM PDT 24
Peak memory 241924 kb
Host smart-8d337628-00fb-4c82-a556-a6b3d45c794b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949815441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2949815441
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.3554997331
Short name T80
Test name
Test status
Simulation time 240518089 ps
CPU time 10.9 seconds
Started Jun 29 07:28:29 PM PDT 24
Finished Jun 29 07:28:41 PM PDT 24
Peak memory 241788 kb
Host smart-345fa75b-85ae-4b42-be3c-655f9503d256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554997331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3554997331
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1736026674
Short name T826
Test name
Test status
Simulation time 498873882 ps
CPU time 4.85 seconds
Started Jun 29 07:28:33 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 242388 kb
Host smart-0fec0229-b7d6-45da-b4c1-c047cb36fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736026674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1736026674
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.1875157432
Short name T655
Test name
Test status
Simulation time 183134151 ps
CPU time 9.53 seconds
Started Jun 29 07:28:33 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 241724 kb
Host smart-20169d22-6ca1-4ac3-a0a6-155882034b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875157432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1875157432
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.3364312981
Short name T1127
Test name
Test status
Simulation time 2055428685 ps
CPU time 5.35 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:37 PM PDT 24
Peak memory 242424 kb
Host smart-4b0ecd2c-c632-4560-af43-7b3d83acf945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364312981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3364312981
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.456787596
Short name T408
Test name
Test status
Simulation time 1116708281 ps
CPU time 16.44 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:48 PM PDT 24
Peak memory 241952 kb
Host smart-7fa34f4c-a8be-4bd2-bb61-c53b7db395a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456787596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.456787596
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.1741081012
Short name T247
Test name
Test status
Simulation time 785968080 ps
CPU time 2.63 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:02 PM PDT 24
Peak memory 240304 kb
Host smart-0f5c54e6-cb00-48aa-b5b9-e86969e00c1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741081012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1741081012
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.2454633851
Short name T76
Test name
Test status
Simulation time 12198007829 ps
CPU time 25.02 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 248868 kb
Host smart-b85099f1-5be1-40e4-bcd0-bc46488c482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454633851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2454633851
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.3783014905
Short name T750
Test name
Test status
Simulation time 507810732 ps
CPU time 14.3 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242000 kb
Host smart-1bf48a06-bfea-4f3f-a4a8-7bdcb7cca100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783014905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3783014905
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.1788964446
Short name T455
Test name
Test status
Simulation time 167752771 ps
CPU time 5.74 seconds
Started Jun 29 07:25:50 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 242080 kb
Host smart-328a474b-6ef9-45e0-bf14-f9b99148a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788964446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1788964446
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.2046598407
Short name T1125
Test name
Test status
Simulation time 1850730339 ps
CPU time 5.07 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 242068 kb
Host smart-b7174c1b-b0c0-4f23-8932-0510475d4520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046598407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2046598407
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.1209932342
Short name T103
Test name
Test status
Simulation time 445335642 ps
CPU time 11.81 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 248792 kb
Host smart-4a61ffbc-6bad-437c-934f-e3aa0f1a4925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209932342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.1209932342
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.785484827
Short name T907
Test name
Test status
Simulation time 788065616 ps
CPU time 5.28 seconds
Started Jun 29 07:25:51 PM PDT 24
Finished Jun 29 07:25:57 PM PDT 24
Peak memory 241956 kb
Host smart-5126fd60-adce-408e-bcf1-b50ea25aa106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785484827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.785484827
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.496646059
Short name T955
Test name
Test status
Simulation time 1827612376 ps
CPU time 13.77 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:26:02 PM PDT 24
Peak memory 248732 kb
Host smart-1f79e416-18e4-4a55-8f3c-39dbcab852c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=496646059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.496646059
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2133161337
Short name T384
Test name
Test status
Simulation time 504491514 ps
CPU time 8.35 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 242120 kb
Host smart-49159cdc-bb47-470c-b267-8b2c2bba48da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133161337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2133161337
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1197217959
Short name T737
Test name
Test status
Simulation time 240623751 ps
CPU time 5.8 seconds
Started Jun 29 07:25:53 PM PDT 24
Finished Jun 29 07:26:00 PM PDT 24
Peak memory 242020 kb
Host smart-ae1d172b-7d0c-4572-b6cc-a0f686145a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197217959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1197217959
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.416881870
Short name T918
Test name
Test status
Simulation time 10885962256 ps
CPU time 35.87 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:26:33 PM PDT 24
Peak memory 244588 kb
Host smart-e54c67a5-a47f-4353-b44c-e4955b710a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416881870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
416881870
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.4224100103
Short name T745
Test name
Test status
Simulation time 1374768411 ps
CPU time 23.73 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:27 PM PDT 24
Peak memory 242240 kb
Host smart-178df587-4c62-4b7d-b636-69d605db0636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224100103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.4224100103
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2912601332
Short name T810
Test name
Test status
Simulation time 1888494370 ps
CPU time 5.16 seconds
Started Jun 29 07:28:30 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 241920 kb
Host smart-e306c0a6-d749-467d-9bc3-eb6f9ae0bb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912601332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2912601332
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2348859073
Short name T590
Test name
Test status
Simulation time 968654518 ps
CPU time 15.17 seconds
Started Jun 29 07:28:33 PM PDT 24
Finished Jun 29 07:28:49 PM PDT 24
Peak memory 242376 kb
Host smart-c523508f-aebe-47cf-ae6a-11f1727f1783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348859073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2348859073
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.840976738
Short name T507
Test name
Test status
Simulation time 2409750858 ps
CPU time 6.75 seconds
Started Jun 29 07:28:35 PM PDT 24
Finished Jun 29 07:28:42 PM PDT 24
Peak memory 241996 kb
Host smart-2bd08eb9-48d7-4cd8-8a35-04fd87d2cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840976738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.840976738
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.3627382230
Short name T803
Test name
Test status
Simulation time 135500457 ps
CPU time 3.78 seconds
Started Jun 29 07:28:31 PM PDT 24
Finished Jun 29 07:28:36 PM PDT 24
Peak memory 242348 kb
Host smart-003c39c5-5dc9-4f54-9cf8-9a5aa4527c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627382230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3627382230
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.1261404964
Short name T564
Test name
Test status
Simulation time 4658867828 ps
CPU time 8.46 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:49 PM PDT 24
Peak memory 241848 kb
Host smart-cc1f2cff-7c3d-4b50-aa28-52ac73972ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261404964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1261404964
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.2991040845
Short name T618
Test name
Test status
Simulation time 259643587 ps
CPU time 5.18 seconds
Started Jun 29 07:28:40 PM PDT 24
Finished Jun 29 07:28:46 PM PDT 24
Peak memory 241944 kb
Host smart-a4a93bc5-4817-498d-99db-be685be7b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991040845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2991040845
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2622521460
Short name T605
Test name
Test status
Simulation time 319857626 ps
CPU time 8.37 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:48 PM PDT 24
Peak memory 241968 kb
Host smart-4fcf6194-80f9-4596-acf1-05897ebfc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622521460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2622521460
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.3075083528
Short name T495
Test name
Test status
Simulation time 482264500 ps
CPU time 5.41 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:46 PM PDT 24
Peak memory 241964 kb
Host smart-cde7cd1d-2ebc-40a7-925e-be614e58a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075083528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3075083528
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.977059788
Short name T594
Test name
Test status
Simulation time 1723910797 ps
CPU time 7.83 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:48 PM PDT 24
Peak memory 241952 kb
Host smart-504b670b-4965-453b-9d7b-d608c80bbfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977059788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.977059788
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.3880142170
Short name T432
Test name
Test status
Simulation time 520932204 ps
CPU time 4.65 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:45 PM PDT 24
Peak memory 241940 kb
Host smart-b81d4a98-17d7-4840-9503-bea1870e9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880142170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.3880142170
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.3713711998
Short name T1054
Test name
Test status
Simulation time 920343257 ps
CPU time 8.9 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:49 PM PDT 24
Peak memory 241880 kb
Host smart-88d90e72-2176-40d4-b860-c6b98e2bac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713711998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.3713711998
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.956430926
Short name T522
Test name
Test status
Simulation time 159218022 ps
CPU time 4.32 seconds
Started Jun 29 07:28:40 PM PDT 24
Finished Jun 29 07:28:45 PM PDT 24
Peak memory 242040 kb
Host smart-65141b88-d78a-4db4-b05f-edd077f6f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956430926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.956430926
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.358637870
Short name T424
Test name
Test status
Simulation time 239552042 ps
CPU time 4.14 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:45 PM PDT 24
Peak memory 242156 kb
Host smart-d1c888f5-e14e-4d2c-8c4b-aebbdb366aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358637870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.358637870
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1752426951
Short name T1082
Test name
Test status
Simulation time 9705392489 ps
CPU time 25.35 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:29:05 PM PDT 24
Peak memory 242032 kb
Host smart-fa89ce6c-36fc-4da4-8a66-f1cdb97441ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752426951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1752426951
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2191108040
Short name T604
Test name
Test status
Simulation time 1649558120 ps
CPU time 4.98 seconds
Started Jun 29 07:28:40 PM PDT 24
Finished Jun 29 07:28:46 PM PDT 24
Peak memory 242072 kb
Host smart-24f8de4b-8c7e-4b20-8a05-08e331b26ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191108040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2191108040
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.749254210
Short name T346
Test name
Test status
Simulation time 3787892037 ps
CPU time 7.79 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:48 PM PDT 24
Peak memory 242040 kb
Host smart-b261ef8d-17ac-4a53-83b5-e0cab6dfebcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749254210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.749254210
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2844187882
Short name T794
Test name
Test status
Simulation time 160732305 ps
CPU time 4.15 seconds
Started Jun 29 07:28:37 PM PDT 24
Finished Jun 29 07:28:42 PM PDT 24
Peak memory 242084 kb
Host smart-60ad99e5-1b63-4e2b-a535-1132af1a2b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844187882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2844187882
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.2860189639
Short name T263
Test name
Test status
Simulation time 198524890 ps
CPU time 9.52 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:49 PM PDT 24
Peak memory 241908 kb
Host smart-8e8ae872-e803-4c92-bf39-13f6c115df94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860189639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2860189639
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.2469069692
Short name T1183
Test name
Test status
Simulation time 46571071 ps
CPU time 1.52 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 240388 kb
Host smart-6ea1db4b-e3be-434c-9355-34f15030dfab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469069692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2469069692
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1946667111
Short name T122
Test name
Test status
Simulation time 1756995948 ps
CPU time 3.75 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:03 PM PDT 24
Peak memory 247512 kb
Host smart-5baf07a6-2d59-4243-80e3-4bd3103994a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946667111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1946667111
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3388765697
Short name T5
Test name
Test status
Simulation time 2569937921 ps
CPU time 10.67 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:13 PM PDT 24
Peak memory 241980 kb
Host smart-7c3116e4-6da4-4e85-aeff-d8534a98de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388765697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3388765697
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.609013005
Short name T525
Test name
Test status
Simulation time 599843106 ps
CPU time 14.07 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:12 PM PDT 24
Peak memory 242320 kb
Host smart-725d683c-632f-461d-9ff7-711708ad9332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609013005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.609013005
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.804764839
Short name T232
Test name
Test status
Simulation time 154744388 ps
CPU time 4.65 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 241888 kb
Host smart-ae951c09-c8bc-4af9-823a-e0d1f7f26c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804764839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.804764839
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.2708132899
Short name T711
Test name
Test status
Simulation time 15080404825 ps
CPU time 40.36 seconds
Started Jun 29 07:26:00 PM PDT 24
Finished Jun 29 07:26:41 PM PDT 24
Peak memory 249108 kb
Host smart-f9e93d78-99f2-4662-87c1-8c88a2db137d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708132899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2708132899
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3116909392
Short name T988
Test name
Test status
Simulation time 1089041660 ps
CPU time 35.62 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:35 PM PDT 24
Peak memory 242496 kb
Host smart-40baaf43-ccb2-4ec3-91f8-d349e696395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116909392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3116909392
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.832340886
Short name T100
Test name
Test status
Simulation time 727867445 ps
CPU time 6.98 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:05 PM PDT 24
Peak memory 241892 kb
Host smart-a14d9325-c52a-409c-a819-dc523ec293a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832340886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.832340886
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.3619894565
Short name T698
Test name
Test status
Simulation time 432888650 ps
CPU time 15.44 seconds
Started Jun 29 07:26:00 PM PDT 24
Finished Jun 29 07:26:16 PM PDT 24
Peak memory 242040 kb
Host smart-aa7f45c5-439c-483a-a933-e800455d6ca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3619894565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.3619894565
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1420227413
Short name T570
Test name
Test status
Simulation time 102770865 ps
CPU time 3.34 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:26:00 PM PDT 24
Peak memory 248608 kb
Host smart-2ae4e5ae-cf6b-4c70-9601-cea8bcb4b310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420227413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1420227413
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.619049122
Short name T1132
Test name
Test status
Simulation time 4218699603 ps
CPU time 13.56 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:14 PM PDT 24
Peak memory 242160 kb
Host smart-af19008c-e5fd-4e50-afcd-518752df256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619049122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.619049122
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1767234170
Short name T199
Test name
Test status
Simulation time 7863179257 ps
CPU time 135.76 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:28:13 PM PDT 24
Peak memory 257096 kb
Host smart-422106e8-8783-43f7-83e3-57bb37ae411e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767234170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1767234170
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.660455924
Short name T342
Test name
Test status
Simulation time 182441949958 ps
CPU time 2196.34 seconds
Started Jun 29 07:26:00 PM PDT 24
Finished Jun 29 08:02:38 PM PDT 24
Peak memory 281848 kb
Host smart-ccbcc74f-e4d8-40a5-b919-abc3de92d8b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660455924 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.660455924
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.287958577
Short name T626
Test name
Test status
Simulation time 3131791886 ps
CPU time 6.02 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:06 PM PDT 24
Peak memory 242340 kb
Host smart-68dc1d13-3677-42c8-b19b-8b3280dbe313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287958577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.287958577
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1095804097
Short name T1092
Test name
Test status
Simulation time 250309470 ps
CPU time 3.73 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 242256 kb
Host smart-d6cf2801-1592-46e1-8563-3b71ec54aee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095804097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1095804097
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.4059461312
Short name T1014
Test name
Test status
Simulation time 3227951998 ps
CPU time 12.05 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242044 kb
Host smart-153670e4-5ff8-46af-9a35-5a04b37e88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059461312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.4059461312
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.4163189428
Short name T639
Test name
Test status
Simulation time 317325226 ps
CPU time 4.17 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 241852 kb
Host smart-b0e19b07-93f1-40e3-8237-056d044c0fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163189428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.4163189428
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.3987301631
Short name T1158
Test name
Test status
Simulation time 540045855 ps
CPU time 14.56 seconds
Started Jun 29 07:28:37 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242116 kb
Host smart-32b9b0c5-47fd-4d68-b384-67d14c9a01d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987301631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.3987301631
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.311463546
Short name T973
Test name
Test status
Simulation time 474292585 ps
CPU time 5.27 seconds
Started Jun 29 07:28:40 PM PDT 24
Finished Jun 29 07:28:46 PM PDT 24
Peak memory 242036 kb
Host smart-343d4571-7a1c-422b-b2e1-750dda9790cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311463546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.311463546
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.3102729524
Short name T1078
Test name
Test status
Simulation time 1745903634 ps
CPU time 6.14 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:47 PM PDT 24
Peak memory 241900 kb
Host smart-048e920d-e0d4-4f24-acde-8ab6b1494ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102729524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3102729524
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2067345648
Short name T874
Test name
Test status
Simulation time 252793606 ps
CPU time 3.94 seconds
Started Jun 29 07:28:39 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 242204 kb
Host smart-94825d65-50cb-445e-9c6a-6aec650f344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067345648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2067345648
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.4156890439
Short name T463
Test name
Test status
Simulation time 728024871 ps
CPU time 16.5 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 241824 kb
Host smart-3161656f-aa25-4087-a8c5-050d7bb0ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156890439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.4156890439
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.4280029633
Short name T1077
Test name
Test status
Simulation time 294320432 ps
CPU time 5.05 seconds
Started Jun 29 07:28:38 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 242008 kb
Host smart-dc3392ee-f4e9-4b08-9a67-56de1b450977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280029633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.4280029633
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.4018033086
Short name T12
Test name
Test status
Simulation time 997371260 ps
CPU time 2.66 seconds
Started Jun 29 07:28:40 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 241880 kb
Host smart-8d5645bb-853d-481b-a712-8fff73eb3ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018033086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.4018033086
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.723286100
Short name T923
Test name
Test status
Simulation time 131075545 ps
CPU time 5.49 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 241916 kb
Host smart-6d593029-8af0-4666-9dbf-ca5fb07b6930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723286100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.723286100
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.2888656031
Short name T512
Test name
Test status
Simulation time 2443950228 ps
CPU time 28.1 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242444 kb
Host smart-87978c1d-3afb-4511-8541-e7916c679def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888656031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2888656031
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3673918915
Short name T516
Test name
Test status
Simulation time 217955544 ps
CPU time 4.46 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242184 kb
Host smart-4f6538da-b5ab-4cfb-a1fe-6536925dab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673918915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3673918915
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.3413390307
Short name T159
Test name
Test status
Simulation time 395390054 ps
CPU time 5.84 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:56 PM PDT 24
Peak memory 242216 kb
Host smart-23d9bad3-343d-452e-9857-5997fd32c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413390307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3413390307
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.2700603478
Short name T38
Test name
Test status
Simulation time 152076993 ps
CPU time 5.09 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 242076 kb
Host smart-68b5d11d-2168-40ba-b7d9-c629e8de4236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700603478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2700603478
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.2350793649
Short name T355
Test name
Test status
Simulation time 371701789 ps
CPU time 4.8 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 241900 kb
Host smart-1db54e17-22ff-46bc-9c51-46ae3a898a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350793649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2350793649
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1627977054
Short name T848
Test name
Test status
Simulation time 561326832 ps
CPU time 4.41 seconds
Started Jun 29 07:28:48 PM PDT 24
Finished Jun 29 07:28:53 PM PDT 24
Peak memory 242072 kb
Host smart-4b48287b-bf29-4ceb-87e3-3b2890e815ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627977054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1627977054
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2185069373
Short name T357
Test name
Test status
Simulation time 2726126761 ps
CPU time 12.35 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 242256 kb
Host smart-9ed0a7de-ee69-44a5-b8ba-b8679f315790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185069373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2185069373
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.3603598229
Short name T791
Test name
Test status
Simulation time 206207665 ps
CPU time 4.33 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 242016 kb
Host smart-c9006a31-bb21-45eb-8a53-ec11fbd22ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603598229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3603598229
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.4106889299
Short name T220
Test name
Test status
Simulation time 155316961 ps
CPU time 4.23 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:50 PM PDT 24
Peak memory 241728 kb
Host smart-780e1822-9573-4685-b5ad-8de66aaff25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106889299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.4106889299
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2100701536
Short name T529
Test name
Test status
Simulation time 160430048 ps
CPU time 2.47 seconds
Started Jun 29 07:26:00 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 240232 kb
Host smart-ffc64c29-1a44-4512-8e43-3014852ad147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100701536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2100701536
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.866587577
Short name T805
Test name
Test status
Simulation time 291047707 ps
CPU time 17.58 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 248684 kb
Host smart-14bdc23f-cfa6-4ed4-8914-9362779066b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866587577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.866587577
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.2499868072
Short name T686
Test name
Test status
Simulation time 743277929 ps
CPU time 19.19 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:18 PM PDT 24
Peak memory 242532 kb
Host smart-60038e0c-a7d1-49de-82c7-9053321f5838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499868072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2499868072
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1877490422
Short name T500
Test name
Test status
Simulation time 119857543 ps
CPU time 3.21 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 241968 kb
Host smart-62272df4-ac7e-4d05-b820-b0b69b484771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877490422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1877490422
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.3892070846
Short name T186
Test name
Test status
Simulation time 353361553 ps
CPU time 11.17 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 248776 kb
Host smart-9bfea511-ad1e-4c2f-be99-6d341606b1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892070846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3892070846
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.380986662
Short name T513
Test name
Test status
Simulation time 375266004 ps
CPU time 12.63 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:12 PM PDT 24
Peak memory 248808 kb
Host smart-086aefe7-90e9-4201-9e9b-028849735b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380986662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.380986662
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.228484297
Short name T137
Test name
Test status
Simulation time 276418612 ps
CPU time 5.41 seconds
Started Jun 29 07:25:55 PM PDT 24
Finished Jun 29 07:26:01 PM PDT 24
Peak memory 241956 kb
Host smart-d2f28fa7-cd52-4359-873b-429a9315701e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228484297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.228484297
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3078820331
Short name T1188
Test name
Test status
Simulation time 659432483 ps
CPU time 15.26 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 242112 kb
Host smart-2c2f9409-71c2-4a78-b024-b29ca8f8f85d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3078820331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3078820331
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.1767673241
Short name T1185
Test name
Test status
Simulation time 222977399 ps
CPU time 6.58 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 248748 kb
Host smart-13e5c688-eebf-46d5-a741-9f5004b80326
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767673241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.1767673241
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3694111620
Short name T1071
Test name
Test status
Simulation time 682095542 ps
CPU time 5.79 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:06 PM PDT 24
Peak memory 242320 kb
Host smart-ec146683-0634-4477-a43d-0c8b3288d085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694111620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3694111620
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.1131544590
Short name T397
Test name
Test status
Simulation time 48078757586 ps
CPU time 130.72 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:28:11 PM PDT 24
Peak memory 253268 kb
Host smart-7ddae4e5-dd22-49d4-a6d7-8204690090cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131544590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.1131544590
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2216105527
Short name T348
Test name
Test status
Simulation time 227477256282 ps
CPU time 1154.21 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:45:14 PM PDT 24
Peak memory 262708 kb
Host smart-9884f498-915e-4aa3-9063-ef3eb9119e54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216105527 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.2216105527
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.149912823
Short name T1040
Test name
Test status
Simulation time 369002901 ps
CPU time 4.97 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 241932 kb
Host smart-949041a9-dcc0-4cad-8eb7-4d9f3f6ca28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149912823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.149912823
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.277429488
Short name T59
Test name
Test status
Simulation time 124116356 ps
CPU time 4.33 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 241924 kb
Host smart-8e33ee26-10c0-4954-ab58-153edeb69f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277429488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.277429488
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3556635915
Short name T1034
Test name
Test status
Simulation time 1131369333 ps
CPU time 8.55 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242124 kb
Host smart-357c1f8c-6ea5-4a65-b47e-e53d6da77656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556635915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3556635915
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.3290751207
Short name T179
Test name
Test status
Simulation time 420154191 ps
CPU time 3.46 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:50 PM PDT 24
Peak memory 242364 kb
Host smart-22fd8d18-410c-43f1-a9f9-5376806721c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290751207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3290751207
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.739633683
Short name T300
Test name
Test status
Simulation time 107489215 ps
CPU time 4.32 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:28:53 PM PDT 24
Peak memory 242296 kb
Host smart-f633984d-261d-456a-ac8e-7d07e28857ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739633683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.739633683
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.762254766
Short name T587
Test name
Test status
Simulation time 434551337 ps
CPU time 4.95 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 241956 kb
Host smart-fdf58bc5-575c-4f32-9503-7e1b4f0b1663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762254766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.762254766
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.2636715370
Short name T497
Test name
Test status
Simulation time 409439017 ps
CPU time 5.38 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 242096 kb
Host smart-c222ab85-5bf8-4fe4-a949-9674d5f1dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636715370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.2636715370
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2196926442
Short name T89
Test name
Test status
Simulation time 134781880 ps
CPU time 4.57 seconds
Started Jun 29 07:28:54 PM PDT 24
Finished Jun 29 07:28:59 PM PDT 24
Peak memory 241940 kb
Host smart-098354df-b0f8-4ab9-a3c7-256f0f3b6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196926442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2196926442
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.3956478661
Short name T101
Test name
Test status
Simulation time 3887225210 ps
CPU time 9.73 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:05 PM PDT 24
Peak memory 241952 kb
Host smart-b3618835-2fd1-443a-87f3-a2286f9904d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956478661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.3956478661
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.1264775947
Short name T1020
Test name
Test status
Simulation time 689187345 ps
CPU time 4.18 seconds
Started Jun 29 07:28:48 PM PDT 24
Finished Jun 29 07:28:53 PM PDT 24
Peak memory 242164 kb
Host smart-69a20f6e-d02d-45e0-8646-8b36648b1ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264775947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1264775947
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1842915424
Short name T486
Test name
Test status
Simulation time 717607837 ps
CPU time 8.69 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:29:03 PM PDT 24
Peak memory 241892 kb
Host smart-656353de-290a-4db7-b025-448c24454c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842915424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1842915424
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.2507695316
Short name T688
Test name
Test status
Simulation time 388291526 ps
CPU time 4.76 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:01 PM PDT 24
Peak memory 242064 kb
Host smart-c437e6b6-ddaf-48e1-818a-59f327fdcd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507695316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2507695316
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3883555453
Short name T665
Test name
Test status
Simulation time 211633080 ps
CPU time 12.13 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:59 PM PDT 24
Peak memory 241900 kb
Host smart-c562ad01-c9d6-44e7-ac98-e73260df2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883555453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3883555453
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.2818322967
Short name T532
Test name
Test status
Simulation time 275849099 ps
CPU time 4.12 seconds
Started Jun 29 07:28:48 PM PDT 24
Finished Jun 29 07:28:53 PM PDT 24
Peak memory 241996 kb
Host smart-6baece9f-17b1-4983-860e-6afa852a002f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818322967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2818322967
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.306247956
Short name T728
Test name
Test status
Simulation time 96986230 ps
CPU time 4.12 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:54 PM PDT 24
Peak memory 242236 kb
Host smart-01995fc9-39ae-4e75-9360-90e98d501d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306247956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.306247956
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.361432708
Short name T645
Test name
Test status
Simulation time 1949326054 ps
CPU time 4.82 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 241876 kb
Host smart-e57168a0-a3a9-47f7-aab9-b35de1814eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361432708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.361432708
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3900901697
Short name T1008
Test name
Test status
Simulation time 980726621 ps
CPU time 15.18 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:29:05 PM PDT 24
Peak memory 242272 kb
Host smart-2f8b0ed3-93ff-4331-bc9f-d47cfb4c670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900901697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3900901697
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1565464617
Short name T863
Test name
Test status
Simulation time 200180726 ps
CPU time 4.84 seconds
Started Jun 29 07:28:45 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 242136 kb
Host smart-315c5913-9b66-485e-bdb8-368fea9b080e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565464617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1565464617
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.620475944
Short name T217
Test name
Test status
Simulation time 1677787267 ps
CPU time 5.49 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 241876 kb
Host smart-ba8f1141-df86-4530-9e41-e2049c35f4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620475944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.620475944
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.4013388977
Short name T666
Test name
Test status
Simulation time 1797064216 ps
CPU time 5.68 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242068 kb
Host smart-05f40004-1b98-4afc-8c9d-1c814ec6d6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013388977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.4013388977
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1414768765
Short name T471
Test name
Test status
Simulation time 344455025 ps
CPU time 10.02 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:57 PM PDT 24
Peak memory 241820 kb
Host smart-8000d03c-9d80-4dcf-bc68-111687fde6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414768765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1414768765
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.2987582409
Short name T1011
Test name
Test status
Simulation time 189320470 ps
CPU time 3.36 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:05 PM PDT 24
Peak memory 240132 kb
Host smart-2657a651-fc44-47ed-b021-13a16be7adc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987582409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2987582409
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.1783069659
Short name T35
Test name
Test status
Simulation time 878454811 ps
CPU time 19.82 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:18 PM PDT 24
Peak memory 242332 kb
Host smart-9b50c749-8329-45bc-b4da-f7a716913440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783069659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1783069659
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.966061033
Short name T692
Test name
Test status
Simulation time 331072103 ps
CPU time 19.83 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:18 PM PDT 24
Peak memory 242340 kb
Host smart-cad3482d-9d60-4d45-84fe-51255657b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966061033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.966061033
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.4223903639
Short name T1146
Test name
Test status
Simulation time 1645856040 ps
CPU time 31.48 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:35 PM PDT 24
Peak memory 242504 kb
Host smart-109b2cd6-5016-42e5-bce4-24199d1c0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223903639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.4223903639
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.186777904
Short name T221
Test name
Test status
Simulation time 2116137839 ps
CPU time 26.55 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:25 PM PDT 24
Peak memory 248792 kb
Host smart-649232a2-f858-4225-a58a-76ea56059bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186777904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.186777904
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3381754227
Short name T1075
Test name
Test status
Simulation time 1854132069 ps
CPU time 20.78 seconds
Started Jun 29 07:25:57 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 242168 kb
Host smart-fe4ffb52-de61-4c60-812b-d972972074a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381754227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3381754227
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.234523476
Short name T409
Test name
Test status
Simulation time 626728287 ps
CPU time 12.36 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:12 PM PDT 24
Peak memory 241776 kb
Host smart-69284484-fae1-4671-9127-6a0bd2c973b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234523476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.234523476
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2307836553
Short name T703
Test name
Test status
Simulation time 387504858 ps
CPU time 11.5 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:26:14 PM PDT 24
Peak memory 242072 kb
Host smart-d7d1ed84-8aef-4c67-87c7-1e68ca86e05d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2307836553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2307836553
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.564107019
Short name T866
Test name
Test status
Simulation time 233019863 ps
CPU time 4.89 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:26:01 PM PDT 24
Peak memory 241772 kb
Host smart-c274f434-c64b-468a-953e-786b0f983968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564107019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.564107019
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.2770338261
Short name T970
Test name
Test status
Simulation time 246527831 ps
CPU time 8.77 seconds
Started Jun 29 07:25:59 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 242468 kb
Host smart-bebc8757-c900-4618-abdc-72d003a79d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770338261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2770338261
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4096464138
Short name T576
Test name
Test status
Simulation time 15573454269 ps
CPU time 69.53 seconds
Started Jun 29 07:26:01 PM PDT 24
Finished Jun 29 07:27:12 PM PDT 24
Peak memory 245412 kb
Host smart-f8821db5-c0c3-4c8f-bf4c-02e9f4ca27b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096464138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4096464138
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3852784202
Short name T705
Test name
Test status
Simulation time 113322216356 ps
CPU time 1164.99 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:45:25 PM PDT 24
Peak memory 257228 kb
Host smart-f46157b5-1332-433b-ab6b-50dfd7b3b7e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852784202 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.3852784202
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.345474409
Short name T496
Test name
Test status
Simulation time 3919758903 ps
CPU time 23.6 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:27 PM PDT 24
Peak memory 248820 kb
Host smart-ff16992b-29a4-450f-8d2e-0e8a47a88d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345474409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.345474409
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.848364005
Short name T1112
Test name
Test status
Simulation time 321449686 ps
CPU time 4.52 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 241940 kb
Host smart-b90de292-6c21-4d77-bc2a-c55996946b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848364005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.848364005
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.231617983
Short name T1176
Test name
Test status
Simulation time 290621640 ps
CPU time 6.35 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:54 PM PDT 24
Peak memory 241712 kb
Host smart-896e5386-f2ea-41ca-af0f-cb4b757e804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231617983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.231617983
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.2929567440
Short name T82
Test name
Test status
Simulation time 358047034 ps
CPU time 4.82 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242436 kb
Host smart-69f7319b-ab76-4ba8-bc90-161154d4dfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929567440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2929567440
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3681242005
Short name T78
Test name
Test status
Simulation time 682503951 ps
CPU time 5.18 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:28:53 PM PDT 24
Peak memory 241736 kb
Host smart-c2306e89-2de1-4531-90f9-dbc2e3958842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681242005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3681242005
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.2247120679
Short name T852
Test name
Test status
Simulation time 2409685892 ps
CPU time 4.97 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242460 kb
Host smart-e5d00012-7fce-41a6-84ea-d22043054b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247120679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2247120679
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.4271222764
Short name T985
Test name
Test status
Simulation time 768329450 ps
CPU time 11.07 seconds
Started Jun 29 07:28:50 PM PDT 24
Finished Jun 29 07:29:02 PM PDT 24
Peak memory 241884 kb
Host smart-a74b881b-5aa6-45d6-9cb1-58b4ac82149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271222764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.4271222764
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.2023321533
Short name T637
Test name
Test status
Simulation time 2183060515 ps
CPU time 5.1 seconds
Started Jun 29 07:28:49 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 242184 kb
Host smart-5d28a189-ccd6-47cc-b3e1-63a8b4c53523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023321533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2023321533
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1832413088
Short name T900
Test name
Test status
Simulation time 1217352583 ps
CPU time 17.36 seconds
Started Jun 29 07:28:50 PM PDT 24
Finished Jun 29 07:29:08 PM PDT 24
Peak memory 242376 kb
Host smart-20cab725-a6cb-46ab-b6b2-e2ac9bf27564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832413088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1832413088
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.2949713714
Short name T93
Test name
Test status
Simulation time 107038691 ps
CPU time 3.2 seconds
Started Jun 29 07:28:48 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242492 kb
Host smart-cf96ab2e-cd58-4320-bf3e-2f23a0652d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949713714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.2949713714
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.759021135
Short name T480
Test name
Test status
Simulation time 332425318 ps
CPU time 3.87 seconds
Started Jun 29 07:28:47 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 242076 kb
Host smart-c0d05414-4295-4b63-9d7e-54784c5d32db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759021135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.759021135
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.3945157405
Short name T493
Test name
Test status
Simulation time 370241180 ps
CPU time 8.38 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:55 PM PDT 24
Peak memory 242068 kb
Host smart-afb9df8b-dc89-44bb-aecb-cb7554c71a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945157405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.3945157405
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.1554938170
Short name T899
Test name
Test status
Simulation time 275344003 ps
CPU time 4.01 seconds
Started Jun 29 07:28:46 PM PDT 24
Finished Jun 29 07:28:51 PM PDT 24
Peak memory 242128 kb
Host smart-38485b30-507a-4900-a727-1dc933ffea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554938170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1554938170
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.770747383
Short name T389
Test name
Test status
Simulation time 638799484 ps
CPU time 10.95 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:15 PM PDT 24
Peak memory 242368 kb
Host smart-838f780e-e2fa-4b16-a3ad-46ca797ca751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770747383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.770747383
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.667534436
Short name T886
Test name
Test status
Simulation time 227686129 ps
CPU time 3.52 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:06 PM PDT 24
Peak memory 242048 kb
Host smart-6b788b5c-0d8c-4967-be01-e6c58daa4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667534436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.667534436
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.187511718
Short name T619
Test name
Test status
Simulation time 956056318 ps
CPU time 22.52 seconds
Started Jun 29 07:28:56 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 241960 kb
Host smart-4eb2da6d-2b8d-4588-852e-b12d1c782f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187511718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.187511718
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.57574798
Short name T795
Test name
Test status
Simulation time 192446089 ps
CPU time 3.97 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242080 kb
Host smart-444080a7-38ae-4317-9df0-31d387abf1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57574798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.57574798
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.2219034625
Short name T1140
Test name
Test status
Simulation time 134431551 ps
CPU time 6.46 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 242296 kb
Host smart-3ee77a16-ae2d-46e9-8a47-83e8fd0a4f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219034625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2219034625
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.3185501612
Short name T749
Test name
Test status
Simulation time 191335506 ps
CPU time 1.96 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 07:26:08 PM PDT 24
Peak memory 240184 kb
Host smart-81faac0c-03c7-4046-ad05-73a71e6bc272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185501612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.3185501612
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.2748517477
Short name T559
Test name
Test status
Simulation time 189907336 ps
CPU time 4.25 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 242256 kb
Host smart-4544ef5d-7905-48e8-9a31-4b0b998deaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748517477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2748517477
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.1540475853
Short name T804
Test name
Test status
Simulation time 2518653725 ps
CPU time 22.2 seconds
Started Jun 29 07:26:06 PM PDT 24
Finished Jun 29 07:26:30 PM PDT 24
Peak memory 242120 kb
Host smart-9cdcf8f7-5457-49e8-9f74-08dcf4a64b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540475853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1540475853
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.1655514517
Short name T956
Test name
Test status
Simulation time 675335039 ps
CPU time 12.72 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 248812 kb
Host smart-ca757c28-edca-409b-8865-6fee4549d55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655514517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.1655514517
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.4279538032
Short name T1049
Test name
Test status
Simulation time 1152582596 ps
CPU time 21.61 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 07:26:28 PM PDT 24
Peak memory 241908 kb
Host smart-5ae5b8af-24d5-4f32-a654-1008f04f2cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279538032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.4279538032
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.2349703533
Short name T485
Test name
Test status
Simulation time 490920785 ps
CPU time 6.35 seconds
Started Jun 29 07:25:56 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 241924 kb
Host smart-70b214c1-0f87-4950-b148-3b8b6ff19670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349703533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.2349703533
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3536794625
Short name T834
Test name
Test status
Simulation time 4137088387 ps
CPU time 10.92 seconds
Started Jun 29 07:25:58 PM PDT 24
Finished Jun 29 07:26:10 PM PDT 24
Peak memory 242172 kb
Host smart-940370a3-da0f-48ea-8183-0db36ce8e3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536794625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3536794625
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2948069645
Short name T194
Test name
Test status
Simulation time 2964315588 ps
CPU time 7.4 seconds
Started Jun 29 07:26:07 PM PDT 24
Finished Jun 29 07:26:16 PM PDT 24
Peak memory 242240 kb
Host smart-47e9e5b6-5af9-4e41-af1e-db6bc8bddc34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948069645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2948069645
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3222110363
Short name T283
Test name
Test status
Simulation time 126316355 ps
CPU time 4.27 seconds
Started Jun 29 07:26:02 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 242268 kb
Host smart-1a399b7a-9e98-498f-91f3-827d5c321509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222110363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3222110363
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2091705779
Short name T351
Test name
Test status
Simulation time 1256503146717 ps
CPU time 2335.01 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 08:05:02 PM PDT 24
Peak memory 317724 kb
Host smart-46f4a900-1435-431c-b71c-c1d2e5cd2845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091705779 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2091705779
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.2069222680
Short name T699
Test name
Test status
Simulation time 1527651418 ps
CPU time 28.9 seconds
Started Jun 29 07:26:06 PM PDT 24
Finished Jun 29 07:26:37 PM PDT 24
Peak memory 242164 kb
Host smart-5527a991-ad68-4ed9-85dd-15f25a809098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069222680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.2069222680
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.1060555697
Short name T875
Test name
Test status
Simulation time 281346582 ps
CPU time 7.9 seconds
Started Jun 29 07:28:54 PM PDT 24
Finished Jun 29 07:29:03 PM PDT 24
Peak memory 241916 kb
Host smart-b3bd4946-83e1-46ea-9b87-e9cafa479556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060555697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1060555697
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3091758891
Short name T743
Test name
Test status
Simulation time 444132214 ps
CPU time 5.11 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 241896 kb
Host smart-ac73e52d-0f1e-4aff-9c05-2478c6318ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091758891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3091758891
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2745898712
Short name T162
Test name
Test status
Simulation time 495363614 ps
CPU time 15.39 seconds
Started Jun 29 07:28:55 PM PDT 24
Finished Jun 29 07:29:11 PM PDT 24
Peak memory 241948 kb
Host smart-08494cd9-6758-47c2-ab95-47d034340e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745898712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2745898712
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.1690038307
Short name T586
Test name
Test status
Simulation time 320264464 ps
CPU time 4.05 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242364 kb
Host smart-af8c94a2-3d9a-4ed5-9885-438f3b41e91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690038307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1690038307
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1061183198
Short name T546
Test name
Test status
Simulation time 249388983 ps
CPU time 5.94 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:59 PM PDT 24
Peak memory 241780 kb
Host smart-6b06c281-5edf-403f-a5f9-4cebab88ee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061183198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1061183198
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2642492938
Short name T669
Test name
Test status
Simulation time 199011214 ps
CPU time 3.7 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242164 kb
Host smart-1959a7ae-61ca-45eb-90f5-5af84921efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642492938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2642492938
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2769542971
Short name T643
Test name
Test status
Simulation time 321408687 ps
CPU time 4.43 seconds
Started Jun 29 07:28:54 PM PDT 24
Finished Jun 29 07:28:59 PM PDT 24
Peak memory 241760 kb
Host smart-609a0a6d-266e-4c45-a3f3-09191f06cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769542971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2769542971
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.2838116015
Short name T1080
Test name
Test status
Simulation time 535526852 ps
CPU time 3.97 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242152 kb
Host smart-942885d4-8a73-4ad4-a7e3-9cff38ce1d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838116015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.2838116015
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1008597232
Short name T260
Test name
Test status
Simulation time 4223910604 ps
CPU time 24.04 seconds
Started Jun 29 07:28:51 PM PDT 24
Finished Jun 29 07:29:15 PM PDT 24
Peak memory 242276 kb
Host smart-add16c84-4159-4cd9-829c-1c4da3bc7b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008597232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1008597232
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1704930272
Short name T690
Test name
Test status
Simulation time 515322812 ps
CPU time 4.11 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:07 PM PDT 24
Peak memory 242400 kb
Host smart-86b0a512-f16c-4caa-9b0e-813594967c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704930272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1704930272
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.2560476705
Short name T718
Test name
Test status
Simulation time 201206368 ps
CPU time 5.33 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 241832 kb
Host smart-aeea95bb-aca1-4cfe-a1a5-d8a0d327b7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560476705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2560476705
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.1299283336
Short name T797
Test name
Test status
Simulation time 301342275 ps
CPU time 9.09 seconds
Started Jun 29 07:28:54 PM PDT 24
Finished Jun 29 07:29:04 PM PDT 24
Peak memory 242180 kb
Host smart-174b577d-473b-45f3-be5f-f81a7346c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299283336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.1299283336
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2718745027
Short name T1015
Test name
Test status
Simulation time 348512880 ps
CPU time 3.58 seconds
Started Jun 29 07:29:00 PM PDT 24
Finished Jun 29 07:29:05 PM PDT 24
Peak memory 242088 kb
Host smart-2663f1de-55ff-4217-ab97-10a07da1466a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718745027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2718745027
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.728242024
Short name T944
Test name
Test status
Simulation time 282397698 ps
CPU time 4.56 seconds
Started Jun 29 07:28:54 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 241948 kb
Host smart-b81c151c-0c47-4d2e-a15d-0248b60af72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728242024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.728242024
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3857590258
Short name T741
Test name
Test status
Simulation time 384823742 ps
CPU time 4.19 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:08 PM PDT 24
Peak memory 241916 kb
Host smart-94f1f1c5-465b-4824-844f-1d9762ffcbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857590258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3857590258
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.48144370
Short name T158
Test name
Test status
Simulation time 293045865 ps
CPU time 3.26 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 241960 kb
Host smart-9f7e7296-521f-48da-a771-0fd744ff5b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48144370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.48144370
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.401346711
Short name T65
Test name
Test status
Simulation time 344028225 ps
CPU time 4.84 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242080 kb
Host smart-a6a8406c-a78f-481b-91ea-2e19ab1e52cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401346711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.401346711
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.4174184556
Short name T547
Test name
Test status
Simulation time 8567849951 ps
CPU time 26.04 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 242028 kb
Host smart-3b271267-101e-44f6-9835-f6d5d572737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174184556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.4174184556
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.3769773385
Short name T1035
Test name
Test status
Simulation time 172292698 ps
CPU time 1.71 seconds
Started Jun 29 07:26:14 PM PDT 24
Finished Jun 29 07:26:16 PM PDT 24
Peak memory 240480 kb
Host smart-90b50304-3796-4f74-b22b-78411529012c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769773385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.3769773385
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.92712256
Short name T195
Test name
Test status
Simulation time 4020463734 ps
CPU time 17.44 seconds
Started Jun 29 07:26:09 PM PDT 24
Finished Jun 29 07:26:27 PM PDT 24
Peak memory 242188 kb
Host smart-ea1ca9a0-5eca-401a-b1e7-7eab5a188a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92712256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.92712256
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.3672074718
Short name T712
Test name
Test status
Simulation time 1323978962 ps
CPU time 8.2 seconds
Started Jun 29 07:26:06 PM PDT 24
Finished Jun 29 07:26:16 PM PDT 24
Peak memory 242332 kb
Host smart-9582bf1b-28de-4aba-9b6d-4ce8d2e09862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672074718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.3672074718
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.399880553
Short name T684
Test name
Test status
Simulation time 487506319 ps
CPU time 3.82 seconds
Started Jun 29 07:26:06 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 242424 kb
Host smart-22610bbd-e446-4576-9898-db0bb2e03cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399880553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.399880553
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.3536800568
Short name T169
Test name
Test status
Simulation time 3914939208 ps
CPU time 46.3 seconds
Started Jun 29 07:26:11 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 248812 kb
Host smart-63676fa4-a155-46bf-830e-398b9f5df6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536800568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3536800568
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.80836652
Short name T1086
Test name
Test status
Simulation time 707161952 ps
CPU time 15.75 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:29 PM PDT 24
Peak memory 242304 kb
Host smart-48291406-02d3-4d5a-9d15-757f172dcf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80836652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.80836652
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.3068183546
Short name T476
Test name
Test status
Simulation time 528108926 ps
CPU time 7.19 seconds
Started Jun 29 07:26:08 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 242412 kb
Host smart-cceb19ce-1262-47a7-ba57-d055c65db481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068183546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.3068183546
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.625480203
Short name T394
Test name
Test status
Simulation time 545248553 ps
CPU time 16.69 seconds
Started Jun 29 07:26:08 PM PDT 24
Finished Jun 29 07:26:26 PM PDT 24
Peak memory 242356 kb
Host smart-9aff29b3-bf54-4404-b20f-1043521da616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625480203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.625480203
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.1051959599
Short name T545
Test name
Test status
Simulation time 111125492 ps
CPU time 4.21 seconds
Started Jun 29 07:26:12 PM PDT 24
Finished Jun 29 07:26:17 PM PDT 24
Peak memory 242144 kb
Host smart-554b623b-08c4-450f-b5fc-d9c3951a8641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051959599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1051959599
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.837036078
Short name T431
Test name
Test status
Simulation time 320431550 ps
CPU time 6.66 seconds
Started Jun 29 07:26:05 PM PDT 24
Finished Jun 29 07:26:13 PM PDT 24
Peak memory 242112 kb
Host smart-f6487fd7-36a9-465d-ae76-6c395d5787bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837036078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.837036078
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.296892407
Short name T762
Test name
Test status
Simulation time 117825060938 ps
CPU time 1106.72 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:44:41 PM PDT 24
Peak memory 294756 kb
Host smart-43a5d669-dc31-49ef-91e8-16f8a4e6ecf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296892407 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.296892407
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.925636202
Short name T616
Test name
Test status
Simulation time 4419896137 ps
CPU time 49.67 seconds
Started Jun 29 07:26:15 PM PDT 24
Finished Jun 29 07:27:06 PM PDT 24
Peak memory 242644 kb
Host smart-e83fdc1c-2122-49d5-95dc-1433e94c1bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925636202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.925636202
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.3043325104
Short name T99
Test name
Test status
Simulation time 408479846 ps
CPU time 4.2 seconds
Started Jun 29 07:28:53 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 242056 kb
Host smart-e7520a74-c962-4737-8ec9-23377b2e3179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043325104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3043325104
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3653324438
Short name T578
Test name
Test status
Simulation time 162429670 ps
CPU time 2.72 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:56 PM PDT 24
Peak memory 241964 kb
Host smart-d3387d02-c808-49a7-8641-9fa930f6843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653324438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3653324438
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3388519419
Short name T37
Test name
Test status
Simulation time 1893315515 ps
CPU time 3.93 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:06 PM PDT 24
Peak memory 242432 kb
Host smart-9a4ecaf7-d61a-48d9-ac6e-cbfae9940479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388519419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3388519419
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.4066040443
Short name T451
Test name
Test status
Simulation time 417106839 ps
CPU time 5.96 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 241864 kb
Host smart-27bb72d1-b708-4478-965d-59ca4eeb6a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066040443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.4066040443
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.2214661778
Short name T1110
Test name
Test status
Simulation time 2015642074 ps
CPU time 3.24 seconds
Started Jun 29 07:28:52 PM PDT 24
Finished Jun 29 07:28:56 PM PDT 24
Peak memory 242148 kb
Host smart-28c3338d-17b5-400a-a508-e7c7650f23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214661778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2214661778
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.4245500554
Short name T143
Test name
Test status
Simulation time 509301987 ps
CPU time 3.88 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 242036 kb
Host smart-7b623289-a844-434f-863c-9b71eea5c0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245500554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.4245500554
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1222462918
Short name T390
Test name
Test status
Simulation time 1689120655 ps
CPU time 5.79 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:12 PM PDT 24
Peak memory 241884 kb
Host smart-570084f4-1f87-42e4-8603-c655f719a23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222462918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1222462918
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.3298131162
Short name T608
Test name
Test status
Simulation time 2023642537 ps
CPU time 5.64 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 241824 kb
Host smart-39ba4a4a-5bc3-4ad0-9ccb-3a1e262b3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298131162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.3298131162
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2815560904
Short name T593
Test name
Test status
Simulation time 670537899 ps
CPU time 8.43 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:12 PM PDT 24
Peak memory 241884 kb
Host smart-c32fe916-0ccc-4e95-939d-cd0a07c64da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815560904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2815560904
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.1421340385
Short name T568
Test name
Test status
Simulation time 236931093 ps
CPU time 4.79 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242080 kb
Host smart-be142d2f-0743-495f-8c84-25e1a607fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421340385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.1421340385
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3963984242
Short name T433
Test name
Test status
Simulation time 2656121904 ps
CPU time 6.99 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:12 PM PDT 24
Peak memory 241956 kb
Host smart-5a655434-f9b3-49a4-a92e-de9c7f9a5c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963984242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3963984242
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.3323737080
Short name T420
Test name
Test status
Simulation time 170149838 ps
CPU time 5.29 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 241924 kb
Host smart-b4c8a13b-8d61-4e60-8936-5efc39f11c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323737080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.3323737080
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.202824406
Short name T418
Test name
Test status
Simulation time 136494280 ps
CPU time 6.01 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:11 PM PDT 24
Peak memory 242364 kb
Host smart-bef5f1fa-00be-49ec-baf8-f47a60d2edbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202824406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.202824406
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.386223587
Short name T1017
Test name
Test status
Simulation time 154829569 ps
CPU time 4.91 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:11 PM PDT 24
Peak memory 241972 kb
Host smart-7ca1170c-6de8-4bbe-aa5c-578d84f74ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386223587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.386223587
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.1078610623
Short name T259
Test name
Test status
Simulation time 522885579 ps
CPU time 13.77 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241872 kb
Host smart-d07c90df-d024-4425-be9d-c4204959bd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078610623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1078610623
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2936062228
Short name T934
Test name
Test status
Simulation time 106151166 ps
CPU time 3.52 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242152 kb
Host smart-4d36c323-a607-47f2-8320-28fcf7275b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936062228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2936062228
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.729054244
Short name T326
Test name
Test status
Simulation time 358897627 ps
CPU time 7.69 seconds
Started Jun 29 07:29:10 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242152 kb
Host smart-61124a42-fa53-4012-b4f2-b3999c374f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729054244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.729054244
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2384188845
Short name T953
Test name
Test status
Simulation time 356263801 ps
CPU time 3.39 seconds
Started Jun 29 07:29:01 PM PDT 24
Finished Jun 29 07:29:07 PM PDT 24
Peak memory 242420 kb
Host smart-334daa13-9973-4fca-87fc-130bf136429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384188845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2384188845
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.666917812
Short name T503
Test name
Test status
Simulation time 110519489 ps
CPU time 3.82 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 241896 kb
Host smart-4e7cd8c2-6b0e-45e6-ad60-1042e6a66342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666917812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.666917812
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3966592080
Short name T417
Test name
Test status
Simulation time 76998508 ps
CPU time 1.96 seconds
Started Jun 29 07:26:11 PM PDT 24
Finished Jun 29 07:26:14 PM PDT 24
Peak memory 240256 kb
Host smart-90515865-34f7-4311-a89c-85775074d4d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966592080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3966592080
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1904488113
Short name T1065
Test name
Test status
Simulation time 7537961291 ps
CPU time 26.16 seconds
Started Jun 29 07:26:14 PM PDT 24
Finished Jun 29 07:26:41 PM PDT 24
Peak memory 243164 kb
Host smart-29877c29-852f-4f49-b3b8-743df6fcbd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904488113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1904488113
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.3564058076
Short name T1081
Test name
Test status
Simulation time 773175615 ps
CPU time 10.1 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:24 PM PDT 24
Peak memory 242088 kb
Host smart-033044a3-f3cb-44bb-8419-0d37dfeb9518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564058076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.3564058076
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.3414791156
Short name T444
Test name
Test status
Simulation time 14998771935 ps
CPU time 28.18 seconds
Started Jun 29 07:26:15 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 243804 kb
Host smart-5d41c829-8f9d-4604-92fd-ef1da8ddf9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414791156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.3414791156
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.3870619033
Short name T913
Test name
Test status
Simulation time 119844494 ps
CPU time 4.59 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 241916 kb
Host smart-cb5c27b1-4191-4012-a56e-52eb3be2689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870619033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.3870619033
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3957004741
Short name T1119
Test name
Test status
Simulation time 19566403696 ps
CPU time 62 seconds
Started Jun 29 07:26:14 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 248824 kb
Host smart-6fa38eef-da95-40f7-9f3d-72f37feaed3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957004741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3957004741
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.268032661
Short name T772
Test name
Test status
Simulation time 3261849726 ps
CPU time 21.73 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:36 PM PDT 24
Peak memory 242308 kb
Host smart-1fae5cf2-4f8a-4184-a29a-bb334a0035db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268032661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.268032661
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.2140228102
Short name T868
Test name
Test status
Simulation time 314792326 ps
CPU time 8.13 seconds
Started Jun 29 07:26:12 PM PDT 24
Finished Jun 29 07:26:21 PM PDT 24
Peak memory 241964 kb
Host smart-30e92315-cecb-43df-9708-aeed0688baa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140228102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2140228102
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.710217382
Short name T468
Test name
Test status
Simulation time 534735370 ps
CPU time 4.84 seconds
Started Jun 29 07:26:14 PM PDT 24
Finished Jun 29 07:26:20 PM PDT 24
Peak memory 248716 kb
Host smart-40a31919-3453-4909-9b60-678b679ba3cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710217382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.710217382
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.1591288822
Short name T694
Test name
Test status
Simulation time 711975790 ps
CPU time 11.1 seconds
Started Jun 29 07:26:15 PM PDT 24
Finished Jun 29 07:26:27 PM PDT 24
Peak memory 242112 kb
Host smart-50f924c9-b1ea-48d7-954a-7cdee33aef43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591288822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1591288822
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1430719566
Short name T484
Test name
Test status
Simulation time 334714929 ps
CPU time 4.69 seconds
Started Jun 29 07:26:15 PM PDT 24
Finished Jun 29 07:26:21 PM PDT 24
Peak memory 241848 kb
Host smart-5e0381f7-95dc-473c-9b9c-9220dfc7157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430719566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1430719566
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.961644878
Short name T155
Test name
Test status
Simulation time 322229994235 ps
CPU time 1845.64 seconds
Started Jun 29 07:26:14 PM PDT 24
Finished Jun 29 07:57:01 PM PDT 24
Peak memory 613980 kb
Host smart-2246fefb-4209-4a50-8d45-06c5bb5d99df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961644878 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.961644878
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3230685779
Short name T562
Test name
Test status
Simulation time 866542550 ps
CPU time 17.81 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 242328 kb
Host smart-746767a9-127f-4ca9-aee2-01429a6bc956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230685779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3230685779
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.3021911506
Short name T524
Test name
Test status
Simulation time 257785285 ps
CPU time 3.58 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242180 kb
Host smart-5df7e3b9-4e10-4db1-9419-b0f58f5966f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021911506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.3021911506
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3774913369
Short name T995
Test name
Test status
Simulation time 1897211564 ps
CPU time 11.88 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241800 kb
Host smart-f18752bd-c973-497c-ba3f-8f46f44e8902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774913369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3774913369
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.894381350
Short name T785
Test name
Test status
Simulation time 6475225197 ps
CPU time 16.37 seconds
Started Jun 29 07:29:00 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242432 kb
Host smart-1b6fa9db-fd9d-479f-a71c-ac28276c491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894381350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.894381350
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.2937200005
Short name T40
Test name
Test status
Simulation time 272747489 ps
CPU time 3.82 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 241920 kb
Host smart-89f6d1f2-9d1a-4635-a866-8dfdea3476f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937200005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2937200005
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1966731382
Short name T1099
Test name
Test status
Simulation time 904454859 ps
CPU time 11.71 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 242216 kb
Host smart-dd4b8185-03e6-472c-968a-608a327ecb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966731382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1966731382
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.1333244891
Short name T206
Test name
Test status
Simulation time 1582617786 ps
CPU time 4.71 seconds
Started Jun 29 07:29:05 PM PDT 24
Finished Jun 29 07:29:11 PM PDT 24
Peak memory 242376 kb
Host smart-4cb0b62e-7344-4864-8813-3a0c449c82f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333244891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1333244891
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.3380139309
Short name T889
Test name
Test status
Simulation time 106762323 ps
CPU time 4.58 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242116 kb
Host smart-9f41cccb-c6b2-45cd-955f-55051b271578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380139309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.3380139309
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.268290562
Short name T231
Test name
Test status
Simulation time 335292226 ps
CPU time 3.5 seconds
Started Jun 29 07:29:05 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 242080 kb
Host smart-dcdf2c3e-d176-4bd1-9612-1c7b8fd3c9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268290562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.268290562
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.1472196511
Short name T527
Test name
Test status
Simulation time 982004909 ps
CPU time 13.22 seconds
Started Jun 29 07:29:10 PM PDT 24
Finished Jun 29 07:29:24 PM PDT 24
Peak memory 241956 kb
Host smart-d3fcf043-a24e-41df-9bba-1d47282b99d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472196511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1472196511
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.707540109
Short name T651
Test name
Test status
Simulation time 263732160 ps
CPU time 4.09 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242124 kb
Host smart-0a34ebc8-f783-44bb-b293-0868be8727dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707540109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.707540109
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2880410539
Short name T997
Test name
Test status
Simulation time 1149890800 ps
CPU time 16.9 seconds
Started Jun 29 07:29:06 PM PDT 24
Finished Jun 29 07:29:24 PM PDT 24
Peak memory 242364 kb
Host smart-7213dc60-2c80-4e07-8004-da703eb3fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880410539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2880410539
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.302544339
Short name T1091
Test name
Test status
Simulation time 196491551 ps
CPU time 3.65 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242080 kb
Host smart-27fbb53c-fdcb-4484-8588-c40992763d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302544339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.302544339
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2287788292
Short name T472
Test name
Test status
Simulation time 580545039 ps
CPU time 16.33 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 241948 kb
Host smart-2890029b-2681-433f-9536-6ff33dce71b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287788292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2287788292
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3345945835
Short name T178
Test name
Test status
Simulation time 109807142 ps
CPU time 3.65 seconds
Started Jun 29 07:29:03 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 242392 kb
Host smart-12b82970-a767-47be-b8a3-8fdbde2dfe19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345945835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3345945835
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.2906667366
Short name T778
Test name
Test status
Simulation time 494529446 ps
CPU time 14.3 seconds
Started Jun 29 07:29:02 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241888 kb
Host smart-30b0d986-a2ac-4849-9620-f0783d73a5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906667366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2906667366
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.426663634
Short name T932
Test name
Test status
Simulation time 134527071 ps
CPU time 3.58 seconds
Started Jun 29 07:29:05 PM PDT 24
Finished Jun 29 07:29:10 PM PDT 24
Peak memory 242080 kb
Host smart-5846757a-db8e-4af5-a349-7f634a6085d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426663634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.426663634
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.2775826749
Short name T850
Test name
Test status
Simulation time 110279928 ps
CPU time 3.8 seconds
Started Jun 29 07:29:04 PM PDT 24
Finished Jun 29 07:29:09 PM PDT 24
Peak memory 241972 kb
Host smart-b1f941d0-d49e-4b3f-b754-3eaa4a2acb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775826749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2775826749
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2425628263
Short name T588
Test name
Test status
Simulation time 1948145971 ps
CPU time 27.93 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:42 PM PDT 24
Peak memory 241816 kb
Host smart-04658afe-331d-47dd-a89d-50cd86e5a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425628263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2425628263
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2228293106
Short name T538
Test name
Test status
Simulation time 708613558 ps
CPU time 1.87 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:28 PM PDT 24
Peak memory 240548 kb
Host smart-aef5b237-12f3-4c1c-9c8a-f0a2172c7f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228293106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2228293106
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.1482177811
Short name T1094
Test name
Test status
Simulation time 935469723 ps
CPU time 18.68 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:44 PM PDT 24
Peak memory 242360 kb
Host smart-fe0675ed-3c0b-4d27-843e-34ba42cd6dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482177811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1482177811
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3232310511
Short name T782
Test name
Test status
Simulation time 406218496 ps
CPU time 7.88 seconds
Started Jun 29 07:25:28 PM PDT 24
Finished Jun 29 07:25:37 PM PDT 24
Peak memory 242324 kb
Host smart-245eccc4-dc52-46ce-8277-7c162ff6f516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232310511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3232310511
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.2925429204
Short name T966
Test name
Test status
Simulation time 768953780 ps
CPU time 18.97 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:45 PM PDT 24
Peak memory 242132 kb
Host smart-a2096b18-71ea-4956-8d53-8529b4d7f51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925429204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2925429204
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.2738443749
Short name T499
Test name
Test status
Simulation time 1384396713 ps
CPU time 15.78 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:44 PM PDT 24
Peak memory 242628 kb
Host smart-702463ff-1b17-4967-9e75-4732b715d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738443749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2738443749
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.4110001752
Short name T1137
Test name
Test status
Simulation time 140942923 ps
CPU time 4.93 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:25:29 PM PDT 24
Peak memory 241916 kb
Host smart-af2a341b-ce44-4072-b8a6-4c721fb3e7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110001752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.4110001752
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.1439269041
Short name T175
Test name
Test status
Simulation time 1783491773 ps
CPU time 30.58 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:57 PM PDT 24
Peak memory 248460 kb
Host smart-875d8ca4-13c3-4758-abb2-c709b54b154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439269041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.1439269041
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2817247659
Short name T767
Test name
Test status
Simulation time 1019543466 ps
CPU time 25.74 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:52 PM PDT 24
Peak memory 242208 kb
Host smart-6c3860a8-77ad-4ec3-b851-1eccb4a6e374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817247659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2817247659
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.1267705497
Short name T540
Test name
Test status
Simulation time 364106754 ps
CPU time 9.61 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 241884 kb
Host smart-d3cab5b1-f6b3-45c0-8eb9-7935f09edc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267705497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1267705497
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.2309638674
Short name T510
Test name
Test status
Simulation time 402997121 ps
CPU time 7.05 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 248132 kb
Host smart-187a4d5f-99f2-4124-a21b-c1872e754b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309638674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.2309638674
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.2817582078
Short name T26
Test name
Test status
Simulation time 10874348051 ps
CPU time 205.06 seconds
Started Jun 29 07:25:28 PM PDT 24
Finished Jun 29 07:28:54 PM PDT 24
Peak memory 266768 kb
Host smart-d7a4e905-ca65-4fd2-b2d2-326b254a9a0d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817582078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2817582078
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.1220709277
Short name T888
Test name
Test status
Simulation time 183506001 ps
CPU time 5.01 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:30 PM PDT 24
Peak memory 241896 kb
Host smart-53f63de7-8b12-47cf-97fc-138c9c28732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220709277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1220709277
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.1748221960
Short name T107
Test name
Test status
Simulation time 4157220241 ps
CPU time 80.1 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:26:48 PM PDT 24
Peak memory 250972 kb
Host smart-99d343e1-207c-40a2-b1d7-6e0f86e58b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748221960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
1748221960
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3693072568
Short name T864
Test name
Test status
Simulation time 1185074821 ps
CPU time 14.68 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:41 PM PDT 24
Peak memory 242652 kb
Host smart-18d4cda9-f14b-496c-bd13-966963d105b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693072568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3693072568
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.786988691
Short name T440
Test name
Test status
Simulation time 608329224 ps
CPU time 2.08 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:24 PM PDT 24
Peak memory 240156 kb
Host smart-01697603-1784-4449-a3a7-2a6b9653f5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786988691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.786988691
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.2514925223
Short name T124
Test name
Test status
Simulation time 1933086445 ps
CPU time 13 seconds
Started Jun 29 07:26:24 PM PDT 24
Finished Jun 29 07:26:38 PM PDT 24
Peak memory 248792 kb
Host smart-6e46b502-ae1d-4a89-a063-5516e3f30983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514925223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2514925223
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.578629498
Short name T687
Test name
Test status
Simulation time 1781410808 ps
CPU time 31.62 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:26:51 PM PDT 24
Peak memory 243608 kb
Host smart-68c9b059-af2a-43b2-913b-1bfe2eb8b82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578629498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.578629498
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.2588726640
Short name T833
Test name
Test status
Simulation time 392538038 ps
CPU time 7.08 seconds
Started Jun 29 07:26:24 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 242076 kb
Host smart-221ad409-36d2-431f-b484-df6b46b94bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588726640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.2588726640
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.964258782
Short name T1164
Test name
Test status
Simulation time 562552317 ps
CPU time 4.34 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:26 PM PDT 24
Peak memory 241872 kb
Host smart-64839f37-e101-4057-9284-bbd07cb27212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964258782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.964258782
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3046963851
Short name T1029
Test name
Test status
Simulation time 5910033476 ps
CPU time 25.47 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 243140 kb
Host smart-1561c1a4-4cce-4a43-b3c4-5327f3a80714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046963851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3046963851
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.2978701144
Short name T1135
Test name
Test status
Simulation time 338743665 ps
CPU time 8.35 seconds
Started Jun 29 07:26:23 PM PDT 24
Finished Jun 29 07:26:33 PM PDT 24
Peak memory 242184 kb
Host smart-c4134a0f-5b6c-4a71-bbcf-e1688812d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978701144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.2978701144
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.2278947976
Short name T614
Test name
Test status
Simulation time 962779217 ps
CPU time 14.31 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:26:34 PM PDT 24
Peak memory 241888 kb
Host smart-22767cb5-f2a1-4933-8eb7-f6280af77164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278947976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2278947976
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.4075030271
Short name T789
Test name
Test status
Simulation time 8722334041 ps
CPU time 26.27 seconds
Started Jun 29 07:26:20 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242296 kb
Host smart-52363c16-a511-4a91-85c6-54041ff6643c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4075030271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.4075030271
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.640385056
Short name T759
Test name
Test status
Simulation time 223232188 ps
CPU time 6.85 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:26:31 PM PDT 24
Peak memory 242016 kb
Host smart-fc6db86f-9d18-4f08-8a11-1cfc9b211bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640385056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.640385056
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.131450033
Short name T869
Test name
Test status
Simulation time 788503832 ps
CPU time 6.61 seconds
Started Jun 29 07:26:13 PM PDT 24
Finished Jun 29 07:26:20 PM PDT 24
Peak memory 248772 kb
Host smart-b28d443c-6482-415d-a8a0-15ba65d624c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131450033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.131450033
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3073292152
Short name T237
Test name
Test status
Simulation time 37730146009 ps
CPU time 164.06 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:29:08 PM PDT 24
Peak memory 248824 kb
Host smart-4d988d17-9224-4c26-b8ef-4d13455d300a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073292152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3073292152
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.3160557136
Short name T31
Test name
Test status
Simulation time 11501052554 ps
CPU time 310.65 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:31:30 PM PDT 24
Peak memory 257084 kb
Host smart-c6270c4e-ddef-40c5-9e59-05a40410324e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160557136 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.3160557136
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.3870190469
Short name T201
Test name
Test status
Simulation time 3881778063 ps
CPU time 19.96 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:26:43 PM PDT 24
Peak memory 242296 kb
Host smart-ba950344-643a-46d2-a88c-8782fdf52ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870190469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3870190469
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.706528208
Short name T535
Test name
Test status
Simulation time 165076345 ps
CPU time 4.43 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242176 kb
Host smart-075c7abe-7cbd-49f4-ad33-d77ae9859679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706528208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.706528208
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.1161838298
Short name T622
Test name
Test status
Simulation time 398099563 ps
CPU time 3.51 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 241924 kb
Host smart-becdb5a0-f802-414e-a59d-20551e4139a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161838298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.1161838298
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.306333228
Short name T982
Test name
Test status
Simulation time 2452007113 ps
CPU time 4.81 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 242196 kb
Host smart-0ff1c5d7-0e23-404f-948a-84db0ba621bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306333228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.306333228
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.616072692
Short name T88
Test name
Test status
Simulation time 1455846619 ps
CPU time 5.46 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 242384 kb
Host smart-d9253d6f-40e8-4b64-9b56-27a1f315c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616072692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.616072692
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.1716725813
Short name T912
Test name
Test status
Simulation time 114517026 ps
CPU time 4.14 seconds
Started Jun 29 07:29:16 PM PDT 24
Finished Jun 29 07:29:21 PM PDT 24
Peak memory 241924 kb
Host smart-e504fc27-3ff3-480d-8158-91b4622cadcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716725813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.1716725813
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.3836433080
Short name T851
Test name
Test status
Simulation time 2008800795 ps
CPU time 6.32 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 242112 kb
Host smart-3ef9ccf1-e09a-4d99-af72-401fc5b25880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836433080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3836433080
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3457011714
Short name T788
Test name
Test status
Simulation time 674333644 ps
CPU time 4.74 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242508 kb
Host smart-7c52d892-ccd3-4570-8b6e-b0cb19a72473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457011714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3457011714
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2496071435
Short name T555
Test name
Test status
Simulation time 86435040 ps
CPU time 3.6 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 241828 kb
Host smart-5cc9fd84-72fa-4b77-b87d-45748c52bde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496071435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2496071435
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3760904141
Short name T580
Test name
Test status
Simulation time 90875574 ps
CPU time 3.08 seconds
Started Jun 29 07:29:16 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 242404 kb
Host smart-f05cdd6c-1bac-4de6-bfc7-6b87de63f45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760904141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3760904141
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.2034339637
Short name T239
Test name
Test status
Simulation time 535727178 ps
CPU time 3.2 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242172 kb
Host smart-9c5eaf14-9b77-479e-9a02-328dde9e3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034339637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2034339637
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.737509693
Short name T941
Test name
Test status
Simulation time 657490500 ps
CPU time 2.38 seconds
Started Jun 29 07:26:18 PM PDT 24
Finished Jun 29 07:26:21 PM PDT 24
Peak memory 240156 kb
Host smart-1c88ece6-683f-463d-92c2-a9d75407a3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737509693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.737509693
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.13947636
Short name T358
Test name
Test status
Simulation time 2289493512 ps
CPU time 33.95 seconds
Started Jun 29 07:26:23 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 248804 kb
Host smart-04d05ae2-d93c-4420-950b-187fdbf554f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13947636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.13947636
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1166644507
Short name T989
Test name
Test status
Simulation time 405425710 ps
CPU time 13.19 seconds
Started Jun 29 07:26:23 PM PDT 24
Finished Jun 29 07:26:37 PM PDT 24
Peak memory 242228 kb
Host smart-2dd466c7-c266-4eb3-ad21-505f617c8898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166644507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1166644507
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.4058394898
Short name T827
Test name
Test status
Simulation time 1051429880 ps
CPU time 25.27 seconds
Started Jun 29 07:26:20 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 244720 kb
Host smart-d5ad4f52-b44c-428d-b2f5-54335497efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058394898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.4058394898
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.2537671696
Short name T822
Test name
Test status
Simulation time 413721706 ps
CPU time 15.7 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:38 PM PDT 24
Peak memory 248792 kb
Host smart-58ff70af-ec30-4c52-8fa9-0c98bd93293a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537671696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2537671696
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.4060562042
Short name T935
Test name
Test status
Simulation time 367563962 ps
CPU time 4.86 seconds
Started Jun 29 07:26:23 PM PDT 24
Finished Jun 29 07:26:29 PM PDT 24
Peak memory 242088 kb
Host smart-3bd90336-1cc5-4394-8fe0-1e1af8e65248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060562042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4060562042
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.47563722
Short name T960
Test name
Test status
Simulation time 6356677884 ps
CPU time 14.75 seconds
Started Jun 29 07:26:20 PM PDT 24
Finished Jun 29 07:26:35 PM PDT 24
Peak memory 242080 kb
Host smart-744d7f75-e85b-4b87-9ca3-17c7d1d46c53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47563722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.47563722
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.1170842278
Short name T388
Test name
Test status
Simulation time 1339941216 ps
CPU time 10.17 seconds
Started Jun 29 07:26:19 PM PDT 24
Finished Jun 29 07:26:30 PM PDT 24
Peak memory 242000 kb
Host smart-007072fd-62a8-4691-8757-3a5d5b0b073d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170842278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1170842278
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.2312499673
Short name T491
Test name
Test status
Simulation time 543294805 ps
CPU time 11.1 seconds
Started Jun 29 07:26:20 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 242100 kb
Host smart-40f90b6d-6996-4b4e-9463-ef20ca93d08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312499673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2312499673
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.75682007
Short name T930
Test name
Test status
Simulation time 54858088118 ps
CPU time 121.11 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 260488 kb
Host smart-6d947dd1-e486-4164-9f2c-1338260ef785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75682007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.75682007
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.3598029054
Short name T161
Test name
Test status
Simulation time 360965463298 ps
CPU time 869 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:40:52 PM PDT 24
Peak memory 297860 kb
Host smart-ea99721c-c064-479a-b557-cdfd19cd4d8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598029054 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.3598029054
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.1544465622
Short name T1169
Test name
Test status
Simulation time 9771064917 ps
CPU time 32.53 seconds
Started Jun 29 07:26:20 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 243508 kb
Host smart-78ee8dbd-7785-427f-a9eb-a15668bd1d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544465622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.1544465622
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3588527687
Short name T246
Test name
Test status
Simulation time 213745699 ps
CPU time 4.71 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241916 kb
Host smart-389bbf49-e485-4af8-b2af-cb8c0edd1a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588527687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3588527687
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.1477550084
Short name T46
Test name
Test status
Simulation time 228256038 ps
CPU time 4.44 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242168 kb
Host smart-a20bff59-e505-4345-8326-7b7ce1777d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477550084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1477550084
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.2404543136
Short name T208
Test name
Test status
Simulation time 146669352 ps
CPU time 3.92 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241932 kb
Host smart-f1817b05-fdcc-4ccd-8b0f-35be7edd87c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404543136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2404543136
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.3503453085
Short name T245
Test name
Test status
Simulation time 681905735 ps
CPU time 4.69 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242368 kb
Host smart-05c4470c-2ac3-4d07-8972-e4a8849e0283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503453085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3503453085
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.2791905901
Short name T213
Test name
Test status
Simulation time 566936633 ps
CPU time 5.13 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242068 kb
Host smart-dcd72cb0-7625-4b05-80eb-eae6dcc54f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791905901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2791905901
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.1783583551
Short name T223
Test name
Test status
Simulation time 207326592 ps
CPU time 3.92 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242044 kb
Host smart-bfe470d6-8b31-4c9f-b582-b6f0a42db139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783583551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1783583551
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.1272631663
Short name T612
Test name
Test status
Simulation time 1590262543 ps
CPU time 5.61 seconds
Started Jun 29 07:29:15 PM PDT 24
Finished Jun 29 07:29:21 PM PDT 24
Peak memory 242092 kb
Host smart-634532c3-15bb-48ff-bb82-54f727251ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272631663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1272631663
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.4212636805
Short name T41
Test name
Test status
Simulation time 355860036 ps
CPU time 3.47 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242056 kb
Host smart-723682e0-2edf-4038-ba58-6c0067c5d52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212636805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.4212636805
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.2733925671
Short name T773
Test name
Test status
Simulation time 1803418039 ps
CPU time 4.43 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 242188 kb
Host smart-70f1ba95-2802-426a-a410-b1264312c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733925671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2733925671
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.587220026
Short name T634
Test name
Test status
Simulation time 376896215 ps
CPU time 3.75 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242284 kb
Host smart-88a7d365-39fe-400c-99c7-9ad3d8e17db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587220026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.587220026
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.2855568041
Short name T466
Test name
Test status
Simulation time 1330801342 ps
CPU time 2.54 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:31 PM PDT 24
Peak memory 240160 kb
Host smart-3529d097-106b-4515-bf54-d30453a2196f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855568041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2855568041
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.4146196332
Short name T33
Test name
Test status
Simulation time 521298181 ps
CPU time 17.27 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242704 kb
Host smart-acb5c951-a582-4daf-a043-0e76fe7e650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146196332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.4146196332
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.506882062
Short name T787
Test name
Test status
Simulation time 207690554 ps
CPU time 11.71 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:33 PM PDT 24
Peak memory 242008 kb
Host smart-e9d0d977-cbbe-4ebf-a3f1-2341bd64ae60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506882062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.506882062
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.976827744
Short name T396
Test name
Test status
Simulation time 19302960887 ps
CPU time 46.16 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 243384 kb
Host smart-5fabb90e-aaa0-4a60-aca4-1f0c4e6cf571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976827744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.976827744
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.3866440615
Short name T829
Test name
Test status
Simulation time 122909550 ps
CPU time 4.65 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:26:28 PM PDT 24
Peak memory 241924 kb
Host smart-a5b2c506-198e-44d3-8be5-ed27be683d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866440615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3866440615
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3330943547
Short name T233
Test name
Test status
Simulation time 822884483 ps
CPU time 27.31 seconds
Started Jun 29 07:26:30 PM PDT 24
Finished Jun 29 07:26:59 PM PDT 24
Peak memory 244896 kb
Host smart-e59c4df3-dc15-4722-bd15-66100db265da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330943547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3330943547
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.3395443959
Short name T1093
Test name
Test status
Simulation time 3933789403 ps
CPU time 29.46 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:57 PM PDT 24
Peak memory 242888 kb
Host smart-99a2c9b7-a0f1-4158-a6ee-34021e360b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395443959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3395443959
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2318213122
Short name T620
Test name
Test status
Simulation time 4603171628 ps
CPU time 21.69 seconds
Started Jun 29 07:26:23 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 242028 kb
Host smart-49645ee5-9844-4e15-aff4-5622c892d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318213122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2318213122
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.740254918
Short name T477
Test name
Test status
Simulation time 1968229245 ps
CPU time 17.3 seconds
Started Jun 29 07:26:22 PM PDT 24
Finished Jun 29 07:26:40 PM PDT 24
Peak memory 241972 kb
Host smart-05623e75-43c7-4568-ae02-bd2dcb76a83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740254918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.740254918
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1393562639
Short name T905
Test name
Test status
Simulation time 106964404 ps
CPU time 3.56 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 242296 kb
Host smart-9532aac7-996e-4d1f-b460-1c4f459d36ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393562639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1393562639
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2173205369
Short name T460
Test name
Test status
Simulation time 1836721470 ps
CPU time 4.65 seconds
Started Jun 29 07:26:21 PM PDT 24
Finished Jun 29 07:26:27 PM PDT 24
Peak memory 242224 kb
Host smart-e3642e32-e4d4-4dd0-bbea-ab34e45247dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173205369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2173205369
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.2843673350
Short name T267
Test name
Test status
Simulation time 77210943939 ps
CPU time 284.87 seconds
Started Jun 29 07:26:29 PM PDT 24
Finished Jun 29 07:31:15 PM PDT 24
Peak memory 248828 kb
Host smart-405de841-469a-41e2-a2cb-60b1a9c82639
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843673350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.2843673350
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2876039117
Short name T241
Test name
Test status
Simulation time 789534201 ps
CPU time 13.56 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:43 PM PDT 24
Peak memory 241964 kb
Host smart-8f4ebb31-e854-4634-a855-fbc9a03aa52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876039117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2876039117
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.697187744
Short name T1177
Test name
Test status
Simulation time 161161872 ps
CPU time 4.08 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242360 kb
Host smart-f66f3fbe-707c-4a05-99e2-35e00f7dae20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697187744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.697187744
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.1096090656
Short name T695
Test name
Test status
Simulation time 377025242 ps
CPU time 3.71 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 242412 kb
Host smart-d39cd5d1-aea1-4355-9487-6843498d1a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096090656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1096090656
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1663532740
Short name T898
Test name
Test status
Simulation time 209832353 ps
CPU time 4.75 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 241816 kb
Host smart-f6912cda-784b-43ab-b29c-44b38b9ae97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663532740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1663532740
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.782902605
Short name T1000
Test name
Test status
Simulation time 277995650 ps
CPU time 4.52 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 241832 kb
Host smart-2476c0f5-df99-471f-bd5a-e5e908a5b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782902605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.782902605
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2818733279
Short name T1060
Test name
Test status
Simulation time 162879460 ps
CPU time 4.92 seconds
Started Jun 29 07:29:16 PM PDT 24
Finished Jun 29 07:29:21 PM PDT 24
Peak memory 242076 kb
Host smart-7480b2f7-a175-42a7-bf4d-bd322482ecb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818733279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2818733279
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.574316916
Short name T994
Test name
Test status
Simulation time 302154420 ps
CPU time 4.64 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241932 kb
Host smart-87f8e1e1-caf9-4301-9140-0f3bbe4d15cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574316916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.574316916
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.2459696589
Short name T126
Test name
Test status
Simulation time 240726324 ps
CPU time 5.11 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242068 kb
Host smart-553929c2-b478-48ff-a189-eeb80bea8a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459696589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.2459696589
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.941701741
Short name T922
Test name
Test status
Simulation time 273674670 ps
CPU time 3.85 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242068 kb
Host smart-763635eb-536f-4c0e-a440-44616401d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941701741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.941701741
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.3869023012
Short name T1175
Test name
Test status
Simulation time 820266075 ps
CPU time 1.92 seconds
Started Jun 29 07:26:30 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 240224 kb
Host smart-325c7c5b-1c24-4d6f-8a59-017324cb3c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869023012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.3869023012
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3632107070
Short name T871
Test name
Test status
Simulation time 635818464 ps
CPU time 21 seconds
Started Jun 29 07:26:26 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242224 kb
Host smart-4e3010e8-c5c4-4b8f-a8e1-108a9212e651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632107070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3632107070
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.470081846
Short name T1126
Test name
Test status
Simulation time 596646290 ps
CPU time 9.26 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 242052 kb
Host smart-98f514bb-073e-4627-a557-12f5434c3a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470081846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.470081846
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.1326490691
Short name T661
Test name
Test status
Simulation time 323960027 ps
CPU time 3.81 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:33 PM PDT 24
Peak memory 242080 kb
Host smart-e3ab4b66-fe69-4e77-b7db-9598bd5ca793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326490691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.1326490691
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.2013508546
Short name T1105
Test name
Test status
Simulation time 28278467058 ps
CPU time 54.95 seconds
Started Jun 29 07:26:31 PM PDT 24
Finished Jun 29 07:27:27 PM PDT 24
Peak memory 257656 kb
Host smart-433e851a-b6e9-4d5e-9983-fd6a842ce4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013508546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2013508546
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.170013660
Short name T961
Test name
Test status
Simulation time 2638889664 ps
CPU time 30.83 seconds
Started Jun 29 07:26:31 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 242132 kb
Host smart-f1203483-408a-4de0-838f-6ac8ed733002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170013660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.170013660
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2370363052
Short name T514
Test name
Test status
Simulation time 388586059 ps
CPU time 8.98 seconds
Started Jun 29 07:26:30 PM PDT 24
Finished Jun 29 07:26:40 PM PDT 24
Peak memory 241772 kb
Host smart-4e775dfc-85a7-4500-b4e6-649e0e1a7379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370363052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2370363052
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.500048604
Short name T796
Test name
Test status
Simulation time 8382806227 ps
CPU time 19.42 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:48 PM PDT 24
Peak memory 242492 kb
Host smart-ef1d3a83-7df7-4910-97df-f771a13a5356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500048604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.500048604
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.2411613454
Short name T1172
Test name
Test status
Simulation time 4689085774 ps
CPU time 12.2 seconds
Started Jun 29 07:26:31 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 242096 kb
Host smart-43176d98-682e-4807-9f31-2c77a6a4a8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2411613454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2411613454
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.1053566727
Short name T940
Test name
Test status
Simulation time 557642803 ps
CPU time 4.64 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:32 PM PDT 24
Peak memory 242480 kb
Host smart-a310be05-1b0c-44d9-af20-dc1f61d35a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053566727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.1053566727
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.2571863890
Short name T838
Test name
Test status
Simulation time 1942613085 ps
CPU time 48.68 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 245400 kb
Host smart-818d9844-cfd5-4675-96b2-72f885187b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571863890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.2571863890
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.1885718505
Short name T813
Test name
Test status
Simulation time 952872878 ps
CPU time 20.19 seconds
Started Jun 29 07:26:31 PM PDT 24
Finished Jun 29 07:26:52 PM PDT 24
Peak memory 242512 kb
Host smart-191e2ce2-d2ec-4e51-9aa3-75683f73dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885718505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.1885718505
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.1436287007
Short name T551
Test name
Test status
Simulation time 283159142 ps
CPU time 4.13 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 242404 kb
Host smart-56fe3a86-04c8-4299-a71d-c8f6587f5a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436287007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.1436287007
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.88345984
Short name T243
Test name
Test status
Simulation time 424025863 ps
CPU time 4.02 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 241880 kb
Host smart-c6102b94-3fd6-4867-9a8b-3f90dc090d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88345984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.88345984
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.3080175316
Short name T2
Test name
Test status
Simulation time 96403348 ps
CPU time 3.82 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 242064 kb
Host smart-dafaf046-cd9e-4b75-b25f-83006248bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080175316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3080175316
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.1476994557
Short name T1027
Test name
Test status
Simulation time 133037973 ps
CPU time 5.12 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 241948 kb
Host smart-74f2a329-e6e5-4882-85e7-51f32f16cbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476994557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1476994557
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1681181790
Short name T469
Test name
Test status
Simulation time 345950199 ps
CPU time 3.38 seconds
Started Jun 29 07:29:13 PM PDT 24
Finished Jun 29 07:29:17 PM PDT 24
Peak memory 242388 kb
Host smart-e1c14fcd-d5aa-4365-827b-1079a14cd16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681181790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1681181790
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2064926210
Short name T779
Test name
Test status
Simulation time 489135438 ps
CPU time 3.63 seconds
Started Jun 29 07:29:10 PM PDT 24
Finished Jun 29 07:29:14 PM PDT 24
Peak memory 242144 kb
Host smart-7c195876-859b-40c4-9018-f1b908f78e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064926210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2064926210
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.2729934057
Short name T1122
Test name
Test status
Simulation time 246794188 ps
CPU time 4.2 seconds
Started Jun 29 07:29:12 PM PDT 24
Finished Jun 29 07:29:18 PM PDT 24
Peak memory 242132 kb
Host smart-34676894-fe06-4b3c-ab73-9dfb99dcd293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729934057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2729934057
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.2641095696
Short name T29
Test name
Test status
Simulation time 197346102 ps
CPU time 4.45 seconds
Started Jun 29 07:29:14 PM PDT 24
Finished Jun 29 07:29:20 PM PDT 24
Peak memory 241932 kb
Host smart-fd1a11ef-4597-405a-9811-927c3f9b610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641095696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2641095696
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2045128332
Short name T83
Test name
Test status
Simulation time 253459067 ps
CPU time 3.95 seconds
Started Jun 29 07:29:11 PM PDT 24
Finished Jun 29 07:29:16 PM PDT 24
Peak memory 242060 kb
Host smart-f78d9c42-c2ea-4cdd-aef7-2a2ea3be9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045128332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2045128332
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.2060586975
Short name T719
Test name
Test status
Simulation time 99194456 ps
CPU time 1.81 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:38 PM PDT 24
Peak memory 240212 kb
Host smart-a1253879-9fb2-4ce9-ad67-703ba5871337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060586975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2060586975
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.1463776169
Short name T90
Test name
Test status
Simulation time 430171477 ps
CPU time 7.04 seconds
Started Jun 29 07:26:30 PM PDT 24
Finished Jun 29 07:26:39 PM PDT 24
Peak memory 248024 kb
Host smart-a89a44ae-bf36-461f-bdcc-a98bbf584b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463776169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1463776169
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.2587172967
Short name T192
Test name
Test status
Simulation time 2411157209 ps
CPU time 19.61 seconds
Started Jun 29 07:26:25 PM PDT 24
Finished Jun 29 07:26:45 PM PDT 24
Peak memory 242268 kb
Host smart-ea81e079-1c5a-4f37-8ad7-657c6b56d41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587172967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2587172967
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.3733980278
Short name T488
Test name
Test status
Simulation time 15705240290 ps
CPU time 119.49 seconds
Started Jun 29 07:26:29 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 242148 kb
Host smart-0989cc91-12c7-4e7d-97eb-8c7ec7cb9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733980278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.3733980278
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.1510023166
Short name T52
Test name
Test status
Simulation time 2552278958 ps
CPU time 7.14 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:34 PM PDT 24
Peak memory 242280 kb
Host smart-921f5bed-ccec-489a-9733-94693177a59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510023166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.1510023166
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.1384352822
Short name T865
Test name
Test status
Simulation time 1498540120 ps
CPU time 31.63 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:59 PM PDT 24
Peak memory 245692 kb
Host smart-d3a3e04c-8bcc-47dd-90f6-77b425760c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384352822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1384352822
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3400534293
Short name T406
Test name
Test status
Simulation time 484407910 ps
CPU time 18.3 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242612 kb
Host smart-61385eed-4997-45df-917f-0574ac29e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400534293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3400534293
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.2673483662
Short name T606
Test name
Test status
Simulation time 1793249425 ps
CPU time 7.27 seconds
Started Jun 29 07:26:29 PM PDT 24
Finished Jun 29 07:26:37 PM PDT 24
Peak memory 241876 kb
Host smart-8fb257fa-1ff2-4621-bc43-ce29c7aba09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673483662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2673483662
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.4272040380
Short name T399
Test name
Test status
Simulation time 8591706025 ps
CPU time 22.93 seconds
Started Jun 29 07:26:26 PM PDT 24
Finished Jun 29 07:26:49 PM PDT 24
Peak memory 241996 kb
Host smart-cc13ca25-0316-42fe-a845-38a835bdcfd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272040380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.4272040380
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.1388083499
Short name T1061
Test name
Test status
Simulation time 137298093 ps
CPU time 5.32 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:34 PM PDT 24
Peak memory 242112 kb
Host smart-349848bc-4441-4f89-a1c7-98f547960ef1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388083499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1388083499
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.848752315
Short name T964
Test name
Test status
Simulation time 2256269711 ps
CPU time 17.6 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 242216 kb
Host smart-5e2bf986-0cbc-426e-a05d-1d18de843a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848752315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.848752315
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2931270662
Short name T347
Test name
Test status
Simulation time 158506700651 ps
CPU time 1684.4 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:54:32 PM PDT 24
Peak memory 342144 kb
Host smart-0216251e-2f4f-4bb8-9c05-98d2a03f72e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931270662 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2931270662
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3418071833
Short name T776
Test name
Test status
Simulation time 559580504 ps
CPU time 20.27 seconds
Started Jun 29 07:26:27 PM PDT 24
Finished Jun 29 07:26:48 PM PDT 24
Peak memory 242244 kb
Host smart-03fe092d-4ca7-40f4-8e8e-1daa2fec41b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418071833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3418071833
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1693114843
Short name T204
Test name
Test status
Simulation time 132789325 ps
CPU time 4.31 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242168 kb
Host smart-e6b966fc-33c4-4327-ba18-547d30d84af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693114843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1693114843
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.498249200
Short name T51
Test name
Test status
Simulation time 311937898 ps
CPU time 5.41 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242092 kb
Host smart-7b79d3ed-f855-47c9-88f5-e92320833a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498249200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.498249200
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1362763303
Short name T722
Test name
Test status
Simulation time 256545795 ps
CPU time 3.77 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 242024 kb
Host smart-a5cb5644-506a-4076-bf8a-abb03445c299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362763303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1362763303
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.1858135322
Short name T166
Test name
Test status
Simulation time 187227476 ps
CPU time 3.88 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 241756 kb
Host smart-8084653e-fc4c-401f-8bb7-9739062138c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858135322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1858135322
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1005750829
Short name T134
Test name
Test status
Simulation time 371945864 ps
CPU time 4.36 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 242064 kb
Host smart-9f506814-e943-47e0-8dcf-4591945caedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005750829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1005750829
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1687870343
Short name T70
Test name
Test status
Simulation time 366698313 ps
CPU time 3.94 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 242072 kb
Host smart-0f7129af-8979-4b9c-a5c0-44b88fc9a703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687870343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1687870343
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.1501706596
Short name T234
Test name
Test status
Simulation time 1343901515 ps
CPU time 3.3 seconds
Started Jun 29 07:29:18 PM PDT 24
Finished Jun 29 07:29:22 PM PDT 24
Peak memory 242400 kb
Host smart-2d555f2b-e849-468e-ac1f-2f6363fecf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501706596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1501706596
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.504911372
Short name T1030
Test name
Test status
Simulation time 267811416 ps
CPU time 3.95 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242012 kb
Host smart-9c80a59e-4d3e-460a-b333-2f24b4ee5eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504911372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.504911372
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1747403072
Short name T1053
Test name
Test status
Simulation time 638447178 ps
CPU time 5.43 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 242356 kb
Host smart-1221ff4b-5b5d-4855-b0b2-f7b10bcb14a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747403072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1747403072
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.3199757623
Short name T909
Test name
Test status
Simulation time 197616932 ps
CPU time 1.81 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:26:38 PM PDT 24
Peak memory 240232 kb
Host smart-f7b71e38-f141-4b95-a603-a1e74b32390d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199757623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.3199757623
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.1469576239
Short name T1039
Test name
Test status
Simulation time 2223314451 ps
CPU time 15.73 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:45 PM PDT 24
Peak memory 242940 kb
Host smart-73c6f4c2-cda3-4fd6-90cf-de2479809cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469576239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.1469576239
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2470314928
Short name T438
Test name
Test status
Simulation time 4129915906 ps
CPU time 39.23 seconds
Started Jun 29 07:26:29 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 249428 kb
Host smart-e07503f8-275d-4b1e-b87f-f8fcf6bff7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470314928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2470314928
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4080428448
Short name T925
Test name
Test status
Simulation time 2705733965 ps
CPU time 29.55 seconds
Started Jun 29 07:26:26 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 248868 kb
Host smart-82c44995-d8b3-4029-93b4-79b1b080e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080428448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4080428448
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.920838519
Short name T457
Test name
Test status
Simulation time 265645240 ps
CPU time 4.99 seconds
Started Jun 29 07:26:34 PM PDT 24
Finished Jun 29 07:26:40 PM PDT 24
Peak memory 242084 kb
Host smart-08397ac1-f10f-41ad-89f2-10f130529104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920838519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.920838519
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.1986435677
Short name T1170
Test name
Test status
Simulation time 1657423110 ps
CPU time 24.91 seconds
Started Jun 29 07:26:28 PM PDT 24
Finished Jun 29 07:26:54 PM PDT 24
Peak memory 243444 kb
Host smart-882c0ed8-076f-40fc-b505-0fd97735acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986435677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1986435677
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2030614737
Short name T1012
Test name
Test status
Simulation time 214696361 ps
CPU time 5.98 seconds
Started Jun 29 07:26:29 PM PDT 24
Finished Jun 29 07:26:36 PM PDT 24
Peak memory 241904 kb
Host smart-d98f124d-8e1b-46a0-895e-29ca7ae35ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030614737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2030614737
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.2597596004
Short name T462
Test name
Test status
Simulation time 371607887 ps
CPU time 9.67 seconds
Started Jun 29 07:26:26 PM PDT 24
Finished Jun 29 07:26:36 PM PDT 24
Peak memory 242028 kb
Host smart-e38852db-9831-4d19-a4a7-4792b30a0257
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597596004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2597596004
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1084613421
Short name T378
Test name
Test status
Simulation time 493030869 ps
CPU time 10.03 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 242036 kb
Host smart-204a6ac3-a6c3-4ba8-b9ab-b267326b68f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1084613421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1084613421
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.142170540
Short name T189
Test name
Test status
Simulation time 635561742 ps
CPU time 6.08 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:26:41 PM PDT 24
Peak memory 248784 kb
Host smart-bce9221d-c253-4c65-bbca-c95ab13c8a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142170540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.142170540
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1877681635
Short name T290
Test name
Test status
Simulation time 395435663972 ps
CPU time 1366.37 seconds
Started Jun 29 07:26:39 PM PDT 24
Finished Jun 29 07:49:26 PM PDT 24
Peak memory 452832 kb
Host smart-cb52f51f-4cab-4a3f-a6da-5500884ea94b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877681635 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1877681635
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.1716499448
Short name T509
Test name
Test status
Simulation time 1786771154 ps
CPU time 19.24 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242500 kb
Host smart-8256ac6f-7150-4c47-8487-0358e1eb07fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716499448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.1716499448
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3182790203
Short name T563
Test name
Test status
Simulation time 492029790 ps
CPU time 4.15 seconds
Started Jun 29 07:29:19 PM PDT 24
Finished Jun 29 07:29:23 PM PDT 24
Peak memory 242036 kb
Host smart-4f505cf1-3da1-4b52-9f97-52eb4ecefd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182790203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3182790203
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.2306517681
Short name T180
Test name
Test status
Simulation time 131658601 ps
CPU time 4.42 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 241932 kb
Host smart-7dfe7776-d8ba-4bea-95ec-96affe5d9967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306517681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2306517681
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3012458842
Short name T1144
Test name
Test status
Simulation time 222682191 ps
CPU time 3.38 seconds
Started Jun 29 07:29:24 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 241900 kb
Host smart-b143467e-297e-4841-b208-c1c254607cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012458842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3012458842
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.3038644026
Short name T214
Test name
Test status
Simulation time 2171392282 ps
CPU time 4.2 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 242120 kb
Host smart-8d0966b2-75cb-4a1f-998a-b41a23527831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038644026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3038644026
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.3581804369
Short name T1062
Test name
Test status
Simulation time 1901897996 ps
CPU time 4.83 seconds
Started Jun 29 07:29:26 PM PDT 24
Finished Jun 29 07:29:31 PM PDT 24
Peak memory 242436 kb
Host smart-9d4d5dab-6300-474f-902f-bf2e3cd25e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581804369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3581804369
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.3389939027
Short name T601
Test name
Test status
Simulation time 1849200031 ps
CPU time 4.74 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242252 kb
Host smart-bf17e531-d6b2-49d0-b286-cb3226c8201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389939027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3389939027
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.430827442
Short name T584
Test name
Test status
Simulation time 492457593 ps
CPU time 5.01 seconds
Started Jun 29 07:29:24 PM PDT 24
Finished Jun 29 07:29:30 PM PDT 24
Peak memory 242156 kb
Host smart-0f49f222-259f-4b31-aab4-56b879d35555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430827442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.430827442
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1820950718
Short name T236
Test name
Test status
Simulation time 248558943 ps
CPU time 3.62 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 241892 kb
Host smart-aaed313c-a451-4994-8429-faec8dc4f572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820950718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1820950718
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.665712483
Short name T184
Test name
Test status
Simulation time 247150669 ps
CPU time 4.16 seconds
Started Jun 29 07:29:18 PM PDT 24
Finished Jun 29 07:29:23 PM PDT 24
Peak memory 242380 kb
Host smart-19337485-6763-4720-bf22-9bb94fd01e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665712483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.665712483
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.2942992565
Short name T411
Test name
Test status
Simulation time 260765867 ps
CPU time 2.03 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:41 PM PDT 24
Peak memory 240244 kb
Host smart-fa251c98-465c-4098-b4bd-d5ab27a4c91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942992565 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2942992565
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3251835263
Short name T73
Test name
Test status
Simulation time 353545838 ps
CPU time 7.47 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 248792 kb
Host smart-d1567e8b-71eb-4dcd-8323-507b309f8c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251835263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3251835263
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3441861692
Short name T359
Test name
Test status
Simulation time 2828006695 ps
CPU time 32.05 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:27:10 PM PDT 24
Peak memory 246124 kb
Host smart-f7fe54d8-f2a7-428d-990b-e43bd74f6266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441861692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3441861692
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.977545419
Short name T1048
Test name
Test status
Simulation time 1093899281 ps
CPU time 22.45 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:27:02 PM PDT 24
Peak memory 242436 kb
Host smart-379f0b76-1bfc-485e-90de-8850d19e5413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977545419 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.977545419
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.474227869
Short name T1074
Test name
Test status
Simulation time 151816914 ps
CPU time 4.03 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:26:42 PM PDT 24
Peak memory 241932 kb
Host smart-172847e2-15ec-45d4-8647-5d05ab7322ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474227869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.474227869
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.3757117966
Short name T662
Test name
Test status
Simulation time 378804524 ps
CPU time 7.72 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 242040 kb
Host smart-a32e52ee-692b-4743-975f-432b35926f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757117966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.3757117966
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.1671186311
Short name T552
Test name
Test status
Simulation time 422285575 ps
CPU time 14.5 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:54 PM PDT 24
Peak memory 242428 kb
Host smart-e4d6920f-e11d-4c61-84a8-116a3d6d43dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671186311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1671186311
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.2914681367
Short name T710
Test name
Test status
Simulation time 2318330518 ps
CPU time 6.44 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 242264 kb
Host smart-77629773-3f06-4070-bfcd-7c40224b44a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914681367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2914681367
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.4025272558
Short name T731
Test name
Test status
Simulation time 1053707826 ps
CPU time 7.39 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:26:43 PM PDT 24
Peak memory 241908 kb
Host smart-ee01bf6d-345b-44bf-bead-0e265900c635
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025272558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.4025272558
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.2703797537
Short name T648
Test name
Test status
Simulation time 262203269 ps
CPU time 7.39 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 242412 kb
Host smart-3a1b0e50-a8ed-4f4c-ba24-29637a0ab165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2703797537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2703797537
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.1394669497
Short name T766
Test name
Test status
Simulation time 421146498 ps
CPU time 10.21 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:26:45 PM PDT 24
Peak memory 242232 kb
Host smart-d064c2e1-00f3-470b-9d84-d376c61ea90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394669497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.1394669497
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.1586953792
Short name T689
Test name
Test status
Simulation time 34223284979 ps
CPU time 65.98 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 244524 kb
Host smart-70229dba-e944-4846-93b3-5f47bed20786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586953792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all
.1586953792
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3041344005
Short name T948
Test name
Test status
Simulation time 44829291740 ps
CPU time 628.08 seconds
Started Jun 29 07:26:35 PM PDT 24
Finished Jun 29 07:37:04 PM PDT 24
Peak memory 265340 kb
Host smart-a8a02b9c-f53a-4d67-8f7d-da7cb4e9d653
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041344005 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.3041344005
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.1583470479
Short name T653
Test name
Test status
Simulation time 12157080145 ps
CPU time 68.51 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 243496 kb
Host smart-48f65c08-675d-4b33-957b-f412ea1927ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583470479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.1583470479
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2194153313
Short name T537
Test name
Test status
Simulation time 335730146 ps
CPU time 4.93 seconds
Started Jun 29 07:29:27 PM PDT 24
Finished Jun 29 07:29:32 PM PDT 24
Peak memory 241856 kb
Host smart-e8e809d6-2e67-4be0-9d74-a16ec263709c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194153313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2194153313
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2568579048
Short name T630
Test name
Test status
Simulation time 116043847 ps
CPU time 3.83 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 241912 kb
Host smart-cbf53f13-2ac5-48a3-94b3-c9c4681b5cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568579048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2568579048
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1684003136
Short name T28
Test name
Test status
Simulation time 135418299 ps
CPU time 4.62 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 242128 kb
Host smart-f3fc09e7-8d8a-4203-b21f-8d271ed726e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684003136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1684003136
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.73794159
Short name T1032
Test name
Test status
Simulation time 2433270400 ps
CPU time 7.03 seconds
Started Jun 29 07:29:19 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242248 kb
Host smart-954267d5-5d43-4c88-beda-a82af1485ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73794159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.73794159
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2941538316
Short name T625
Test name
Test status
Simulation time 280170865 ps
CPU time 4.26 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 242076 kb
Host smart-815bd73a-de84-43aa-a503-5c91bc5e41fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941538316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2941538316
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.2565972173
Short name T678
Test name
Test status
Simulation time 165711956 ps
CPU time 4.68 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 242028 kb
Host smart-c10cbd07-9333-417d-8ccc-3487e1f67a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565972173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2565972173
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.3646316718
Short name T680
Test name
Test status
Simulation time 422776718 ps
CPU time 4.01 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:33 PM PDT 24
Peak memory 242100 kb
Host smart-a0fa1614-d7f2-4caf-8a22-6aa6684f7926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646316718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3646316718
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.2319274258
Short name T536
Test name
Test status
Simulation time 66660270 ps
CPU time 1.63 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:40 PM PDT 24
Peak memory 240512 kb
Host smart-81e96baa-8d49-4ed3-bdf5-fe8c24b6e815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319274258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.2319274258
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1988422307
Short name T148
Test name
Test status
Simulation time 2611528477 ps
CPU time 18.73 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242788 kb
Host smart-7e6dee0a-c5ff-47d6-a223-4ff276e0d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988422307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1988422307
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.2659027671
Short name T780
Test name
Test status
Simulation time 4398411924 ps
CPU time 40.09 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 250860 kb
Host smart-078c39ef-f146-4a64-865d-7317a69a157c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659027671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.2659027671
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.3260536634
Short name T1147
Test name
Test status
Simulation time 1239883799 ps
CPU time 25.17 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:27:04 PM PDT 24
Peak memory 242412 kb
Host smart-dd14dc18-2f81-41bc-b414-3f9bc41d5c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260536634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3260536634
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3650670656
Short name T414
Test name
Test status
Simulation time 630016508 ps
CPU time 5.75 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:44 PM PDT 24
Peak memory 242152 kb
Host smart-5f02ffe3-6e09-4953-8087-52a5fbcfa56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650670656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3650670656
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.4003857765
Short name T242
Test name
Test status
Simulation time 2333467815 ps
CPU time 36.37 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:27:15 PM PDT 24
Peak memory 257092 kb
Host smart-b383ca63-1581-4fac-b554-7ee272df54f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003857765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.4003857765
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.2735393999
Short name T216
Test name
Test status
Simulation time 2327809800 ps
CPU time 35.01 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:27:12 PM PDT 24
Peak memory 242168 kb
Host smart-ba23963d-76e5-479b-aba3-4c993652c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735393999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.2735393999
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.1004552042
Short name T939
Test name
Test status
Simulation time 14682191367 ps
CPU time 39.55 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 242440 kb
Host smart-6de60b18-cc7e-47a8-bae4-6f5e56b78f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004552042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.1004552042
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2626757097
Short name T825
Test name
Test status
Simulation time 594897212 ps
CPU time 16.37 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:26:54 PM PDT 24
Peak memory 242028 kb
Host smart-7691faad-97db-4355-89ca-be947d7c9415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2626757097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2626757097
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2022772205
Short name T386
Test name
Test status
Simulation time 272232692 ps
CPU time 4.95 seconds
Started Jun 29 07:26:36 PM PDT 24
Finished Jun 29 07:26:42 PM PDT 24
Peak memory 242124 kb
Host smart-1c489349-e7e8-4da4-8cf7-b6f59a0ed351
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2022772205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2022772205
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.3565450984
Short name T1103
Test name
Test status
Simulation time 1332313222 ps
CPU time 8.59 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242500 kb
Host smart-66fe3017-794b-4873-a48e-9d09f3c817e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565450984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.3565450984
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.973017416
Short name T352
Test name
Test status
Simulation time 31328713808 ps
CPU time 359.16 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:32:38 PM PDT 24
Peak memory 248940 kb
Host smart-b4e58cb4-8e47-4afe-8dec-4159355d8500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973017416 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.973017416
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.2168064102
Short name T215
Test name
Test status
Simulation time 761683969 ps
CPU time 18.12 seconds
Started Jun 29 07:26:38 PM PDT 24
Finished Jun 29 07:26:57 PM PDT 24
Peak memory 242384 kb
Host smart-aa23d3e4-ba69-4036-b18d-6ce2000a2439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168064102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2168064102
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.50237690
Short name T683
Test name
Test status
Simulation time 263338971 ps
CPU time 4.22 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242280 kb
Host smart-f10e3fe1-6068-488a-a355-b5acb2350919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50237690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.50237690
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.2622555022
Short name T421
Test name
Test status
Simulation time 544002810 ps
CPU time 4.27 seconds
Started Jun 29 07:29:27 PM PDT 24
Finished Jun 29 07:29:31 PM PDT 24
Peak memory 242116 kb
Host smart-3afe8f99-ce84-497c-ba31-446c232d4076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622555022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.2622555022
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.3587614930
Short name T890
Test name
Test status
Simulation time 353319986 ps
CPU time 4.29 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 242012 kb
Host smart-19448c0e-2fbf-4587-b5ac-b64946b16d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587614930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3587614930
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2629259964
Short name T1007
Test name
Test status
Simulation time 248838893 ps
CPU time 4.87 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 241924 kb
Host smart-74d58abc-6dea-4759-b553-9ba2f3ed5e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629259964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2629259964
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2721513317
Short name T542
Test name
Test status
Simulation time 185904492 ps
CPU time 4.69 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 241920 kb
Host smart-f610a7a9-c9ee-4a57-9d70-96945dde54d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721513317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2721513317
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.1497403105
Short name T715
Test name
Test status
Simulation time 1794570814 ps
CPU time 4.41 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:33 PM PDT 24
Peak memory 241940 kb
Host smart-4613715f-af54-4d9e-b83d-96316d842798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497403105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.1497403105
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1277648940
Short name T768
Test name
Test status
Simulation time 394269924 ps
CPU time 4.01 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 241840 kb
Host smart-46d02a15-88bc-4890-bc7e-c327b970bb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277648940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1277648940
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.4196997503
Short name T654
Test name
Test status
Simulation time 148098208 ps
CPU time 3.47 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242004 kb
Host smart-ed91a6ef-a4f3-422f-8a3a-b632ff1c1f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196997503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.4196997503
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.1644655686
Short name T971
Test name
Test status
Simulation time 208884395 ps
CPU time 3.13 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242244 kb
Host smart-e599e427-8f4b-43be-9ecd-275e9f2bec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644655686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1644655686
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.1409635108
Short name T427
Test name
Test status
Simulation time 232480870 ps
CPU time 5.24 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 241952 kb
Host smart-8bd1379a-53b8-4f9e-bdf8-f1caf1f752d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409635108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1409635108
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.1560912699
Short name T879
Test name
Test status
Simulation time 637055886 ps
CPU time 2.22 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 240164 kb
Host smart-6ec1afe0-c03b-41e2-8c37-41c899042fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560912699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1560912699
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3528599595
Short name T84
Test name
Test status
Simulation time 1504962856 ps
CPU time 8.9 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 248812 kb
Host smart-32794540-5e62-45ac-9323-94725a6b656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528599595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3528599595
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.4216080127
Short name T915
Test name
Test status
Simulation time 7681951782 ps
CPU time 27.45 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:14 PM PDT 24
Peak memory 241608 kb
Host smart-2ffbf9ac-71c9-4643-b777-9f74ff017937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216080127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.4216080127
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3700562017
Short name T506
Test name
Test status
Simulation time 1508098975 ps
CPU time 10.9 seconds
Started Jun 29 07:26:48 PM PDT 24
Finished Jun 29 07:27:00 PM PDT 24
Peak memory 242036 kb
Host smart-df0ca898-41b4-4066-9353-8ba9c7a7444d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700562017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3700562017
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.2514258146
Short name T938
Test name
Test status
Simulation time 537285123 ps
CPU time 3.54 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 241932 kb
Host smart-9149af20-9de3-4f98-aab7-ec47949092a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514258146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2514258146
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.4163051011
Short name T304
Test name
Test status
Simulation time 13813827718 ps
CPU time 21.16 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:27:04 PM PDT 24
Peak memory 248868 kb
Host smart-e9dd9b5d-a467-4929-98ec-853cea65b88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163051011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.4163051011
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.3773262231
Short name T1058
Test name
Test status
Simulation time 3819680602 ps
CPU time 9.32 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 248976 kb
Host smart-87c0b5e0-1aad-4f66-a832-f555bfa360fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773262231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.3773262231
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.1654996804
Short name T539
Test name
Test status
Simulation time 2248087987 ps
CPU time 19.16 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 241936 kb
Host smart-ca9552b8-d5ab-46f8-a4ce-e7625595774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654996804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1654996804
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.610645715
Short name T849
Test name
Test status
Simulation time 408957556 ps
CPU time 6.92 seconds
Started Jun 29 07:26:47 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 242308 kb
Host smart-3319ab9e-8cc7-4a9b-b3b0-0c8ffd0fe243
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=610645715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.610645715
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.4265775423
Short name T379
Test name
Test status
Simulation time 438222444 ps
CPU time 10.56 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 242108 kb
Host smart-8492f0b9-4c84-4357-98e8-b05ecf6be707
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265775423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.4265775423
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.3524994138
Short name T434
Test name
Test status
Simulation time 252024026 ps
CPU time 7.8 seconds
Started Jun 29 07:26:37 PM PDT 24
Finished Jun 29 07:26:46 PM PDT 24
Peak memory 242376 kb
Host smart-06ed7e16-f5ed-4595-b9d4-ba4832158c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524994138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3524994138
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.1453546772
Short name T1001
Test name
Test status
Simulation time 97782311452 ps
CPU time 140.33 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:29:07 PM PDT 24
Peak memory 249208 kb
Host smart-db8effe1-d807-4a2e-9d66-f3668a124e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453546772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.1453546772
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.2389381046
Short name T459
Test name
Test status
Simulation time 1871848561 ps
CPU time 14.69 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:01 PM PDT 24
Peak memory 242480 kb
Host smart-41c1bcec-b9be-4a63-b1f9-738ef25d749d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389381046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2389381046
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.1952169867
Short name T202
Test name
Test status
Simulation time 2618621176 ps
CPU time 6.83 seconds
Started Jun 29 07:29:23 PM PDT 24
Finished Jun 29 07:29:31 PM PDT 24
Peak memory 241880 kb
Host smart-601e61fa-d109-4c1a-8523-63c7d32f27a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952169867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1952169867
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3189264269
Short name T517
Test name
Test status
Simulation time 157200252 ps
CPU time 5.25 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 241964 kb
Host smart-3f7d8f50-16aa-4ead-a7c1-75704d30dc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189264269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3189264269
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.4208597875
Short name T1041
Test name
Test status
Simulation time 108204632 ps
CPU time 3.08 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 241824 kb
Host smart-eefa3232-ba35-4a8b-a6df-e7d7f951c217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208597875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.4208597875
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.1448978568
Short name T1150
Test name
Test status
Simulation time 485032750 ps
CPU time 4.82 seconds
Started Jun 29 07:29:20 PM PDT 24
Finished Jun 29 07:29:26 PM PDT 24
Peak memory 241820 kb
Host smart-5c3c5fda-0b36-458d-b75b-714d8dd54936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448978568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1448978568
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3354229717
Short name T887
Test name
Test status
Simulation time 309333834 ps
CPU time 4.09 seconds
Started Jun 29 07:29:24 PM PDT 24
Finished Jun 29 07:29:30 PM PDT 24
Peak memory 242136 kb
Host smart-6208fddd-40d3-41de-bb5a-d050c1630395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354229717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3354229717
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.4223698946
Short name T1129
Test name
Test status
Simulation time 589274586 ps
CPU time 5.16 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 241896 kb
Host smart-be1c6729-2a00-41e1-aa99-9948d6c7a4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223698946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.4223698946
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.559080151
Short name T519
Test name
Test status
Simulation time 326879955 ps
CPU time 4.16 seconds
Started Jun 29 07:29:22 PM PDT 24
Finished Jun 29 07:29:27 PM PDT 24
Peak memory 242096 kb
Host smart-a363f560-b9af-475a-84b2-f00e6bed28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559080151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.559080151
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.769222684
Short name T736
Test name
Test status
Simulation time 776465552 ps
CPU time 5.8 seconds
Started Jun 29 07:29:24 PM PDT 24
Finished Jun 29 07:29:31 PM PDT 24
Peak memory 242160 kb
Host smart-0bd93bfd-aea3-478d-9d34-a9808e151aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769222684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.769222684
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3237722471
Short name T115
Test name
Test status
Simulation time 2391400545 ps
CPU time 7.64 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:30 PM PDT 24
Peak memory 241960 kb
Host smart-5020631a-b365-4b3f-b43b-7b4fd4bc53c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237722471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3237722471
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.646841322
Short name T610
Test name
Test status
Simulation time 475356482 ps
CPU time 5.16 seconds
Started Jun 29 07:29:21 PM PDT 24
Finished Jun 29 07:29:28 PM PDT 24
Peak memory 242388 kb
Host smart-353946a2-a900-4444-884b-80ebb8e196cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646841322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.646841322
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2953939406
Short name T252
Test name
Test status
Simulation time 140562593 ps
CPU time 1.74 seconds
Started Jun 29 07:26:48 PM PDT 24
Finished Jun 29 07:26:50 PM PDT 24
Peak memory 240508 kb
Host smart-95a4acd3-7d9f-4c75-9182-a0166039f92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953939406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2953939406
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.3578711669
Short name T858
Test name
Test status
Simulation time 189153489 ps
CPU time 5.64 seconds
Started Jun 29 07:26:46 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 242068 kb
Host smart-bf2955bb-d677-4ee5-a3dd-2c80e10295ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578711669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.3578711669
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3129355189
Short name T224
Test name
Test status
Simulation time 2807976268 ps
CPU time 16.85 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 242188 kb
Host smart-4306d64c-9af4-47bd-b430-2e3252702f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129355189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3129355189
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.2683903949
Short name T892
Test name
Test status
Simulation time 2420421751 ps
CPU time 7.81 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:26:51 PM PDT 24
Peak memory 242556 kb
Host smart-4ca397fe-8563-4873-b862-eab22203dffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683903949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2683903949
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2729906819
Short name T244
Test name
Test status
Simulation time 208970371 ps
CPU time 3.21 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:50 PM PDT 24
Peak memory 242012 kb
Host smart-296ac7af-9604-42c2-9ef2-33754319381c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729906819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2729906819
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.111064674
Short name T979
Test name
Test status
Simulation time 837654410 ps
CPU time 21.26 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:27:07 PM PDT 24
Peak memory 242900 kb
Host smart-d7196ace-0a51-473f-b718-8b30bd23f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111064674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.111064674
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.3789632622
Short name T1180
Test name
Test status
Simulation time 4469212942 ps
CPU time 49.6 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:27:35 PM PDT 24
Peak memory 242236 kb
Host smart-2a1e5288-3114-425f-af17-e77854a581fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789632622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.3789632622
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2111724909
Short name T442
Test name
Test status
Simulation time 272316290 ps
CPU time 6.81 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 241884 kb
Host smart-8c311cbc-9d1d-4bc3-b8c8-140ddcc7006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111724909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2111724909
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1375919702
Short name T473
Test name
Test status
Simulation time 2650138971 ps
CPU time 20.76 seconds
Started Jun 29 07:26:46 PM PDT 24
Finished Jun 29 07:27:08 PM PDT 24
Peak memory 241968 kb
Host smart-6bf9df35-b230-4cce-9219-f32b57a6fe58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375919702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1375919702
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.3736366805
Short name T987
Test name
Test status
Simulation time 217661685 ps
CPU time 2.96 seconds
Started Jun 29 07:26:47 PM PDT 24
Finished Jun 29 07:26:51 PM PDT 24
Peak memory 242020 kb
Host smart-e1cb2517-f886-42a0-9949-b45598e169c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3736366805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3736366805
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1004348762
Short name T884
Test name
Test status
Simulation time 385788886 ps
CPU time 7.3 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:50 PM PDT 24
Peak memory 242128 kb
Host smart-b4d5b55b-b35a-4da6-9f5b-12a19ae52465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004348762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1004348762
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.1168596884
Short name T113
Test name
Test status
Simulation time 807273592 ps
CPU time 36.19 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 248748 kb
Host smart-d8561543-9ebd-4b09-a559-c6df455c2b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168596884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.1168596884
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3514794105
Short name T160
Test name
Test status
Simulation time 189886233711 ps
CPU time 1655.2 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:54:19 PM PDT 24
Peak memory 511104 kb
Host smart-7940a043-cc9a-49c1-92cf-cc899d68a2fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514794105 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3514794105
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.354064089
Short name T1162
Test name
Test status
Simulation time 1725283434 ps
CPU time 18.47 seconds
Started Jun 29 07:26:47 PM PDT 24
Finished Jun 29 07:27:06 PM PDT 24
Peak memory 242420 kb
Host smart-745f8685-0c1b-40a6-8596-50bf36eae21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354064089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.354064089
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.928409446
Short name T1096
Test name
Test status
Simulation time 655645951 ps
CPU time 4.97 seconds
Started Jun 29 07:29:32 PM PDT 24
Finished Jun 29 07:29:37 PM PDT 24
Peak memory 242404 kb
Host smart-df3c5999-893e-4584-a5c8-68616e0391f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928409446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.928409446
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.3730432552
Short name T949
Test name
Test status
Simulation time 264587916 ps
CPU time 3.84 seconds
Started Jun 29 07:29:29 PM PDT 24
Finished Jun 29 07:29:34 PM PDT 24
Peak memory 242244 kb
Host smart-e0985dd6-847e-4557-8ffa-5cf0d475eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730432552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3730432552
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.2420720179
Short name T228
Test name
Test status
Simulation time 259934683 ps
CPU time 3.69 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:33 PM PDT 24
Peak memory 242396 kb
Host smart-a4a8dea1-8f66-4f45-bead-eae12de50232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420720179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2420720179
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.2787345426
Short name T450
Test name
Test status
Simulation time 389095375 ps
CPU time 4.34 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:34 PM PDT 24
Peak memory 241836 kb
Host smart-6664270b-81d4-466f-956d-8fbcb629fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787345426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2787345426
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.2000957212
Short name T125
Test name
Test status
Simulation time 130595306 ps
CPU time 3.43 seconds
Started Jun 29 07:29:31 PM PDT 24
Finished Jun 29 07:29:35 PM PDT 24
Peak memory 242184 kb
Host smart-cd886c2c-aff3-4f37-a595-9e7b95a7da4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000957212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2000957212
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3216310964
Short name T13
Test name
Test status
Simulation time 171518688 ps
CPU time 4.19 seconds
Started Jun 29 07:29:32 PM PDT 24
Finished Jun 29 07:29:37 PM PDT 24
Peak memory 242012 kb
Host smart-2300cb67-3019-4ba8-bccc-387e276c7b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216310964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3216310964
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1391773708
Short name T704
Test name
Test status
Simulation time 89834967 ps
CPU time 2.89 seconds
Started Jun 29 07:29:29 PM PDT 24
Finished Jun 29 07:29:32 PM PDT 24
Peak memory 241992 kb
Host smart-3a8d0c08-137b-47cb-891d-6788dd479cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391773708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1391773708
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2394654831
Short name T881
Test name
Test status
Simulation time 677808167 ps
CPU time 5.53 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:34 PM PDT 24
Peak memory 241932 kb
Host smart-0acb917c-ecc0-4756-b792-1aa9e8240da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394654831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2394654831
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.2469665768
Short name T1043
Test name
Test status
Simulation time 307982557 ps
CPU time 4.29 seconds
Started Jun 29 07:29:28 PM PDT 24
Finished Jun 29 07:29:34 PM PDT 24
Peak memory 242044 kb
Host smart-cd7cd7ce-dc67-46b3-a1f2-9fb29b02b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469665768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2469665768
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.2986546003
Short name T981
Test name
Test status
Simulation time 96474020 ps
CPU time 3.67 seconds
Started Jun 29 07:29:31 PM PDT 24
Finished Jun 29 07:29:35 PM PDT 24
Peak memory 242196 kb
Host smart-91cd6ddb-9440-43d3-a265-c0bb1996d81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986546003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2986546003
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.3809841089
Short name T487
Test name
Test status
Simulation time 134738790 ps
CPU time 1.98 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 240644 kb
Host smart-75235044-4ac7-4112-a6eb-d47fc9eea59b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809841089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3809841089
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.1407910847
Short name T322
Test name
Test status
Simulation time 12673313569 ps
CPU time 21.53 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:25:45 PM PDT 24
Peak memory 243028 kb
Host smart-916934f0-540f-4e18-9163-9ba5523f6824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407910847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.1407910847
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1579329436
Short name T56
Test name
Test status
Simulation time 514174364 ps
CPU time 8.22 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:34 PM PDT 24
Peak memory 248792 kb
Host smart-f73a1d7a-b6c9-4bb1-848c-d33208309907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579329436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1579329436
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.4095830607
Short name T361
Test name
Test status
Simulation time 1238059942 ps
CPU time 20.11 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:46 PM PDT 24
Peak memory 242220 kb
Host smart-8e1047a4-2817-4152-9c10-73ceb39b37ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095830607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.4095830607
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2413255157
Short name T398
Test name
Test status
Simulation time 3846509050 ps
CPU time 32.85 seconds
Started Jun 29 07:25:26 PM PDT 24
Finished Jun 29 07:26:01 PM PDT 24
Peak memory 242460 kb
Host smart-31141d9e-63ea-43f2-9129-faefbf36097a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413255157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2413255157
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1526552912
Short name T548
Test name
Test status
Simulation time 177487600 ps
CPU time 4.5 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:32 PM PDT 24
Peak memory 242028 kb
Host smart-ad08214b-6b4e-478d-8530-6448c97a3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526552912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1526552912
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.955576051
Short name T183
Test name
Test status
Simulation time 153427806 ps
CPU time 4.03 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:28 PM PDT 24
Peak memory 242536 kb
Host smart-889d8a25-f1fb-430c-ad7d-cac76c730eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955576051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.955576051
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.3803330701
Short name T685
Test name
Test status
Simulation time 6668870949 ps
CPU time 13.9 seconds
Started Jun 29 07:25:24 PM PDT 24
Finished Jun 29 07:25:39 PM PDT 24
Peak memory 248860 kb
Host smart-03cc3f18-30c0-44c0-8fa2-726da4be4e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803330701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.3803330701
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2152581084
Short name T465
Test name
Test status
Simulation time 430955259 ps
CPU time 3.39 seconds
Started Jun 29 07:25:27 PM PDT 24
Finished Jun 29 07:25:31 PM PDT 24
Peak memory 241912 kb
Host smart-7b2dee10-b701-4c8e-8113-8f72ae6f57de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152581084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2152581084
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1936207570
Short name T1026
Test name
Test status
Simulation time 646896386 ps
CPU time 23.02 seconds
Started Jun 29 07:25:25 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 242240 kb
Host smart-bd76adb3-aac9-4929-9309-e5919a9d97e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936207570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1936207570
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.4085152836
Short name T377
Test name
Test status
Simulation time 483174524 ps
CPU time 6.24 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:39 PM PDT 24
Peak memory 241972 kb
Host smart-32c14120-3316-4b89-8096-e3b928b04580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085152836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4085152836
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3638058381
Short name T250
Test name
Test status
Simulation time 43320843027 ps
CPU time 221.79 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:29:19 PM PDT 24
Peak memory 274204 kb
Host smart-e92ff087-8d3b-4409-b2fa-27d26e033cb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638058381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3638058381
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.625194759
Short name T1100
Test name
Test status
Simulation time 212416257 ps
CPU time 3.77 seconds
Started Jun 29 07:25:23 PM PDT 24
Finished Jun 29 07:25:27 PM PDT 24
Peak memory 248072 kb
Host smart-4a1851cb-34bb-4f06-afe1-1c9cec947882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625194759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.625194759
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.579248702
Short name T142
Test name
Test status
Simulation time 62930898647 ps
CPU time 736.45 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:37:53 PM PDT 24
Peak memory 275236 kb
Host smart-f5195150-03db-4ce3-90ba-3d227e7c0f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579248702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.579248702
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3733530494
Short name T350
Test name
Test status
Simulation time 195578336205 ps
CPU time 413.53 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:32:29 PM PDT 24
Peak memory 272364 kb
Host smart-9bc30159-741e-4dfe-a710-4073e800e822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733530494 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3733530494
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.2165965228
Short name T445
Test name
Test status
Simulation time 9801209574 ps
CPU time 14.97 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 243328 kb
Host smart-9fe049f7-805f-4173-822d-f86d3ac32350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165965228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2165965228
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2211284101
Short name T1069
Test name
Test status
Simulation time 113978539 ps
CPU time 2.33 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:26:48 PM PDT 24
Peak memory 240420 kb
Host smart-a3f2c69e-644c-4f83-98cd-0b9542c0850f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211284101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2211284101
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.3871596159
Short name T145
Test name
Test status
Simulation time 809266929 ps
CPU time 12.59 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 242576 kb
Host smart-e5446ef5-b5f7-4a99-81cd-219c74bd91d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871596159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3871596159
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.2740332338
Short name T628
Test name
Test status
Simulation time 823798360 ps
CPU time 26.67 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:13 PM PDT 24
Peak memory 241936 kb
Host smart-0e8320a1-5a44-4da0-a832-1fa974531e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740332338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.2740332338
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.1852814603
Short name T748
Test name
Test status
Simulation time 1243567289 ps
CPU time 20.26 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:27:07 PM PDT 24
Peak memory 241468 kb
Host smart-a02456ab-1129-483e-b2e1-7da74ad201c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852814603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.1852814603
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.369644454
Short name T1095
Test name
Test status
Simulation time 229255428 ps
CPU time 4.57 seconds
Started Jun 29 07:26:48 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 242268 kb
Host smart-7783d925-84d9-4f4f-8d07-c1fdce7833d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369644454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.369644454
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.1388961891
Short name T667
Test name
Test status
Simulation time 9109286762 ps
CPU time 18.65 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:27:04 PM PDT 24
Peak memory 244048 kb
Host smart-b3d89ede-e3b2-4f0d-b194-9e11df197dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388961891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1388961891
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3902046727
Short name T523
Test name
Test status
Simulation time 523351227 ps
CPU time 3.52 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:50 PM PDT 24
Peak memory 242376 kb
Host smart-e8fb5719-3b2b-499d-b639-223ea5e5fded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902046727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3902046727
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.4184686132
Short name T897
Test name
Test status
Simulation time 478337621 ps
CPU time 5.46 seconds
Started Jun 29 07:26:46 PM PDT 24
Finished Jun 29 07:26:53 PM PDT 24
Peak memory 242272 kb
Host smart-bdb38d48-6a68-4719-882d-7dd585e82964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184686132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.4184686132
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1241820908
Short name T931
Test name
Test status
Simulation time 1009651466 ps
CPU time 16.24 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:59 PM PDT 24
Peak memory 242572 kb
Host smart-19e2051a-9fba-4784-95e3-b7a5c9ccc3d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241820908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1241820908
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.552359737
Short name T756
Test name
Test status
Simulation time 386926277 ps
CPU time 6.69 seconds
Started Jun 29 07:26:41 PM PDT 24
Finished Jun 29 07:26:49 PM PDT 24
Peak memory 242104 kb
Host smart-2b2f39f9-b94d-4644-9336-a2d362521c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552359737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.552359737
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.1454663530
Short name T642
Test name
Test status
Simulation time 223079096 ps
CPU time 5.67 seconds
Started Jun 29 07:26:42 PM PDT 24
Finished Jun 29 07:26:48 PM PDT 24
Peak memory 242280 kb
Host smart-a9d1c1a8-a4f1-4982-9dac-2933728d8f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454663530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1454663530
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.437991194
Short name T153
Test name
Test status
Simulation time 119835999970 ps
CPU time 183.87 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:29:47 PM PDT 24
Peak memory 265772 kb
Host smart-a6aeb5a1-b746-4ffa-aea1-00c41cdbff59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437991194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.
437991194
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.1861311905
Short name T270
Test name
Test status
Simulation time 120201633318 ps
CPU time 1527.99 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:52:12 PM PDT 24
Peak memory 330452 kb
Host smart-9b9c4c31-ed74-4354-b6c0-2eb37239acf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861311905 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.1861311905
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.176057230
Short name T549
Test name
Test status
Simulation time 3017243309 ps
CPU time 17.21 seconds
Started Jun 29 07:26:44 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 242448 kb
Host smart-3cea1137-074b-4790-b544-88ae81407ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176057230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.176057230
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.2533698589
Short name T700
Test name
Test status
Simulation time 623922516 ps
CPU time 1.81 seconds
Started Jun 29 07:26:54 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 240184 kb
Host smart-057b2e6c-57ec-49e0-89b2-5d0df9d797db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533698589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2533698589
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.4183032751
Short name T50
Test name
Test status
Simulation time 15802435775 ps
CPU time 28.89 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 248868 kb
Host smart-7c770784-e269-41f3-84aa-d6b4a722dabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183032751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.4183032751
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1581318813
Short name T1097
Test name
Test status
Simulation time 261237231 ps
CPU time 12.83 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 242204 kb
Host smart-44c1dfc3-0a95-4461-95c6-ed2a0b932993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581318813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1581318813
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1633306707
Short name T412
Test name
Test status
Simulation time 412164691 ps
CPU time 4.79 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242252 kb
Host smart-203fc1df-2e60-44e1-bc7b-8e57d4f5a8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633306707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1633306707
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.3008889135
Short name T786
Test name
Test status
Simulation time 1782778407 ps
CPU time 4.17 seconds
Started Jun 29 07:26:43 PM PDT 24
Finished Jun 29 07:26:47 PM PDT 24
Peak memory 242100 kb
Host smart-3806d0a2-a08b-4d1d-b144-ce91deb925a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008889135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.3008889135
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.3757051878
Short name T1083
Test name
Test status
Simulation time 170338076 ps
CPU time 3.1 seconds
Started Jun 29 07:26:55 PM PDT 24
Finished Jun 29 07:26:59 PM PDT 24
Peak memory 242212 kb
Host smart-b63c5e15-b0f0-4f72-806e-606b2582fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757051878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3757051878
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.3071934670
Short name T927
Test name
Test status
Simulation time 16568640881 ps
CPU time 31.51 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:27:23 PM PDT 24
Peak memory 243492 kb
Host smart-26ff4064-c3b2-48b7-a60b-231281b327ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071934670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3071934670
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2043235863
Short name T1033
Test name
Test status
Simulation time 1652295598 ps
CPU time 4.77 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 241900 kb
Host smart-d9e2a645-3823-464a-8706-c27c603fe8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043235863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2043235863
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.765572752
Short name T761
Test name
Test status
Simulation time 2095143692 ps
CPU time 4.36 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 242104 kb
Host smart-ba092caa-5c8f-43c4-9aef-7fd776c5a9ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765572752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.765572752
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.1217317026
Short name T600
Test name
Test status
Simulation time 161613059 ps
CPU time 6.15 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242040 kb
Host smart-bc17ef10-2fe7-4c7d-aa4f-77fb0149e53f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1217317026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1217317026
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.3511226157
Short name T817
Test name
Test status
Simulation time 1581658123 ps
CPU time 12 seconds
Started Jun 29 07:26:45 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242228 kb
Host smart-f681f07d-ec14-456c-9ddd-bc4391b8d00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511226157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.3511226157
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3813032341
Short name T730
Test name
Test status
Simulation time 146810312739 ps
CPU time 1684.78 seconds
Started Jun 29 07:26:56 PM PDT 24
Finished Jun 29 07:55:02 PM PDT 24
Peak memory 275288 kb
Host smart-1914b168-2e96-4ad8-adc0-71157fdfaa52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813032341 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3813032341
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.2155074109
Short name T793
Test name
Test status
Simulation time 2204068820 ps
CPU time 15.6 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:27:07 PM PDT 24
Peak memory 242488 kb
Host smart-d209e06c-9424-4459-af1b-bce181d274db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155074109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.2155074109
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.369870706
Short name T896
Test name
Test status
Simulation time 175323995 ps
CPU time 2.78 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 240420 kb
Host smart-c44468d2-e459-4454-9e23-abc770df11ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369870706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.369870706
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.780790180
Short name T771
Test name
Test status
Simulation time 3938720214 ps
CPU time 37.15 seconds
Started Jun 29 07:26:53 PM PDT 24
Finished Jun 29 07:27:31 PM PDT 24
Peak memory 248336 kb
Host smart-814a2c8d-07dc-4a0a-a64e-eca1ef1e515e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780790180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.780790180
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.3140922622
Short name T1013
Test name
Test status
Simulation time 3805393171 ps
CPU time 25.7 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 242484 kb
Host smart-8d6dc714-11c0-4fe9-bf14-d64a38bd529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140922622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3140922622
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.1999637625
Short name T97
Test name
Test status
Simulation time 231029830 ps
CPU time 4.32 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 241928 kb
Host smart-3232538c-7928-48ee-a08d-ed7a2fbbc136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999637625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1999637625
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.3353857023
Short name T818
Test name
Test status
Simulation time 1310287490 ps
CPU time 28.16 seconds
Started Jun 29 07:26:56 PM PDT 24
Finished Jun 29 07:27:24 PM PDT 24
Peak memory 243896 kb
Host smart-3a09a5c4-b300-4324-b225-40275b75c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353857023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3353857023
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2090114249
Short name T633
Test name
Test status
Simulation time 2276671851 ps
CPU time 27.9 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 242392 kb
Host smart-1e1058e5-97cd-48bf-bcec-36cdf8ad9004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090114249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2090114249
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.968293891
Short name T914
Test name
Test status
Simulation time 524095910 ps
CPU time 3.99 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 241948 kb
Host smart-2869f14f-1105-4852-b6f2-a58b8186bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968293891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.968293891
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.3458440695
Short name T623
Test name
Test status
Simulation time 1291306817 ps
CPU time 20.82 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:27:13 PM PDT 24
Peak memory 242232 kb
Host smart-a78dd64d-3df3-462a-9003-878204942aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458440695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.3458440695
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.3645158643
Short name T967
Test name
Test status
Simulation time 5307411058 ps
CPU time 12.31 seconds
Started Jun 29 07:26:56 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 242476 kb
Host smart-701c6ab7-fa69-435b-9f8f-53fdaf5528dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3645158643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.3645158643
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.3340643977
Short name T823
Test name
Test status
Simulation time 1175537951 ps
CPU time 11.88 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 242176 kb
Host smart-b588fc50-baaa-4c1a-9232-5bdfd725da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340643977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3340643977
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.808131643
Short name T289
Test name
Test status
Simulation time 18427887802 ps
CPU time 111.45 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:28:44 PM PDT 24
Peak memory 248804 kb
Host smart-2ab5f979-273d-4b29-9945-4420560deaa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808131643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.
808131643
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2798881227
Short name T1155
Test name
Test status
Simulation time 150358245295 ps
CPU time 1028.18 seconds
Started Jun 29 07:26:53 PM PDT 24
Finished Jun 29 07:44:02 PM PDT 24
Peak memory 294544 kb
Host smart-4647e6bd-b4bb-4b2c-ab60-336ded0970bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798881227 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2798881227
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.3402238539
Short name T461
Test name
Test status
Simulation time 787016364 ps
CPU time 14.13 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 248800 kb
Host smart-a96e8ad0-4c30-4a39-88c9-e8be468e97dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402238539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.3402238539
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.460722616
Short name T738
Test name
Test status
Simulation time 613689464 ps
CPU time 1.7 seconds
Started Jun 29 07:26:53 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 240408 kb
Host smart-dc872192-9ebe-4ce9-ba35-9d630611be87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460722616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.460722616
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2069554879
Short name T85
Test name
Test status
Simulation time 1084271709 ps
CPU time 11.94 seconds
Started Jun 29 07:26:53 PM PDT 24
Finished Jun 29 07:27:06 PM PDT 24
Peak memory 242684 kb
Host smart-40a4b0bb-3828-46ac-a74f-f9971a460d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069554879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2069554879
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1598578743
Short name T873
Test name
Test status
Simulation time 621460501 ps
CPU time 19.11 seconds
Started Jun 29 07:26:49 PM PDT 24
Finished Jun 29 07:27:08 PM PDT 24
Peak memory 242052 kb
Host smart-e9df6d2e-b67e-4a97-bf5b-5505d64b2779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598578743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1598578743
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.1886577067
Short name T903
Test name
Test status
Simulation time 323293328 ps
CPU time 6.58 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:27:00 PM PDT 24
Peak memory 242084 kb
Host smart-4b95f0d5-1b39-4773-8752-f1e297849f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886577067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1886577067
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.1403341860
Short name T566
Test name
Test status
Simulation time 432287426 ps
CPU time 4.03 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:26:57 PM PDT 24
Peak memory 242512 kb
Host smart-888403da-df57-4b97-9adc-e4678aaa02a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403341860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.1403341860
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.967562276
Short name T4
Test name
Test status
Simulation time 6543649974 ps
CPU time 68.28 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:28:00 PM PDT 24
Peak memory 257108 kb
Host smart-4953ff2a-0c76-4bde-8b8b-50d82a78f6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967562276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.967562276
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.1233363280
Short name T954
Test name
Test status
Simulation time 410880314 ps
CPU time 17.19 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:27:11 PM PDT 24
Peak memory 241976 kb
Host smart-3c9e5c20-1368-464b-a031-abc385b1fbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233363280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.1233363280
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.3332398543
Short name T557
Test name
Test status
Simulation time 2368097228 ps
CPU time 5.87 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:57 PM PDT 24
Peak memory 241852 kb
Host smart-d14632b7-183f-4b85-9226-49e07fc5164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332398543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3332398543
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1154392672
Short name T629
Test name
Test status
Simulation time 638734297 ps
CPU time 15.42 seconds
Started Jun 29 07:26:54 PM PDT 24
Finished Jun 29 07:27:10 PM PDT 24
Peak memory 242012 kb
Host smart-1799a99a-27be-4f6d-98c3-bd548ce3e286
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154392672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1154392672
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.1710805510
Short name T751
Test name
Test status
Simulation time 1529237190 ps
CPU time 5.69 seconds
Started Jun 29 07:26:50 PM PDT 24
Finished Jun 29 07:26:56 PM PDT 24
Peak memory 242216 kb
Host smart-c7f7c08d-6b7e-4819-be0e-1aac4cfa69f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1710805510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1710805510
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2875315892
Short name T1002
Test name
Test status
Simulation time 227199765 ps
CPU time 4.7 seconds
Started Jun 29 07:26:49 PM PDT 24
Finished Jun 29 07:26:55 PM PDT 24
Peak memory 248416 kb
Host smart-a27b9a00-7753-40d3-b10a-b5cc4f31d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875315892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2875315892
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.3379405883
Short name T118
Test name
Test status
Simulation time 28339680352 ps
CPU time 151.65 seconds
Started Jun 29 07:26:53 PM PDT 24
Finished Jun 29 07:29:25 PM PDT 24
Peak memory 247532 kb
Host smart-53c171ad-62e3-4f54-8985-c3b3b61e6d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379405883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.3379405883
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2639146935
Short name T286
Test name
Test status
Simulation time 98229777204 ps
CPU time 396.24 seconds
Started Jun 29 07:26:48 PM PDT 24
Finished Jun 29 07:33:25 PM PDT 24
Peak memory 258296 kb
Host smart-3f1cbba8-836d-4181-b96c-0a7fe6fe245e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639146935 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.2639146935
Directory /workspace/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.1161280135
Short name T1111
Test name
Test status
Simulation time 4873727425 ps
CPU time 49.82 seconds
Started Jun 29 07:26:52 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 242552 kb
Host smart-2e5820f6-72ca-40c4-8bf1-39c012c92608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161280135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.1161280135
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.4100399918
Short name T635
Test name
Test status
Simulation time 155927030 ps
CPU time 1.79 seconds
Started Jun 29 07:26:59 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 240100 kb
Host smart-d554fd50-a3c7-49ee-8e89-84a39dc10e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100399918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.4100399918
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.2102533556
Short name T991
Test name
Test status
Simulation time 3271369035 ps
CPU time 21.17 seconds
Started Jun 29 07:26:56 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 248872 kb
Host smart-c9772b14-2425-4bcc-b892-732a169a4002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102533556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.2102533556
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3249734174
Short name T1016
Test name
Test status
Simulation time 1168167564 ps
CPU time 21.6 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:22 PM PDT 24
Peak memory 242132 kb
Host smart-b57fc9f2-5163-4e36-939e-501297cf3bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249734174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3249734174
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.1259183341
Short name T916
Test name
Test status
Simulation time 1156893325 ps
CPU time 11.25 seconds
Started Jun 29 07:27:01 PM PDT 24
Finished Jun 29 07:27:13 PM PDT 24
Peak memory 242268 kb
Host smart-f11d8945-f3b7-475a-9cab-992c14578dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259183341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1259183341
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.812897357
Short name T508
Test name
Test status
Simulation time 1506049023 ps
CPU time 5.83 seconds
Started Jun 29 07:27:00 PM PDT 24
Finished Jun 29 07:27:08 PM PDT 24
Peak memory 242096 kb
Host smart-84d2a79e-9fb8-48c9-961c-4143fffe423a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812897357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.812897357
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.621723276
Short name T812
Test name
Test status
Simulation time 338238538 ps
CPU time 4.95 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 242112 kb
Host smart-693f5900-ec31-441a-aa07-3e3613359325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621723276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.621723276
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.586085697
Short name T240
Test name
Test status
Simulation time 642951956 ps
CPU time 13.57 seconds
Started Jun 29 07:26:57 PM PDT 24
Finished Jun 29 07:27:11 PM PDT 24
Peak memory 242352 kb
Host smart-ed2fdd26-c4d1-4bd1-99bb-d3a2071c75d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586085697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.586085697
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.1612595530
Short name T219
Test name
Test status
Simulation time 256008867 ps
CPU time 6.05 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:06 PM PDT 24
Peak memory 241896 kb
Host smart-7f5a60cb-2396-4ba4-b729-7737f3b0be7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612595530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1612595530
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.3798326113
Short name T1154
Test name
Test status
Simulation time 2631834653 ps
CPU time 17.87 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 248800 kb
Host smart-bceee538-593f-4f4a-aea9-73ed0cbc18a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798326113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.3798326113
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.4054843511
Short name T998
Test name
Test status
Simulation time 133116494 ps
CPU time 4.41 seconds
Started Jun 29 07:26:59 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 242216 kb
Host smart-1bd15096-7add-4d5a-b4f6-8b620a8b27ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054843511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.4054843511
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1839225335
Short name T441
Test name
Test status
Simulation time 479588601 ps
CPU time 5.82 seconds
Started Jun 29 07:26:51 PM PDT 24
Finished Jun 29 07:26:58 PM PDT 24
Peak memory 242232 kb
Host smart-7f5cd2f0-1ad6-4154-aa23-520d2848c923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839225335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1839225335
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.2799309935
Short name T777
Test name
Test status
Simulation time 3532869518 ps
CPU time 76.49 seconds
Started Jun 29 07:27:00 PM PDT 24
Finished Jun 29 07:28:18 PM PDT 24
Peak memory 248872 kb
Host smart-bd4192eb-6393-4c7f-b677-a256468efdeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799309935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.2799309935
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1898120270
Short name T295
Test name
Test status
Simulation time 954145003998 ps
CPU time 3314.75 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 08:22:15 PM PDT 24
Peak memory 342776 kb
Host smart-244f7593-53a0-42b7-b807-b3215a067fc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898120270 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.1898120270
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.435690199
Short name T19
Test name
Test status
Simulation time 3636034201 ps
CPU time 38.12 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:38 PM PDT 24
Peak memory 248872 kb
Host smart-ae264600-4dc2-40e8-8d7c-5271da17d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435690199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.435690199
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.372692136
Short name T308
Test name
Test status
Simulation time 727874698 ps
CPU time 2.62 seconds
Started Jun 29 07:26:59 PM PDT 24
Finished Jun 29 07:27:03 PM PDT 24
Peak memory 240572 kb
Host smart-7c9d84f7-28a1-41a4-87a4-635819a0f0e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372692136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.372692136
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.1565904212
Short name T55
Test name
Test status
Simulation time 8079883978 ps
CPU time 54.2 seconds
Started Jun 29 07:27:01 PM PDT 24
Finished Jun 29 07:27:56 PM PDT 24
Peak memory 248824 kb
Host smart-f2fb14bd-b8a3-49a1-89c5-1f32243de187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565904212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.1565904212
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.4127008522
Short name T533
Test name
Test status
Simulation time 339509059 ps
CPU time 21.66 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:22 PM PDT 24
Peak memory 241920 kb
Host smart-f58f646c-baec-47ea-b425-b2157bea1a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127008522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.4127008522
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2987124207
Short name T770
Test name
Test status
Simulation time 12130220089 ps
CPU time 44.23 seconds
Started Jun 29 07:26:59 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 242336 kb
Host smart-b2eb6fed-1a05-49e0-b553-1511a568012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987124207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2987124207
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.3215048171
Short name T1165
Test name
Test status
Simulation time 1882650027 ps
CPU time 3.49 seconds
Started Jun 29 07:26:57 PM PDT 24
Finished Jun 29 07:27:01 PM PDT 24
Peak memory 242072 kb
Host smart-94f88c5a-814a-4817-a0ff-f281e705bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215048171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3215048171
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.1519979314
Short name T856
Test name
Test status
Simulation time 1632741786 ps
CPU time 18.13 seconds
Started Jun 29 07:27:00 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 242528 kb
Host smart-1959bcc0-baff-47de-8ae8-83bd782c6d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519979314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.1519979314
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3262530173
Short name T972
Test name
Test status
Simulation time 557011985 ps
CPU time 7.57 seconds
Started Jun 29 07:27:00 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 242400 kb
Host smart-fed0b8cb-0f8f-4935-82fb-fe99a0303c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262530173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3262530173
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.4139451333
Short name T670
Test name
Test status
Simulation time 220897087 ps
CPU time 4.06 seconds
Started Jun 29 07:26:56 PM PDT 24
Finished Jun 29 07:27:01 PM PDT 24
Peak memory 241824 kb
Host smart-318140a2-7930-42f0-a761-795de5afd55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139451333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.4139451333
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2540520701
Short name T993
Test name
Test status
Simulation time 219642410 ps
CPU time 6.37 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:05 PM PDT 24
Peak memory 242220 kb
Host smart-ebde9aef-f412-48fd-8361-a9e8c2868162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2540520701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2540520701
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.1666149073
Short name T561
Test name
Test status
Simulation time 153364681 ps
CPU time 5.7 seconds
Started Jun 29 07:26:59 PM PDT 24
Finished Jun 29 07:27:06 PM PDT 24
Peak memory 242284 kb
Host smart-8e24c0a7-d206-4d12-8905-ea04745e609d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666149073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1666149073
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1056007462
Short name T696
Test name
Test status
Simulation time 714361381 ps
CPU time 8.79 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 242400 kb
Host smart-fec02602-933f-4693-929d-28eb5b8284e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056007462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1056007462
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.2214590122
Short name T830
Test name
Test status
Simulation time 11430429423 ps
CPU time 152.69 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:29:33 PM PDT 24
Peak memory 249292 kb
Host smart-50ad51ae-02bb-4886-a591-34b93f80ac7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214590122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.2214590122
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1393157085
Short name T1189
Test name
Test status
Simulation time 1276589791529 ps
CPU time 2594.57 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 08:10:15 PM PDT 24
Peak memory 514208 kb
Host smart-57ad081c-1a8f-4dff-9720-9da9959b20f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393157085 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1393157085
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.4189439362
Short name T714
Test name
Test status
Simulation time 1265318027 ps
CPU time 17.5 seconds
Started Jun 29 07:26:58 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 242572 kb
Host smart-06a1da3d-e88f-447f-ab32-46281684e0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189439362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.4189439362
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.2478702757
Short name T734
Test name
Test status
Simulation time 224135222 ps
CPU time 1.99 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:10 PM PDT 24
Peak memory 240176 kb
Host smart-9fa9b317-72f2-46fd-b463-f869241740b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478702757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2478702757
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.3531578018
Short name T1173
Test name
Test status
Simulation time 892025366 ps
CPU time 11.66 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 248784 kb
Host smart-f5fe73e2-93d0-4d45-9065-0cbca634e65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531578018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3531578018
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.1134532453
Short name T671
Test name
Test status
Simulation time 339994050 ps
CPU time 20.53 seconds
Started Jun 29 07:27:05 PM PDT 24
Finished Jun 29 07:27:26 PM PDT 24
Peak memory 241852 kb
Host smart-b5f248e6-02ac-47f6-9c1c-8e6d3da66ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134532453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1134532453
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.4019057588
Short name T636
Test name
Test status
Simulation time 1191868105 ps
CPU time 11.36 seconds
Started Jun 29 07:27:04 PM PDT 24
Finished Jun 29 07:27:16 PM PDT 24
Peak memory 242316 kb
Host smart-f5632432-d6eb-49bd-9b18-170e54750d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019057588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.4019057588
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.1121647317
Short name T123
Test name
Test status
Simulation time 109872977 ps
CPU time 4.54 seconds
Started Jun 29 07:27:08 PM PDT 24
Finished Jun 29 07:27:13 PM PDT 24
Peak memory 242208 kb
Host smart-7ba22d37-ee50-4d2e-bdf4-5b431aa5bb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121647317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1121647317
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.3283769434
Short name T98
Test name
Test status
Simulation time 5334182306 ps
CPU time 31.15 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 246380 kb
Host smart-1d41655b-d36d-4543-a50e-078431e18c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283769434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3283769434
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.1365341039
Short name T716
Test name
Test status
Simulation time 713619877 ps
CPU time 14.19 seconds
Started Jun 29 07:27:05 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 242540 kb
Host smart-d8faa74e-9a66-4477-9469-7916f07bd25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365341039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.1365341039
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.4177552805
Short name T951
Test name
Test status
Simulation time 140401045 ps
CPU time 5.88 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:14 PM PDT 24
Peak memory 241960 kb
Host smart-9b794487-174e-45f4-866d-6c24f3819932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177552805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.4177552805
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.3301847403
Short name T664
Test name
Test status
Simulation time 763516537 ps
CPU time 18.08 seconds
Started Jun 29 07:27:06 PM PDT 24
Finished Jun 29 07:27:24 PM PDT 24
Peak memory 248752 kb
Host smart-664afad1-44f9-4575-a6cb-89993c11f0d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301847403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3301847403
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.3814238909
Short name T381
Test name
Test status
Simulation time 249534595 ps
CPU time 4.31 seconds
Started Jun 29 07:27:04 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 242048 kb
Host smart-2a3bded4-1925-46fd-8889-3ac618920569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814238909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3814238909
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.4218549178
Short name T482
Test name
Test status
Simulation time 3003587813 ps
CPU time 6.16 seconds
Started Jun 29 07:27:06 PM PDT 24
Finished Jun 29 07:27:13 PM PDT 24
Peak memory 242136 kb
Host smart-cea46943-6e27-46e8-a71b-aa23d5672115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218549178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.4218549178
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.1118380009
Short name T859
Test name
Test status
Simulation time 1992194533 ps
CPU time 42.48 seconds
Started Jun 29 07:27:06 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 245364 kb
Host smart-9b113712-ffaf-46ac-b038-e0a37fc53383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118380009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.1118380009
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.360562109
Short name T400
Test name
Test status
Simulation time 47311697439 ps
CPU time 1417.97 seconds
Started Jun 29 07:27:06 PM PDT 24
Finished Jun 29 07:50:45 PM PDT 24
Peak memory 329996 kb
Host smart-227a17e2-334f-4bd1-9491-2349477070ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360562109 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.360562109
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.3518850795
Short name T933
Test name
Test status
Simulation time 3287835938 ps
CPU time 31.27 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 242200 kb
Host smart-2d556cbc-e399-474d-a324-22eb6177dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518850795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3518850795
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.3759761737
Short name T531
Test name
Test status
Simulation time 852566587 ps
CPU time 3.15 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 240164 kb
Host smart-e0240f41-47be-47bc-9518-b843ea08ca55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759761737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3759761737
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.311924553
Short name T518
Test name
Test status
Simulation time 192304017 ps
CPU time 2.72 seconds
Started Jun 29 07:27:06 PM PDT 24
Finished Jun 29 07:27:09 PM PDT 24
Peak memory 242612 kb
Host smart-c395fa47-2bcc-4fee-a00d-c0f48f84064a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311924553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.311924553
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.1052953702
Short name T360
Test name
Test status
Simulation time 9102947229 ps
CPU time 25.63 seconds
Started Jun 29 07:27:05 PM PDT 24
Finished Jun 29 07:27:32 PM PDT 24
Peak memory 241980 kb
Host smart-59856ec4-b5c7-4463-8db6-56c657d8c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052953702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1052953702
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.2458485094
Short name T501
Test name
Test status
Simulation time 1015816087 ps
CPU time 16.61 seconds
Started Jun 29 07:27:04 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 242544 kb
Host smart-b14e0acc-b328-4c38-85f9-4f27da692902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458485094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.2458485094
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.2390115497
Short name T112
Test name
Test status
Simulation time 1656025268 ps
CPU time 4.26 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:12 PM PDT 24
Peak memory 242080 kb
Host smart-55d9d4a9-f2d6-4c33-9bd6-9f4546963c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390115497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2390115497
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.448607303
Short name T209
Test name
Test status
Simulation time 896681963 ps
CPU time 21.89 seconds
Started Jun 29 07:27:10 PM PDT 24
Finished Jun 29 07:27:32 PM PDT 24
Peak memory 242572 kb
Host smart-f5294c5d-d0fc-4651-a754-8c8eb04bd58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448607303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.448607303
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.1150802080
Short name T395
Test name
Test status
Simulation time 438709960 ps
CPU time 11.02 seconds
Started Jun 29 07:27:09 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 242312 kb
Host smart-994e99e1-da4e-490b-a8cb-d36bfe7e1a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150802080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.1150802080
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.3692302685
Short name T943
Test name
Test status
Simulation time 4671481062 ps
CPU time 34.89 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 243100 kb
Host smart-08584476-d17a-4c8f-a65a-febe30eb5f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692302685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3692302685
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.114337876
Short name T526
Test name
Test status
Simulation time 2035379081 ps
CPU time 5.53 seconds
Started Jun 29 07:27:07 PM PDT 24
Finished Jun 29 07:27:14 PM PDT 24
Peak memory 241628 kb
Host smart-73df249d-4dd1-421e-8a22-befdeb4f6ebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114337876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.114337876
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.1455535576
Short name T299
Test name
Test status
Simulation time 403857034 ps
CPU time 7.02 seconds
Started Jun 29 07:27:09 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 242216 kb
Host smart-f2cd2eb6-1ca7-403f-800c-c571de3e2310
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455535576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.1455535576
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.1489051077
Short name T419
Test name
Test status
Simulation time 304744299 ps
CPU time 6.62 seconds
Started Jun 29 07:27:05 PM PDT 24
Finished Jun 29 07:27:12 PM PDT 24
Peak memory 242344 kb
Host smart-734b715e-ca20-4122-b95b-91dd7aca1783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489051077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1489051077
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2361154788
Short name T1046
Test name
Test status
Simulation time 1814848579 ps
CPU time 23.52 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 243424 kb
Host smart-7b3f6af0-d7c5-42a0-a27e-f1c3c09faa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361154788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2361154788
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.1929508463
Short name T621
Test name
Test status
Simulation time 1116445353 ps
CPU time 10.5 seconds
Started Jun 29 07:27:05 PM PDT 24
Finished Jun 29 07:27:16 PM PDT 24
Peak memory 242088 kb
Host smart-4f4787c6-6910-400c-a8c6-6501497ce05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929508463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.1929508463
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.2945052345
Short name T1115
Test name
Test status
Simulation time 748124814 ps
CPU time 2.6 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:27:17 PM PDT 24
Peak memory 240200 kb
Host smart-773e2ebd-6bc8-4b4e-86c0-219443c1ed23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945052345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.2945052345
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3023443038
Short name T1152
Test name
Test status
Simulation time 633099139 ps
CPU time 9.72 seconds
Started Jun 29 07:27:16 PM PDT 24
Finished Jun 29 07:27:26 PM PDT 24
Peak memory 249012 kb
Host smart-c704193c-69cb-4b1d-9f9d-b753eb83c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023443038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3023443038
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.626627318
Short name T595
Test name
Test status
Simulation time 1885074470 ps
CPU time 33.65 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:48 PM PDT 24
Peak memory 244496 kb
Host smart-21ccf7c7-f77a-4917-9a6b-4119f03b96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626627318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.626627318
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.1796940910
Short name T405
Test name
Test status
Simulation time 442219943 ps
CPU time 15.51 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:29 PM PDT 24
Peak memory 242340 kb
Host smart-ba90efa9-3cb6-4003-be06-c0e36ab89d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796940910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1796940910
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.149983966
Short name T821
Test name
Test status
Simulation time 337679329 ps
CPU time 4.61 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:27:19 PM PDT 24
Peak memory 241924 kb
Host smart-48bfb46c-4aca-4e43-9872-fbaaffa89406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149983966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.149983966
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.186230552
Short name T454
Test name
Test status
Simulation time 262932200 ps
CPU time 4.82 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:27:19 PM PDT 24
Peak memory 248812 kb
Host smart-44381bd5-43a6-4fd9-8bc8-eb3b70a6029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186230552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.186230552
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1127834946
Short name T565
Test name
Test status
Simulation time 1445251556 ps
CPU time 24.87 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:27:40 PM PDT 24
Peak memory 242264 kb
Host smart-2302aaf8-9cb4-4c55-9560-e65e64cfc78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127834946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1127834946
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.2097868169
Short name T467
Test name
Test status
Simulation time 614580694 ps
CPU time 16.09 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:27:32 PM PDT 24
Peak memory 242584 kb
Host smart-09e1dd88-f358-4e8d-ad8f-6f299ba2ca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097868169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2097868169
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.3278625664
Short name T1163
Test name
Test status
Simulation time 845513992 ps
CPU time 16.83 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:31 PM PDT 24
Peak memory 242236 kb
Host smart-8b9e0a8e-934d-4547-9b32-de8413dde75b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3278625664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3278625664
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.2474030724
Short name T952
Test name
Test status
Simulation time 160578003 ps
CPU time 6.11 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 242476 kb
Host smart-62150ac2-2eaa-4def-98cb-899edb224937
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2474030724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2474030724
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.2514289476
Short name T1047
Test name
Test status
Simulation time 1419666725 ps
CPU time 10.55 seconds
Started Jun 29 07:27:12 PM PDT 24
Finished Jun 29 07:27:22 PM PDT 24
Peak memory 242148 kb
Host smart-74a9d3ad-201d-4759-8256-fa584038c277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514289476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2514289476
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.560539943
Short name T401
Test name
Test status
Simulation time 28087808243 ps
CPU time 200.19 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:30:35 PM PDT 24
Peak memory 248808 kb
Host smart-7fbbe415-4648-48a4-b389-ddeca3e3f3af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560539943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.
560539943
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.702109305
Short name T844
Test name
Test status
Simulation time 669178141603 ps
CPU time 1259.57 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:48:16 PM PDT 24
Peak memory 313612 kb
Host smart-28ed0c13-71f9-4e1c-b9b7-9038527335e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702109305 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.702109305
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3847704223
Short name T820
Test name
Test status
Simulation time 203369500 ps
CPU time 4.65 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:18 PM PDT 24
Peak memory 248756 kb
Host smart-6ee279ab-3230-4e6b-8525-7b59cf003143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847704223 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3847704223
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.706590795
Short name T1161
Test name
Test status
Simulation time 108779964 ps
CPU time 1.89 seconds
Started Jun 29 07:27:18 PM PDT 24
Finished Jun 29 07:27:20 PM PDT 24
Peak memory 240436 kb
Host smart-cc64fd23-ecd3-4f3a-b55c-f721ae129ff2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706590795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.706590795
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3732301077
Short name T3
Test name
Test status
Simulation time 872574782 ps
CPU time 5.79 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 242452 kb
Host smart-338a0b02-4c0c-443a-8855-84c82e1aa5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732301077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3732301077
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.1457243252
Short name T1044
Test name
Test status
Simulation time 1797068498 ps
CPU time 32.39 seconds
Started Jun 29 07:27:12 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 244088 kb
Host smart-8b0c68d1-d04b-432d-918b-d2496ead02f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457243252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1457243252
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.3233352159
Short name T1109
Test name
Test status
Simulation time 315129369 ps
CPU time 3.33 seconds
Started Jun 29 07:27:12 PM PDT 24
Finished Jun 29 07:27:16 PM PDT 24
Peak memory 242244 kb
Host smart-5add3e61-028d-4842-9601-f595bbdea4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233352159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3233352159
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.332915734
Short name T130
Test name
Test status
Simulation time 573611458 ps
CPU time 4.9 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:19 PM PDT 24
Peak memory 242156 kb
Host smart-2408cf53-fd25-452d-b07e-c492619e7a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332915734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.332915734
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.4134560821
Short name T1024
Test name
Test status
Simulation time 839500885 ps
CPU time 15.17 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:29 PM PDT 24
Peak memory 242116 kb
Host smart-649a02ef-7d47-45fc-9939-6c9a60fc3f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134560821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.4134560821
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3269611033
Short name T1179
Test name
Test status
Simulation time 303621771 ps
CPU time 7.15 seconds
Started Jun 29 07:27:16 PM PDT 24
Finished Jun 29 07:27:23 PM PDT 24
Peak memory 241772 kb
Host smart-6dfa5665-1f77-414b-a650-560fcdcc5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269611033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3269611033
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.2787735308
Short name T1068
Test name
Test status
Simulation time 601485475 ps
CPU time 18.05 seconds
Started Jun 29 07:27:18 PM PDT 24
Finished Jun 29 07:27:36 PM PDT 24
Peak memory 248648 kb
Host smart-fe13db8b-afc6-4c99-9057-e610b121807c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787735308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2787735308
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.4053838941
Short name T774
Test name
Test status
Simulation time 797479067 ps
CPU time 8.01 seconds
Started Jun 29 07:27:13 PM PDT 24
Finished Jun 29 07:27:22 PM PDT 24
Peak memory 242380 kb
Host smart-52179eed-0233-495a-a244-8d683abea39c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053838941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4053838941
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.3826428981
Short name T1051
Test name
Test status
Simulation time 376024982 ps
CPU time 5.78 seconds
Started Jun 29 07:27:12 PM PDT 24
Finished Jun 29 07:27:19 PM PDT 24
Peak memory 242256 kb
Host smart-85141ba4-e03f-4327-aaaa-669d7ba5960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826428981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.3826428981
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.719885607
Short name T1166
Test name
Test status
Simulation time 796179517 ps
CPU time 17.38 seconds
Started Jun 29 07:27:14 PM PDT 24
Finished Jun 29 07:27:32 PM PDT 24
Peak memory 248716 kb
Host smart-b906f783-387e-49ad-b285-565f96cbc5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719885607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.719885607
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.2350188887
Short name T1038
Test name
Test status
Simulation time 44391416 ps
CPU time 1.67 seconds
Started Jun 29 07:25:39 PM PDT 24
Finished Jun 29 07:25:42 PM PDT 24
Peak memory 239916 kb
Host smart-9f56f7ec-a962-4324-ac9f-83e856a3ab53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350188887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.2350188887
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.275039017
Short name T974
Test name
Test status
Simulation time 1364194181 ps
CPU time 29.54 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:26:02 PM PDT 24
Peak memory 242700 kb
Host smart-3fb0e7fa-4596-4e42-960b-d2b21cff1650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275039017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.275039017
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.639556166
Short name T94
Test name
Test status
Simulation time 2268487436 ps
CPU time 16.69 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:53 PM PDT 24
Peak memory 248840 kb
Host smart-ad6749ed-77e9-4fa9-a863-4b4c1b5e7fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639556166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.639556166
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.4057390179
Short name T413
Test name
Test status
Simulation time 19724785837 ps
CPU time 39.36 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:26:15 PM PDT 24
Peak memory 244076 kb
Host smart-4bbb007f-d990-4a67-afe6-42d15b70c9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057390179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.4057390179
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.1520412226
Short name T127
Test name
Test status
Simulation time 1300655688 ps
CPU time 19.97 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:25:53 PM PDT 24
Peak memory 242084 kb
Host smart-9fbf7035-adb5-4710-a8b1-62e6c4793908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520412226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1520412226
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.1637970243
Short name T893
Test name
Test status
Simulation time 237802009 ps
CPU time 4.37 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:25:37 PM PDT 24
Peak memory 242112 kb
Host smart-046b8ca7-4129-4327-a205-86d6f73f8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637970243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1637970243
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.947011674
Short name T980
Test name
Test status
Simulation time 894637818 ps
CPU time 12.94 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 242748 kb
Host smart-26766400-9529-405b-8f59-638bf7acf78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947011674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.947011674
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3931724612
Short name T458
Test name
Test status
Simulation time 4902390519 ps
CPU time 34.91 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 243076 kb
Host smart-cfe9c81d-b30d-4a79-99fa-d79916bae2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931724612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3931724612
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.4085365688
Short name T1114
Test name
Test status
Simulation time 159508970 ps
CPU time 7.75 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:44 PM PDT 24
Peak memory 241884 kb
Host smart-71a7c9fc-eec1-4d23-9a98-99538b686963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085365688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.4085365688
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.3296111938
Short name T976
Test name
Test status
Simulation time 1062602792 ps
CPU time 26.49 seconds
Started Jun 29 07:25:39 PM PDT 24
Finished Jun 29 07:26:06 PM PDT 24
Peak memory 248708 kb
Host smart-1f7c775e-5b07-48e0-a58e-869ea802435d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296111938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.3296111938
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1725593227
Short name T273
Test name
Test status
Simulation time 136511062 ps
CPU time 4.28 seconds
Started Jun 29 07:25:31 PM PDT 24
Finished Jun 29 07:25:35 PM PDT 24
Peak memory 248628 kb
Host smart-f6d29224-3f58-4374-b068-d442fb0763ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725593227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1725593227
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.4126461129
Short name T25
Test name
Test status
Simulation time 12358441488 ps
CPU time 201.85 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:28:58 PM PDT 24
Peak memory 277704 kb
Host smart-e7fd937b-d0d2-4b02-a708-ddde2d5c493e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126461129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.4126461129
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.4103471377
Short name T1136
Test name
Test status
Simulation time 643772951 ps
CPU time 12.91 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:52 PM PDT 24
Peak memory 242280 kb
Host smart-e6b04335-1813-4f9d-9368-079e8ea56916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103471377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.4103471377
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.823152118
Short name T582
Test name
Test status
Simulation time 2655421338 ps
CPU time 44.38 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 249584 kb
Host smart-da37563a-c9cb-4ae0-825e-8751bf6801be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823152118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.823152118
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.3486628239
Short name T1143
Test name
Test status
Simulation time 39417879263 ps
CPU time 1003.39 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:42:18 PM PDT 24
Peak memory 257152 kb
Host smart-7088fb3f-e420-4d25-b3ba-b9bac6dba487
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486628239 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.3486628239
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.3068896758
Short name T904
Test name
Test status
Simulation time 441643958 ps
CPU time 9.08 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:45 PM PDT 24
Peak memory 242552 kb
Host smart-5e7fdc4c-1bb8-491f-91aa-475566beb53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068896758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3068896758
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.311060825
Short name T1151
Test name
Test status
Simulation time 153261053 ps
CPU time 1.99 seconds
Started Jun 29 07:27:20 PM PDT 24
Finished Jun 29 07:27:23 PM PDT 24
Peak memory 240348 kb
Host smart-a31ff061-6797-451c-865a-29e13fcf40e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311060825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.311060825
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.2835913071
Short name T147
Test name
Test status
Simulation time 2415097973 ps
CPU time 14.4 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:38 PM PDT 24
Peak memory 242852 kb
Host smart-1760f548-e341-4e7b-95b2-965e1a8635c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835913071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.2835913071
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.187375700
Short name T763
Test name
Test status
Simulation time 4160635853 ps
CPU time 22.34 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 242104 kb
Host smart-154a19cf-8aa8-486c-9d76-1ec73193cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187375700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.187375700
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.59552424
Short name T116
Test name
Test status
Simulation time 739536895 ps
CPU time 13.12 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:37 PM PDT 24
Peak memory 241780 kb
Host smart-5066595f-9419-44d0-a92d-b8a8b43ac648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59552424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.59552424
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1768090247
Short name T583
Test name
Test status
Simulation time 130308341 ps
CPU time 3.34 seconds
Started Jun 29 07:27:17 PM PDT 24
Finished Jun 29 07:27:21 PM PDT 24
Peak memory 241916 kb
Host smart-be6f121d-a021-4b56-9d90-69207ed3d9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768090247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1768090247
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.3082622566
Short name T693
Test name
Test status
Simulation time 637818342 ps
CPU time 4.98 seconds
Started Jun 29 07:27:20 PM PDT 24
Finished Jun 29 07:27:26 PM PDT 24
Peak memory 242588 kb
Host smart-5974fd6d-5102-4d2e-a7b7-4bae480d1dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082622566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3082622566
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.1322221301
Short name T837
Test name
Test status
Simulation time 2306166294 ps
CPU time 24.17 seconds
Started Jun 29 07:27:20 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 242208 kb
Host smart-fe6eefba-c1d9-4d99-9807-5313add79efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322221301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1322221301
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2524451931
Short name T574
Test name
Test status
Simulation time 510319565 ps
CPU time 13.17 seconds
Started Jun 29 07:27:20 PM PDT 24
Finished Jun 29 07:27:34 PM PDT 24
Peak memory 241796 kb
Host smart-15a9b88c-c7ee-41d9-93aa-b3b92fb61e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524451931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2524451931
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.4125252684
Short name T428
Test name
Test status
Simulation time 550401174 ps
CPU time 11.7 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:36 PM PDT 24
Peak memory 241952 kb
Host smart-0dc18dec-86ec-4ac5-ae98-0a1775caaf18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4125252684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.4125252684
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3705119836
Short name T385
Test name
Test status
Simulation time 677937708 ps
CPU time 9.6 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:33 PM PDT 24
Peak memory 242380 kb
Host smart-db38a6f1-9c73-474b-9fbe-85cdacc4eb30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705119836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3705119836
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1401266994
Short name T248
Test name
Test status
Simulation time 4892217824 ps
CPU time 8.85 seconds
Started Jun 29 07:27:15 PM PDT 24
Finished Jun 29 07:27:24 PM PDT 24
Peak memory 242248 kb
Host smart-b3bef43d-6f9a-473d-82ec-bfc87931393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401266994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1401266994
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.4279519463
Short name T975
Test name
Test status
Simulation time 42762331274 ps
CPU time 139 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:29:43 PM PDT 24
Peak memory 248044 kb
Host smart-221c6a96-1db3-432a-a29a-104061962a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279519463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.4279519463
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.937143487
Short name T17
Test name
Test status
Simulation time 973735336 ps
CPU time 20.19 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:44 PM PDT 24
Peak memory 242712 kb
Host smart-02877a05-e203-441b-8987-1157e9970def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937143487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.937143487
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.4117439095
Short name T249
Test name
Test status
Simulation time 759058767 ps
CPU time 2.65 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:26 PM PDT 24
Peak memory 239816 kb
Host smart-87f7c8b6-837b-46c9-a31f-74c1c0e7eb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117439095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.4117439095
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.1500181151
Short name T1023
Test name
Test status
Simulation time 505819974 ps
CPU time 10.59 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:34 PM PDT 24
Peak memory 242396 kb
Host smart-0f41ecde-f718-444f-ab75-8f660f8cd288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500181151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1500181151
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3748091572
Short name T436
Test name
Test status
Simulation time 4363818757 ps
CPU time 41.6 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 249200 kb
Host smart-2442668b-bd02-4242-a0ec-92dc8ef24a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748091572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3748091572
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3845022823
Short name T579
Test name
Test status
Simulation time 4213670011 ps
CPU time 12.61 seconds
Started Jun 29 07:27:21 PM PDT 24
Finished Jun 29 07:27:35 PM PDT 24
Peak memory 242240 kb
Host smart-b2702b01-2051-4d2b-8fd5-f176631aa5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845022823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3845022823
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.196221478
Short name T60
Test name
Test status
Simulation time 157034024 ps
CPU time 4.49 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:27 PM PDT 24
Peak memory 241832 kb
Host smart-bb59c10a-f07e-4851-9ef1-15ce77a47469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196221478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.196221478
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2371476072
Short name T1134
Test name
Test status
Simulation time 7013420361 ps
CPU time 20.43 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 248564 kb
Host smart-942b81fb-6e7a-4758-a218-c1e61690217a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371476072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2371476072
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.1294261833
Short name T1059
Test name
Test status
Simulation time 6092849812 ps
CPU time 20.13 seconds
Started Jun 29 07:27:21 PM PDT 24
Finished Jun 29 07:27:42 PM PDT 24
Peak memory 248864 kb
Host smart-5eb56936-d026-4a1d-a31f-1428bf6435ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294261833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.1294261833
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3665876482
Short name T747
Test name
Test status
Simulation time 1049621691 ps
CPU time 18.96 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:42 PM PDT 24
Peak memory 242052 kb
Host smart-ab8a4594-ee0f-4945-95ee-03c2368f343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665876482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3665876482
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.1546502113
Short name T1018
Test name
Test status
Simulation time 304292277 ps
CPU time 8.17 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:31 PM PDT 24
Peak memory 242116 kb
Host smart-682c0d0a-25e3-4f40-bae7-4e54f3da83c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1546502113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.1546502113
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3445289425
Short name T383
Test name
Test status
Simulation time 327588839 ps
CPU time 5.17 seconds
Started Jun 29 07:27:20 PM PDT 24
Finished Jun 29 07:27:26 PM PDT 24
Peak memory 242080 kb
Host smart-2f6b9b6a-c014-409d-8e5c-70f1b9a865a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445289425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3445289425
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.965634235
Short name T870
Test name
Test status
Simulation time 228725514 ps
CPU time 3.72 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:27 PM PDT 24
Peak memory 242268 kb
Host smart-669845d9-e5aa-4912-8a52-78c80893b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965634235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.965634235
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.2869899187
Short name T1178
Test name
Test status
Simulation time 435636892 ps
CPU time 9.1 seconds
Started Jun 29 07:27:21 PM PDT 24
Finished Jun 29 07:27:31 PM PDT 24
Peak memory 242076 kb
Host smart-f49281aa-652f-419c-ad2f-7cad8385928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869899187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.2869899187
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2150719374
Short name T1084
Test name
Test status
Simulation time 201644557 ps
CPU time 1.62 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:34 PM PDT 24
Peak memory 240100 kb
Host smart-7a9d889c-9c30-4f64-b15b-e696a745860c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150719374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2150719374
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.2931580218
Short name T68
Test name
Test status
Simulation time 412985788 ps
CPU time 12.03 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 242504 kb
Host smart-cd82a558-651f-40ec-954e-dfb6a96ff442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931580218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2931580218
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.2711237745
Short name T764
Test name
Test status
Simulation time 1115028129 ps
CPU time 28.71 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:28:00 PM PDT 24
Peak memory 242048 kb
Host smart-f1c901d2-801b-44d5-a17d-e42affa0cc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711237745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2711237745
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.638463686
Short name T657
Test name
Test status
Simulation time 11160640796 ps
CPU time 17.48 seconds
Started Jun 29 07:27:24 PM PDT 24
Finished Jun 29 07:27:42 PM PDT 24
Peak memory 243044 kb
Host smart-e8742ccd-b950-438c-b599-ffbe06643789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638463686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.638463686
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2407319310
Short name T571
Test name
Test status
Simulation time 133115172 ps
CPU time 3.74 seconds
Started Jun 29 07:27:23 PM PDT 24
Finished Jun 29 07:27:28 PM PDT 24
Peak memory 242084 kb
Host smart-80623722-ac54-461e-a632-9ecf2d632335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407319310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2407319310
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1878257517
Short name T171
Test name
Test status
Simulation time 23072582556 ps
CPU time 46.55 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:28:18 PM PDT 24
Peak memory 249008 kb
Host smart-96e304c9-a254-437c-8635-a80bc4f65134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878257517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1878257517
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2534900249
Short name T478
Test name
Test status
Simulation time 644519968 ps
CPU time 8.2 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:40 PM PDT 24
Peak memory 242320 kb
Host smart-a144bb68-bdfc-4d7b-9ee8-b53c4869240f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534900249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2534900249
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.257652545
Short name T475
Test name
Test status
Simulation time 1101295895 ps
CPU time 26.37 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:49 PM PDT 24
Peak memory 242040 kb
Host smart-fdd3ec7c-cff5-48bb-a065-086fee1b2ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257652545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.257652545
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3502539192
Short name T382
Test name
Test status
Simulation time 3827572474 ps
CPU time 9.93 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:27:48 PM PDT 24
Peak memory 242316 kb
Host smart-aac9971f-9924-4468-83a3-e4199bd43d9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502539192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3502539192
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.652076385
Short name T744
Test name
Test status
Simulation time 126793284 ps
CPU time 4.93 seconds
Started Jun 29 07:27:22 PM PDT 24
Finished Jun 29 07:27:27 PM PDT 24
Peak memory 242116 kb
Host smart-9d2adc29-438c-48b9-9c48-0d469f5c2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652076385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.652076385
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.2013224946
Short name T894
Test name
Test status
Simulation time 76178363635 ps
CPU time 132.51 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:29:45 PM PDT 24
Peak memory 249916 kb
Host smart-3e31808e-205c-4702-a9b1-079c638e86c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013224946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.2013224946
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.2933238733
Short name T924
Test name
Test status
Simulation time 6779519849 ps
CPU time 18.47 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 242508 kb
Host smart-7afb7e7e-69f3-40a6-a12e-69ea8b9d822a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933238733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2933238733
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.2286051009
Short name T1186
Test name
Test status
Simulation time 114803153 ps
CPU time 1.7 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:33 PM PDT 24
Peak memory 240164 kb
Host smart-dd9b1664-2fb9-42da-8c3b-e0b5bb26aaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286051009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2286051009
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.1153941496
Short name T801
Test name
Test status
Simulation time 1018761408 ps
CPU time 21.19 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 241972 kb
Host smart-92e67ac2-a5c0-45cd-be79-f7a8f323dfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153941496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1153941496
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.2750772253
Short name T946
Test name
Test status
Simulation time 2012920784 ps
CPU time 17.13 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:49 PM PDT 24
Peak memory 248812 kb
Host smart-d8833168-d70c-4508-9ffa-dcc8655ce81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750772253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2750772253
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.269699054
Short name T847
Test name
Test status
Simulation time 2231953781 ps
CPU time 4.93 seconds
Started Jun 29 07:27:34 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 242084 kb
Host smart-bf6188ab-bfa6-4e00-ba1f-c5b5bf6f88ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269699054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.269699054
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.4267481519
Short name T556
Test name
Test status
Simulation time 9055166639 ps
CPU time 81.31 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:28:52 PM PDT 24
Peak memory 244032 kb
Host smart-f7dce07b-8fc2-4226-8cab-085e86b4e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267481519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.4267481519
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.1051351117
Short name T936
Test name
Test status
Simulation time 2128679544 ps
CPU time 22.14 seconds
Started Jun 29 07:27:29 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 242104 kb
Host smart-4e92efd7-6b16-4c66-9cba-eb868f312505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051351117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.1051351117
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2703584276
Short name T110
Test name
Test status
Simulation time 749245175 ps
CPU time 10.57 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 242300 kb
Host smart-70d84539-df58-44b0-95ce-ce31c8f3b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703584276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2703584276
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.950798393
Short name T391
Test name
Test status
Simulation time 11667394376 ps
CPU time 31.6 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 242124 kb
Host smart-4118a9c8-adde-4bf7-87c2-dc2e2d14f833
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950798393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.950798393
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1555252206
Short name T725
Test name
Test status
Simulation time 404874353 ps
CPU time 4.1 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:37 PM PDT 24
Peak memory 242212 kb
Host smart-6afdc492-a4ea-4e52-ab8d-fa6f5cb080a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555252206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1555252206
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.316270384
Short name T613
Test name
Test status
Simulation time 152480225 ps
CPU time 4.23 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:36 PM PDT 24
Peak memory 242040 kb
Host smart-27d3b4b9-ea49-4e37-99a2-ba9fc6046ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316270384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.316270384
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.199536371
Short name T1128
Test name
Test status
Simulation time 6746431872 ps
CPU time 68.76 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:28:39 PM PDT 24
Peak memory 244660 kb
Host smart-67588f7d-05bd-42a2-8f92-83d2415d0d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199536371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.
199536371
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.1067127644
Short name T343
Test name
Test status
Simulation time 112743782024 ps
CPU time 1849.19 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:58:21 PM PDT 24
Peak memory 315348 kb
Host smart-368f6322-a711-4a9f-84a4-5cc246ddbc8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067127644 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.1067127644
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.1855915859
Short name T706
Test name
Test status
Simulation time 2000569372 ps
CPU time 15.13 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242568 kb
Host smart-7e1f4a6e-7296-4955-9e8a-14563799d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855915859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.1855915859
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.3247819244
Short name T1089
Test name
Test status
Simulation time 153229703 ps
CPU time 2.78 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:36 PM PDT 24
Peak memory 240096 kb
Host smart-1f4aa1bb-e6ee-4392-8886-af277771a449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247819244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3247819244
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.1482925809
Short name T64
Test name
Test status
Simulation time 538537871 ps
CPU time 14.72 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242804 kb
Host smart-ae05223b-cdd3-4c30-9963-5a7ee6031a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482925809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1482925809
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.2745134699
Short name T430
Test name
Test status
Simulation time 1965222386 ps
CPU time 27.35 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:59 PM PDT 24
Peak memory 243864 kb
Host smart-95099869-0eaf-4bcb-9ac2-00192390e29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745134699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2745134699
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3909451717
Short name T843
Test name
Test status
Simulation time 369836757 ps
CPU time 5.09 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 242508 kb
Host smart-3362df36-cea1-4996-9426-f1d17d99f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909451717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3909451717
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.702369337
Short name T191
Test name
Test status
Simulation time 236608024 ps
CPU time 3.63 seconds
Started Jun 29 07:27:35 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 242068 kb
Host smart-4d91d0cc-7aef-46a4-909c-f3504108f327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702369337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.702369337
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3978014601
Short name T726
Test name
Test status
Simulation time 1416982460 ps
CPU time 7.82 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:42 PM PDT 24
Peak memory 242588 kb
Host smart-dfa8140f-6bef-4c6c-8ae9-41d201290c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978014601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3978014601
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.3702875138
Short name T188
Test name
Test status
Simulation time 847367626 ps
CPU time 14.74 seconds
Started Jun 29 07:27:33 PM PDT 24
Finished Jun 29 07:27:49 PM PDT 24
Peak memory 242576 kb
Host smart-5841f398-ebd8-425d-9649-ff2dc5c3c24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702875138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.3702875138
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3049930637
Short name T470
Test name
Test status
Simulation time 462663202 ps
CPU time 15.29 seconds
Started Jun 29 07:27:31 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242172 kb
Host smart-d334655d-c875-4273-a42b-2f080e83d9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049930637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3049930637
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3725932914
Short name T752
Test name
Test status
Simulation time 1379787675 ps
CPU time 35.26 seconds
Started Jun 29 07:27:29 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 242024 kb
Host smart-bb8a1739-1b85-4797-b2c3-e1f39ac971b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725932914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3725932914
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.1332271550
Short name T1157
Test name
Test status
Simulation time 607172901 ps
CPU time 6.22 seconds
Started Jun 29 07:27:30 PM PDT 24
Finished Jun 29 07:27:37 PM PDT 24
Peak memory 242036 kb
Host smart-20415baa-c404-40f2-98d8-3fc162c73ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332271550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1332271550
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.14053433
Short name T942
Test name
Test status
Simulation time 1824169111 ps
CPU time 15.34 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:48 PM PDT 24
Peak memory 242276 kb
Host smart-8bd10c69-fb4e-4449-873c-c02da1f9e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14053433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.14053433
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.615324449
Short name T709
Test name
Test status
Simulation time 1808090945 ps
CPU time 8.9 seconds
Started Jun 29 07:27:32 PM PDT 24
Finished Jun 29 07:27:42 PM PDT 24
Peak memory 242424 kb
Host smart-4ac89e8f-ff9e-425b-8efe-bbb34da2ede3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615324449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.615324449
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.226865252
Short name T456
Test name
Test status
Simulation time 803313699 ps
CPU time 2.49 seconds
Started Jun 29 07:27:43 PM PDT 24
Finished Jun 29 07:27:46 PM PDT 24
Peak memory 240484 kb
Host smart-860fdb1e-f002-4a6e-8b71-60c512afaa30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226865252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.226865252
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.619596998
Short name T720
Test name
Test status
Simulation time 880329458 ps
CPU time 27.32 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 242308 kb
Host smart-1124bd37-b8bb-4cd7-a897-07f98332c88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619596998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.619596998
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.628029231
Short name T543
Test name
Test status
Simulation time 964302279 ps
CPU time 26.3 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:28:07 PM PDT 24
Peak memory 242360 kb
Host smart-251d6486-fc13-4ba7-8f10-ceb481ede2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628029231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.628029231
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.843424428
Short name T723
Test name
Test status
Simulation time 597101661 ps
CPU time 5.15 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:44 PM PDT 24
Peak memory 241828 kb
Host smart-07bcc40d-88fa-49cd-921b-c0f16bc1f61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843424428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.843424428
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.187167799
Short name T854
Test name
Test status
Simulation time 766078568 ps
CPU time 6.16 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:27:46 PM PDT 24
Peak memory 241964 kb
Host smart-6b94b45a-450e-44f5-aa6f-d797b2db830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187167799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.187167799
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1970283050
Short name T814
Test name
Test status
Simulation time 5602496015 ps
CPU time 45.98 seconds
Started Jun 29 07:27:41 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 244020 kb
Host smart-464d5cc1-b378-41bd-8a9b-7bd831014b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970283050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1970283050
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1572792777
Short name T672
Test name
Test status
Simulation time 1381862097 ps
CPU time 22.12 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:27:59 PM PDT 24
Peak memory 241884 kb
Host smart-78c01b07-50ee-42f7-b38c-b50d88289c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572792777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1572792777
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.4225164060
Short name T452
Test name
Test status
Simulation time 776159856 ps
CPU time 5.74 seconds
Started Jun 29 07:27:43 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 241628 kb
Host smart-b1df4faf-77ae-464f-bdb7-c86ffcb58e19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225164060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.4225164060
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.1079375222
Short name T435
Test name
Test status
Simulation time 126660235 ps
CPU time 4.19 seconds
Started Jun 29 07:27:36 PM PDT 24
Finished Jun 29 07:27:40 PM PDT 24
Peak memory 241952 kb
Host smart-111fee6e-4364-41dd-92e2-81a1854153a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079375222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.1079375222
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.3028652624
Short name T842
Test name
Test status
Simulation time 7822909005 ps
CPU time 144.78 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:30:02 PM PDT 24
Peak memory 257028 kb
Host smart-530f6762-e9d7-48ac-9af7-f7d07ae07300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028652624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.3028652624
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.4138517345
Short name T1159
Test name
Test status
Simulation time 1670688614 ps
CPU time 38.37 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:28:25 PM PDT 24
Peak memory 242740 kb
Host smart-55b8b0d1-6665-4e1a-8465-2739ed349b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138517345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4138517345
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.3126461429
Short name T416
Test name
Test status
Simulation time 95451774 ps
CPU time 1.77 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:27:39 PM PDT 24
Peak memory 240244 kb
Host smart-ce2d048b-d7d4-41dc-a864-a08439380253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126461429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3126461429
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.3008165754
Short name T1045
Test name
Test status
Simulation time 2253304779 ps
CPU time 20.39 seconds
Started Jun 29 07:27:41 PM PDT 24
Finished Jun 29 07:28:03 PM PDT 24
Peak memory 242376 kb
Host smart-41ebc5f2-41df-4984-b4c4-f7a296ea86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008165754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.3008165754
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.1458141319
Short name T447
Test name
Test status
Simulation time 2282765690 ps
CPU time 21.94 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:03 PM PDT 24
Peak memory 242104 kb
Host smart-7614db98-119b-4718-bfd0-2500802837d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458141319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1458141319
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.1161141013
Short name T581
Test name
Test status
Simulation time 1082718702 ps
CPU time 23.52 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 242260 kb
Host smart-fe1dd404-6d4d-45d9-9864-013f04775dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161141013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1161141013
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.3924446316
Short name T660
Test name
Test status
Simulation time 460557735 ps
CPU time 4.47 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242056 kb
Host smart-9ec4eab6-7d43-4605-a84b-dec2e28d395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924446316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3924446316
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.1626658758
Short name T1070
Test name
Test status
Simulation time 8656381487 ps
CPU time 80.5 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:29:00 PM PDT 24
Peak memory 245320 kb
Host smart-9fa592d6-5c02-4922-96be-772bc358dcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626658758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1626658758
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.1384868324
Short name T404
Test name
Test status
Simulation time 902334522 ps
CPU time 34.42 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:28:15 PM PDT 24
Peak memory 248792 kb
Host smart-0350a357-3da6-4ad9-b0bb-6e1fbc622018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384868324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1384868324
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.3140082884
Short name T652
Test name
Test status
Simulation time 1779262646 ps
CPU time 6.37 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:27:46 PM PDT 24
Peak memory 241884 kb
Host smart-fafed246-6273-4e94-b049-992bf347fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140082884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3140082884
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.4017715116
Short name T301
Test name
Test status
Simulation time 8867527221 ps
CPU time 29.98 seconds
Started Jun 29 07:27:43 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 248692 kb
Host smart-6a56dc74-37ba-4da6-800c-bf335313b176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4017715116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.4017715116
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.378414479
Short name T656
Test name
Test status
Simulation time 485109758 ps
CPU time 7.35 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:27:45 PM PDT 24
Peak memory 242100 kb
Host smart-fa0ec6cb-167f-4101-b1df-bf5387a1f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378414479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.378414479
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.710461338
Short name T819
Test name
Test status
Simulation time 6138164095 ps
CPU time 61.36 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 245496 kb
Host smart-ac5defff-de0a-4c6b-9fd2-6acad8cfbc25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710461338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
710461338
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2949673216
Short name T1145
Test name
Test status
Simulation time 72554540607 ps
CPU time 2315.18 seconds
Started Jun 29 07:27:41 PM PDT 24
Finished Jun 29 08:06:19 PM PDT 24
Peak memory 339036 kb
Host smart-33a6bb06-cc3a-436a-97a7-dda7484bc455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949673216 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.2949673216
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.778112026
Short name T255
Test name
Test status
Simulation time 10914021980 ps
CPU time 21.33 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:28:02 PM PDT 24
Peak memory 243436 kb
Host smart-566fbea6-9f9c-4d6c-a2d9-8a124d2ce0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778112026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.778112026
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2014321901
Short name T798
Test name
Test status
Simulation time 64912429 ps
CPU time 1.99 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:27:49 PM PDT 24
Peak memory 240276 kb
Host smart-07be3025-6403-49f9-a0b7-d2efbff03d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014321901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2014321901
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.659771165
Short name T1187
Test name
Test status
Simulation time 1160408629 ps
CPU time 10.52 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:49 PM PDT 24
Peak memory 242396 kb
Host smart-8c443f57-ca33-46ee-91d1-b1f68f9e52ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659771165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.659771165
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.909193746
Short name T530
Test name
Test status
Simulation time 427526684 ps
CPU time 23.81 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 241940 kb
Host smart-a1333c21-caeb-411b-8643-c7c9cf8ff4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909193746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.909193746
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.3932047789
Short name T802
Test name
Test status
Simulation time 1150445049 ps
CPU time 16.56 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:58 PM PDT 24
Peak memory 242456 kb
Host smart-6d888b4d-02a4-4e6c-9335-56482ca40c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932047789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3932047789
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.543934347
Short name T238
Test name
Test status
Simulation time 492370358 ps
CPU time 3.76 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:27:44 PM PDT 24
Peak memory 242048 kb
Host smart-31f55cbe-1361-4cdd-a09b-03295d522103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543934347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.543934347
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.3276841081
Short name T489
Test name
Test status
Simulation time 267310794 ps
CPU time 7.11 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:27:48 PM PDT 24
Peak memory 242200 kb
Host smart-bcdecde6-03c8-42e7-ae7d-32aea0837534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276841081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3276841081
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.1464419572
Short name T641
Test name
Test status
Simulation time 660728685 ps
CPU time 18.7 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:57 PM PDT 24
Peak memory 248820 kb
Host smart-7c804957-4c83-47bf-89c0-0823630e8e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464419572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.1464419572
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.2197963131
Short name T1056
Test name
Test status
Simulation time 845830594 ps
CPU time 13.2 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 242132 kb
Host smart-004cf4e8-f0e3-416b-930c-2969723d8a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197963131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2197963131
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.749178163
Short name T885
Test name
Test status
Simulation time 1349889217 ps
CPU time 22.4 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:28:04 PM PDT 24
Peak memory 248728 kb
Host smart-a0e4f37a-0438-40bc-98b6-7da1ac849ea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=749178163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.749178163
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.235991377
Short name T296
Test name
Test status
Simulation time 319499364 ps
CPU time 5.27 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242280 kb
Host smart-a4f4ce35-4c37-414c-9016-fedffdc8e3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=235991377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.235991377
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.418144533
Short name T560
Test name
Test status
Simulation time 2565771936 ps
CPU time 16.48 seconds
Started Jun 29 07:27:37 PM PDT 24
Finished Jun 29 07:27:54 PM PDT 24
Peak memory 242932 kb
Host smart-ebf6ba7f-edf0-4894-adc0-b71b8fcd02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418144533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.418144533
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.3954637196
Short name T502
Test name
Test status
Simulation time 3585677116 ps
CPU time 10.24 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 241776 kb
Host smart-ec7dc6e2-13dd-4840-a6c2-92fa9ca78751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954637196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.3954637196
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3209442729
Short name T264
Test name
Test status
Simulation time 64699880144 ps
CPU time 863.15 seconds
Started Jun 29 07:27:42 PM PDT 24
Finished Jun 29 07:42:07 PM PDT 24
Peak memory 303464 kb
Host smart-3944abca-6df6-412b-ac3b-90baa0f39ddb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209442729 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.3209442729
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.3997060101
Short name T490
Test name
Test status
Simulation time 1110799130 ps
CPU time 13.8 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:53 PM PDT 24
Peak memory 242508 kb
Host smart-f68a9dbb-2e57-4d5b-a9ff-5f7d0fda1e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997060101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3997060101
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.2794346436
Short name T841
Test name
Test status
Simulation time 109444953 ps
CPU time 1.93 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 240348 kb
Host smart-b2fb88b0-08f2-4699-b2e3-0dbcd248710f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794346436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2794346436
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.2714850122
Short name T86
Test name
Test status
Simulation time 9916888282 ps
CPU time 16.67 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 248864 kb
Host smart-ab9621a4-fb67-4a66-be46-1cbfc7925a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714850122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.2714850122
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2424056521
Short name T426
Test name
Test status
Simulation time 395872376 ps
CPU time 9.44 seconds
Started Jun 29 07:27:41 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 242052 kb
Host smart-f54f53e8-4099-4be7-b9df-3dc4888eec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424056521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2424056521
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.552959348
Short name T877
Test name
Test status
Simulation time 1196851345 ps
CPU time 14.14 seconds
Started Jun 29 07:27:40 PM PDT 24
Finished Jun 29 07:27:56 PM PDT 24
Peak memory 242028 kb
Host smart-e8b96d08-f8b4-4d1c-9230-acd1236674d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552959348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.552959348
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.3091621147
Short name T111
Test name
Test status
Simulation time 158081340 ps
CPU time 4.34 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:27:43 PM PDT 24
Peak memory 242088 kb
Host smart-7259262f-6c85-4eb5-a12f-8ee915ccd220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091621147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3091621147
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.2935432049
Short name T658
Test name
Test status
Simulation time 2209643981 ps
CPU time 55.95 seconds
Started Jun 29 07:27:38 PM PDT 24
Finished Jun 29 07:28:34 PM PDT 24
Peak memory 261704 kb
Host smart-9999d5d8-a640-4e7a-97bf-14d5377bebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935432049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2935432049
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.563399780
Short name T106
Test name
Test status
Simulation time 372468799 ps
CPU time 8.91 seconds
Started Jun 29 07:27:39 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 242632 kb
Host smart-40c55537-bfda-4d34-ab13-b5b2d07d6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563399780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.563399780
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.1032959686
Short name T835
Test name
Test status
Simulation time 219461458 ps
CPU time 4.19 seconds
Started Jun 29 07:27:42 PM PDT 24
Finished Jun 29 07:27:47 PM PDT 24
Peak memory 242276 kb
Host smart-e0e5ad7a-de2d-4fa2-b730-ec889b18db4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032959686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.1032959686
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.3644747856
Short name T1050
Test name
Test status
Simulation time 1807837312 ps
CPU time 5.72 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 241944 kb
Host smart-6e4a422d-15d5-4be2-a0e6-e1ac3cd1bdc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644747856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.3644747856
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1217532422
Short name T1076
Test name
Test status
Simulation time 350847002 ps
CPU time 9.67 seconds
Started Jun 29 07:27:44 PM PDT 24
Finished Jun 29 07:27:56 PM PDT 24
Peak memory 242028 kb
Host smart-d3688bda-b1e1-4412-bc40-02e241e6660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217532422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1217532422
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.817969665
Short name T1079
Test name
Test status
Simulation time 11684568208 ps
CPU time 135.77 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:30:05 PM PDT 24
Peak memory 249036 kb
Host smart-2152c28f-9546-4463-95dc-66f715987004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817969665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.
817969665
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3812008747
Short name T1160
Test name
Test status
Simulation time 50917119074 ps
CPU time 456.34 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:35:24 PM PDT 24
Peak memory 257120 kb
Host smart-b81e0c43-0b86-44ff-b219-b45bedfc13cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812008747 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3812008747
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.4199806546
Short name T528
Test name
Test status
Simulation time 1220884178 ps
CPU time 25.89 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 242672 kb
Host smart-fb7e4247-504f-4632-a713-815d9545139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199806546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.4199806546
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.4272054723
Short name T1181
Test name
Test status
Simulation time 153796543 ps
CPU time 2.1 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:27:51 PM PDT 24
Peak memory 240100 kb
Host smart-8974d3fd-b7ce-4bf5-9ad9-22e92543bff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272054723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.4272054723
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.294743170
Short name T920
Test name
Test status
Simulation time 1395335484 ps
CPU time 13.23 seconds
Started Jun 29 07:27:44 PM PDT 24
Finished Jun 29 07:27:57 PM PDT 24
Peak memory 242272 kb
Host smart-36719a5b-1928-4f05-865c-d0ac87b17592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294743170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.294743170
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.4121504376
Short name T708
Test name
Test status
Simulation time 3934133811 ps
CPU time 34.76 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 248252 kb
Host smart-b06febc9-fd7e-49b5-aed4-5950c25a6a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121504376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.4121504376
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.2116313714
Short name T1004
Test name
Test status
Simulation time 1475884057 ps
CPU time 26.26 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 248784 kb
Host smart-289b0542-2bc0-4507-b801-bd9ecf938360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116313714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.2116313714
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2453496043
Short name T511
Test name
Test status
Simulation time 126129041 ps
CPU time 3.44 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:27:50 PM PDT 24
Peak memory 241800 kb
Host smart-945000c8-cfca-48bb-b667-07a59ed59049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453496043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2453496043
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1960701468
Short name T624
Test name
Test status
Simulation time 3635821807 ps
CPU time 7.95 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:27:56 PM PDT 24
Peak memory 242220 kb
Host smart-6b9722eb-b5d6-4074-ac55-e2aaf47ba426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960701468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1960701468
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2740339772
Short name T402
Test name
Test status
Simulation time 5476380823 ps
CPU time 15.99 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 243088 kb
Host smart-a042a4a7-0df3-47d4-ac51-643f0941e39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740339772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2740339772
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.3661262011
Short name T611
Test name
Test status
Simulation time 210755147 ps
CPU time 4.67 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 242028 kb
Host smart-bfe30444-1ffa-4e4c-bd99-7b068c3d12cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661262011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3661262011
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.3032336361
Short name T449
Test name
Test status
Simulation time 1116284202 ps
CPU time 10.43 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:13 PM PDT 24
Peak memory 242564 kb
Host smart-42e2fbff-05f8-4517-a427-3e61773fa504
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032336361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3032336361
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.536685713
Short name T853
Test name
Test status
Simulation time 245240808 ps
CPU time 5.95 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:09 PM PDT 24
Peak memory 241744 kb
Host smart-8896c678-0aac-4ce0-81a5-de2741c3056f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=536685713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.536685713
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1614552490
Short name T603
Test name
Test status
Simulation time 436927241 ps
CPU time 5.3 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 242100 kb
Host smart-3c4de12b-74cb-472b-96ee-b8c2136702b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614552490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1614552490
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.589453812
Short name T151
Test name
Test status
Simulation time 2789952979 ps
CPU time 99.56 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:29:29 PM PDT 24
Peak memory 248808 kb
Host smart-3b3205d4-1f42-41a3-9eee-7cae89d625a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589453812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
589453812
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3058224582
Short name T356
Test name
Test status
Simulation time 108416343551 ps
CPU time 739.45 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:40:07 PM PDT 24
Peak memory 286132 kb
Host smart-33de0567-7a01-4988-b2d0-d110b5193f7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058224582 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.3058224582
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3385353030
Short name T585
Test name
Test status
Simulation time 106362872 ps
CPU time 2.84 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 241888 kb
Host smart-015c0938-c9b0-42a3-9f61-65424bb83d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385353030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3385353030
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.2670280362
Short name T1153
Test name
Test status
Simulation time 117970909 ps
CPU time 1.88 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:25:37 PM PDT 24
Peak memory 240164 kb
Host smart-2049fcc6-9610-4022-b447-b834a7289b6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670280362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2670280362
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.4266307021
Short name T32
Test name
Test status
Simulation time 1057660021 ps
CPU time 11.7 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:47 PM PDT 24
Peak memory 242092 kb
Host smart-31a273ba-c903-464a-94e3-a2f343c7dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266307021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.4266307021
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.1937583953
Short name T550
Test name
Test status
Simulation time 690122597 ps
CPU time 9.66 seconds
Started Jun 29 07:25:39 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 242820 kb
Host smart-5d93343b-2941-47c2-bbc5-7fe983dbdfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937583953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1937583953
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.4266552231
Short name T453
Test name
Test status
Simulation time 23108521199 ps
CPU time 55.39 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:26:31 PM PDT 24
Peak memory 251196 kb
Host smart-102bfd6d-1c6e-426c-8c21-28887a03891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266552231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.4266552231
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.317644499
Short name T965
Test name
Test status
Simulation time 1603781084 ps
CPU time 23.67 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:26:01 PM PDT 24
Peak memory 241916 kb
Host smart-2e0efc12-9d4b-4d9c-9dd9-d3d24ec1108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317644499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.317644499
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.751708233
Short name T257
Test name
Test status
Simulation time 7151623146 ps
CPU time 15.19 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:25:52 PM PDT 24
Peak memory 248844 kb
Host smart-63691542-6b48-4a9b-9d31-32a3b1218296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751708233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.751708233
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.1024242153
Short name T996
Test name
Test status
Simulation time 606576743 ps
CPU time 18.01 seconds
Started Jun 29 07:25:39 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 248564 kb
Host smart-4176487c-d3da-4208-a519-b3d3fcacc073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024242153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.1024242153
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.637521948
Short name T906
Test name
Test status
Simulation time 1464497204 ps
CPU time 30.27 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:26:05 PM PDT 24
Peak memory 241892 kb
Host smart-e6ec89db-6293-413b-b409-b2fff65f1842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637521948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.637521948
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1430183476
Short name T921
Test name
Test status
Simulation time 1086526071 ps
CPU time 9.19 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:48 PM PDT 24
Peak memory 248724 kb
Host smart-391246d6-6cb7-4a7b-b56d-f4efa43e8edc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430183476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1430183476
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3926128557
Short name T1168
Test name
Test status
Simulation time 222018337 ps
CPU time 4.18 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:38 PM PDT 24
Peak memory 242492 kb
Host smart-59f97fb2-742e-4129-a275-f54e4f2f6959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926128557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3926128557
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.3259362081
Short name T446
Test name
Test status
Simulation time 276888220 ps
CPU time 6.72 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:25:39 PM PDT 24
Peak memory 242068 kb
Host smart-4189cc69-fb56-49da-99cb-69af91e82bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259362081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3259362081
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.742424321
Short name T1118
Test name
Test status
Simulation time 21261168924 ps
CPU time 119.17 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:27:35 PM PDT 24
Peak memory 261548 kb
Host smart-9c0ad445-468d-495c-83dc-f22165953978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742424321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.742424321
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1633043156
Short name T294
Test name
Test status
Simulation time 93530621711 ps
CPU time 1134.33 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:44:29 PM PDT 24
Peak memory 325376 kb
Host smart-88ecd8e6-c961-4995-8957-cc29d57b0f27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633043156 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1633043156
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.1694600804
Short name T554
Test name
Test status
Simulation time 1086133462 ps
CPU time 18.4 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 248820 kb
Host smart-c82a6447-c1a6-4ec4-b683-b38fe558ccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694600804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1694600804
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.4122292632
Short name T1063
Test name
Test status
Simulation time 131915366 ps
CPU time 4.46 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:27:54 PM PDT 24
Peak memory 242104 kb
Host smart-fea070a6-63c2-4e53-b526-f2899b6a1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122292632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.4122292632
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.2695744657
Short name T327
Test name
Test status
Simulation time 306549325 ps
CPU time 7.43 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:27:56 PM PDT 24
Peak memory 241828 kb
Host smart-ecf5218b-5d00-4eaf-9a4f-f48c42edec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695744657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2695744657
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.3665463622
Short name T729
Test name
Test status
Simulation time 102008745 ps
CPU time 3.38 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:27:52 PM PDT 24
Peak memory 242336 kb
Host smart-196bf936-d225-4836-a42b-041450bb2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665463622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.3665463622
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.1321871407
Short name T1138
Test name
Test status
Simulation time 3763710488 ps
CPU time 12.2 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:28:02 PM PDT 24
Peak memory 242060 kb
Host smart-96a6cc68-8731-4735-8cec-817ca26e7d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321871407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.1321871407
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.56066297
Short name T836
Test name
Test status
Simulation time 81791602064 ps
CPU time 861.34 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:42:08 PM PDT 24
Peak memory 260408 kb
Host smart-879eccab-3917-4da9-9cac-a5405652a3ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56066297 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.56066297
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.1123801614
Short name T483
Test name
Test status
Simulation time 205170661 ps
CPU time 3.7 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:27:53 PM PDT 24
Peak memory 241964 kb
Host smart-802885fb-be61-45a8-a20d-41e045887a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123801614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1123801614
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.445244037
Short name T950
Test name
Test status
Simulation time 8630243033 ps
CPU time 25.54 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241936 kb
Host smart-6543bb88-1ebb-4142-81f3-f9d88d788e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445244037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.445244037
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.3907915856
Short name T968
Test name
Test status
Simulation time 70920080454 ps
CPU time 1588.92 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:54:18 PM PDT 24
Peak memory 265312 kb
Host smart-be774ec2-5d47-439f-87a0-707e81c74320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907915856 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3907915856
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.4274702406
Short name T644
Test name
Test status
Simulation time 138951357 ps
CPU time 3.43 seconds
Started Jun 29 07:27:48 PM PDT 24
Finished Jun 29 07:27:53 PM PDT 24
Peak memory 241720 kb
Host smart-c28a4c4e-3a3b-4f69-89cd-4cff5c17b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274702406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.4274702406
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.1499972158
Short name T1142
Test name
Test status
Simulation time 724307444 ps
CPU time 7.41 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:27:55 PM PDT 24
Peak memory 241864 kb
Host smart-c706c91f-1a53-4f53-a535-17d496046513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499972158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.1499972158
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3647256475
Short name T717
Test name
Test status
Simulation time 1913717633 ps
CPU time 5.16 seconds
Started Jun 29 07:27:45 PM PDT 24
Finished Jun 29 07:27:51 PM PDT 24
Peak memory 241932 kb
Host smart-bc7cb91a-c70f-4ce3-8f9b-5a2d5d37cfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647256475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3647256475
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.1695372238
Short name T742
Test name
Test status
Simulation time 2028235509 ps
CPU time 24.36 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:27 PM PDT 24
Peak memory 242068 kb
Host smart-9222b565-ebea-479e-b284-a971a3a5c33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695372238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.1695372238
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.400705621
Short name T353
Test name
Test status
Simulation time 49780813258 ps
CPU time 700.04 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:39:29 PM PDT 24
Peak memory 262524 kb
Host smart-05aacae6-fb97-4a68-90eb-d2c19f328db8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400705621 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.400705621
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.1461591050
Short name T857
Test name
Test status
Simulation time 301011745 ps
CPU time 4.1 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:27:53 PM PDT 24
Peak memory 242188 kb
Host smart-33a2a085-d7a2-438c-bf21-2a12a89b384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461591050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.1461591050
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.3228773255
Short name T154
Test name
Test status
Simulation time 1013854775 ps
CPU time 26.07 seconds
Started Jun 29 07:27:46 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241948 kb
Host smart-b839b405-5adf-4f1c-a972-6e1816d9952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228773255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.3228773255
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.2050814039
Short name T288
Test name
Test status
Simulation time 1954737838064 ps
CPU time 3370.94 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 08:24:15 PM PDT 24
Peak memory 415332 kb
Host smart-ac636015-1a7e-4304-ab13-2df04d092784
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050814039 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.2050814039
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.1559683632
Short name T494
Test name
Test status
Simulation time 321601567 ps
CPU time 3.59 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:27:53 PM PDT 24
Peak memory 242396 kb
Host smart-83105b2d-972d-4cb4-b083-2c2885faed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559683632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1559683632
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.4009579598
Short name T902
Test name
Test status
Simulation time 3164386529 ps
CPU time 26.32 seconds
Started Jun 29 07:27:47 PM PDT 24
Finished Jun 29 07:28:16 PM PDT 24
Peak memory 242056 kb
Host smart-0968c568-5ee8-4502-9d26-3e010b32e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009579598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.4009579598
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.2294025310
Short name T344
Test name
Test status
Simulation time 74107997929 ps
CPU time 1706.84 seconds
Started Jun 29 07:27:51 PM PDT 24
Finished Jun 29 07:56:19 PM PDT 24
Peak memory 265340 kb
Host smart-7dcddc52-b0c7-45cc-a89b-6e19485debdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294025310 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.2294025310
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1952109031
Short name T305
Test name
Test status
Simulation time 167737343 ps
CPU time 4.07 seconds
Started Jun 29 07:27:54 PM PDT 24
Finished Jun 29 07:27:58 PM PDT 24
Peak memory 242080 kb
Host smart-edd322a6-10be-48ad-a19e-84a6fced9b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952109031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1952109031
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1316592916
Short name T597
Test name
Test status
Simulation time 663099903 ps
CPU time 9.52 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:12 PM PDT 24
Peak memory 241980 kb
Host smart-85b1b3f0-15d7-423e-9842-4f0f9c7faf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316592916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1316592916
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.3771976309
Short name T701
Test name
Test status
Simulation time 285538354 ps
CPU time 4.21 seconds
Started Jun 29 07:27:54 PM PDT 24
Finished Jun 29 07:27:58 PM PDT 24
Peak memory 242016 kb
Host smart-98be3ea9-2b21-433d-bb8b-5b8361a094a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771976309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3771976309
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.1424806137
Short name T607
Test name
Test status
Simulation time 216070214 ps
CPU time 5.2 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:27:59 PM PDT 24
Peak memory 241716 kb
Host smart-bc86f044-cf42-4831-bfb2-067a05b9c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424806137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.1424806137
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1814238378
Short name T293
Test name
Test status
Simulation time 1126821861047 ps
CPU time 2291.23 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 08:06:05 PM PDT 24
Peak memory 710760 kb
Host smart-a75bfd04-8205-4d32-b935-9aae87d2c65b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814238378 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.1814238378
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.3535607360
Short name T1085
Test name
Test status
Simulation time 96637631 ps
CPU time 3.61 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:27:57 PM PDT 24
Peak memory 241868 kb
Host smart-1ab273be-2b1c-4a7e-afab-35519d519f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535607360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.3535607360
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.3821326884
Short name T783
Test name
Test status
Simulation time 1036195167 ps
CPU time 22.96 seconds
Started Jun 29 07:27:57 PM PDT 24
Finished Jun 29 07:28:20 PM PDT 24
Peak memory 242028 kb
Host smart-cefc3117-d091-4232-8c50-caaeacab6a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821326884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3821326884
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1891811918
Short name T908
Test name
Test status
Simulation time 42203019386 ps
CPU time 1108.13 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:46:22 PM PDT 24
Peak memory 281716 kb
Host smart-b9592b7c-78d5-4a98-a3e4-153c6c9633b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891811918 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1891811918
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.749418717
Short name T811
Test name
Test status
Simulation time 75238859 ps
CPU time 2.06 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:25:43 PM PDT 24
Peak memory 240168 kb
Host smart-c1d4ce31-183a-441a-9f20-4feff3d0609e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749418717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.749418717
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.499282924
Short name T769
Test name
Test status
Simulation time 498244198 ps
CPU time 9.99 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:25:47 PM PDT 24
Peak memory 242256 kb
Host smart-da77098b-1fde-4bf6-81c8-12b5489ebb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499282924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.499282924
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.1440793362
Short name T174
Test name
Test status
Simulation time 5160694368 ps
CPU time 22.96 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 242284 kb
Host smart-9030b8e4-a379-4d8b-a6dd-a4bee637fd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440793362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.1440793362
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.3725310557
Short name T104
Test name
Test status
Simulation time 6622484175 ps
CPU time 39.03 seconds
Started Jun 29 07:25:32 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 243544 kb
Host smart-697bbf8d-92ae-4070-bc4d-1574886d9713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725310557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3725310557
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.2540264147
Short name T882
Test name
Test status
Simulation time 105004026 ps
CPU time 3.57 seconds
Started Jun 29 07:25:36 PM PDT 24
Finished Jun 29 07:25:40 PM PDT 24
Peak memory 242404 kb
Host smart-454e6d5e-e1ad-4d25-94bd-74b80d4a6811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540264147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.2540264147
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3626589462
Short name T1102
Test name
Test status
Simulation time 1735045040 ps
CPU time 24.13 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:25:59 PM PDT 24
Peak memory 243264 kb
Host smart-634fb737-3ad6-4514-9709-8ca438120302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626589462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3626589462
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.280435225
Short name T146
Test name
Test status
Simulation time 440341364 ps
CPU time 10.8 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:45 PM PDT 24
Peak memory 242420 kb
Host smart-0c976856-b403-4280-a987-6f7a85a3aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280435225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.280435225
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.3376995913
Short name T832
Test name
Test status
Simulation time 672557202 ps
CPU time 19.39 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:53 PM PDT 24
Peak memory 242440 kb
Host smart-8da353ad-e09a-4812-a6ff-e1166172b6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376995913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.3376995913
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3303414854
Short name T172
Test name
Test status
Simulation time 117743796 ps
CPU time 3.68 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:43 PM PDT 24
Peak memory 248544 kb
Host smart-1620c640-7bbd-444f-9699-587698dd4587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3303414854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3303414854
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.184989077
Short name T1171
Test name
Test status
Simulation time 4168287700 ps
CPU time 9.57 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:25:46 PM PDT 24
Peak memory 242252 kb
Host smart-be7ee29c-e587-432f-8c16-6d7c1dcb7f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=184989077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.184989077
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.708728076
Short name T959
Test name
Test status
Simulation time 466562175 ps
CPU time 10.47 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:44 PM PDT 24
Peak memory 242412 kb
Host smart-8588587a-ad67-4da9-805d-0e9c3ff449a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708728076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.708728076
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.2260627032
Short name T589
Test name
Test status
Simulation time 2662757690 ps
CPU time 32.62 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:26:07 PM PDT 24
Peak memory 248884 kb
Host smart-dd737e95-838a-426d-be10-622932ba1eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260627032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2260627032
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.938314671
Short name T977
Test name
Test status
Simulation time 581190205 ps
CPU time 4.56 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:27:58 PM PDT 24
Peak memory 242000 kb
Host smart-3da87614-43d9-4ac6-84ea-0caae56c1328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938314671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.938314671
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1879884602
Short name T193
Test name
Test status
Simulation time 204677660 ps
CPU time 6.07 seconds
Started Jun 29 07:27:52 PM PDT 24
Finished Jun 29 07:27:59 PM PDT 24
Peak memory 241824 kb
Host smart-0b42d606-7b8d-48af-ba80-4b2d17d7a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879884602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1879884602
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.88843383
Short name T349
Test name
Test status
Simulation time 58082672378 ps
CPU time 706.64 seconds
Started Jun 29 07:27:56 PM PDT 24
Finished Jun 29 07:39:43 PM PDT 24
Peak memory 273364 kb
Host smart-b3ac3412-c7ac-4e87-8356-42c18e224c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88843383 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.88843383
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1529176815
Short name T422
Test name
Test status
Simulation time 2766909648 ps
CPU time 7.61 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:10 PM PDT 24
Peak memory 242148 kb
Host smart-8b1d8154-14b6-4386-88c8-7f7c5b684537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529176815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1529176815
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.2204728667
Short name T1131
Test name
Test status
Simulation time 797763320 ps
CPU time 22.2 seconds
Started Jun 29 07:27:52 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241708 kb
Host smart-6b7e8771-bd8f-44c3-8773-d7dd54410973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204728667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.2204728667
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2596798059
Short name T403
Test name
Test status
Simulation time 74495306266 ps
CPU time 697.23 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:39:39 PM PDT 24
Peak memory 257284 kb
Host smart-103e28c9-83ae-46a4-81ff-b7b208f36caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596798059 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2596798059
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.413680935
Short name T1117
Test name
Test status
Simulation time 1995302616 ps
CPU time 5.42 seconds
Started Jun 29 07:27:55 PM PDT 24
Finished Jun 29 07:28:01 PM PDT 24
Peak memory 241832 kb
Host smart-97e51b52-5adf-48eb-90fa-5ae984607e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413680935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.413680935
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.3678724687
Short name T1113
Test name
Test status
Simulation time 750433047 ps
CPU time 4.86 seconds
Started Jun 29 07:27:55 PM PDT 24
Finished Jun 29 07:28:00 PM PDT 24
Peak memory 241944 kb
Host smart-97b80bfb-5a7c-41cd-b3b0-d316a63dbb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678724687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3678724687
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.867309046
Short name T663
Test name
Test status
Simulation time 84834910595 ps
CPU time 1620.87 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:55:04 PM PDT 24
Peak memory 273268 kb
Host smart-6b35c59c-41aa-4e5c-a99a-3132f046c5a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867309046 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.867309046
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.962318616
Short name T754
Test name
Test status
Simulation time 366101495 ps
CPU time 4.79 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:27:58 PM PDT 24
Peak memory 242316 kb
Host smart-1b9a2aff-f16f-4e5a-9bbb-8389645b70e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962318616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.962318616
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1538677741
Short name T285
Test name
Test status
Simulation time 199272798724 ps
CPU time 2805.12 seconds
Started Jun 29 07:27:52 PM PDT 24
Finished Jun 29 08:14:38 PM PDT 24
Peak memory 269452 kb
Host smart-cc752367-8093-4d8c-86d9-38fb9bff2f71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538677741 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1538677741
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.42905507
Short name T187
Test name
Test status
Simulation time 154395384 ps
CPU time 4.24 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 242256 kb
Host smart-604e5bad-11d2-401d-a1fb-cc130436114a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42905507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.42905507
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1089063040
Short name T163
Test name
Test status
Simulation time 126782174 ps
CPU time 3.29 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 242448 kb
Host smart-15711c2f-601f-4769-b9e6-0cc9289d0bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089063040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1089063040
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1719177541
Short name T963
Test name
Test status
Simulation time 100509708263 ps
CPU time 797.99 seconds
Started Jun 29 07:27:52 PM PDT 24
Finished Jun 29 07:41:11 PM PDT 24
Peak memory 330876 kb
Host smart-18bdd5cf-f33a-48ad-a2ff-e4e7f6eaf360
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719177541 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1719177541
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.1236320831
Short name T990
Test name
Test status
Simulation time 261489546 ps
CPU time 4.34 seconds
Started Jun 29 07:27:55 PM PDT 24
Finished Jun 29 07:28:00 PM PDT 24
Peak memory 241932 kb
Host smart-bca1325e-4fe3-4783-8467-7b70c90902e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236320831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1236320831
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.2582790195
Short name T200
Test name
Test status
Simulation time 1031623185 ps
CPU time 16.98 seconds
Started Jun 29 07:27:53 PM PDT 24
Finished Jun 29 07:28:11 PM PDT 24
Peak memory 242336 kb
Host smart-1023ae0f-c3c1-417c-ad41-45bee5d82f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582790195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.2582790195
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.700226452
Short name T807
Test name
Test status
Simulation time 207957103850 ps
CPU time 671.8 seconds
Started Jun 29 07:27:56 PM PDT 24
Finished Jun 29 07:39:09 PM PDT 24
Peak memory 307496 kb
Host smart-98730bdb-c41c-4d93-a218-0b8b17151cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700226452 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.700226452
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.4133107183
Short name T47
Test name
Test status
Simulation time 399815718 ps
CPU time 5.37 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:07 PM PDT 24
Peak memory 242172 kb
Host smart-09d20c1f-c2fc-4309-abf2-6bef2e4264a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133107183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.4133107183
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.2403644303
Short name T423
Test name
Test status
Simulation time 552852022 ps
CPU time 4.21 seconds
Started Jun 29 07:27:55 PM PDT 24
Finished Jun 29 07:28:00 PM PDT 24
Peak memory 242188 kb
Host smart-d664b0b8-d36a-4b0d-ae0a-93c156de9bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403644303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.2403644303
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.4241912388
Short name T227
Test name
Test status
Simulation time 138605587398 ps
CPU time 2444.55 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 08:08:47 PM PDT 24
Peak memory 341436 kb
Host smart-95f2f402-7684-421f-841b-23e660b52a5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241912388 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.4241912388
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.514049829
Short name T114
Test name
Test status
Simulation time 1832272890 ps
CPU time 5.5 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:28:10 PM PDT 24
Peak memory 242400 kb
Host smart-5f5122dd-a2c6-49af-bedd-62032261ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514049829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.514049829
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.34344538
Short name T674
Test name
Test status
Simulation time 407615107 ps
CPU time 3.76 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 241972 kb
Host smart-eb06c82f-1973-49d2-bdc0-18a8ebd403a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34344538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.34344538
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.3786777927
Short name T947
Test name
Test status
Simulation time 247561625628 ps
CPU time 1036.54 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:45:20 PM PDT 24
Peak memory 294688 kb
Host smart-164941fb-1e75-4f41-818a-fc5609f4d579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786777927 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.3786777927
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.879874343
Short name T1003
Test name
Test status
Simulation time 96424420 ps
CPU time 3.85 seconds
Started Jun 29 07:28:04 PM PDT 24
Finished Jun 29 07:28:09 PM PDT 24
Peak memory 241964 kb
Host smart-36b031d5-1a72-438f-929b-b0d99a67584a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879874343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.879874343
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.3714222438
Short name T287
Test name
Test status
Simulation time 67291466578 ps
CPU time 1010.54 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:44:51 PM PDT 24
Peak memory 253960 kb
Host smart-12861e25-8d6f-4bab-858f-3c494436345e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714222438 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.3714222438
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1137267392
Short name T254
Test name
Test status
Simulation time 307268526 ps
CPU time 4.45 seconds
Started Jun 29 07:27:58 PM PDT 24
Finished Jun 29 07:28:03 PM PDT 24
Peak memory 242168 kb
Host smart-7af945e7-0ba4-4cfb-a73c-93aec713d1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137267392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1137267392
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.2167289934
Short name T323
Test name
Test status
Simulation time 211790347 ps
CPU time 3.41 seconds
Started Jun 29 07:25:43 PM PDT 24
Finished Jun 29 07:25:48 PM PDT 24
Peak memory 240348 kb
Host smart-3f7a0044-05a9-4174-a187-ca9634fa9173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167289934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2167289934
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.596101432
Short name T393
Test name
Test status
Simulation time 3744181834 ps
CPU time 21.82 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 243168 kb
Host smart-79090319-6823-47b6-9421-31ec4187115a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596101432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.596101432
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2608889480
Short name T62
Test name
Test status
Simulation time 1846639170 ps
CPU time 17.83 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:01 PM PDT 24
Peak memory 242216 kb
Host smart-d61262f1-fccb-4450-8aeb-1876bdeb914c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608889480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2608889480
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.2425054603
Short name T891
Test name
Test status
Simulation time 778202630 ps
CPU time 9.85 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:25:51 PM PDT 24
Peak memory 242100 kb
Host smart-ea87191a-0686-4f11-99e7-454f6aa6fbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425054603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2425054603
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.1638183048
Short name T306
Test name
Test status
Simulation time 6323459266 ps
CPU time 22.72 seconds
Started Jun 29 07:25:33 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 243460 kb
Host smart-72cf3fa4-e4cd-4bde-b882-e4d8f917ac79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638183048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1638183048
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.2761411085
Short name T210
Test name
Test status
Simulation time 2074996864 ps
CPU time 4.78 seconds
Started Jun 29 07:25:34 PM PDT 24
Finished Jun 29 07:25:40 PM PDT 24
Peak memory 242084 kb
Host smart-e97f3e65-1e06-44b1-bb53-ac6bb92ebcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761411085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.2761411085
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.356320283
Short name T1104
Test name
Test status
Simulation time 5791305613 ps
CPU time 35.6 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 257392 kb
Host smart-6a53516f-ea25-4f9c-aea4-03e17727e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356320283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.356320283
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.749973366
Short name T753
Test name
Test status
Simulation time 3775667130 ps
CPU time 10.5 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:53 PM PDT 24
Peak memory 243244 kb
Host smart-5ec97094-76a1-4dcb-9189-8902d8446fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749973366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.749973366
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2723944887
Short name T824
Test name
Test status
Simulation time 4530058375 ps
CPU time 35.05 seconds
Started Jun 29 07:25:35 PM PDT 24
Finished Jun 29 07:26:11 PM PDT 24
Peak memory 242424 kb
Host smart-5b2e40ba-85bd-499b-8d4d-3f21f4cb4e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723944887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2723944887
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.2065779700
Short name T627
Test name
Test status
Simulation time 559446718 ps
CPU time 15.22 seconds
Started Jun 29 07:25:38 PM PDT 24
Finished Jun 29 07:25:54 PM PDT 24
Peak memory 248708 kb
Host smart-ed1c9390-e6d5-46f9-bfde-351f67bf63aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065779700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2065779700
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.1677654023
Short name T380
Test name
Test status
Simulation time 130658872 ps
CPU time 6.62 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:50 PM PDT 24
Peak memory 241824 kb
Host smart-ccab0962-c001-4d57-bc33-84647ca757d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677654023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1677654023
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3840178604
Short name T479
Test name
Test status
Simulation time 5551713277 ps
CPU time 24.17 seconds
Started Jun 29 07:25:39 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242304 kb
Host smart-bc0cccb3-c6ce-4d67-a819-267de040886f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840178604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3840178604
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.3257768807
Short name T800
Test name
Test status
Simulation time 11008476963 ps
CPU time 146.77 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:28:09 PM PDT 24
Peak memory 247640 kb
Host smart-10fc4471-bfa9-493d-b41f-22d7c8a9fe0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257768807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
3257768807
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2062320160
Short name T302
Test name
Test status
Simulation time 481094925132 ps
CPU time 1445.56 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:49:47 PM PDT 24
Peak memory 301068 kb
Host smart-5d349148-3001-4f78-adb9-3e54c789c754
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062320160 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2062320160
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2733241030
Short name T1021
Test name
Test status
Simulation time 270325211 ps
CPU time 3.61 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:47 PM PDT 24
Peak memory 242264 kb
Host smart-73d4f97a-e8e1-4842-a3df-1736db917487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733241030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2733241030
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.4102236192
Short name T828
Test name
Test status
Simulation time 168383496 ps
CPU time 4.05 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 242160 kb
Host smart-16491032-4fe3-4898-9b2e-3d955061ff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102236192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.4102236192
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.706963210
Short name T165
Test name
Test status
Simulation time 156879206 ps
CPU time 7.59 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 241896 kb
Host smart-0d412799-62fa-48ef-b517-2bd31c90c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706963210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.706963210
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.6457356
Short name T185
Test name
Test status
Simulation time 126390221 ps
CPU time 3.77 seconds
Started Jun 29 07:28:02 PM PDT 24
Finished Jun 29 07:28:07 PM PDT 24
Peak memory 242412 kb
Host smart-a782e197-d6d3-4586-80cc-0ce88ff86bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6457356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.6457356
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.605409137
Short name T541
Test name
Test status
Simulation time 6423674219 ps
CPU time 13.75 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:15 PM PDT 24
Peak memory 242300 kb
Host smart-e0d07d03-3a92-4454-87d7-3a27414be91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605409137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.605409137
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.3903951905
Short name T42
Test name
Test status
Simulation time 180338848427 ps
CPU time 949.03 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:43:53 PM PDT 24
Peak memory 289360 kb
Host smart-8c66bf8e-2497-4118-bd11-8d507064301f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903951905 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.3903951905
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.3508727006
Short name T230
Test name
Test status
Simulation time 299512491 ps
CPU time 4.18 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 241828 kb
Host smart-24c609be-14a5-4a6e-80ed-1676a6687fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508727006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.3508727006
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.2922567130
Short name T1009
Test name
Test status
Simulation time 10241198700 ps
CPU time 25.63 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:28 PM PDT 24
Peak memory 241900 kb
Host smart-75868eff-af2c-484d-a198-959d8ead83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922567130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2922567130
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1890697267
Short name T577
Test name
Test status
Simulation time 275214733957 ps
CPU time 564.4 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:37:24 PM PDT 24
Peak memory 265308 kb
Host smart-c3b4b905-ba8b-4046-9882-9be2bd4d6500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890697267 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1890697267
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.219115707
Short name T758
Test name
Test status
Simulation time 92778433 ps
CPU time 3.59 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 242300 kb
Host smart-dc79a4ee-3434-4055-80f3-56716603fcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219115707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.219115707
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.4038039051
Short name T321
Test name
Test status
Simulation time 3193567217 ps
CPU time 9.15 seconds
Started Jun 29 07:27:58 PM PDT 24
Finished Jun 29 07:28:08 PM PDT 24
Peak memory 241836 kb
Host smart-d4e3dc3a-9951-4417-8596-1591c46e1373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038039051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.4038039051
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.617455187
Short name T632
Test name
Test status
Simulation time 203294669871 ps
CPU time 1201.3 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:48:02 PM PDT 24
Peak memory 257600 kb
Host smart-f12fc130-99c6-44d1-a3d3-5635a8ccac0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617455187 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.617455187
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.2235742434
Short name T681
Test name
Test status
Simulation time 138856451 ps
CPU time 3.53 seconds
Started Jun 29 07:28:00 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 242396 kb
Host smart-fe497636-13bb-4dae-9994-0e5e075ab1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235742434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.2235742434
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1221862420
Short name T443
Test name
Test status
Simulation time 412866435 ps
CPU time 6.05 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:28:10 PM PDT 24
Peak memory 241820 kb
Host smart-13efdb69-fc59-4fed-b2d5-f4fde6f3455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221862420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1221862420
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.329735936
Short name T609
Test name
Test status
Simulation time 47203448676 ps
CPU time 678.43 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:39:21 PM PDT 24
Peak memory 257124 kb
Host smart-7937c27f-46d5-4fe1-b4d8-4311f10178bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329735936 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.329735936
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.828608530
Short name T520
Test name
Test status
Simulation time 1835089243 ps
CPU time 5.2 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:28:06 PM PDT 24
Peak memory 241832 kb
Host smart-1528296b-7411-4a1d-8f0b-d065714e4f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828608530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.828608530
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2863663133
Short name T945
Test name
Test status
Simulation time 1437327310 ps
CPU time 21.68 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 07:28:25 PM PDT 24
Peak memory 241820 kb
Host smart-e4e94371-3401-4d9d-8551-cfc8f7c07b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863663133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2863663133
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.3456799515
Short name T474
Test name
Test status
Simulation time 148178247 ps
CPU time 3.75 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:28:03 PM PDT 24
Peak memory 241856 kb
Host smart-8d7d9fd4-0f35-4af6-80c7-52d1be97a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456799515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3456799515
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.696924349
Short name T1031
Test name
Test status
Simulation time 220713761 ps
CPU time 11.29 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:28:15 PM PDT 24
Peak memory 241720 kb
Host smart-f9be38c1-8e31-4cf8-b0b4-da1665765424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696924349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.696924349
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2684574749
Short name T268
Test name
Test status
Simulation time 93263634707 ps
CPU time 782.35 seconds
Started Jun 29 07:28:02 PM PDT 24
Finished Jun 29 07:41:06 PM PDT 24
Peak memory 258536 kb
Host smart-9a8d5dc9-0701-4bdb-94d9-17362fcbf557
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684574749 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.2684574749
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.2294175737
Short name T58
Test name
Test status
Simulation time 548184072 ps
CPU time 5.38 seconds
Started Jun 29 07:28:04 PM PDT 24
Finished Jun 29 07:28:10 PM PDT 24
Peak memory 241996 kb
Host smart-9961b100-3533-43c9-b6ab-1324d268f3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294175737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.2294175737
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.2873672757
Short name T258
Test name
Test status
Simulation time 768345627 ps
CPU time 16.16 seconds
Started Jun 29 07:28:03 PM PDT 24
Finished Jun 29 07:28:20 PM PDT 24
Peak memory 241904 kb
Host smart-31e84da0-7b48-40c6-92b7-18ca9f69ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873672757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2873672757
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2637849210
Short name T1184
Test name
Test status
Simulation time 530309979 ps
CPU time 4.33 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:28:05 PM PDT 24
Peak memory 242084 kb
Host smart-0d57c98c-3186-4516-9284-fa038bf12601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637849210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2637849210
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1533873209
Short name T806
Test name
Test status
Simulation time 2328359114 ps
CPU time 21.69 seconds
Started Jun 29 07:27:59 PM PDT 24
Finished Jun 29 07:28:22 PM PDT 24
Peak memory 241976 kb
Host smart-db5c1832-11db-40f9-a7a7-58c348a265e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533873209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1533873209
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.4156497735
Short name T1133
Test name
Test status
Simulation time 334191866823 ps
CPU time 1951.19 seconds
Started Jun 29 07:28:01 PM PDT 24
Finished Jun 29 08:00:34 PM PDT 24
Peak memory 358940 kb
Host smart-c0324f5a-6e34-4ad1-a6fd-acb72f443096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156497735 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.4156497735
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.313220790
Short name T646
Test name
Test status
Simulation time 1942477099 ps
CPU time 5.69 seconds
Started Jun 29 07:28:08 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241932 kb
Host smart-595c2067-2e94-4efc-afc2-39631bf025e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313220790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.313220790
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.2594074944
Short name T677
Test name
Test status
Simulation time 212537367 ps
CPU time 8.11 seconds
Started Jun 29 07:28:08 PM PDT 24
Finished Jun 29 07:28:16 PM PDT 24
Peak memory 241656 kb
Host smart-fefac811-8cb8-43e1-9364-de431691a620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594074944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2594074944
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2057866821
Short name T1037
Test name
Test status
Simulation time 124695083958 ps
CPU time 1810.44 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:58:21 PM PDT 24
Peak memory 265340 kb
Host smart-1a4a3bc7-9bcb-469c-8886-3965f92d0211
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057866821 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.2057866821
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.1770164907
Short name T481
Test name
Test status
Simulation time 69487503 ps
CPU time 1.97 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:46 PM PDT 24
Peak memory 240428 kb
Host smart-8fd514ba-44a8-45c2-a1d1-62456348a992
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770164907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.1770164907
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.2003254567
Short name T790
Test name
Test status
Simulation time 2082351671 ps
CPU time 12.86 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:55 PM PDT 24
Peak memory 242596 kb
Host smart-31df4e3d-6fa4-4087-a8e7-e551d926d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003254567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.2003254567
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.3325203769
Short name T136
Test name
Test status
Simulation time 4249525158 ps
CPU time 35.36 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:19 PM PDT 24
Peak memory 243128 kb
Host smart-242890be-b25f-4940-bb37-dca34b8cbec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325203769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3325203769
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.977981802
Short name T845
Test name
Test status
Simulation time 1320599007 ps
CPU time 27.84 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:26:09 PM PDT 24
Peak memory 241820 kb
Host smart-e4c172bc-5388-43f9-b11f-57c422ae6a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977981802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.977981802
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1836553683
Short name T544
Test name
Test status
Simulation time 811457251 ps
CPU time 6.72 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:25:48 PM PDT 24
Peak memory 242364 kb
Host smart-c1544917-07f6-4fcd-aef4-c5423700d255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836553683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1836553683
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.2233049110
Short name T61
Test name
Test status
Simulation time 199705197 ps
CPU time 4.64 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:47 PM PDT 24
Peak memory 242108 kb
Host smart-bb98a6f8-2176-4fbd-b354-15edc1c2912b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233049110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.2233049110
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.727540375
Short name T958
Test name
Test status
Simulation time 398241468 ps
CPU time 10.59 seconds
Started Jun 29 07:25:47 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 242716 kb
Host smart-db8857b6-3e14-40da-bb36-a303cc493741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727540375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.727540375
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1949969594
Short name T992
Test name
Test status
Simulation time 686907214 ps
CPU time 11.87 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:56 PM PDT 24
Peak memory 242288 kb
Host smart-341481e5-dfa6-45fc-831d-0565b098c52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949969594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1949969594
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.652742802
Short name T808
Test name
Test status
Simulation time 96033995 ps
CPU time 2.67 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:45 PM PDT 24
Peak memory 241928 kb
Host smart-307047c4-4347-4a00-b2e0-ddbb8db2162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652742802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.652742802
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.1872563713
Short name T867
Test name
Test status
Simulation time 697197461 ps
CPU time 7.98 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:50 PM PDT 24
Peak memory 242204 kb
Host smart-b94a8987-751e-42d3-9a82-433cdcbe308a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872563713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.1872563713
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.2386878890
Short name T1123
Test name
Test status
Simulation time 2520161419 ps
CPU time 5.99 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:50 PM PDT 24
Peak memory 241660 kb
Host smart-e2d49e05-a76c-4db0-86cd-48eb32793b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2386878890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2386878890
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3842314770
Short name T901
Test name
Test status
Simulation time 663138114 ps
CPU time 5.33 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:49 PM PDT 24
Peak memory 242296 kb
Host smart-24f77cdd-0947-4aff-9255-08db37ba4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842314770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3842314770
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3349724028
Short name T1072
Test name
Test status
Simulation time 34229967471 ps
CPU time 80.1 seconds
Started Jun 29 07:25:47 PM PDT 24
Finished Jun 29 07:27:08 PM PDT 24
Peak memory 244832 kb
Host smart-83ec1676-50fc-4b32-9e3e-80eaaba6c299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349724028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3349724028
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.4269542879
Short name T697
Test name
Test status
Simulation time 3290064968 ps
CPU time 30.26 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:26:12 PM PDT 24
Peak memory 248864 kb
Host smart-91beca99-2421-43d6-bbc4-e267bfa5220e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269542879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.4269542879
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.2620026562
Short name T567
Test name
Test status
Simulation time 138401914 ps
CPU time 4.4 seconds
Started Jun 29 07:28:08 PM PDT 24
Finished Jun 29 07:28:13 PM PDT 24
Peak memory 241944 kb
Host smart-1cadde3d-c0a2-4654-8367-10779b407db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620026562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.2620026562
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.3608352937
Short name T675
Test name
Test status
Simulation time 1144249127 ps
CPU time 15.91 seconds
Started Jun 29 07:28:07 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 242072 kb
Host smart-d3444bc0-7aee-4a83-9fe3-80a50b26ef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608352937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3608352937
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1550283891
Short name T919
Test name
Test status
Simulation time 455478202 ps
CPU time 3.52 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 242164 kb
Host smart-2e3fa210-ac53-428a-ba47-a88518d52872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550283891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1550283891
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.1677709270
Short name T1019
Test name
Test status
Simulation time 3650140824 ps
CPU time 11.27 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:21 PM PDT 24
Peak memory 242016 kb
Host smart-f7bf7a2b-e454-4ad1-8b8b-cccaaa545a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677709270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1677709270
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1584324843
Short name T911
Test name
Test status
Simulation time 28754739683 ps
CPU time 833.57 seconds
Started Jun 29 07:28:10 PM PDT 24
Finished Jun 29 07:42:04 PM PDT 24
Peak memory 299000 kb
Host smart-4e95abda-21f9-415e-87a4-a5869512bf0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584324843 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1584324843
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1549103563
Short name T702
Test name
Test status
Simulation time 514516923 ps
CPU time 4.89 seconds
Started Jun 29 07:28:11 PM PDT 24
Finished Jun 29 07:28:16 PM PDT 24
Peak memory 242412 kb
Host smart-6e6de90a-6b36-41e4-8a19-545259765dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549103563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1549103563
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.957944515
Short name T275
Test name
Test status
Simulation time 2867777504 ps
CPU time 8.18 seconds
Started Jun 29 07:28:11 PM PDT 24
Finished Jun 29 07:28:19 PM PDT 24
Peak memory 242252 kb
Host smart-b1ac30af-6d5d-429f-9c24-98face02f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957944515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.957944515
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.3717731897
Short name T492
Test name
Test status
Simulation time 2146234085 ps
CPU time 6.63 seconds
Started Jun 29 07:28:13 PM PDT 24
Finished Jun 29 07:28:20 PM PDT 24
Peak memory 241924 kb
Host smart-6adcf1fa-54e4-49a8-9fa1-c52114aca133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717731897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3717731897
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3755154681
Short name T673
Test name
Test status
Simulation time 1716462053 ps
CPU time 10.89 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:21 PM PDT 24
Peak memory 242516 kb
Host smart-fad07f0e-8e57-45f3-b9d1-4c7bcff8d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755154681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3755154681
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.2147482217
Short name T573
Test name
Test status
Simulation time 36280438779 ps
CPU time 980.46 seconds
Started Jun 29 07:28:10 PM PDT 24
Finished Jun 29 07:44:32 PM PDT 24
Peak memory 257356 kb
Host smart-063309e2-cb39-4fab-b2e5-2dd5d113e706
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147482217 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.2147482217
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.691352624
Short name T71
Test name
Test status
Simulation time 137186858 ps
CPU time 4.54 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:15 PM PDT 24
Peak memory 242220 kb
Host smart-52589e8f-36d0-4b63-a023-1382449be1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691352624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.691352624
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.2575205440
Short name T253
Test name
Test status
Simulation time 631805172 ps
CPU time 4.96 seconds
Started Jun 29 07:28:08 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 241896 kb
Host smart-4703413b-19b2-49d5-80c4-14e422577a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575205440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2575205440
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2271910913
Short name T721
Test name
Test status
Simulation time 45081411812 ps
CPU time 351.22 seconds
Started Jun 29 07:28:08 PM PDT 24
Finished Jun 29 07:34:01 PM PDT 24
Peak memory 256700 kb
Host smart-e0ca6288-d376-4d55-98ae-cfeed133f3ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271910913 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2271910913
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.584535136
Short name T569
Test name
Test status
Simulation time 226006448 ps
CPU time 4.44 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 07:28:14 PM PDT 24
Peak memory 242416 kb
Host smart-7b024dbe-749a-4e9c-9627-964dcdb08e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584535136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.584535136
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.68236682
Short name T553
Test name
Test status
Simulation time 1220975410456 ps
CPU time 2900.33 seconds
Started Jun 29 07:28:09 PM PDT 24
Finished Jun 29 08:16:31 PM PDT 24
Peak memory 327076 kb
Host smart-83266576-8782-4325-9943-db113eff3d64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68236682 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.68236682
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2383149165
Short name T1116
Test name
Test status
Simulation time 475791077 ps
CPU time 5.31 seconds
Started Jun 29 07:28:17 PM PDT 24
Finished Jun 29 07:28:23 PM PDT 24
Peak memory 242192 kb
Host smart-6cfa5e16-2560-43a1-9478-c4199d7401a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383149165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2383149165
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.2112617956
Short name T831
Test name
Test status
Simulation time 2998297436 ps
CPU time 10.32 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:28:26 PM PDT 24
Peak memory 242020 kb
Host smart-10916c38-f8f6-47ce-b8ef-a438699ba9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112617956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2112617956
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.619401460
Short name T707
Test name
Test status
Simulation time 27113754504 ps
CPU time 692.07 seconds
Started Jun 29 07:28:14 PM PDT 24
Finished Jun 29 07:39:47 PM PDT 24
Peak memory 265272 kb
Host smart-0ce8735b-8309-47b9-b5e7-6f5a4eca4616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619401460 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.619401460
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.3038085323
Short name T1055
Test name
Test status
Simulation time 217705187 ps
CPU time 4.03 seconds
Started Jun 29 07:28:18 PM PDT 24
Finished Jun 29 07:28:22 PM PDT 24
Peak memory 242176 kb
Host smart-b738d786-9391-4d89-b7c8-afbdfb35c0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038085323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3038085323
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.283112833
Short name T999
Test name
Test status
Simulation time 1298306089 ps
CPU time 18.87 seconds
Started Jun 29 07:28:19 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 241908 kb
Host smart-be7ce1b5-89e6-43a9-a7bd-cb1194dfe611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283112833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.283112833
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.511623488
Short name T14
Test name
Test status
Simulation time 191785415364 ps
CPU time 2619.29 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 08:11:56 PM PDT 24
Peak memory 565516 kb
Host smart-afa0a228-05f7-4116-a82a-c6c773affe1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511623488 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.511623488
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1907052475
Short name T676
Test name
Test status
Simulation time 2023378693 ps
CPU time 5.63 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:28:22 PM PDT 24
Peak memory 242500 kb
Host smart-6a469ea8-a61d-4ceb-b665-b4cc4027fb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907052475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1907052475
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.307941551
Short name T437
Test name
Test status
Simulation time 288679943 ps
CPU time 3.85 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:28:20 PM PDT 24
Peak memory 241848 kb
Host smart-3f2c79c3-4b5f-449a-950d-498bece95a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307941551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.307941551
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.977653979
Short name T225
Test name
Test status
Simulation time 2095743899 ps
CPU time 5.38 seconds
Started Jun 29 07:28:19 PM PDT 24
Finished Jun 29 07:28:25 PM PDT 24
Peak memory 242144 kb
Host smart-e98b3472-4198-4e6e-b920-1c0acab4ee99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977653979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.977653979
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.921839774
Short name T929
Test name
Test status
Simulation time 1870126239 ps
CPU time 26.77 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:28:43 PM PDT 24
Peak memory 241908 kb
Host smart-13d6fe44-4e89-4b07-af63-d4327a2cfdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921839774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.921839774
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.3298920052
Short name T1141
Test name
Test status
Simulation time 230174884211 ps
CPU time 2780.61 seconds
Started Jun 29 07:28:18 PM PDT 24
Finished Jun 29 08:14:39 PM PDT 24
Peak memory 333648 kb
Host smart-283326a3-094c-4261-9c04-261bf8c09707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298920052 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.3298920052
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3884846730
Short name T504
Test name
Test status
Simulation time 48754412 ps
CPU time 1.64 seconds
Started Jun 29 07:25:43 PM PDT 24
Finished Jun 29 07:25:46 PM PDT 24
Peak memory 240160 kb
Host smart-2300e2c4-5f33-49fd-b674-0c692451f81c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884846730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3884846730
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.1838789060
Short name T984
Test name
Test status
Simulation time 1022105487 ps
CPU time 26.54 seconds
Started Jun 29 07:25:45 PM PDT 24
Finished Jun 29 07:26:12 PM PDT 24
Peak memory 242896 kb
Host smart-fcb9b4fc-a603-42a4-9614-0dcf5e10667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838789060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1838789060
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2298424453
Short name T969
Test name
Test status
Simulation time 431303973 ps
CPU time 8.08 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:51 PM PDT 24
Peak memory 242336 kb
Host smart-a991a7c2-3516-4773-9ca7-5650d6238a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298424453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2298424453
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.1484921148
Short name T799
Test name
Test status
Simulation time 2027041326 ps
CPU time 19.19 seconds
Started Jun 29 07:25:43 PM PDT 24
Finished Jun 29 07:26:04 PM PDT 24
Peak memory 242148 kb
Host smart-04465f95-df00-4ac1-988e-7bc5580e349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484921148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1484921148
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.828355162
Short name T840
Test name
Test status
Simulation time 598486133 ps
CPU time 9.23 seconds
Started Jun 29 07:25:41 PM PDT 24
Finished Jun 29 07:25:51 PM PDT 24
Peak memory 242620 kb
Host smart-9f9d05f4-c87b-4d84-b6e6-907c5327586c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828355162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.828355162
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.2858536969
Short name T235
Test name
Test status
Simulation time 182070592 ps
CPU time 3.98 seconds
Started Jun 29 07:25:49 PM PDT 24
Finished Jun 29 07:25:54 PM PDT 24
Peak memory 242080 kb
Host smart-a1383716-ac22-4527-b7bb-e446cf5f2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858536969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2858536969
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.3298593488
Short name T1025
Test name
Test status
Simulation time 3939311567 ps
CPU time 29.89 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:13 PM PDT 24
Peak memory 245436 kb
Host smart-4e0b0e67-779a-4c73-a6e8-77f07bc5a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298593488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.3298593488
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.201372942
Short name T809
Test name
Test status
Simulation time 1457398394 ps
CPU time 21.73 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:05 PM PDT 24
Peak memory 248768 kb
Host smart-4e90f0e3-b809-45fd-a24a-6b39381798c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201372942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.201372942
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.3501799257
Short name T598
Test name
Test status
Simulation time 5426289944 ps
CPU time 14.28 seconds
Started Jun 29 07:25:43 PM PDT 24
Finished Jun 29 07:25:58 PM PDT 24
Peak memory 241972 kb
Host smart-dd96a45f-274e-4978-be01-e257c8a1e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501799257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3501799257
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.316763618
Short name T760
Test name
Test status
Simulation time 1915941451 ps
CPU time 24.81 seconds
Started Jun 29 07:25:48 PM PDT 24
Finished Jun 29 07:26:14 PM PDT 24
Peak memory 242260 kb
Host smart-bd5f36a1-0fd6-4429-a76f-fd414cd1e7bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316763618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.316763618
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.3247883021
Short name T120
Test name
Test status
Simulation time 328923878 ps
CPU time 12.19 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:25:55 PM PDT 24
Peak memory 242120 kb
Host smart-0df353e1-d109-41c3-8b63-44e04783b584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247883021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3247883021
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.1900490
Short name T464
Test name
Test status
Simulation time 1281327310 ps
CPU time 6.55 seconds
Started Jun 29 07:25:40 PM PDT 24
Finished Jun 29 07:25:48 PM PDT 24
Peak memory 242508 kb
Host smart-2974ec39-927c-48a6-8e73-b4adc75aeb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.1900490
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.2744269150
Short name T291
Test name
Test status
Simulation time 863117989283 ps
CPU time 1468.01 seconds
Started Jun 29 07:25:47 PM PDT 24
Finished Jun 29 07:50:16 PM PDT 24
Peak memory 298100 kb
Host smart-0abe874e-40a3-4c46-8e46-913790da64e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744269150 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.2744269150
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.3406678962
Short name T307
Test name
Test status
Simulation time 23495464017 ps
CPU time 49.34 seconds
Started Jun 29 07:25:42 PM PDT 24
Finished Jun 29 07:26:33 PM PDT 24
Peak memory 248876 kb
Host smart-a9ed38de-73b7-4ffe-afa6-8163820ec085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406678962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3406678962
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.430152766
Short name T650
Test name
Test status
Simulation time 1738422430 ps
CPU time 6.38 seconds
Started Jun 29 07:28:17 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 242084 kb
Host smart-f9214cdc-778c-4702-8bc2-b52927247f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430152766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.430152766
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.4035828889
Short name T617
Test name
Test status
Simulation time 459843025 ps
CPU time 4.61 seconds
Started Jun 29 07:28:17 PM PDT 24
Finished Jun 29 07:28:22 PM PDT 24
Peak memory 242292 kb
Host smart-aefb6cc2-cb19-4bcb-a1ff-68167d3afb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035828889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.4035828889
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.123480787
Short name T880
Test name
Test status
Simulation time 127850413355 ps
CPU time 882.05 seconds
Started Jun 29 07:28:18 PM PDT 24
Finished Jun 29 07:43:01 PM PDT 24
Peak memory 268348 kb
Host smart-132947b8-123a-450c-86de-14e9d01ad69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123480787 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.123480787
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.2159273816
Short name T784
Test name
Test status
Simulation time 346479831 ps
CPU time 4.45 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:28:21 PM PDT 24
Peak memory 242084 kb
Host smart-68403e11-6785-4121-aaca-31a99d7e3881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159273816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2159273816
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.1991380696
Short name T615
Test name
Test status
Simulation time 81426766 ps
CPU time 2.87 seconds
Started Jun 29 07:28:14 PM PDT 24
Finished Jun 29 07:28:17 PM PDT 24
Peak memory 241816 kb
Host smart-19c07513-4f28-4b8b-ad2c-0ac592c1f3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991380696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1991380696
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1611782639
Short name T839
Test name
Test status
Simulation time 90619923212 ps
CPU time 1619.86 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:55:17 PM PDT 24
Peak memory 273508 kb
Host smart-75a508fc-49a6-4567-9f14-2b732f5a0fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611782639 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.1611782639
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2937351803
Short name T129
Test name
Test status
Simulation time 449112320 ps
CPU time 10.39 seconds
Started Jun 29 07:28:20 PM PDT 24
Finished Jun 29 07:28:31 PM PDT 24
Peak memory 241868 kb
Host smart-e57ab8f9-63f7-4a30-b189-78c9c7b0a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937351803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2937351803
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.1726436963
Short name T755
Test name
Test status
Simulation time 2292410946 ps
CPU time 5.28 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:28:21 PM PDT 24
Peak memory 242472 kb
Host smart-8c18c5ad-57f8-46fb-9844-c9e8fa277207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726436963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1726436963
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.255562519
Short name T572
Test name
Test status
Simulation time 183086215 ps
CPU time 4.14 seconds
Started Jun 29 07:28:15 PM PDT 24
Finished Jun 29 07:28:19 PM PDT 24
Peak memory 241832 kb
Host smart-30fff8ba-3ca5-40b1-ae74-4c1d4def5f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255562519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.255562519
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.606421424
Short name T649
Test name
Test status
Simulation time 122768915 ps
CPU time 4.63 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:28:21 PM PDT 24
Peak memory 241928 kb
Host smart-db954fad-e3a1-4af0-94a9-2be498b249d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606421424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.606421424
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.130519842
Short name T133
Test name
Test status
Simulation time 2253917246 ps
CPU time 17.7 seconds
Started Jun 29 07:28:20 PM PDT 24
Finished Jun 29 07:28:38 PM PDT 24
Peak memory 242200 kb
Host smart-e6c13fe4-16b1-4f5c-95fb-870147bcef44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130519842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.130519842
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.2505856069
Short name T265
Test name
Test status
Simulation time 80472065469 ps
CPU time 1037.29 seconds
Started Jun 29 07:28:17 PM PDT 24
Finished Jun 29 07:45:36 PM PDT 24
Peak memory 470244 kb
Host smart-215d5a7f-10eb-4216-af63-858f8595af81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505856069 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2505856069
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.4045945957
Short name T325
Test name
Test status
Simulation time 337508811 ps
CPU time 3.77 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:28:20 PM PDT 24
Peak memory 241940 kb
Host smart-555a76c9-ac3f-487e-a568-bf4fdf46bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045945957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4045945957
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.4283662802
Short name T297
Test name
Test status
Simulation time 250914681 ps
CPU time 7.65 seconds
Started Jun 29 07:28:16 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 242452 kb
Host smart-70903eea-b31c-489f-acf7-2f80a0c692c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283662802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.4283662802
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.1812910569
Short name T341
Test name
Test status
Simulation time 343747574133 ps
CPU time 2049.53 seconds
Started Jun 29 07:28:18 PM PDT 24
Finished Jun 29 08:02:29 PM PDT 24
Peak memory 265348 kb
Host smart-2520114a-13b6-4844-99fb-ff282d628af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812910569 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.1812910569
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.314544192
Short name T96
Test name
Test status
Simulation time 2172006978 ps
CPU time 3.94 seconds
Started Jun 29 07:28:20 PM PDT 24
Finished Jun 29 07:28:24 PM PDT 24
Peak memory 242380 kb
Host smart-42e7c275-9804-4d25-9221-3e27c9353300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314544192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.314544192
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.3710451925
Short name T1087
Test name
Test status
Simulation time 1958778740 ps
CPU time 20.84 seconds
Started Jun 29 07:28:25 PM PDT 24
Finished Jun 29 07:28:47 PM PDT 24
Peak memory 241956 kb
Host smart-28526fa8-a2b2-4ad8-beb0-641007e2411e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710451925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.3710451925
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2406682781
Short name T1148
Test name
Test status
Simulation time 265816713 ps
CPU time 4.72 seconds
Started Jun 29 07:28:23 PM PDT 24
Finished Jun 29 07:28:29 PM PDT 24
Peak memory 241928 kb
Host smart-7ff36578-c0e8-4af9-a12b-c2ea61465193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406682781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2406682781
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.2254855236
Short name T682
Test name
Test status
Simulation time 2346047255 ps
CPU time 5.18 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:31 PM PDT 24
Peak memory 242116 kb
Host smart-5fb08ce0-3dcf-4a5f-85a1-a7f5480f5c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254855236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.2254855236
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2731359986
Short name T448
Test name
Test status
Simulation time 416252821 ps
CPU time 3.49 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:28:26 PM PDT 24
Peak memory 242296 kb
Host smart-8bd47926-da28-44ff-9ba1-cd1da6df783d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731359986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2731359986
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.573481633
Short name T95
Test name
Test status
Simulation time 281700507 ps
CPU time 4.74 seconds
Started Jun 29 07:28:24 PM PDT 24
Finished Jun 29 07:28:30 PM PDT 24
Peak memory 242376 kb
Host smart-c50b7433-851c-433c-b7ac-878e99b8f661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573481633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.573481633
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3675755021
Short name T505
Test name
Test status
Simulation time 451572040 ps
CPU time 7.3 seconds
Started Jun 29 07:28:25 PM PDT 24
Finished Jun 29 07:28:33 PM PDT 24
Peak memory 241748 kb
Host smart-2d9505fd-50ae-4abb-85f3-d748197f92b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675755021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3675755021
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1233703028
Short name T20
Test name
Test status
Simulation time 76971318470 ps
CPU time 1649.73 seconds
Started Jun 29 07:28:22 PM PDT 24
Finished Jun 29 07:55:53 PM PDT 24
Peak memory 297944 kb
Host smart-7bf8fd43-1034-47ba-a2cc-2bac8eae6a8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233703028 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1233703028
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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