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Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 9 1 10.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 10886 1 T1 2 T2 2 T3 3
true 17793 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 8 2 20.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[0] 0 1 1
others[1] 0 1 1
others[2] 0 1 1
others[3] 0 1 1
others[4] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 11887 1 T1 2 T2 3 T3 3
true 17857 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T9 2 T67 4 T64 4
others[1] 114 1 T4 2 T5 2 T67 2
others[2] 116 1 T4 2 T67 4 T62 2
others[3] 86 1 T9 2 T67 2 T188 2
others[4] 114 1 T130 2 T107 2 T73 4
others[5] 114 1 T5 2 T9 2 T102 2
others[6] 112 1 T9 2 T67 2 T93 2
others[7] 120 1 T5 8 T431 2 T64 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 80 1 T61 2 T67 2 T101 2
others[1] 68 1 T64 6 T265 2 T432 2
others[2] 86 1 T67 4 T62 4 T97 2
others[3] 98 1 T5 4 T67 2 T63 2
others[4] 98 1 T9 2 T62 2 T64 4
others[5] 102 1 T5 4 T94 2 T95 2
others[6] 84 1 T5 2 T62 2 T64 2
others[7] 150 1 T5 4 T67 2 T62 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 102 1 T5 2 T95 2 T99 2
others[1] 104 1 T5 2 T62 2 T64 2
others[2] 116 1 T9 2 T67 2 T93 2
others[3] 90 1 T5 4 T67 2 T63 2
others[4] 106 1 T5 2 T94 2 T431 2
others[5] 104 1 T5 2 T9 2 T67 2
others[6] 124 1 T5 2 T67 2 T99 2
others[7] 148 1 T5 2 T9 2 T62 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 60 1 T4 2 T133 2 T130 2
others[1] 80 1 T5 4 T95 2 T130 4
others[2] 68 1 T187 2 T99 2 T130 2
others[3] 66 1 T4 2 T5 2 T9 2
others[4] 76 1 T5 2 T9 6 T62 2
others[5] 78 1 T5 6 T9 2 T67 4
others[6] 72 1 T4 2 T9 2 T130 2
others[7] 98 1 T5 4 T67 2 T64 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 110 1 T5 4 T67 2 T64 2
others[1] 118 1 T5 2 T9 2 T95 2
others[2] 116 1 T5 2 T9 4 T67 2
others[3] 98 1 T5 2 T64 2 T130 2
others[4] 112 1 T4 2 T67 2 T62 2
others[5] 108 1 T5 2 T94 2 T96 4
others[6] 96 1 T64 6 T130 8 T433 2
others[7] 146 1 T4 2 T5 2 T9 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T5 2 T96 2 T64 2
others[1] 26 1 T73 2 T434 2 T435 2
others[2] 46 1 T101 2 T130 4 T436 2
others[3] 30 1 T67 2 T437 2 T438 2
others[4] 38 1 T188 2 T205 2 T439 2
others[5] 38 1 T67 2 T96 2 T63 2
others[6] 32 1 T99 2 T73 4 T440 2
others[7] 48 1 T67 2 T62 2 T63 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 122 1 T9 4 T62 2 T98 2
others[1] 84 1 T67 2 T62 2 T97 2
others[2] 126 1 T5 4 T95 2 T96 2
others[3] 88 1 T5 2 T67 2 T96 4
others[4] 104 1 T5 2 T67 2 T62 2
others[5] 104 1 T9 2 T95 2 T64 4
others[6] 120 1 T67 4 T62 4 T93 2
others[7] 122 1 T5 2 T9 2 T99 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 94 1 T4 2 T5 2 T67 2
others[1] 92 1 T64 2 T133 2 T130 10
others[2] 94 1 T5 2 T9 2 T62 2
others[3] 92 1 T5 4 T9 2 T99 2
others[4] 98 1 T4 2 T5 2 T67 2
others[5] 114 1 T5 2 T9 2 T62 6
others[6] 106 1 T67 2 T64 2 T130 8
others[7] 136 1 T5 2 T67 2 T62 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 126 1 T4 4 T5 4 T9 2
others[1] 92 1 T4 2 T67 2 T95 2
others[2] 100 1 T5 2 T9 2 T94 2
others[3] 72 1 T5 2 T95 2 T188 2
others[4] 90 1 T5 6 T9 2 T94 2
others[5] 100 1 T5 4 T62 2 T99 6
others[6] 84 1 T5 2 T9 2 T67 2
others[7] 114 1 T62 2 T95 2 T99 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T9 4 T64 2 T437 2
others[1] 102 1 T5 2 T62 2 T64 6
others[2] 106 1 T5 6 T67 2 T62 2
others[3] 120 1 T5 2 T9 2 T67 2
others[4] 122 1 T9 2 T62 2 T64 2
others[5] 100 1 T67 4 T95 2 T64 4
others[6] 92 1 T64 6 T130 6 T73 2
others[7] 126 1 T5 4 T62 2 T64 4
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 1 9 90.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
true 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 118 1 T5 4 T9 2 T67 2
others[1] 78 1 T5 2 T9 2 T67 2
others[2] 92 1 T95 2 T96 4 T130 4
others[3] 92 1 T67 2 T63 2 T130 8
others[4] 126 1 T4 2 T5 2 T67 2
others[5] 132 1 T4 2 T5 4 T9 2
others[6] 112 1 T9 2 T67 2 T95 2
others[7] 118 1 T5 2 T9 2 T63 2
false 15302 1 T1 4 T2 4 T3 4


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T8 1 T67 2 T134 1
others[1] 36 1 T245 1 T441 2 T299 1
others[2] 32 1 T96 2 T64 2 T245 1
others[3] 28 1 T137 1 T133 2 T292 1
others[4] 34 1 T292 2 T245 2 T395 1
others[5] 33 1 T231 1 T275 1 T294 1
others[6] 35 1 T8 1 T137 1 T130 2
others[7] 52 1 T8 1 T184 2 T137 2
false 15302 1 T1 4 T2 4 T3 4
true 2548 1 T4 7 T5 48 T6 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 41 1 T67 2 T245 2 T73 2
others[1] 37 1 T245 2 T275 1 T294 1
others[2] 39 1 T96 2 T137 1 T245 1
others[3] 43 1 T134 1 T231 1 T137 1
others[4] 28 1 T278 1 T275 2 T442 1
others[5] 28 1 T8 2 T137 1 T292 1
others[6] 30 1 T8 1 T292 2 T245 1
others[7] 42 1 T184 2 T64 2 T137 1
false 12367 1 T1 2 T2 3 T3 3
true 20321 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 108 1 T5 2 T9 2 T63 2
others[1] 110 1 T4 2 T5 2 T67 6
others[2] 112 1 T5 2 T9 4 T67 2
others[3] 110 1 T5 2 T98 2 T99 2
others[4] 106 1 T9 2 T102 2 T188 2
others[5] 96 1 T5 2 T67 2 T62 2
others[6] 106 1 T4 2 T5 2 T67 2
others[7] 130 1 T67 2 T93 2 T98 2
false 8117 1 T1 2 T2 3 T3 1
true 17876 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T62 4 T94 2 T133 2
others[1] 108 1 T5 2 T9 2 T67 2
others[2] 90 1 T5 8 T67 4 T63 2
others[3] 112 1 T5 2 T67 2 T94 2
others[4] 76 1 T130 2 T443 2 T54 2
others[5] 102 1 T62 2 T64 2 T130 2
others[6] 90 1 T99 2 T64 2 T130 4
others[7] 118 1 T5 2 T61 2 T67 2
false 7260 1 T1 2 T2 2 T3 3
true 17657 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 84 1 T5 2 T64 4 T130 4
others[1] 110 1 T5 2 T9 2 T67 2
others[2] 104 1 T5 4 T95 2 T102 2
others[3] 104 1 T5 2 T67 2 T62 2
others[4] 112 1 T5 4 T9 2 T62 2
others[5] 114 1 T9 2 T99 2 T64 4
others[6] 128 1 T5 2 T67 4 T93 4
others[7] 138 1 T431 2 T64 4 T130 10
false 7638 1 T1 2 T2 3 T3 3
true 17667 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 27 1 T8 2 T13 1 T292 1
others[1] 34 1 T13 1 T294 2 T266 1
others[2] 39 1 T5 2 T13 1 T17 1
others[3] 29 1 T8 1 T13 1 T137 1
others[4] 29 1 T137 1 T292 1 T245 1
others[5] 30 1 T8 1 T31 1 T137 1
others[6] 32 1 T292 1 T130 2 T245 3
others[7] 47 1 T6 2 T13 1 T231 1
false 12301 1 T1 2 T2 3 T3 3
true 20275 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 72 1 T4 2 T5 2 T9 2
others[1] 84 1 T5 6 T9 2 T67 4
others[2] 66 1 T5 4 T93 2 T433 2
others[3] 82 1 T4 2 T9 4 T95 4
others[4] 66 1 T9 2 T67 2 T62 2
others[5] 80 1 T5 2 T9 2 T99 2
others[6] 54 1 T130 4 T444 2 T47 2
others[7] 94 1 T4 2 T5 4 T67 2
false 9435 1 T1 2 T2 3 T3 3
true 17891 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 29 1 T17 1 T278 1 T294 2
others[1] 26 1 T8 1 T294 1 T228 1
others[2] 33 1 T278 3 T445 1 T206 2
others[3] 30 1 T8 1 T31 1 T137 1
others[4] 47 1 T67 2 T292 1 T269 1
others[5] 34 1 T231 1 T292 1 T278 1
others[6] 36 1 T5 2 T137 1 T52 2
others[7] 37 1 T137 1 T292 1 T245 2
false 12254 1 T1 2 T2 3 T3 3
true 20257 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 90 1 T5 2 T67 2 T62 2
others[1] 120 1 T94 2 T63 2 T64 2
others[2] 108 1 T9 2 T67 2 T62 2
others[3] 112 1 T5 2 T9 2 T62 2
others[4] 130 1 T4 2 T5 6 T95 2
others[5] 90 1 T4 2 T5 2 T96 2
others[6] 104 1 T9 2 T431 2 T130 4
others[7] 150 1 T5 2 T9 2 T67 2
false 8117 1 T1 2 T2 3 T3 3
true 17819 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T8 1 T292 1 T278 1
others[1] 28 1 T13 1 T67 2 T134 1
others[2] 37 1 T8 1 T62 2 T137 1
others[3] 38 1 T231 1 T137 1 T275 2
others[4] 38 1 T275 1 T441 2 T446 1
others[5] 46 1 T8 2 T17 2 T245 1
others[6] 25 1 T231 1 T269 1 T394 2
others[7] 51 1 T8 1 T245 2 T294 1
false 12223 1 T1 2 T2 3 T3 3
true 20243 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 38 1 T99 4 T130 2 T265 2
others[1] 30 1 T5 2 T130 2 T205 2
others[2] 46 1 T101 2 T96 2 T63 2
others[3] 26 1 T437 2 T447 2 T438 2
others[4] 42 1 T67 2 T96 2 T130 2
others[5] 30 1 T67 4 T62 2 T99 2
others[6] 54 1 T63 2 T73 4 T205 2
others[7] 30 1 T188 2 T73 2 T434 2
false 10588 1 T1 2 T2 3 T3 3
true 17864 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T5 4 T67 2 T96 2
others[1] 116 1 T5 2 T67 2 T95 4
others[2] 118 1 T67 2 T62 4 T93 2
others[3] 100 1 T97 2 T99 2 T64 2
others[4] 106 1 T5 2 T9 6 T67 2
others[5] 96 1 T5 2 T62 4 T96 2
others[6] 94 1 T99 4 T448 2 T73 4
others[7] 128 1 T9 2 T67 2 T62 2
false 7232 1 T1 2 T2 2 T3 3
true 17639 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 88 1 T62 4 T96 2 T63 2
others[1] 96 1 T5 4 T67 2 T63 2
others[2] 86 1 T4 2 T5 2 T9 2
others[3] 104 1 T67 2 T64 2 T130 2
others[4] 110 1 T4 2 T5 2 T9 2
others[5] 100 1 T62 2 T130 2 T444 2
others[6] 116 1 T5 2 T99 4 T431 2
others[7] 126 1 T5 4 T9 2 T67 4
false 7232 1 T1 2 T2 2 T3 3
true 17639 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 74 1 T5 4 T449 2 T99 2
others[1] 100 1 T5 2 T67 2 T94 2
others[2] 106 1 T4 4 T5 2 T62 4
others[3] 108 1 T5 2 T67 2 T99 2
others[4] 94 1 T5 2 T9 2 T67 2
others[5] 98 1 T4 2 T5 2 T67 2
others[6] 92 1 T9 4 T125 2 T99 4
others[7] 106 1 T5 6 T9 2 T95 2
false 6657 1 T1 2 T2 1 T3 3
true 17632 1 T1 5 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 112 1 T9 2 T67 2 T64 6
others[1] 78 1 T5 4 T62 2 T64 2
others[2] 98 1 T9 2 T62 4 T64 10
others[3] 128 1 T9 4 T95 2 T64 4
others[4] 94 1 T67 4 T62 4 T64 2
others[5] 116 1 T5 4 T67 2 T64 2
others[6] 104 1 T5 4 T99 2 T64 2
others[7] 126 1 T5 2 T97 2 T64 4
false 6657 1 T1 2 T2 1 T3 3
true 17632 1 T1 5 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 70 1 T4 2 T5 6 T9 2
others[1] 66 1 T64 2 T130 4 T448 2
others[2] 68 1 T62 2 T93 2 T99 2
others[3] 68 1 T67 2 T62 2 T95 2
others[4] 82 1 T5 2 T9 4 T99 2
others[5] 76 1 T9 2 T130 4 T448 2
others[6] 76 1 T4 2 T67 2 T64 4
others[7] 96 1 T5 4 T64 4 T130 2
false 7318 1 T1 2 T2 1 T3 2
true 19206 1 T1 5 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 68 1 T4 2 T67 2 T130 10
others[1] 94 1 T5 2 T67 2 T62 2
others[2] 52 1 T5 2 T99 2 T130 2
others[3] 70 1 T5 2 T67 2 T448 2
others[4] 68 1 T5 2 T67 4 T130 4
others[5] 76 1 T67 2 T133 2 T130 4
others[6] 58 1 T4 2 T67 2 T95 2
others[7] 88 1 T5 2 T188 2 T99 2
false 7318 1 T1 2 T2 1 T3 2
true 19206 1 T1 5 T2 4 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 43 1 T13 1 T449 2 T231 1
others[1] 26 1 T17 1 T292 1 T245 1
others[2] 37 1 T231 1 T292 1 T245 1
others[3] 27 1 T8 1 T13 1 T98 2
others[4] 24 1 T437 2 T450 2 T451 1
others[5] 24 1 T137 2 T245 1 T73 2
others[6] 33 1 T245 1 T294 1 T266 1
others[7] 38 1 T8 1 T17 1 T292 1
false 12452 1 T1 2 T2 3 T3 3
true 20414 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 130 1 T5 2 T9 4 T67 2
others[1] 108 1 T5 2 T95 2 T63 2
others[2] 96 1 T5 2 T431 2 T400 2
others[3] 80 1 T5 2 T9 2 T95 2
others[4] 88 1 T5 2 T67 2 T63 2
others[5] 120 1 T67 4 T94 2 T95 2
others[6] 116 1 T5 2 T9 2 T96 2
others[7] 130 1 T4 4 T5 2 T9 2
false 8084 1 T1 2 T2 3 T3 3
true 17862 1 T1 5 T2 5 T3 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 0 10 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 40 1 T8 1 T13 1 T294 2
others[1] 43 1 T8 2 T31 1 T245 4
others[2] 31 1 T8 1 T137 1 T292 3
others[3] 39 1 T13 1 T292 1 T130 2
others[4] 22 1 T8 1 T441 2 T452 2
others[5] 33 1 T231 1 T137 1 T446 1
others[6] 26 1 T13 1 T137 1 T245 1
others[7] 32 1 T5 2 T6 2 T13 2
false 15302 1 T1 4 T2 4 T3 4
true 2542 1 T4 9 T5 47 T6 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%