Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48207	1			T1	180		T3	282		T6	92
access_err	68547	1			T1	1		T4	29		T5	1063
write_blank_err	482	1			T7	4		T8	2		T9	7
ecc_uncorr_err	82452	1			T6	177		T7	476		T8	499
ecc_corr_err	1256	1			T6	8		T9	2		T149	12
no_err	99565	1			T1	1		T4	13		T5	1179

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	769	1			T7	2		T8	3		T9	16
secret2	25067	1			T1	181		T4	13		T5	266
secret1	28394	1			T4	10		T5	230		T6	6
secret0	44755	1			T5	192		T6	2		T7	5
hw_cfg1	43046	1			T4	5		T5	193		T6	84
hw_cfg0	24661	1			T4	3		T5	244		T6	37
rot_creator_auth_state	24222	1			T4	2		T5	206		T6	10
rot_creator_auth_codesign	27819	1			T4	3		T5	241		T6	27
owner_sw_cfg	25552	1			T5	209		T6	7		T7	8
creator_sw_cfg	21941	1			T3	282		T5	226		T6	48
vendor_test	34283	1			T1	1		T4	6		T5	235

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	2674	1			T1	180		T134	327		T277	153
fsm_err	secret1	2050	1			T238	27		T239	189		T401	69
fsm_err	secret0	4068	1			T9	263		T402	515		T403	73
fsm_err	hw_cfg1	3526	1			T67	253		T190	82		T404	519
fsm_err	hw_cfg0	2810	1			T405	63		T406	166		T268	132
fsm_err	rot_creator_auth_state	2629	1			T143	12		T392	448		T394	61
fsm_err	rot_creator_auth_codesign	7417	1			T12	607		T277	89		T17	46
fsm_err	owner_sw_cfg	5744	1			T100	133		T67	274		T99	351
fsm_err	creator_sw_cfg	2844	1			T3	282		T143	10		T246	157
fsm_err	vendor_test	14445	1			T6	92		T149	33		T67	703
access_err	life_cycle	769	1			T7	2		T8	3		T9	16
access_err	secret2	11825	1			T1	1		T4	13		T5	161
access_err	secret1	6925	1			T4	10		T5	127		T9	68
access_err	secret0	5475	1			T5	121		T6	2		T8	4
access_err	hw_cfg1	1508	1			T5	21		T8	2		T9	18
access_err	hw_cfg0	2332	1			T4	1		T5	43		T8	2
access_err	rot_creator_auth_state	6265	1			T5	58		T6	2		T7	1
access_err	rot_creator_auth_codesign	8662	1			T4	3		T5	124		T6	1
access_err	owner_sw_cfg	7625	1			T5	148		T7	1		T8	57
access_err	creator_sw_cfg	8714	1			T5	137		T7	7		T8	60
access_err	vendor_test	8447	1			T4	2		T5	123		T8	32
write_blank_err	secret2	13	1			T7	1		T67	1		T392	1
write_blank_err	secret1	23	1			T9	2		T67	2		T137	1
write_blank_err	secret0	70	1			T13	1		T31	1		T64	1
write_blank_err	hw_cfg1	84	1			T8	1		T9	2		T67	1
write_blank_err	hw_cfg0	16	1			T7	1		T185	1		T63	1
write_blank_err	rot_creator_auth_state	126	1			T8	1		T9	1		T13	10
write_blank_err	rot_creator_auth_codesign	53	1			T13	2		T67	2		T14	2
write_blank_err	owner_sw_cfg	42	1			T7	1		T9	1		T399	7
write_blank_err	creator_sw_cfg	23	1			T7	1		T9	1		T399	1
write_blank_err	vendor_test	32	1			T67	1		T407	3		T228	1
ecc_uncorr_err	secret2	4503	1			T7	476		T67	698		T142	51
ecc_uncorr_err	secret1	9575	1			T9	744		T67	612		T137	152
ecc_uncorr_err	secret0	26222	1			T13	504		T149	67		T31	95
ecc_uncorr_err	hw_cfg1	25605	1			T6	81		T8	499		T9	383
ecc_uncorr_err	hw_cfg0	5862	1			T6	34		T149	19		T185	658
ecc_uncorr_err	rot_creator_auth_state	5692	1			T149	14		T99	371		T142	47
ecc_uncorr_err	rot_creator_auth_codesign	1710	1			T6	21		T143	17		T408	60
ecc_uncorr_err	owner_sw_cfg	1945	1			T149	28		T142	41		T150	105
ecc_uncorr_err	creator_sw_cfg	1338	1			T6	41		T142	86		T143	6
ecc_corr_err	secret2	43	1			T6	2		T52	1		T205	1
ecc_corr_err	secret1	92	1			T6	1		T149	5		T191	1
ecc_corr_err	secret0	113	1			T191	1		T46	2		T52	1
ecc_corr_err	hw_cfg1	256	1			T9	2		T149	4		T185	2
ecc_corr_err	hw_cfg0	253	1			T6	1		T143	4		T107	1
ecc_corr_err	rot_creator_auth_state	99	1			T149	2		T46	2		T142	1
ecc_corr_err	rot_creator_auth_codesign	159	1			T6	1		T142	6		T143	1
ecc_corr_err	owner_sw_cfg	117	1			T150	1		T47	1		T53	9
ecc_corr_err	creator_sw_cfg	124	1			T6	3		T149	1		T142	4
no_err	secret2	6009	1			T5	105		T6	3		T7	7
no_err	secret1	9729	1			T5	103		T6	5		T7	9
no_err	secret0	8807	1			T5	71		T7	5		T8	45
no_err	hw_cfg1	12067	1			T4	5		T5	172		T6	3
no_err	hw_cfg0	13388	1			T4	2		T5	201		T6	2
no_err	rot_creator_auth_state	9411	1			T4	2		T5	148		T6	8
no_err	rot_creator_auth_codesign	9818	1			T5	117		T6	4		T7	4
no_err	owner_sw_cfg	10079	1			T5	61		T6	7		T7	6
no_err	creator_sw_cfg	8898	1			T5	89		T6	4		T7	4
no_err	vendor_test	11359	1			T1	1		T4	4		T5	112

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded