Summary for Variable flash_index
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for flash_index
Excluded/Illegal bins
NAME | COUNT | STATUS |
il |
0 |
Illegal |
Covered bins
| | | | | | | | | | | | |
flash_addr_key |
6816 |
1 |
|
|
T4 |
12 |
|
T5 |
74 |
|
T6 |
8 |
flash_data_key |
6812 |
1 |
|
|
T4 |
12 |
|
T5 |
67 |
|
T6 |
8 |
Summary for Variable secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for secret1_lock
Bins
| | | | | | | | | | | | |
auto[0] |
8055 |
1 |
|
|
T5 |
35 |
|
T6 |
16 |
|
T8 |
46 |
auto[1] |
5573 |
1 |
|
|
T4 |
24 |
|
T5 |
106 |
|
T9 |
50 |
Summary for Cross flash_req_lock_cross
Samples crossed: flash_index secret1_lock
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for flash_req_lock_cross
Bins
| | | | | | | | | | | | | |
flash_addr_key |
auto[0] |
4039 |
1 |
|
|
T5 |
19 |
|
T6 |
8 |
|
T8 |
23 |
flash_addr_key |
auto[1] |
2777 |
1 |
|
|
T4 |
12 |
|
T5 |
55 |
|
T9 |
25 |
flash_data_key |
auto[0] |
4016 |
1 |
|
|
T5 |
16 |
|
T6 |
8 |
|
T8 |
23 |
flash_data_key |
auto[1] |
2796 |
1 |
|
|
T4 |
12 |
|
T5 |
51 |
|
T9 |
25 |