Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1001 1 T5 7 T8 4 T9 11
all_values[1] 1001 1 T5 7 T8 4 T9 11



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1084 1 T5 11 T8 6 T9 12
auto[1] 918 1 T5 3 T8 2 T9 10



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 807 1 T5 3 T8 5 T9 14
auto[1] 1195 1 T5 11 T8 3 T9 8



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1178 1 T5 6 T8 6 T9 16
auto[1] 824 1 T5 8 T8 2 T9 6



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 12 0 12 100.00
Automatically Generated Cross Bins 12 0 12 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 209 1 T5 1 T8 4 T9 3
all_values[0] auto[0] auto[0] auto[1] 100 1 T9 1 T62 1 T231 1
all_values[0] auto[0] auto[1] auto[0] 195 1 T5 1 T9 3 T67 3
all_values[0] auto[0] auto[1] auto[1] 93 1 T5 1 T9 1 T14 1
all_values[0] auto[1] auto[0] auto[1] 235 1 T5 3 T67 1 T14 1
all_values[0] auto[1] auto[1] auto[1] 169 1 T5 1 T9 3 T13 1
all_values[1] auto[0] auto[0] auto[0] 219 1 T5 1 T8 1 T9 5
all_values[1] auto[0] auto[0] auto[1] 93 1 T5 2 T8 1 T13 2
all_values[1] auto[0] auto[1] auto[0] 184 1 T9 3 T67 2 T14 2
all_values[1] auto[0] auto[1] auto[1] 85 1 T17 2 T63 1 T231 1
all_values[1] auto[1] auto[0] auto[1] 228 1 T5 4 T9 3 T67 1
all_values[1] auto[1] auto[1] auto[1] 192 1 T8 2 T13 1 T67 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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