SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 0 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
flash_data_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
flash_data_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
flash_data_req_during_otbn_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
flash_data_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
flash_data_req_during_sram_0_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
flash_data_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12905 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
auto[1] | 931 | 1 | T7 | 2 | T73 | 10 | T91 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 13806 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
lc_esc_on | 30 | 1 | T102 | 1 | T186 | 1 | T100 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12984 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
auto[1] | 852 | 1 | T73 | 12 | T91 | 3 | T93 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2081 | 1 | T2 | 1 | T6 | 1 | T35 | 6 | ||||
auto[1] | 11755 | 1 | T1 | 2 | T2 | 1 | T3 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 11796 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
auto[1] | 2040 | 1 | T4 | 1 | T7 | 45 | T88 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13261 | 1 | T1 | 2 | T2 | 2 | T3 | 2 | ||||
auto[1] | 575 | 1 | T73 | 12 | T91 | 1 | T93 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |