Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_esc_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_esc_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_esc_during_lc_otp_prog_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_esc_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

352

1

T6

2

T97

1

T14

2

auto[1]

46

1

T97

1

T132

1

T370

1

---

Summary for Variable lc_esc_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

352

1

T97

2

T73

4

T102

1

auto[1]

46

1

T6

2

T14

2

T102

1

---

Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

354

1

T6

2

T97

2

T14

2

auto[1]

44

1

T214

1

T128

1

T358

1

---

Summary for Variable lc_esc_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

357

1

T6

2

T97

2

T14

2

auto[1]

41

1

T73

1

T228

1

T371

1

---

Summary for Variable lc_esc_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31

1

T97

1

T73

1

T102

1

auto[1]

367

1

T6

2

T97

1

T14

2

---

Summary for Variable lc_esc_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353

1

T6

2

T97

2

T14

2

auto[1]

45

1

T73

1

T100

1

T187

1

---

Summary for Variable lc_esc_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

351

1

T6

2

T97

2

T14

2

auto[1]

47

1

T73

1

T100

1

T187

2