SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
lc_prog_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_prog_req_during_flash_data_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_prog_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
lc_prog_req_during_otbn_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_prog_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_prog_req_during_sram_0_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
lc_prog_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27626 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
auto[1] | 814 | 1 | T35 | 5 | T7 | 7 | T12 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 27519 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
auto[1] | 921 | 1 | T35 | 2 | T7 | 5 | T12 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 28408 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
lc_esc_on | 32 | 1 | T214 | 1 | T128 | 1 | T358 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26797 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
auto[1] | 1643 | 1 | T35 | 2 | T13 | 1 | T7 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 15153 | 1 | T1 | 1 | T3 | 1 | T4 | 8 | ||||
auto[1] | 13287 | 1 | T1 | 1 | T3 | 1 | T4 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26903 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
auto[1] | 1537 | 1 | T35 | 4 | T7 | 8 | T12 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 26956 | 1 | T1 | 2 | T3 | 2 | T4 | 16 | ||||
auto[1] | 1484 | 1 | T35 | 4 | T7 | 7 | T12 | 4 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |