Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
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Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
secret1_lock 2 0 2 100.00 100 1 1 2
sram_index 4 0 4 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::sram_req_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sram_req_lock_cross 8 0 8 100.00 100 1 1 0


Summary for Variable secret1_lock

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for secret1_lock

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1496 1 T4 6 T7 24 T15 4
auto[1] 899 1 T7 51 T90 8 T372 1



Summary for Variable sram_index

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for sram_index

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] 81 1 T7 1 T15 1 T353 2
sram_key[0x1] 750 1 T4 1 T7 32 T90 2
sram_key[0x2] 809 1 T4 2 T7 32 T90 3
sram_key[0x3] 755 1 T4 3 T7 10 T90 3



Summary for Cross sram_req_lock_cross

Samples crossed: sram_index secret1_lock
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for sram_req_lock_cross

Bins
sram_indexsecret1_lockCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sram_key[0x0] auto[0] 55 1 T7 1 T15 1 T353 2
sram_key[0x0] auto[1] 26 1 T373 1 T130 4 T374 8
sram_key[0x1] auto[0] 448 1 T4 1 T7 10 T188 1
sram_key[0x1] auto[1] 302 1 T7 22 T90 2 T188 2
sram_key[0x2] auto[0] 508 1 T4 2 T7 9 T15 1
sram_key[0x2] auto[1] 301 1 T7 23 T90 3 T188 4
sram_key[0x3] auto[0] 485 1 T4 3 T7 4 T15 2
sram_key[0x3] auto[1] 270 1 T7 6 T90 3 T372 1

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