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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.75 93.81 96.32 95.67 90.69 97.10 96.34 93.28


Total test records in report: 1324
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T1264 /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3209518876 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:34 AM PDT 24 3015039241 ps
T277 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3937096743 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:27 AM PDT 24 1134453602 ps
T1265 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4280773212 Jul 01 10:58:28 AM PDT 24 Jul 01 10:58:36 AM PDT 24 1512296202 ps
T1266 /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.111885316 Jul 01 10:58:22 AM PDT 24 Jul 01 10:58:28 AM PDT 24 174004513 ps
T278 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4134439698 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:21 AM PDT 24 1529241492 ps
T1267 /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4094278728 Jul 01 10:58:31 AM PDT 24 Jul 01 10:58:35 AM PDT 24 103372758 ps
T1268 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3146846306 Jul 01 10:58:17 AM PDT 24 Jul 01 10:58:20 AM PDT 24 75088026 ps
T1269 /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2038195431 Jul 01 10:58:35 AM PDT 24 Jul 01 10:58:38 AM PDT 24 861706076 ps
T1270 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2796173484 Jul 01 10:58:22 AM PDT 24 Jul 01 10:58:29 AM PDT 24 222037009 ps
T1271 /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1408944502 Jul 01 10:58:29 AM PDT 24 Jul 01 10:58:32 AM PDT 24 74518611 ps
T1272 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.301743524 Jul 01 10:58:27 AM PDT 24 Jul 01 10:58:31 AM PDT 24 241716914 ps
T1273 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3496047115 Jul 01 10:58:33 AM PDT 24 Jul 01 10:58:35 AM PDT 24 69413329 ps
T1274 /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4236272496 Jul 01 10:58:17 AM PDT 24 Jul 01 10:58:21 AM PDT 24 108269319 ps
T1275 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2758007276 Jul 01 10:58:34 AM PDT 24 Jul 01 10:58:38 AM PDT 24 111558825 ps
T1276 /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2016607968 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:28 AM PDT 24 42493006 ps
T1277 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2997956420 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:26 AM PDT 24 139414672 ps
T1278 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1300640042 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:41 AM PDT 24 2557581441 ps
T1279 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2282182889 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:28 AM PDT 24 69387239 ps
T1280 /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1243570345 Jul 01 10:58:27 AM PDT 24 Jul 01 10:58:50 AM PDT 24 5061216442 ps
T282 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.798358904 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:29 AM PDT 24 65403023 ps
T1281 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3393795185 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:20 AM PDT 24 118348565 ps
T1282 /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2336196171 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:28 AM PDT 24 148676846 ps
T1283 /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1239255117 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:29 AM PDT 24 1241605017 ps
T1284 /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1670577194 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:28 AM PDT 24 151088269 ps
T1285 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2046040019 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:28 AM PDT 24 142205771 ps
T1286 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.763527636 Jul 01 10:58:17 AM PDT 24 Jul 01 10:58:22 AM PDT 24 99478542 ps
T1287 /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2906601231 Jul 01 10:58:19 AM PDT 24 Jul 01 10:58:22 AM PDT 24 36863280 ps
T1288 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1489812130 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:33 AM PDT 24 764219471 ps
T281 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2025075872 Jul 01 10:58:15 AM PDT 24 Jul 01 10:58:19 AM PDT 24 83777887 ps
T1289 /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4225922373 Jul 01 10:58:35 AM PDT 24 Jul 01 10:58:37 AM PDT 24 141003762 ps
T1290 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4106145518 Jul 01 10:58:22 AM PDT 24 Jul 01 10:58:28 AM PDT 24 1136768169 ps
T333 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3936810793 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:43 AM PDT 24 1257821184 ps
T1291 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2938957530 Jul 01 10:58:15 AM PDT 24 Jul 01 10:58:19 AM PDT 24 1128343359 ps
T1292 /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3303394047 Jul 01 10:58:29 AM PDT 24 Jul 01 10:58:33 AM PDT 24 41284618 ps
T1293 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2511702896 Jul 01 10:58:19 AM PDT 24 Jul 01 10:58:22 AM PDT 24 65443558 ps
T1294 /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2797482137 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:27 AM PDT 24 529512505 ps
T1295 /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.1105798704 Jul 01 10:58:31 AM PDT 24 Jul 01 10:58:34 AM PDT 24 87734305 ps
T243 /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2640943114 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:37 AM PDT 24 1558131045 ps
T1296 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3741262226 Jul 01 10:58:28 AM PDT 24 Jul 01 10:58:33 AM PDT 24 364399290 ps
T1297 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2204025169 Jul 01 10:58:22 AM PDT 24 Jul 01 10:58:27 AM PDT 24 77092340 ps
T1298 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.105181202 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:26 AM PDT 24 189727321 ps
T1299 /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4124763718 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:18 AM PDT 24 45528015 ps
T1300 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1287815453 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:19 AM PDT 24 34911366 ps
T1301 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.409027272 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:30 AM PDT 24 84796225 ps
T1302 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1529986238 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:27 AM PDT 24 826909969 ps
T1303 /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1521222322 Jul 01 10:58:13 AM PDT 24 Jul 01 10:58:15 AM PDT 24 77136907 ps
T279 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.855951868 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:24 AM PDT 24 149919998 ps
T1304 /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1122488271 Jul 01 10:58:19 AM PDT 24 Jul 01 10:58:23 AM PDT 24 602228252 ps
T327 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.432659513 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:47 AM PDT 24 2402964056 ps
T1305 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2806248846 Jul 01 10:58:29 AM PDT 24 Jul 01 10:58:32 AM PDT 24 36292037 ps
T1306 /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1793359573 Jul 01 10:58:16 AM PDT 24 Jul 01 10:58:19 AM PDT 24 639703867 ps
T280 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.479452879 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:28 AM PDT 24 110168964 ps
T1307 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4128418995 Jul 01 10:58:31 AM PDT 24 Jul 01 10:58:34 AM PDT 24 73431084 ps
T291 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4008317154 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:30 AM PDT 24 735653189 ps
T328 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2239744190 Jul 01 10:58:22 AM PDT 24 Jul 01 10:58:45 AM PDT 24 10489346787 ps
T1308 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4085564047 Jul 01 10:58:02 AM PDT 24 Jul 01 10:58:04 AM PDT 24 37410150 ps
T1309 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.107463950 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:24 AM PDT 24 88343768 ps
T1310 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2262254728 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:29 AM PDT 24 73257976 ps
T1311 /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2639745235 Jul 01 10:58:29 AM PDT 24 Jul 01 10:58:33 AM PDT 24 556767773 ps
T1312 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1701148643 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:28 AM PDT 24 779506402 ps
T1313 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2239889910 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:25 AM PDT 24 109778170 ps
T1314 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3973354705 Jul 01 10:58:23 AM PDT 24 Jul 01 10:58:28 AM PDT 24 73176754 ps
T1315 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4211526421 Jul 01 10:58:30 AM PDT 24 Jul 01 10:58:36 AM PDT 24 795114435 ps
T1316 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.802157971 Jul 01 10:58:24 AM PDT 24 Jul 01 10:58:29 AM PDT 24 577666389 ps
T293 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4181649402 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:20 AM PDT 24 72516456 ps
T1317 /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1776678380 Jul 01 10:58:03 AM PDT 24 Jul 01 10:58:05 AM PDT 24 151482445 ps
T1318 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1763552489 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:25 AM PDT 24 145716149 ps
T1319 /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1289155579 Jul 01 10:58:21 AM PDT 24 Jul 01 10:58:26 AM PDT 24 570981954 ps
T1320 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1933346221 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:23 AM PDT 24 111406719 ps
T1321 /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4227690402 Jul 01 10:58:25 AM PDT 24 Jul 01 10:58:29 AM PDT 24 126252239 ps
T1322 /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.651137744 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:24 AM PDT 24 104635463 ps
T292 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1872106360 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:21 AM PDT 24 40229644 ps
T1323 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2575905760 Jul 01 10:58:20 AM PDT 24 Jul 01 10:58:27 AM PDT 24 1817479863 ps
T1324 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2314183949 Jul 01 10:58:18 AM PDT 24 Jul 01 10:58:29 AM PDT 24 573054699 ps

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2020850661
Short name T4
Test name
Test status
Simulation time 105333091381 ps
CPU time 610.07 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 01:02:20 PM PDT 24
Peak memory 304732 kb
Host smart-ac6fbda1-ac73-415e-8fdb-19a19f2cf7c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020850661 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.2020850661
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.1844463214
Short name T73
Test name
Test status
Simulation time 33322388397 ps
CPU time 306.03 seconds
Started Jul 01 12:53:19 PM PDT 24
Finished Jul 01 12:58:28 PM PDT 24
Peak memory 265172 kb
Host smart-ddd5d747-401f-4c9b-9d14-97a12ce066cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844463214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.1844463214
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2724062758
Short name T100
Test name
Test status
Simulation time 14261601434 ps
CPU time 192.97 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:56:10 PM PDT 24
Peak memory 256464 kb
Host smart-075dd80c-a190-4c3e-bacd-5de59b94ed9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724062758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2724062758
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.2165597826
Short name T20
Test name
Test status
Simulation time 10672762871 ps
CPU time 206.69 seconds
Started Jul 01 12:51:02 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 274368 kb
Host smart-606363ec-5fbe-4acc-917c-c8c7dc87736f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165597826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2165597826
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1237136691
Short name T27
Test name
Test status
Simulation time 964638703 ps
CPU time 24.48 seconds
Started Jul 01 12:53:37 PM PDT 24
Finished Jul 01 12:54:03 PM PDT 24
Peak memory 242300 kb
Host smart-73608d1f-8d91-4b99-b770-8d6074a04bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237136691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1237136691
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.3040817877
Short name T153
Test name
Test status
Simulation time 2410230976 ps
CPU time 5.3 seconds
Started Jul 01 12:55:29 PM PDT 24
Finished Jul 01 12:55:36 PM PDT 24
Peak memory 242532 kb
Host smart-e455c823-f483-4f61-b5a5-1054bb0a28a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040817877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.3040817877
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3038553856
Short name T38
Test name
Test status
Simulation time 217803558444 ps
CPU time 2136.02 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 01:27:25 PM PDT 24
Peak memory 312744 kb
Host smart-ca29f6eb-e2d1-46e7-8001-0e22e888eb96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038553856 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3038553856
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.399890659
Short name T97
Test name
Test status
Simulation time 1597332778 ps
CPU time 14.05 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 241756 kb
Host smart-1ea4aca9-d189-413f-a9e5-a16d50788c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399890659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.399890659
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.1439653482
Short name T23
Test name
Test status
Simulation time 131181516 ps
CPU time 3.43 seconds
Started Jul 01 12:55:35 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242132 kb
Host smart-db01b203-4ee3-42f5-adff-7b5da20adead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439653482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.1439653482
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.3630927630
Short name T218
Test name
Test status
Simulation time 12554807544 ps
CPU time 235.88 seconds
Started Jul 01 12:53:34 PM PDT 24
Finished Jul 01 12:57:31 PM PDT 24
Peak memory 249084 kb
Host smart-8ba510fb-4eeb-4a29-af63-067abbd31d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630927630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.3630927630
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3405185384
Short name T237
Test name
Test status
Simulation time 2568315527 ps
CPU time 20.1 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:44 AM PDT 24
Peak memory 239332 kb
Host smart-e1fb8386-d986-4f98-ada7-34054fdf8ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405185384 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.3405185384
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.242028006
Short name T146
Test name
Test status
Simulation time 24967528870 ps
CPU time 37.97 seconds
Started Jul 01 12:52:00 PM PDT 24
Finished Jul 01 12:52:39 PM PDT 24
Peak memory 257940 kb
Host smart-7a927ac2-dbde-4828-b5ed-0ff0bf9a5396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242028006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.242028006
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.1091217607
Short name T26
Test name
Test status
Simulation time 717970397 ps
CPU time 4.81 seconds
Started Jul 01 12:54:37 PM PDT 24
Finished Jul 01 12:54:42 PM PDT 24
Peak memory 241996 kb
Host smart-db1b0e7c-1c97-4025-a27f-8216df2d8baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091217607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1091217607
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3011293145
Short name T7
Test name
Test status
Simulation time 30788119865 ps
CPU time 273.24 seconds
Started Jul 01 12:51:50 PM PDT 24
Finished Jul 01 12:56:24 PM PDT 24
Peak memory 298372 kb
Host smart-8eae5e10-cd52-4eb1-9378-44966156fa6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011293145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3011293145
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.908219081
Short name T84
Test name
Test status
Simulation time 293782047 ps
CPU time 4.51 seconds
Started Jul 01 12:55:05 PM PDT 24
Finished Jul 01 12:55:11 PM PDT 24
Peak memory 241812 kb
Host smart-c96f4cb9-8a02-477a-9ef2-a4ca9203e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908219081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.908219081
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3532694182
Short name T18
Test name
Test status
Simulation time 42104003869 ps
CPU time 1037.09 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 01:11:18 PM PDT 24
Peak memory 337200 kb
Host smart-ee2a6d78-cf7d-446a-8a33-d278daebb395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532694182 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.3532694182
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.293498698
Short name T53
Test name
Test status
Simulation time 1397439413 ps
CPU time 28.64 seconds
Started Jul 01 12:52:22 PM PDT 24
Finished Jul 01 12:52:52 PM PDT 24
Peak memory 248764 kb
Host smart-853b4b6c-243a-4722-a098-0f13147cf41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293498698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.293498698
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.2373513683
Short name T57
Test name
Test status
Simulation time 150539375 ps
CPU time 4.24 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 241964 kb
Host smart-b6f9a649-0689-40df-a50c-fddd80218d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373513683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2373513683
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.1949645422
Short name T254
Test name
Test status
Simulation time 138022093960 ps
CPU time 2181.12 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 01:30:44 PM PDT 24
Peak memory 572732 kb
Host smart-32a17935-1fdc-41a6-90d9-27715e297cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949645422 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.1949645422
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1838914100
Short name T139
Test name
Test status
Simulation time 186164981609 ps
CPU time 1486.12 seconds
Started Jul 01 12:51:07 PM PDT 24
Finished Jul 01 01:15:56 PM PDT 24
Peak memory 346464 kb
Host smart-fd859c24-7493-43c8-8221-18c72a8a2d09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838914100 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.1838914100
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.3970714472
Short name T155
Test name
Test status
Simulation time 268972570 ps
CPU time 3.65 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 241852 kb
Host smart-53213610-507e-4d8e-9bd4-97cebdcecb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970714472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3970714472
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.83819296
Short name T113
Test name
Test status
Simulation time 22961979297 ps
CPU time 184.6 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 249100 kb
Host smart-27fea908-da6e-4fe4-9539-634c8a2f2e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83819296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.83819296
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2295979705
Short name T68
Test name
Test status
Simulation time 2695074178 ps
CPU time 22.35 seconds
Started Jul 01 12:51:37 PM PDT 24
Finished Jul 01 12:52:00 PM PDT 24
Peak memory 245020 kb
Host smart-c727c4bb-d724-48fc-9032-9c938815d852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295979705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2295979705
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.1153313557
Short name T9
Test name
Test status
Simulation time 107144844 ps
CPU time 2.02 seconds
Started Jul 01 12:53:18 PM PDT 24
Finished Jul 01 12:53:23 PM PDT 24
Peak memory 240144 kb
Host smart-91b20168-6b0b-4aa9-a3ba-a97e28170d35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153313557 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1153313557
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.3201715695
Short name T443
Test name
Test status
Simulation time 123382897 ps
CPU time 4.88 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:13 PM PDT 24
Peak memory 242064 kb
Host smart-4cf928ea-c52f-4677-b96f-db846c74fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201715695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.3201715695
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.804383449
Short name T42
Test name
Test status
Simulation time 638170958 ps
CPU time 5.65 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 242340 kb
Host smart-d93e365a-a562-4bd6-8651-6e5f3b58b0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804383449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.804383449
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1565306553
Short name T65
Test name
Test status
Simulation time 2509971177 ps
CPU time 6.52 seconds
Started Jul 01 12:55:16 PM PDT 24
Finished Jul 01 12:55:24 PM PDT 24
Peak memory 242220 kb
Host smart-f05a4cca-a046-4213-860f-f84616e26265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565306553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1565306553
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.2454518145
Short name T130
Test name
Test status
Simulation time 12824585969 ps
CPU time 174.7 seconds
Started Jul 01 12:52:08 PM PDT 24
Finished Jul 01 12:55:03 PM PDT 24
Peak memory 274448 kb
Host smart-b4aa91a0-a6b5-4d6d-a297-29e6a5fa25fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454518145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all
.2454518145
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.1384337115
Short name T16
Test name
Test status
Simulation time 334237688942 ps
CPU time 2239.79 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 01:31:15 PM PDT 24
Peak memory 373100 kb
Host smart-2673dd50-79bc-4ada-91e2-050d80ad9d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384337115 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.1384337115
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2113019283
Short name T60
Test name
Test status
Simulation time 12799507123 ps
CPU time 26.18 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:53:22 PM PDT 24
Peak memory 243708 kb
Host smart-7abcf97e-85f8-4b10-aee7-68fe06ccda99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113019283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2113019283
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.841098336
Short name T197
Test name
Test status
Simulation time 6363959775 ps
CPU time 54.87 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 258024 kb
Host smart-ecf6633d-e42e-492f-ad58-9ab8adf00052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841098336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.841098336
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.4247285018
Short name T69
Test name
Test status
Simulation time 4513437323 ps
CPU time 59.39 seconds
Started Jul 01 12:53:15 PM PDT 24
Finished Jul 01 12:54:17 PM PDT 24
Peak memory 248816 kb
Host smart-329548e1-8fd4-4fbc-a8a5-af1e9fc2293e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247285018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.4247285018
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.1750921041
Short name T143
Test name
Test status
Simulation time 23085358540 ps
CPU time 223.95 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:57:26 PM PDT 24
Peak memory 266440 kb
Host smart-21798758-c7dc-4be5-b171-ddc11597481f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750921041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all
.1750921041
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1967370639
Short name T44
Test name
Test status
Simulation time 656819777 ps
CPU time 4.14 seconds
Started Jul 01 12:54:57 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241952 kb
Host smart-b1d7f133-5dea-4f39-a808-7f27789e0b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967370639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1967370639
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.1109058594
Short name T730
Test name
Test status
Simulation time 2200991419 ps
CPU time 5.78 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 241904 kb
Host smart-7611056d-cd56-4703-8240-eaacb8e5059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109058594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.1109058594
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1995822798
Short name T33
Test name
Test status
Simulation time 1892651782 ps
CPU time 5.31 seconds
Started Jul 01 12:54:38 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 241960 kb
Host smart-eaa31661-627c-4d8f-9c43-0726d64a2bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995822798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1995822798
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.2489299963
Short name T336
Test name
Test status
Simulation time 641557791 ps
CPU time 11.34 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 242240 kb
Host smart-1821fe5e-c52e-47a5-b96d-6391383097fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489299963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2489299963
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.2785197137
Short name T58
Test name
Test status
Simulation time 2574202433 ps
CPU time 7.3 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:03 PM PDT 24
Peak memory 241968 kb
Host smart-5493fd45-0d84-495b-980f-ae1c94998428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785197137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2785197137
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3274841363
Short name T5
Test name
Test status
Simulation time 287537091 ps
CPU time 4.21 seconds
Started Jul 01 12:54:59 PM PDT 24
Finished Jul 01 12:55:04 PM PDT 24
Peak memory 242324 kb
Host smart-ab784011-f6fe-4a2e-8044-a11558f9049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274841363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3274841363
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.122372441
Short name T171
Test name
Test status
Simulation time 504930107 ps
CPU time 3.71 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 242328 kb
Host smart-00cc7501-028b-4559-9b3e-7270a75fd078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122372441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.122372441
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.4050584724
Short name T234
Test name
Test status
Simulation time 16736992305 ps
CPU time 246.97 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:56:38 PM PDT 24
Peak memory 273384 kb
Host smart-5edc858b-0b7d-4031-a6e2-7b6c0dbaefe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050584724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.4050584724
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.639532538
Short name T334
Test name
Test status
Simulation time 1368597863 ps
CPU time 19.43 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:36 AM PDT 24
Peak memory 244452 kb
Host smart-dc93d1c0-0ef0-4919-a1ac-52d0e90deac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639532538 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.639532538
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3937096743
Short name T277
Test name
Test status
Simulation time 1134453602 ps
CPU time 5.76 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239192 kb
Host smart-4b6bc8b4-2772-40a3-a0a0-5c7f859c0ab6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937096743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.3937096743
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.2005889025
Short name T126
Test name
Test status
Simulation time 17085669763 ps
CPU time 229.79 seconds
Started Jul 01 12:52:52 PM PDT 24
Finished Jul 01 12:56:43 PM PDT 24
Peak memory 280840 kb
Host smart-5201b156-3146-45e6-99bb-2eb8fcb54fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005889025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.2005889025
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.382087224
Short name T31
Test name
Test status
Simulation time 968587018 ps
CPU time 22.02 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 242964 kb
Host smart-5d8ff55c-4539-4c4a-9802-40b232e5c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382087224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.382087224
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.112740577
Short name T46
Test name
Test status
Simulation time 1166067211 ps
CPU time 16.75 seconds
Started Jul 01 12:51:11 PM PDT 24
Finished Jul 01 12:51:28 PM PDT 24
Peak memory 242580 kb
Host smart-5cfdc551-faaf-4e4d-af44-2c48a26ec75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112740577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.112740577
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.1037820983
Short name T731
Test name
Test status
Simulation time 762776673 ps
CPU time 4.99 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:36 PM PDT 24
Peak memory 242368 kb
Host smart-11c3b3bf-0fd2-43da-a62a-b7463e29ec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037820983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1037820983
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.3524685519
Short name T311
Test name
Test status
Simulation time 1033257630 ps
CPU time 8.81 seconds
Started Jul 01 12:54:43 PM PDT 24
Finished Jul 01 12:54:53 PM PDT 24
Peak memory 241696 kb
Host smart-9304f4c5-6795-4923-b0c0-59f4819c1672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524685519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.3524685519
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.3849134376
Short name T134
Test name
Test status
Simulation time 508499582 ps
CPU time 6.66 seconds
Started Jul 01 12:54:52 PM PDT 24
Finished Jul 01 12:55:00 PM PDT 24
Peak memory 241820 kb
Host smart-7f47ca67-ad2f-462c-86b0-980598e6c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849134376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.3849134376
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.884814186
Short name T224
Test name
Test status
Simulation time 18410479499 ps
CPU time 60.3 seconds
Started Jul 01 12:54:53 PM PDT 24
Finished Jul 01 12:55:54 PM PDT 24
Peak memory 243340 kb
Host smart-9551baa7-7ce4-43fc-9f54-06f2bd83da24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884814186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.884814186
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.153081752
Short name T120
Test name
Test status
Simulation time 394861065 ps
CPU time 12.18 seconds
Started Jul 01 12:54:59 PM PDT 24
Finished Jul 01 12:55:11 PM PDT 24
Peak memory 242164 kb
Host smart-4fdb431e-ad83-4079-b10e-160e4bf9c171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153081752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.153081752
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2991884448
Short name T36
Test name
Test status
Simulation time 674966336 ps
CPU time 5 seconds
Started Jul 01 12:55:21 PM PDT 24
Finished Jul 01 12:55:27 PM PDT 24
Peak memory 241932 kb
Host smart-a7d7fa80-defb-48a5-9bbf-e7083c20f4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991884448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2991884448
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.717810216
Short name T131
Test name
Test status
Simulation time 1505898706 ps
CPU time 6.46 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:52:40 PM PDT 24
Peak memory 241808 kb
Host smart-73cf648f-0ddc-4873-a457-c1e7ea675fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717810216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.717810216
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.2118115850
Short name T190
Test name
Test status
Simulation time 813302936 ps
CPU time 11.07 seconds
Started Jul 01 12:52:46 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 242280 kb
Host smart-629adfc4-51c6-4d08-8b13-9d3cfbc77dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118115850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2118115850
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.2516956389
Short name T708
Test name
Test status
Simulation time 535833496 ps
CPU time 9.76 seconds
Started Jul 01 12:51:50 PM PDT 24
Finished Jul 01 12:52:00 PM PDT 24
Peak memory 242124 kb
Host smart-1dddc773-d9de-478d-96d7-42d1cadeaa09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516956389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.2516956389
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.2104621617
Short name T332
Test name
Test status
Simulation time 5423762468 ps
CPU time 21.12 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:51 AM PDT 24
Peak memory 239328 kb
Host smart-875fb0b1-cc04-4c5e-a519-3665ebeafb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104621617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_i
ntg_err.2104621617
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.326445183
Short name T249
Test name
Test status
Simulation time 4178421643 ps
CPU time 10.57 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 242080 kb
Host smart-b0997c42-84c9-4f10-a539-59acaf612320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326445183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.326445183
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2466730598
Short name T302
Test name
Test status
Simulation time 94535206 ps
CPU time 1.96 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 242048 kb
Host smart-b680acff-2573-4af2-929b-8761d1b88e05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466730598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_c
trl_same_csr_outstanding.2466730598
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.292105191
Short name T123
Test name
Test status
Simulation time 7922194480 ps
CPU time 37.44 seconds
Started Jul 01 12:52:39 PM PDT 24
Finished Jul 01 12:53:18 PM PDT 24
Peak memory 246492 kb
Host smart-57298088-1dd3-47f5-ba12-95009937a0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292105191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.292105191
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1589379991
Short name T221
Test name
Test status
Simulation time 94060902827 ps
CPU time 336.6 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:59:30 PM PDT 24
Peak memory 287384 kb
Host smart-41871a54-5f4b-4569-a390-afeca39475f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589379991 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.1589379991
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.2099033035
Short name T87
Test name
Test status
Simulation time 1888839469 ps
CPU time 4.15 seconds
Started Jul 01 12:55:32 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 242068 kb
Host smart-85f6e032-869c-45f5-a989-75ed34aab4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099033035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.2099033035
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.2731474344
Short name T204
Test name
Test status
Simulation time 224180008 ps
CPU time 4.39 seconds
Started Jul 01 12:54:34 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 242124 kb
Host smart-60f66dd2-8510-42c3-9bf1-01239eb3a0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731474344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.2731474344
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.1303205562
Short name T77
Test name
Test status
Simulation time 150562775 ps
CPU time 3.7 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241892 kb
Host smart-df6af4ba-ddb4-492f-a007-460b8ac34054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303205562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1303205562
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.432659513
Short name T327
Test name
Test status
Simulation time 2402964056 ps
CPU time 20.61 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:47 AM PDT 24
Peak memory 244696 kb
Host smart-d5f072de-4691-439a-b16c-993ed51fd5dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432659513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_in
tg_err.432659513
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1702156300
Short name T1067
Test name
Test status
Simulation time 1000983751 ps
CPU time 9.14 seconds
Started Jul 01 12:52:31 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 242024 kb
Host smart-a0449c01-15ad-4297-be59-6aa3e8af96ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1702156300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1702156300
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.3506798143
Short name T376
Test name
Test status
Simulation time 80391811585 ps
CPU time 1267.62 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 01:15:34 PM PDT 24
Peak memory 338548 kb
Host smart-ca06a632-bdc6-491b-83a1-bb7413cd2573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506798143 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.3506798143
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1044078724
Short name T217
Test name
Test status
Simulation time 2863742097 ps
CPU time 21.48 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 242008 kb
Host smart-dd2647fa-baa1-4f43-a5da-72988d622462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044078724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1044078724
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.669429948
Short name T149
Test name
Test status
Simulation time 769142474 ps
CPU time 2.27 seconds
Started Jul 01 12:50:50 PM PDT 24
Finished Jul 01 12:50:54 PM PDT 24
Peak memory 240140 kb
Host smart-9b624e15-6e05-4602-8222-9cfe5df2dea3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=669429948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.669429948
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.1488387007
Short name T1140
Test name
Test status
Simulation time 493788481 ps
CPU time 3.8 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 241916 kb
Host smart-4cddaa2e-9153-40d4-94be-cdbc4b79145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488387007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1488387007
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3914821415
Short name T91
Test name
Test status
Simulation time 16506555703 ps
CPU time 92.78 seconds
Started Jul 01 12:53:11 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 247128 kb
Host smart-405189d6-8ddd-4613-80fe-49a38ba38d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914821415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3914821415
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.2640943114
Short name T243
Test name
Test status
Simulation time 1558131045 ps
CPU time 10.23 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:37 AM PDT 24
Peak memory 239212 kb
Host smart-d420615d-a3a5-4a89-93a3-74ed994fcf64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640943114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.2640943114
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2841158815
Short name T244
Test name
Test status
Simulation time 1274926616 ps
CPU time 19.06 seconds
Started Jul 01 10:58:15 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 244368 kb
Host smart-ffedcf17-47e9-4044-89ae-8c98ab6f9f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841158815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2841158815
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.497537085
Short name T61
Test name
Test status
Simulation time 114921400 ps
CPU time 3.37 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 242052 kb
Host smart-e1250090-d609-44a4-a3f2-7d90aad9ab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497537085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.497537085
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.4216849914
Short name T222
Test name
Test status
Simulation time 63461565503 ps
CPU time 505.71 seconds
Started Jul 01 12:51:40 PM PDT 24
Finished Jul 01 01:00:07 PM PDT 24
Peak memory 273372 kb
Host smart-8014fec0-c600-4d27-b68d-34b4e6ac8f82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216849914 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.4216849914
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1589150616
Short name T354
Test name
Test status
Simulation time 789658415 ps
CPU time 19.78 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:51:11 PM PDT 24
Peak memory 242296 kb
Host smart-846409f8-1360-4c13-90d9-70b881015ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589150616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1589150616
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1295117587
Short name T85
Test name
Test status
Simulation time 127252158 ps
CPU time 4.58 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241860 kb
Host smart-3948d8a8-b41b-4ba4-bb57-114c8f42a08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295117587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1295117587
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.3512311456
Short name T11
Test name
Test status
Simulation time 159493962 ps
CPU time 4.75 seconds
Started Jul 01 12:55:04 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 241916 kb
Host smart-3ddee054-e275-414d-8514-d35bf6affdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512311456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3512311456
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.2892285503
Short name T942
Test name
Test status
Simulation time 33608970371 ps
CPU time 368.33 seconds
Started Jul 01 12:52:50 PM PDT 24
Finished Jul 01 12:58:59 PM PDT 24
Peak memory 256988 kb
Host smart-ee14a7e8-1627-4a98-82e0-d3d9028d24c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892285503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.2892285503
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.855951868
Short name T279
Test name
Test status
Simulation time 149919998 ps
CPU time 4.8 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 239108 kb
Host smart-c4243645-b33f-4226-a9e2-d4d0a3f9d5dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855951868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alias
ing.855951868
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2025075872
Short name T281
Test name
Test status
Simulation time 83777887 ps
CPU time 3.9 seconds
Started Jul 01 10:58:15 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 240508 kb
Host smart-5d1cca92-e8aa-45ed-8f49-1b2b8672569e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025075872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_
bash.2025075872
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2077105385
Short name T274
Test name
Test status
Simulation time 201150571 ps
CPU time 2.42 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 239192 kb
Host smart-d1d22711-e056-44e2-8365-dd6a11c84db5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077105385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.2077105385
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.4106145518
Short name T1290
Test name
Test status
Simulation time 1136768169 ps
CPU time 3.07 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 246168 kb
Host smart-c97bf38e-6994-4d31-8d9b-390b60aa317f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106145518 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.4106145518
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.3886217665
Short name T296
Test name
Test status
Simulation time 81078279 ps
CPU time 1.54 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 239248 kb
Host smart-bddac9b6-c9d1-4dd6-896e-ab8fd29eef00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886217665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.3886217665
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1776678380
Short name T1317
Test name
Test status
Simulation time 151482445 ps
CPU time 1.63 seconds
Started Jul 01 10:58:03 AM PDT 24
Finished Jul 01 10:58:05 AM PDT 24
Peak memory 230540 kb
Host smart-df9b1ac2-9649-480c-b118-4042dc9a0cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776678380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1776678380
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3054661093
Short name T1225
Test name
Test status
Simulation time 544046029 ps
CPU time 1.52 seconds
Started Jul 01 10:58:14 AM PDT 24
Finished Jul 01 10:58:15 AM PDT 24
Peak memory 229832 kb
Host smart-d9d89b08-e9cf-420a-90f2-7f1b40e19fbd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054661093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctr
l_mem_partial_access.3054661093
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.4085564047
Short name T1308
Test name
Test status
Simulation time 37410150 ps
CPU time 1.43 seconds
Started Jul 01 10:58:02 AM PDT 24
Finished Jul 01 10:58:04 AM PDT 24
Peak memory 229992 kb
Host smart-1b7d194f-f65a-4f05-b3a0-d1e611a4fb7b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085564047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.4085564047
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.1793359573
Short name T1306
Test name
Test status
Simulation time 639703867 ps
CPU time 2.17 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 239284 kb
Host smart-ec943cc4-c948-46f3-8c8f-b8fa79479d1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793359573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.1793359573
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3068778424
Short name T1254
Test name
Test status
Simulation time 277893429 ps
CPU time 5.09 seconds
Started Jul 01 10:58:02 AM PDT 24
Finished Jul 01 10:58:07 AM PDT 24
Peak memory 246536 kb
Host smart-207e6358-5b13-4dbf-98db-f24fa9d846e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068778424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3068778424
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3566481548
Short name T330
Test name
Test status
Simulation time 4776235327 ps
CPU time 23 seconds
Started Jul 01 10:58:03 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 239476 kb
Host smart-ea8d3e3b-60fc-47d8-bf0a-c9da9eeccfaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566481548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.3566481548
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.2575905760
Short name T1323
Test name
Test status
Simulation time 1817479863 ps
CPU time 5.4 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239228 kb
Host smart-b02d569e-2b3e-4833-b489-270ef7563f9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575905760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alia
sing.2575905760
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.2314183949
Short name T1324
Test name
Test status
Simulation time 573054699 ps
CPU time 9.72 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 239128 kb
Host smart-ba8e91eb-4f1c-4b0e-9748-b347a169b5b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314183949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_
bash.2314183949
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4134439698
Short name T278
Test name
Test status
Simulation time 1529241492 ps
CPU time 4.28 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 241292 kb
Host smart-7436a71c-c13f-4e29-974c-cd90f529dcc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134439698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.4134439698
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1449905320
Short name T1216
Test name
Test status
Simulation time 180738018 ps
CPU time 2.83 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 246492 kb
Host smart-dc1cdb03-76dc-41b7-816c-b8b063179bf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449905320 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1449905320
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2457034592
Short name T275
Test name
Test status
Simulation time 69985338 ps
CPU time 1.58 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 239212 kb
Host smart-95a65b17-f688-42a9-aec0-232d4934a6c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457034592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2457034592
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.1521222322
Short name T1303
Test name
Test status
Simulation time 77136907 ps
CPU time 1.47 seconds
Started Jul 01 10:58:13 AM PDT 24
Finished Jul 01 10:58:15 AM PDT 24
Peak memory 230624 kb
Host smart-ea0cca76-ac20-400b-9bbb-7d819b4d951c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521222322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1521222322
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.21762454
Short name T1205
Test name
Test status
Simulation time 142225674 ps
CPU time 1.52 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 229876 kb
Host smart-57abdd84-c122-4799-9d51-8b8d87498730
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21762454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_
mem_partial_access.21762454
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2667252022
Short name T1231
Test name
Test status
Simulation time 71978794 ps
CPU time 1.33 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 230220 kb
Host smart-7acde933-2e70-4a24-bdc8-695454386d6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667252022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.2667252022
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.4064551482
Short name T1247
Test name
Test status
Simulation time 136722504 ps
CPU time 3.28 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 239396 kb
Host smart-79d9be2a-ee32-457e-9032-b72571e955d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064551482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.4064551482
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3936810793
Short name T333
Test name
Test status
Simulation time 1257821184 ps
CPU time 16.73 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:43 AM PDT 24
Peak memory 244468 kb
Host smart-965a4689-f0a0-4b64-b83a-badc47c8986a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936810793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.3936810793
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.1610557774
Short name T1229
Test name
Test status
Simulation time 74158319 ps
CPU time 2.24 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 244776 kb
Host smart-4ce4a848-a26f-4c35-b718-9d98a43dde4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610557774 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.1610557774
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.798358904
Short name T282
Test name
Test status
Simulation time 65403023 ps
CPU time 1.65 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 239204 kb
Host smart-8a1a860d-bc15-49a9-9dd3-743105429157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798358904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.798358904
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.1763552489
Short name T1318
Test name
Test status
Simulation time 145716149 ps
CPU time 1.43 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:25 AM PDT 24
Peak memory 230552 kb
Host smart-de4df708-1451-47b8-a178-f80c85d3046c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763552489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1763552489
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2282182889
Short name T1279
Test name
Test status
Simulation time 69387239 ps
CPU time 2.37 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 239180 kb
Host smart-197725a5-0e61-4d53-99d1-2ec700f7d5db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282182889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.2282182889
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.1471751642
Short name T1252
Test name
Test status
Simulation time 191548279 ps
CPU time 2.8 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:25 AM PDT 24
Peak memory 246096 kb
Host smart-b677f72f-7e8b-48b9-9ba4-21929bfd3c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471751642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1471751642
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3741262226
Short name T1296
Test name
Test status
Simulation time 364399290 ps
CPU time 3.27 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 247132 kb
Host smart-efac3914-6de6-4dda-bcdf-52da69b03447
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741262226 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3741262226
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.3206051010
Short name T271
Test name
Test status
Simulation time 144674136 ps
CPU time 1.43 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 240676 kb
Host smart-c7e910e6-982a-42a6-8e53-84833654d326
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206051010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.3206051010
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.3973354705
Short name T1314
Test name
Test status
Simulation time 73176754 ps
CPU time 1.41 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 230276 kb
Host smart-791a11c0-eba0-4a06-9d54-78a00f02a22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973354705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3973354705
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.530400961
Short name T295
Test name
Test status
Simulation time 88517939 ps
CPU time 2.9 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 239144 kb
Host smart-8ad44ad2-203f-49f3-9954-06164296df6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530400961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_c
trl_same_csr_outstanding.530400961
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.4280773212
Short name T1265
Test name
Test status
Simulation time 1512296202 ps
CPU time 5.51 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:36 AM PDT 24
Peak memory 246012 kb
Host smart-3e506263-ff6f-4ae9-ab7f-bcaea4e9fd07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280773212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.4280773212
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1759176425
Short name T1256
Test name
Test status
Simulation time 406577577 ps
CPU time 3.66 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 247396 kb
Host smart-0d6cb13c-d295-4fae-a5a4-1e1f97deb4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759176425 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.1759176425
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.4227690402
Short name T1321
Test name
Test status
Simulation time 126252239 ps
CPU time 1.53 seconds
Started Jul 01 10:58:25 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 241124 kb
Host smart-6f72b185-5c66-48ed-b0ea-6a741453d0ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227690402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.4227690402
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.3577529897
Short name T1228
Test name
Test status
Simulation time 128279533 ps
CPU time 1.48 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 230240 kb
Host smart-8d181e59-9f9d-4444-be31-1b8061a82ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577529897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3577529897
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1463605147
Short name T241
Test name
Test status
Simulation time 74250230 ps
CPU time 1.99 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 239252 kb
Host smart-423cd850-53a7-40d0-946f-064c41454813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463605147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_
ctrl_same_csr_outstanding.1463605147
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1819273475
Short name T1257
Test name
Test status
Simulation time 653771759 ps
CPU time 6.23 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 247016 kb
Host smart-b72ea918-fcf3-4d0e-8a93-70654a955160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819273475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1819273475
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2343690498
Short name T331
Test name
Test status
Simulation time 2432870087 ps
CPU time 12.2 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:43 AM PDT 24
Peak memory 244480 kb
Host smart-d201ae2f-f4db-4050-8b93-c113c2dcf87a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343690498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2343690498
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1242239055
Short name T272
Test name
Test status
Simulation time 42979679 ps
CPU time 1.65 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 241160 kb
Host smart-509d4e44-710a-40b6-a3d2-f247195ddc97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242239055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1242239055
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.1676219566
Short name T1251
Test name
Test status
Simulation time 159487049 ps
CPU time 1.59 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 231068 kb
Host smart-0a40cc99-2718-4756-b66d-ce3a9e82314f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676219566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1676219566
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.3521968644
Short name T1220
Test name
Test status
Simulation time 49344536 ps
CPU time 1.88 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 239156 kb
Host smart-6f3d9df6-8759-4ea3-9854-b7cd790c79e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521968644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.3521968644
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.4211526421
Short name T1315
Test name
Test status
Simulation time 795114435 ps
CPU time 4.56 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:36 AM PDT 24
Peak memory 246160 kb
Host smart-3c2f6a0d-7851-4ace-b1ce-cc0d3853629d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211526421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.4211526421
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.2857834608
Short name T239
Test name
Test status
Simulation time 647295775 ps
CPU time 9.95 seconds
Started Jul 01 10:58:25 AM PDT 24
Finished Jul 01 10:58:37 AM PDT 24
Peak memory 243872 kb
Host smart-7ea0da4b-9952-46b2-ab13-c19bd02a91f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857834608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_i
ntg_err.2857834608
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4094278728
Short name T1267
Test name
Test status
Simulation time 103372758 ps
CPU time 2.74 seconds
Started Jul 01 10:58:31 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 246908 kb
Host smart-b3fa5652-60ff-45cb-865a-245f321a1ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094278728 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.4094278728
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.270579208
Short name T1215
Test name
Test status
Simulation time 145498724 ps
CPU time 1.58 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 240952 kb
Host smart-6a378404-09a0-4f33-b8f0-68b39956edd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270579208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.270579208
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.2849161317
Short name T1224
Test name
Test status
Simulation time 54621736 ps
CPU time 1.43 seconds
Started Jul 01 10:58:32 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 231076 kb
Host smart-4a14490b-d1ee-4c9d-9927-d7309c9d3fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849161317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2849161317
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.301743524
Short name T1272
Test name
Test status
Simulation time 241716914 ps
CPU time 2.33 seconds
Started Jul 01 10:58:27 AM PDT 24
Finished Jul 01 10:58:31 AM PDT 24
Peak memory 242332 kb
Host smart-e5af39a1-0c02-4431-b5c4-c8184225ab53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301743524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_same_csr_outstanding.301743524
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2452375806
Short name T1200
Test name
Test status
Simulation time 190139537 ps
CPU time 6.58 seconds
Started Jul 01 10:58:31 AM PDT 24
Finished Jul 01 10:58:39 AM PDT 24
Peak memory 246644 kb
Host smart-82dbcd54-564a-4426-b4d4-4a6fff711763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452375806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2452375806
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1243570345
Short name T1280
Test name
Test status
Simulation time 5061216442 ps
CPU time 21.32 seconds
Started Jul 01 10:58:27 AM PDT 24
Finished Jul 01 10:58:50 AM PDT 24
Peak memory 245036 kb
Host smart-762dacd3-6820-449c-ade9-af6e3b6de57e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243570345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1243570345
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2488909629
Short name T1207
Test name
Test status
Simulation time 79125096 ps
CPU time 2.37 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 246988 kb
Host smart-244c4546-ada8-47d8-bb83-3298ce951bf7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488909629 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.2488909629
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.4128418995
Short name T1307
Test name
Test status
Simulation time 73431084 ps
CPU time 1.65 seconds
Started Jul 01 10:58:31 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 238804 kb
Host smart-1a820c56-efce-4b93-afac-0d26dea8e6ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128418995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.4128418995
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.4225922373
Short name T1289
Test name
Test status
Simulation time 141003762 ps
CPU time 1.48 seconds
Started Jul 01 10:58:35 AM PDT 24
Finished Jul 01 10:58:37 AM PDT 24
Peak memory 230548 kb
Host smart-4ee04734-f21f-4031-b017-acc56a38f584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225922373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.4225922373
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2038195431
Short name T1269
Test name
Test status
Simulation time 861706076 ps
CPU time 2.94 seconds
Started Jul 01 10:58:35 AM PDT 24
Finished Jul 01 10:58:38 AM PDT 24
Peak memory 239148 kb
Host smart-0a93dd39-6daa-45e0-b632-f1bc12d1607b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038195431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2038195431
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2758007276
Short name T1275
Test name
Test status
Simulation time 111558825 ps
CPU time 4.17 seconds
Started Jul 01 10:58:34 AM PDT 24
Finished Jul 01 10:58:38 AM PDT 24
Peak memory 247344 kb
Host smart-80511d25-6d3f-42ef-a9f0-01e28f8f0833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758007276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2758007276
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1196328919
Short name T349
Test name
Test status
Simulation time 264038738 ps
CPU time 2.93 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 247428 kb
Host smart-f24048fc-875b-4915-bd6c-8b8e3162fea2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196328919 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.1196328919
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1046485634
Short name T1206
Test name
Test status
Simulation time 43437263 ps
CPU time 1.59 seconds
Started Jul 01 10:58:07 AM PDT 24
Finished Jul 01 10:58:08 AM PDT 24
Peak memory 239248 kb
Host smart-7ebf630c-d122-44c5-816b-2b08ba686215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046485634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1046485634
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.651137744
Short name T1322
Test name
Test status
Simulation time 104635463 ps
CPU time 1.44 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 231080 kb
Host smart-40d61c40-0834-4155-bd51-d8b10335e29d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651137744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.651137744
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.4277871395
Short name T301
Test name
Test status
Simulation time 194954690 ps
CPU time 2.36 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 242288 kb
Host smart-22075a6d-6ec8-4536-bb11-79e8151e3ea4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277871395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.4277871395
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.1701148643
Short name T1312
Test name
Test status
Simulation time 779506402 ps
CPU time 3.63 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 246308 kb
Host smart-2ea5afd5-8c67-4e9f-8afe-65fc96d19f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701148643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.1701148643
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1489812130
Short name T1288
Test name
Test status
Simulation time 764219471 ps
CPU time 9.55 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 243896 kb
Host smart-649375c0-5f9a-4b23-8070-8db1bfc9d86f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489812130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.1489812130
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.904004091
Short name T1248
Test name
Test status
Simulation time 134606505 ps
CPU time 3.04 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 247448 kb
Host smart-3df498c9-2a39-489a-9e8e-2343304117c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904004091 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.904004091
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.2279233064
Short name T240
Test name
Test status
Simulation time 42274143 ps
CPU time 1.49 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 239240 kb
Host smart-0afb5823-56de-4c8a-ac18-dc318e0c9382
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279233064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.2279233064
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2511702896
Short name T1293
Test name
Test status
Simulation time 65443558 ps
CPU time 1.41 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 231052 kb
Host smart-78eed979-97f9-4893-a5b1-b7f9a8627757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511702896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2511702896
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.710484137
Short name T1223
Test name
Test status
Simulation time 175115139 ps
CPU time 3.46 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 239176 kb
Host smart-74964102-f7c4-49e5-83da-0250a1181629
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710484137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.710484137
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1239255117
Short name T1283
Test name
Test status
Simulation time 1241605017 ps
CPU time 4.97 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 246500 kb
Host smart-9fbfe1d7-e17b-4b00-b0b7-adc5d4752f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239255117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1239255117
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2269557862
Short name T326
Test name
Test status
Simulation time 2601130736 ps
CPU time 11.72 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 239408 kb
Host smart-7d5d22a3-3002-4410-9384-5d03f68d3798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269557862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.2269557862
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2262254728
Short name T1310
Test name
Test status
Simulation time 73257976 ps
CPU time 2.15 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 246320 kb
Host smart-700f2b35-d073-4f7e-a5dc-197750667d68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262254728 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2262254728
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2250426154
Short name T1234
Test name
Test status
Simulation time 41115644 ps
CPU time 1.5 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 240860 kb
Host smart-935f6535-7147-4848-b1db-87b5f6314abd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250426154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2250426154
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.2204025169
Short name T1297
Test name
Test status
Simulation time 77092340 ps
CPU time 1.47 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 230560 kb
Host smart-43858f5f-db04-4bb2-868d-085fe12696f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204025169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2204025169
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.111885316
Short name T1266
Test name
Test status
Simulation time 174004513 ps
CPU time 2.53 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 242328 kb
Host smart-9a4f718f-12e5-4f5b-bffd-56c682c712e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111885316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c
trl_same_csr_outstanding.111885316
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1313259152
Short name T1263
Test name
Test status
Simulation time 116746181 ps
CPU time 3.84 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 246228 kb
Host smart-b53fa6a7-7ef0-4c50-ad43-ba217f8d0383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313259152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1313259152
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.2044571381
Short name T238
Test name
Test status
Simulation time 1599114518 ps
CPU time 21.19 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:48 AM PDT 24
Peak memory 239368 kb
Host smart-7bd5f336-8875-459c-bd06-22d9fd952170
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044571381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_i
ntg_err.2044571381
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.3789562338
Short name T1227
Test name
Test status
Simulation time 74836597 ps
CPU time 2.06 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 245216 kb
Host smart-6dd504aa-bb84-455b-af6a-73f72521ab5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789562338 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.3789562338
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.2016607968
Short name T1276
Test name
Test status
Simulation time 42493006 ps
CPU time 1.55 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 241248 kb
Host smart-b305eb18-f009-469b-974a-46d95a839c84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016607968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.2016607968
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.3540242785
Short name T1226
Test name
Test status
Simulation time 42179095 ps
CPU time 1.44 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 231020 kb
Host smart-a55d4ce9-90ff-4c2a-9d2a-6ef2cd6334b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540242785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.3540242785
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3280905849
Short name T1244
Test name
Test status
Simulation time 301870397 ps
CPU time 2.93 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 239136 kb
Host smart-7add0046-7c4c-4499-b5bb-f49db6edccf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280905849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_
ctrl_same_csr_outstanding.3280905849
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.3874272137
Short name T1255
Test name
Test status
Simulation time 312436950 ps
CPU time 5.23 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 246948 kb
Host smart-b0e6a0d8-b71b-4d7b-be7a-3a8248c4151c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874272137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3874272137
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.763527636
Short name T1286
Test name
Test status
Simulation time 99478542 ps
CPU time 3.76 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 239200 kb
Host smart-2fb1d8dd-9500-4529-aab1-7e00917a9a0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763527636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alias
ing.763527636
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.105181202
Short name T1298
Test name
Test status
Simulation time 189727321 ps
CPU time 3.75 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 239256 kb
Host smart-3632ab5f-1a90-4dce-b2af-f27d6fba5295
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105181202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_b
ash.105181202
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2407458211
Short name T1199
Test name
Test status
Simulation time 986241557 ps
CPU time 2.53 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 241260 kb
Host smart-93ecc5cb-6b40-4938-9043-675904378f3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407458211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_r
eset.2407458211
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3202015581
Short name T1240
Test name
Test status
Simulation time 1594836626 ps
CPU time 4.32 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 247444 kb
Host smart-3c359cf1-7f45-484c-9d59-3637f2032813
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202015581 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.3202015581
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.1406404110
Short name T273
Test name
Test status
Simulation time 594106165 ps
CPU time 1.8 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 239164 kb
Host smart-0ebacd62-6ef9-4724-8fb8-a0fef57c9b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406404110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.1406404110
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.4124763718
Short name T1299
Test name
Test status
Simulation time 45528015 ps
CPU time 1.43 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:18 AM PDT 24
Peak memory 230644 kb
Host smart-5e47e008-0bd0-416d-b213-2efc006ece0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124763718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.4124763718
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.380007567
Short name T1232
Test name
Test status
Simulation time 79251744 ps
CPU time 1.4 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 229852 kb
Host smart-d49cb613-858b-4a6c-816d-3040a2ff9fee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380007567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl
_mem_partial_access.380007567
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.1287815453
Short name T1300
Test name
Test status
Simulation time 34911366 ps
CPU time 1.38 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 230752 kb
Host smart-91fca2c6-e74b-4905-a23a-24879d59e696
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287815453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.1287815453
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2239889910
Short name T1313
Test name
Test status
Simulation time 109778170 ps
CPU time 2.81 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:25 AM PDT 24
Peak memory 239212 kb
Host smart-8df1fdfd-31ac-40bc-9dd3-e7b83ce64e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239889910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.2239889910
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3393795185
Short name T1281
Test name
Test status
Simulation time 118348565 ps
CPU time 3.06 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 245792 kb
Host smart-e09440c1-ec31-4674-8b14-0c4c976be8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393795185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3393795185
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2239744190
Short name T328
Test name
Test status
Simulation time 10489346787 ps
CPU time 18.91 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:45 AM PDT 24
Peak memory 244548 kb
Host smart-1ce4e1a2-f62a-442b-abf3-39e8115e7e23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239744190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2239744190
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.1670577194
Short name T1284
Test name
Test status
Simulation time 151088269 ps
CPU time 1.37 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 230260 kb
Host smart-2e4132b5-47bb-40ab-9e77-5500186d606c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670577194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1670577194
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.3318550670
Short name T1201
Test name
Test status
Simulation time 78192009 ps
CPU time 1.36 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:31 AM PDT 24
Peak memory 230972 kb
Host smart-3b433b62-8814-48f5-96fa-d343eb41bcdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318550670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.3318550670
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.2283650018
Short name T1236
Test name
Test status
Simulation time 40690441 ps
CPU time 1.4 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 231044 kb
Host smart-9e70acb3-d27e-4973-a25d-48162d7d2506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283650018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2283650018
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1965776535
Short name T1261
Test name
Test status
Simulation time 144012425 ps
CPU time 1.4 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 230372 kb
Host smart-5ae556bb-29c6-4fa1-bb56-b7f3a5eeabb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965776535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1965776535
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.2405354571
Short name T1197
Test name
Test status
Simulation time 83634101 ps
CPU time 1.42 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 230176 kb
Host smart-3cf9fd20-f6ba-4127-a3c1-8e39b61d8ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405354571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.2405354571
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.802157971
Short name T1316
Test name
Test status
Simulation time 577666389 ps
CPU time 2.16 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 230260 kb
Host smart-da9630af-3bfa-4c8c-a9dd-eb9cb26c109f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802157971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.802157971
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2336196171
Short name T1282
Test name
Test status
Simulation time 148676846 ps
CPU time 1.44 seconds
Started Jul 01 10:58:24 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 230500 kb
Host smart-8f55b5f6-82e8-4fc4-abce-4e8c2b2a87e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336196171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2336196171
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.786997478
Short name T1218
Test name
Test status
Simulation time 597933267 ps
CPU time 1.68 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 231044 kb
Host smart-c3b71b63-b498-4cb6-8d17-dacce7cdb694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786997478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.786997478
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2273021569
Short name T1196
Test name
Test status
Simulation time 39949452 ps
CPU time 1.38 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:31 AM PDT 24
Peak memory 230288 kb
Host smart-1f174a17-6edb-4d5b-82c5-6ffc2b49d15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273021569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2273021569
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2138210722
Short name T1243
Test name
Test status
Simulation time 539677565 ps
CPU time 1.45 seconds
Started Jul 01 10:58:26 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 230556 kb
Host smart-fd2335a2-f3fe-47fb-8ca6-da9386338736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138210722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2138210722
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.696830816
Short name T1242
Test name
Test status
Simulation time 252707308 ps
CPU time 5.97 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:31 AM PDT 24
Peak memory 230872 kb
Host smart-607777ed-b1ad-456b-8b9a-1a65cb088238
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696830816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_b
ash.696830816
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3618751824
Short name T1235
Test name
Test status
Simulation time 71358943 ps
CPU time 1.81 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 240968 kb
Host smart-1d99b307-0a30-42ea-948c-17937ed9e1a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618751824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.3618751824
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.398630347
Short name T1214
Test name
Test status
Simulation time 73512081 ps
CPU time 2.17 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 245348 kb
Host smart-c47ea96e-24e1-4e13-9caf-7498cb27d2cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398630347 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.398630347
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4181649402
Short name T293
Test name
Test status
Simulation time 72516456 ps
CPU time 1.48 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 240588 kb
Host smart-de61f1a5-7976-4ef5-bac8-6bb35f70659a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181649402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4181649402
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.3146846306
Short name T1268
Test name
Test status
Simulation time 75088026 ps
CPU time 1.42 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:20 AM PDT 24
Peak memory 231068 kb
Host smart-e21b4bbf-95e7-4b4a-9629-cf6546106776
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146846306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3146846306
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1222037481
Short name T1212
Test name
Test status
Simulation time 39851426 ps
CPU time 1.31 seconds
Started Jul 01 10:58:08 AM PDT 24
Finished Jul 01 10:58:10 AM PDT 24
Peak memory 230608 kb
Host smart-8c038685-faf7-432c-b096-0df24f8e1502
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222037481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctr
l_mem_partial_access.1222037481
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.107463950
Short name T1309
Test name
Test status
Simulation time 88343768 ps
CPU time 1.33 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 229952 kb
Host smart-f798a200-aa00-4449-ae7a-a7ce75fd7d68
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107463950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.
107463950
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.3696395503
Short name T294
Test name
Test status
Simulation time 160933902 ps
CPU time 1.98 seconds
Started Jul 01 10:58:15 AM PDT 24
Finished Jul 01 10:58:18 AM PDT 24
Peak memory 239104 kb
Host smart-1303f70c-294b-4833-ab7c-8c03feed068c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696395503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.3696395503
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3448639068
Short name T1250
Test name
Test status
Simulation time 203679294 ps
CPU time 5.7 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 246396 kb
Host smart-5a5adbc2-e33a-4b12-aa5e-2ec070a25585
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448639068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3448639068
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.1616431216
Short name T1204
Test name
Test status
Simulation time 128453269 ps
CPU time 1.39 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 230588 kb
Host smart-411d5ad1-84e1-44e1-a97b-81bf3d23c51c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616431216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1616431216
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.2806248846
Short name T1305
Test name
Test status
Simulation time 36292037 ps
CPU time 1.32 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 231008 kb
Host smart-4a438b5c-5bdb-4744-9ce1-1c36d5b9221d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806248846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2806248846
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1427329026
Short name T1209
Test name
Test status
Simulation time 599268622 ps
CPU time 1.53 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 231088 kb
Host smart-87aec01d-a3fe-40ae-a4a8-fc1c099e4985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427329026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1427329026
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1408944502
Short name T1271
Test name
Test status
Simulation time 74518611 ps
CPU time 1.3 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 230528 kb
Host smart-bec3c5ac-648b-40aa-85cc-010d1d2e550b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408944502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1408944502
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.527415912
Short name T1246
Test name
Test status
Simulation time 45353171 ps
CPU time 1.41 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 230596 kb
Host smart-52a649b2-88c4-46a3-b3b2-716ff59c3b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527415912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.527415912
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3150005630
Short name T1238
Test name
Test status
Simulation time 141523948 ps
CPU time 1.59 seconds
Started Jul 01 10:58:30 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 230244 kb
Host smart-92546a28-1d09-45d6-9931-3bb04369e56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150005630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3150005630
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.3303014917
Short name T1217
Test name
Test status
Simulation time 524970669 ps
CPU time 1.85 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:32 AM PDT 24
Peak memory 230500 kb
Host smart-e455ff8e-5e30-4bdc-bc64-4c7f23ed1f3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303014917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.3303014917
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.3496047115
Short name T1273
Test name
Test status
Simulation time 69413329 ps
CPU time 1.42 seconds
Started Jul 01 10:58:33 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 230580 kb
Host smart-fb9e3d29-4d08-4758-be3c-65e95241c894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496047115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.3496047115
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4277155422
Short name T1203
Test name
Test status
Simulation time 77701788 ps
CPU time 1.58 seconds
Started Jul 01 10:58:25 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 230352 kb
Host smart-1bc9f548-184c-41b7-8cf2-4eb80c8e6bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277155422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.4277155422
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2639745235
Short name T1311
Test name
Test status
Simulation time 556767773 ps
CPU time 1.89 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 230236 kb
Host smart-25d56c65-4b34-49a9-bc86-f75fde3520a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639745235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2639745235
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.4008317154
Short name T291
Test name
Test status
Simulation time 735653189 ps
CPU time 6.74 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 239212 kb
Host smart-08276644-50a9-4819-91b7-715b80aa1288
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008317154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.4008317154
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.409027272
Short name T1301
Test name
Test status
Simulation time 84796225 ps
CPU time 3.76 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 239316 kb
Host smart-78fe3fdf-49f7-47c7-a60e-8a176a7cc08d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409027272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_b
ash.409027272
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3664366213
Short name T1253
Test name
Test status
Simulation time 1431234807 ps
CPU time 4.23 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:25 AM PDT 24
Peak memory 239216 kb
Host smart-90d39c23-5117-4de8-b89f-3b3b22d853b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664366213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.3664366213
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.2715224478
Short name T1249
Test name
Test status
Simulation time 292669043 ps
CPU time 2.3 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 244772 kb
Host smart-d9c77ef6-01a4-425f-bfe4-9052f0119019
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715224478 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.2715224478
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.479452879
Short name T280
Test name
Test status
Simulation time 110168964 ps
CPU time 1.73 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 239248 kb
Host smart-1eeb1e17-dac5-42cf-b0ea-b71c7ef0bd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479452879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.479452879
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.1860819001
Short name T1259
Test name
Test status
Simulation time 66952923 ps
CPU time 1.37 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 231152 kb
Host smart-1c6c7952-75d2-4a9f-8130-dacdb71f02fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860819001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.1860819001
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3158738696
Short name T1210
Test name
Test status
Simulation time 36437193 ps
CPU time 1.31 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 229904 kb
Host smart-61aadef4-10f7-4137-af73-9ab259e53eec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158738696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctr
l_mem_partial_access.3158738696
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.2458292916
Short name T1211
Test name
Test status
Simulation time 73290188 ps
CPU time 1.44 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 229956 kb
Host smart-42c941ca-ac6f-4d91-bd50-11aaedfe50d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458292916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk
.2458292916
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3720107090
Short name T300
Test name
Test status
Simulation time 143445767 ps
CPU time 2.22 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239236 kb
Host smart-49d52c8c-0b5f-4348-85ac-f51d6c670a96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720107090 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.3720107090
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.4236272496
Short name T1274
Test name
Test status
Simulation time 108269319 ps
CPU time 3.56 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 246320 kb
Host smart-bf551c4b-f0d6-4937-8a4a-56c762237f33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236272496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.4236272496
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.370012594
Short name T1239
Test name
Test status
Simulation time 39508489 ps
CPU time 1.39 seconds
Started Jul 01 10:58:28 AM PDT 24
Finished Jul 01 10:58:31 AM PDT 24
Peak memory 230600 kb
Host smart-4d09d2a0-40a1-4d9b-89a7-f3a5ebc66ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370012594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.370012594
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3303394047
Short name T1292
Test name
Test status
Simulation time 41284618 ps
CPU time 1.49 seconds
Started Jul 01 10:58:29 AM PDT 24
Finished Jul 01 10:58:33 AM PDT 24
Peak memory 231004 kb
Host smart-c9d0fa46-3351-464f-8c7d-92356607c1f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303394047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3303394047
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.1968333667
Short name T1230
Test name
Test status
Simulation time 47133149 ps
CPU time 1.38 seconds
Started Jul 01 10:58:31 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 230192 kb
Host smart-caa728e6-a982-462e-bd02-caffdf761da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968333667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.1968333667
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.2394829315
Short name T1245
Test name
Test status
Simulation time 90133788 ps
CPU time 1.43 seconds
Started Jul 01 10:58:12 AM PDT 24
Finished Jul 01 10:58:14 AM PDT 24
Peak memory 230252 kb
Host smart-45ddfe47-cebb-4f7d-be2d-0d02ae59ac9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394829315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.2394829315
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.1105798704
Short name T1295
Test name
Test status
Simulation time 87734305 ps
CPU time 1.34 seconds
Started Jul 01 10:58:31 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 230564 kb
Host smart-1d9478ab-c600-4d91-99f2-0302fbc9c723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105798704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.1105798704
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.3841034415
Short name T1258
Test name
Test status
Simulation time 531537061 ps
CPU time 1.48 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 230600 kb
Host smart-6e3a01ea-4622-4ae1-9594-4410d8065da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841034415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.3841034415
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.2874770270
Short name T1202
Test name
Test status
Simulation time 76828537 ps
CPU time 1.38 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 230548 kb
Host smart-b958741c-083f-49d0-9714-8ca2f3354630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874770270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.2874770270
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.1289155579
Short name T1319
Test name
Test status
Simulation time 570981954 ps
CPU time 2.2 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 230600 kb
Host smart-5ae881ab-7eb6-4143-a765-eb2eafb9e21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289155579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.1289155579
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.2046040019
Short name T1285
Test name
Test status
Simulation time 142205771 ps
CPU time 1.55 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 231048 kb
Host smart-5136fda1-9dff-4bd1-a3a4-11baaa582e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046040019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2046040019
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.2997956420
Short name T1277
Test name
Test status
Simulation time 139414672 ps
CPU time 1.51 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 230196 kb
Host smart-3cc57747-11c1-48cf-90af-7adc86c5f452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997956420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.2997956420
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2938957530
Short name T1291
Test name
Test status
Simulation time 1128343359 ps
CPU time 3.22 seconds
Started Jul 01 10:58:15 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 245944 kb
Host smart-b7e4009b-44b7-4af8-8e86-236381be2ea6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938957530 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2938957530
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.1872106360
Short name T292
Test name
Test status
Simulation time 40229644 ps
CPU time 1.6 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 241468 kb
Host smart-10eedd09-22db-4ea0-85cc-fe1a7471db7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872106360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.1872106360
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.1122488271
Short name T1304
Test name
Test status
Simulation time 602228252 ps
CPU time 2.34 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:23 AM PDT 24
Peak memory 231056 kb
Host smart-cf910f89-9e17-4a68-a784-5f5d50a486ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122488271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.1122488271
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.353817250
Short name T299
Test name
Test status
Simulation time 186427063 ps
CPU time 2.41 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 239168 kb
Host smart-1d8793d7-5099-4467-a3aa-a7bdf2d542db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353817250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct
rl_same_csr_outstanding.353817250
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1689848104
Short name T1260
Test name
Test status
Simulation time 158862827 ps
CPU time 4.72 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 246508 kb
Host smart-8f35403f-dfbd-4f88-8425-619dc679d2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689848104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1689848104
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.1529986238
Short name T1302
Test name
Test status
Simulation time 826909969 ps
CPU time 10.33 seconds
Started Jul 01 10:58:16 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239336 kb
Host smart-1d33df9c-e98b-4b15-8d09-7b1c83204b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529986238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.1529986238
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2796173484
Short name T1270
Test name
Test status
Simulation time 222037009 ps
CPU time 3.45 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 247584 kb
Host smart-f96ca8c2-0782-4442-bb3c-b3a495fc2ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796173484 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2796173484
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.4197057449
Short name T276
Test name
Test status
Simulation time 135192646 ps
CPU time 1.48 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:21 AM PDT 24
Peak memory 241276 kb
Host smart-bbd07134-30cd-417f-9206-a431577269d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197057449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.4197057449
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2797482137
Short name T1294
Test name
Test status
Simulation time 529512505 ps
CPU time 1.93 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 230948 kb
Host smart-e94ec278-c16a-4bd8-8b7b-8b1eef8bb0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797482137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2797482137
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4070928075
Short name T1222
Test name
Test status
Simulation time 70003839 ps
CPU time 2.22 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 239256 kb
Host smart-2d1e5e77-8a82-491e-9833-811f30537e06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070928075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.4070928075
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3209518876
Short name T1264
Test name
Test status
Simulation time 3015039241 ps
CPU time 7.5 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:34 AM PDT 24
Peak memory 246960 kb
Host smart-885e3276-36f2-47f0-8bb5-d50f769e5849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209518876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3209518876
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.1460851314
Short name T1262
Test name
Test status
Simulation time 2364507341 ps
CPU time 11.2 seconds
Started Jul 01 10:58:17 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 244312 kb
Host smart-e860c532-593c-4b58-b041-6068a3a84753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460851314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.1460851314
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.1801439413
Short name T350
Test name
Test status
Simulation time 200223499 ps
CPU time 2.71 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 245200 kb
Host smart-7b1b0538-62f4-4a19-a7ad-d37b81115a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801439413 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.1801439413
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.2612245992
Short name T298
Test name
Test status
Simulation time 168794890 ps
CPU time 2.06 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 239260 kb
Host smart-76d289be-aaaa-4e6b-8b34-75cd75f9d093
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612245992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.2612245992
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.2906601231
Short name T1287
Test name
Test status
Simulation time 36863280 ps
CPU time 1.43 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:22 AM PDT 24
Peak memory 231008 kb
Host smart-b8992ce4-38a7-41e3-8315-37ca909983b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906601231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.2906601231
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1824169373
Short name T1241
Test name
Test status
Simulation time 123089078 ps
CPU time 3.15 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:23 AM PDT 24
Peak memory 239200 kb
Host smart-24739adf-aaed-43fa-971f-7568a4cba4c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824169373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_c
trl_same_csr_outstanding.1824169373
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3956255909
Short name T1233
Test name
Test status
Simulation time 260976815 ps
CPU time 6.82 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 246564 kb
Host smart-bd9bcda7-139f-4a22-af43-9cd50ff272f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956255909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3956255909
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3437342270
Short name T329
Test name
Test status
Simulation time 1279094429 ps
CPU time 19.29 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:43 AM PDT 24
Peak memory 239268 kb
Host smart-5b382703-9825-467f-9db9-8ce450fea6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437342270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_in
tg_err.3437342270
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.925563213
Short name T1237
Test name
Test status
Simulation time 159384316 ps
CPU time 2.11 seconds
Started Jul 01 10:58:19 AM PDT 24
Finished Jul 01 10:58:23 AM PDT 24
Peak memory 244456 kb
Host smart-25cd4bd5-af92-4502-8823-9885d0bcbf41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925563213 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.925563213
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.821628658
Short name T270
Test name
Test status
Simulation time 143095221 ps
CPU time 1.63 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239208 kb
Host smart-7e0f2810-843c-493b-9bf6-a4276ed64a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821628658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.821628658
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.940411559
Short name T1221
Test name
Test status
Simulation time 41738999 ps
CPU time 1.44 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 230288 kb
Host smart-ad22a901-22c4-4fbf-bded-6c4fbb9c3405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940411559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.940411559
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.4171438398
Short name T297
Test name
Test status
Simulation time 172902055 ps
CPU time 2 seconds
Started Jul 01 10:58:22 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 239240 kb
Host smart-19d9649c-685a-4c6a-84c7-2a5af614b5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171438398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.4171438398
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.332996769
Short name T1198
Test name
Test status
Simulation time 94738344 ps
CPU time 3.46 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:25 AM PDT 24
Peak memory 246500 kb
Host smart-68a89b47-2a23-4396-b8cf-502d0ff1ebd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332996769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.332996769
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.1300640042
Short name T1278
Test name
Test status
Simulation time 2557581441 ps
CPU time 21.48 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:41 AM PDT 24
Peak memory 244712 kb
Host smart-87d6e1b7-e230-4998-8f6b-b6f4ce895c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300640042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_in
tg_err.1300640042
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.1933346221
Short name T1320
Test name
Test status
Simulation time 111406719 ps
CPU time 3.04 seconds
Started Jul 01 10:58:18 AM PDT 24
Finished Jul 01 10:58:23 AM PDT 24
Peak memory 247428 kb
Host smart-79441be8-75e8-4a02-97bc-fd1daf60d628
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933346221 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.1933346221
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1765469783
Short name T1219
Test name
Test status
Simulation time 137015366 ps
CPU time 1.53 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:23 AM PDT 24
Peak memory 241036 kb
Host smart-1948e856-00b7-4785-87f4-d16451c48f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765469783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1765469783
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3921508547
Short name T1213
Test name
Test status
Simulation time 105784336 ps
CPU time 1.42 seconds
Started Jul 01 10:58:20 AM PDT 24
Finished Jul 01 10:58:24 AM PDT 24
Peak memory 230296 kb
Host smart-8959371b-8b8c-48c4-be1c-4964f0e65c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921508547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3921508547
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.1453792397
Short name T242
Test name
Test status
Simulation time 994887874 ps
CPU time 2.63 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 242324 kb
Host smart-1249b07a-0951-40d4-9e38-c04f8730045d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453792397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.1453792397
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2842198493
Short name T1208
Test name
Test status
Simulation time 364183958 ps
CPU time 3.12 seconds
Started Jul 01 10:58:21 AM PDT 24
Finished Jul 01 10:58:27 AM PDT 24
Peak memory 246040 kb
Host smart-6e9bde6c-1893-4eb0-b398-623fa86716bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842198493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2842198493
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1701728307
Short name T245
Test name
Test status
Simulation time 19088122323 ps
CPU time 28.17 seconds
Started Jul 01 10:58:23 AM PDT 24
Finished Jul 01 10:58:54 AM PDT 24
Peak memory 245036 kb
Host smart-298f4bb1-08f4-40c7-a36e-f27ef139f4f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701728307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1701728307
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.1356726588
Short name T957
Test name
Test status
Simulation time 183338534 ps
CPU time 1.99 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:50:56 PM PDT 24
Peak memory 240104 kb
Host smart-4c776fb2-6330-42ab-b63a-a91317cc73c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356726588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1356726588
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.3002385155
Short name T1121
Test name
Test status
Simulation time 15319753013 ps
CPU time 50.49 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 242728 kb
Host smart-bf51eb63-3210-4905-bc70-20886bf9bcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002385155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.3002385155
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.3602608951
Short name T409
Test name
Test status
Simulation time 599848100 ps
CPU time 9.56 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:51:04 PM PDT 24
Peak memory 242724 kb
Host smart-065a6b03-ea66-4e88-a067-4d03763e1fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602608951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3602608951
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.4188422933
Short name T472
Test name
Test status
Simulation time 1617770969 ps
CPU time 31.38 seconds
Started Jul 01 12:50:54 PM PDT 24
Finished Jul 01 12:51:27 PM PDT 24
Peak memory 243536 kb
Host smart-0948408f-0005-4878-9d77-551bdd407d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188422933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.4188422933
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.3038671448
Short name T581
Test name
Test status
Simulation time 6166644027 ps
CPU time 9.84 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:51:03 PM PDT 24
Peak memory 242996 kb
Host smart-f3f698ed-834e-4f17-8bae-168d253d7f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038671448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3038671448
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3586482247
Short name T657
Test name
Test status
Simulation time 146558562 ps
CPU time 4.01 seconds
Started Jul 01 12:50:53 PM PDT 24
Finished Jul 01 12:50:58 PM PDT 24
Peak memory 241820 kb
Host smart-9d7c9b9a-5b99-4e5b-89da-98e18d86052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586482247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3586482247
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.2036953271
Short name T924
Test name
Test status
Simulation time 5914008713 ps
CPU time 18.32 seconds
Started Jul 01 12:50:50 PM PDT 24
Finished Jul 01 12:51:10 PM PDT 24
Peak memory 241748 kb
Host smart-333a49cd-96ba-47ef-8356-961bae002491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036953271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.2036953271
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.1935758585
Short name T777
Test name
Test status
Simulation time 3712215045 ps
CPU time 34.91 seconds
Started Jul 01 12:50:53 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 248888 kb
Host smart-9d67e0af-a7dd-4cb0-8814-64a21c23c902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935758585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.1935758585
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.2063737817
Short name T532
Test name
Test status
Simulation time 194365160 ps
CPU time 4.18 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:50:57 PM PDT 24
Peak memory 241888 kb
Host smart-36612dbd-9c7e-46a3-942c-7a055411d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063737817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2063737817
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.218360168
Short name T977
Test name
Test status
Simulation time 216294633 ps
CPU time 7.26 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:51:01 PM PDT 24
Peak memory 242024 kb
Host smart-3e1e1789-55e5-494c-ba67-ec8e9b9cfebc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=218360168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.218360168
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.2691228102
Short name T571
Test name
Test status
Simulation time 2394549640 ps
CPU time 19.94 seconds
Started Jul 01 12:50:49 PM PDT 24
Finished Jul 01 12:51:11 PM PDT 24
Peak memory 241564 kb
Host smart-08821fa9-e375-4acd-8314-6b2c61caf999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691228102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2691228102
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.2123590018
Short name T231
Test name
Test status
Simulation time 478983878 ps
CPU time 8.05 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:51:02 PM PDT 24
Peak memory 242376 kb
Host smart-1b5f210a-28c0-431e-aca5-4f1d3a714d31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123590018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2123590018
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3965185001
Short name T212
Test name
Test status
Simulation time 12674298392 ps
CPU time 192.42 seconds
Started Jul 01 12:50:55 PM PDT 24
Finished Jul 01 12:54:08 PM PDT 24
Peak memory 266184 kb
Host smart-57d29030-1045-480d-a10e-fb65b3bc61da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965185001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3965185001
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.287938867
Short name T496
Test name
Test status
Simulation time 4203745973 ps
CPU time 12.97 seconds
Started Jul 01 12:50:51 PM PDT 24
Finished Jul 01 12:51:06 PM PDT 24
Peak memory 242672 kb
Host smart-ddf87d6d-490c-4c2a-836f-2d6d5d9d0e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287938867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.287938867
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.453454194
Short name T233
Test name
Test status
Simulation time 13635960988 ps
CPU time 94.39 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:52:28 PM PDT 24
Peak memory 254860 kb
Host smart-8d603eec-0059-43db-8af3-9be5a07c2a8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453454194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.453454194
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2903694142
Short name T368
Test name
Test status
Simulation time 422795206566 ps
CPU time 1533.45 seconds
Started Jul 01 12:50:55 PM PDT 24
Finished Jul 01 01:16:29 PM PDT 24
Peak memory 357752 kb
Host smart-63ae1b82-d229-4874-b45e-ab323b6e5d24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903694142 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.2903694142
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.109635186
Short name T451
Test name
Test status
Simulation time 531482005 ps
CPU time 9.01 seconds
Started Jul 01 12:50:53 PM PDT 24
Finished Jul 01 12:51:04 PM PDT 24
Peak memory 242236 kb
Host smart-b0ce4ab8-e5e1-43e2-a901-0be37e4c04e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109635186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.109635186
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.452874784
Short name T1159
Test name
Test status
Simulation time 181754087 ps
CPU time 2.12 seconds
Started Jul 01 12:51:02 PM PDT 24
Finished Jul 01 12:51:05 PM PDT 24
Peak memory 240100 kb
Host smart-e8f18240-1d52-4e6c-a3da-e42069d82a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452874784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.452874784
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.3534184707
Short name T188
Test name
Test status
Simulation time 1550562957 ps
CPU time 33.55 seconds
Started Jul 01 12:50:56 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 242480 kb
Host smart-1b28092b-c85f-4c98-821b-0deb0272f7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534184707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3534184707
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.368554755
Short name T1131
Test name
Test status
Simulation time 369175138 ps
CPU time 12.48 seconds
Started Jul 01 12:50:55 PM PDT 24
Finished Jul 01 12:51:09 PM PDT 24
Peak memory 242192 kb
Host smart-1adcc8ef-fe54-413c-a84b-ff000a18971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368554755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.368554755
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.3135544303
Short name T438
Test name
Test status
Simulation time 652184759 ps
CPU time 19.79 seconds
Started Jul 01 12:50:58 PM PDT 24
Finished Jul 01 12:51:19 PM PDT 24
Peak memory 241872 kb
Host smart-366d2462-6c37-4566-bf37-457bc4a91c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135544303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.3135544303
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.1457208418
Short name T634
Test name
Test status
Simulation time 5566122181 ps
CPU time 23.94 seconds
Started Jul 01 12:50:57 PM PDT 24
Finished Jul 01 12:51:22 PM PDT 24
Peak memory 242092 kb
Host smart-a5fdf08f-5965-487e-91cb-36a358f22867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457208418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.1457208418
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.1508862646
Short name T793
Test name
Test status
Simulation time 1432354827 ps
CPU time 5.77 seconds
Started Jul 01 12:50:56 PM PDT 24
Finished Jul 01 12:51:03 PM PDT 24
Peak memory 242084 kb
Host smart-23c5d92a-b527-4d2b-b6ff-393e8edd758e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508862646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.1508862646
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2916853517
Short name T195
Test name
Test status
Simulation time 8668975541 ps
CPU time 20.21 seconds
Started Jul 01 12:50:56 PM PDT 24
Finished Jul 01 12:51:18 PM PDT 24
Peak memory 248752 kb
Host smart-e883fb36-ba16-491f-8b11-805865dab1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916853517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2916853517
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3768759424
Short name T93
Test name
Test status
Simulation time 4935993338 ps
CPU time 14.55 seconds
Started Jul 01 12:51:03 PM PDT 24
Finished Jul 01 12:51:18 PM PDT 24
Peak memory 242152 kb
Host smart-db95f3cc-7d02-42d9-a207-ea9d6e53dcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768759424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3768759424
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.1883830845
Short name T688
Test name
Test status
Simulation time 5466888092 ps
CPU time 11.85 seconds
Started Jul 01 12:50:59 PM PDT 24
Finished Jul 01 12:51:12 PM PDT 24
Peak memory 241928 kb
Host smart-edfebe97-00b3-48a8-8f8d-c6ce972d3c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883830845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1883830845
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.3598605296
Short name T611
Test name
Test status
Simulation time 1258792086 ps
CPU time 21.7 seconds
Started Jul 01 12:50:57 PM PDT 24
Finished Jul 01 12:51:20 PM PDT 24
Peak memory 241924 kb
Host smart-9b622a47-ba5d-4907-998b-9a4a4b235fcd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598605296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3598605296
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.3798953096
Short name T337
Test name
Test status
Simulation time 435763771 ps
CPU time 10.07 seconds
Started Jul 01 12:51:01 PM PDT 24
Finished Jul 01 12:51:12 PM PDT 24
Peak memory 241860 kb
Host smart-d18b2e03-ccc5-4f35-8342-618e16cbe21c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3798953096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3798953096
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.3854497618
Short name T565
Test name
Test status
Simulation time 2465238713 ps
CPU time 6.9 seconds
Started Jul 01 12:50:52 PM PDT 24
Finished Jul 01 12:51:00 PM PDT 24
Peak memory 242204 kb
Host smart-389a081a-636e-4d35-902c-8f1b1b1ab52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854497618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3854497618
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.2294693236
Short name T1073
Test name
Test status
Simulation time 38961285810 ps
CPU time 196.21 seconds
Started Jul 01 12:51:03 PM PDT 24
Finished Jul 01 12:54:22 PM PDT 24
Peak memory 281624 kb
Host smart-295ba3e4-5f58-4e1c-8629-f755607de788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294693236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
2294693236
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all_with_rand_reset.2458054266
Short name T643
Test name
Test status
Simulation time 952206734789 ps
CPU time 2661.28 seconds
Started Jul 01 12:51:01 PM PDT 24
Finished Jul 01 01:35:24 PM PDT 24
Peak memory 597852 kb
Host smart-e26909ac-5c3f-4a48-b79f-68a5d812141e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458054266 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.2458054266
Directory /workspace/1.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.3771587946
Short name T978
Test name
Test status
Simulation time 815504380 ps
CPU time 5.74 seconds
Started Jul 01 12:51:04 PM PDT 24
Finished Jul 01 12:51:11 PM PDT 24
Peak memory 241976 kb
Host smart-b8949197-eb5d-46ec-a650-e53aafb33c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771587946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.3771587946
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.3113406449
Short name T420
Test name
Test status
Simulation time 864134630 ps
CPU time 2.25 seconds
Started Jul 01 12:51:31 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 240228 kb
Host smart-f2b5f107-5ede-46db-80a7-b01a964b12e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113406449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3113406449
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1057191499
Short name T483
Test name
Test status
Simulation time 3702164478 ps
CPU time 34.38 seconds
Started Jul 01 12:51:31 PM PDT 24
Finished Jul 01 12:52:07 PM PDT 24
Peak memory 247048 kb
Host smart-af75ed27-a01e-443c-bdee-7983f540924b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057191499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1057191499
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.1563498364
Short name T1188
Test name
Test status
Simulation time 10369304057 ps
CPU time 32.62 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 242308 kb
Host smart-5db7ad65-7ee1-4a29-a241-95576d675d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563498364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1563498364
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.3338551642
Short name T1146
Test name
Test status
Simulation time 250241608 ps
CPU time 3.45 seconds
Started Jul 01 12:51:38 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 242012 kb
Host smart-7e1350bb-c086-4f7f-a94a-f5ecc3a58ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338551642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3338551642
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.3611066017
Short name T427
Test name
Test status
Simulation time 328608766 ps
CPU time 7.21 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 12:51:41 PM PDT 24
Peak memory 242160 kb
Host smart-f89c963e-7489-4603-aaa6-4db7b6b76498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611066017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3611066017
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.3094461213
Short name T630
Test name
Test status
Simulation time 792279334 ps
CPU time 7.82 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 248748 kb
Host smart-98807972-4f2a-4f4d-9e40-de7c9d535f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094461213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3094461213
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.3623555017
Short name T926
Test name
Test status
Simulation time 206356015 ps
CPU time 7.91 seconds
Started Jul 01 12:51:35 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 242104 kb
Host smart-21b0c42a-2550-440b-87ec-6093d368dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623555017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.3623555017
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.2945542342
Short name T889
Test name
Test status
Simulation time 4077072129 ps
CPU time 10.96 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:51:44 PM PDT 24
Peak memory 242060 kb
Host smart-00ed72a0-9ebc-4853-bfe1-b9bfc7ec5d89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2945542342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.2945542342
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.1115080177
Short name T1117
Test name
Test status
Simulation time 547458229 ps
CPU time 10.01 seconds
Started Jul 01 12:51:31 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 242144 kb
Host smart-5d08fb62-5fd2-48f7-b59e-3ea1272588d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115080177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.1115080177
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.3939592910
Short name T440
Test name
Test status
Simulation time 2070370952 ps
CPU time 4.9 seconds
Started Jul 01 12:51:31 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 242056 kb
Host smart-514a5c0d-0af7-4afd-be88-a561caedf9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939592910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3939592910
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.1558553270
Short name T885
Test name
Test status
Simulation time 3176750635 ps
CPU time 46.16 seconds
Started Jul 01 12:51:30 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 256944 kb
Host smart-2243e6ae-ced3-43e1-8091-fba519a09484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558553270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all
.1558553270
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1327742656
Short name T825
Test name
Test status
Simulation time 2975822779867 ps
CPU time 5950.02 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 02:30:45 PM PDT 24
Peak memory 671860 kb
Host smart-cc9bd82d-1ba6-43cf-a2fe-ba8fb651e370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327742656 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1327742656
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.1021443806
Short name T860
Test name
Test status
Simulation time 327928393 ps
CPU time 9.39 seconds
Started Jul 01 12:51:38 PM PDT 24
Finished Jul 01 12:51:49 PM PDT 24
Peak memory 242080 kb
Host smart-bd7ad253-b19a-499f-8331-0c6e3d3de12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021443806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1021443806
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.3953330735
Short name T173
Test name
Test status
Simulation time 490456464 ps
CPU time 4.75 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:29 PM PDT 24
Peak memory 241880 kb
Host smart-a894e88d-23c1-4095-85bd-5fcc9a1b7c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953330735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3953330735
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.2326103593
Short name T933
Test name
Test status
Simulation time 924740823 ps
CPU time 12.01 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 241880 kb
Host smart-c1df0e6c-35cc-4739-bd1b-5190737ee01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326103593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2326103593
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.1715121824
Short name T1134
Test name
Test status
Simulation time 112083264 ps
CPU time 4.35 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:31 PM PDT 24
Peak memory 242316 kb
Host smart-69919558-3657-46cd-9dc0-d6f30ed8ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715121824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1715121824
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2253821420
Short name T1186
Test name
Test status
Simulation time 193536091 ps
CPU time 5.67 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 241768 kb
Host smart-1e579f7b-c905-41f1-a673-730499f78006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253821420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2253821420
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.754756381
Short name T1002
Test name
Test status
Simulation time 147424922 ps
CPU time 4.24 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 242204 kb
Host smart-d6a03dae-fb5d-4825-a0df-6286ee775a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754756381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.754756381
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.789167762
Short name T962
Test name
Test status
Simulation time 319902636 ps
CPU time 3.49 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 241640 kb
Host smart-9bd16528-93e7-452a-80e4-d150c1e4cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789167762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.789167762
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.320182601
Short name T676
Test name
Test status
Simulation time 382218386 ps
CPU time 4.6 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 12:54:31 PM PDT 24
Peak memory 241840 kb
Host smart-21b64c50-6e23-4864-b408-2371a0fd2630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320182601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.320182601
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.3126635579
Short name T562
Test name
Test status
Simulation time 825892681 ps
CPU time 6.67 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 12:54:33 PM PDT 24
Peak memory 242008 kb
Host smart-f90aaa3f-4cc6-4826-bfd6-1892d6a52b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126635579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3126635579
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.3258345106
Short name T638
Test name
Test status
Simulation time 2246211384 ps
CPU time 7.15 seconds
Started Jul 01 12:54:32 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 241976 kb
Host smart-501643e9-b52d-4b2c-b11c-0756ce93fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258345106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3258345106
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.3962127319
Short name T508
Test name
Test status
Simulation time 208919535 ps
CPU time 11.87 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 241884 kb
Host smart-f147deb4-b206-4094-93c9-c6cd721fab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962127319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3962127319
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.520897461
Short name T853
Test name
Test status
Simulation time 1919025365 ps
CPU time 5.88 seconds
Started Jul 01 12:54:31 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 241776 kb
Host smart-67b6e585-6e94-4cc9-974e-4b7e5b9961bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520897461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.520897461
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.3326455659
Short name T1118
Test name
Test status
Simulation time 1704411348 ps
CPU time 4.54 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:35 PM PDT 24
Peak memory 242312 kb
Host smart-fa25b652-59d9-4f84-9e47-c0ef2b6c4194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326455659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3326455659
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.716773081
Short name T625
Test name
Test status
Simulation time 406963542 ps
CPU time 10.31 seconds
Started Jul 01 12:54:32 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 242128 kb
Host smart-f7ec82de-5ab3-4e90-bb31-601f641ceb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716773081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.716773081
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.3912371649
Short name T662
Test name
Test status
Simulation time 2114555128 ps
CPU time 6.02 seconds
Started Jul 01 12:54:34 PM PDT 24
Finished Jul 01 12:54:41 PM PDT 24
Peak memory 241888 kb
Host smart-ed0fc5bb-ff2e-48b3-8366-f5ef03e704d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912371649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3912371649
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.3129900912
Short name T890
Test name
Test status
Simulation time 182625293 ps
CPU time 8.52 seconds
Started Jul 01 12:54:29 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 242304 kb
Host smart-930436d7-28e5-4752-b28d-dd497773871c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129900912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3129900912
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3118557444
Short name T706
Test name
Test status
Simulation time 422315516 ps
CPU time 11.23 seconds
Started Jul 01 12:54:33 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241848 kb
Host smart-d3369911-ee91-4be5-8d87-8b2c05f6396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118557444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3118557444
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.1576389593
Short name T208
Test name
Test status
Simulation time 424440442 ps
CPU time 3.44 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:35 PM PDT 24
Peak memory 242332 kb
Host smart-7d6c39c9-d205-4b04-8e9d-9a08301e9fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576389593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.1576389593
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.2137710275
Short name T1019
Test name
Test status
Simulation time 163132357 ps
CPU time 7.8 seconds
Started Jul 01 12:54:29 PM PDT 24
Finished Jul 01 12:54:37 PM PDT 24
Peak memory 242288 kb
Host smart-b8a3b789-9f6b-4c20-8571-321a36e8cb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137710275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2137710275
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.136595625
Short name T458
Test name
Test status
Simulation time 205748774 ps
CPU time 2.17 seconds
Started Jul 01 12:51:38 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 240092 kb
Host smart-8cd2d9a1-d34f-401e-bcf2-87c8cbcb2f29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136595625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.136595625
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.1230020180
Short name T319
Test name
Test status
Simulation time 4075296901 ps
CPU time 27.94 seconds
Started Jul 01 12:51:38 PM PDT 24
Finished Jul 01 12:52:07 PM PDT 24
Peak memory 242568 kb
Host smart-96209859-0a0b-48d2-91c0-dc1f9b6c3bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230020180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1230020180
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.477926393
Short name T654
Test name
Test status
Simulation time 733427621 ps
CPU time 15.71 seconds
Started Jul 01 12:51:41 PM PDT 24
Finished Jul 01 12:51:57 PM PDT 24
Peak memory 241964 kb
Host smart-ba61290c-ee52-49c1-8635-ddebe78a8356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477926393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.477926393
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.1255482300
Short name T8
Test name
Test status
Simulation time 1778901932 ps
CPU time 4.9 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:51:39 PM PDT 24
Peak memory 241868 kb
Host smart-c4d70a67-ead3-4caf-a465-ff4fe93d39fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255482300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.1255482300
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.476348410
Short name T157
Test name
Test status
Simulation time 2047938178 ps
CPU time 24.84 seconds
Started Jul 01 12:51:41 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 244592 kb
Host smart-9f57d1d5-3af6-4cca-ade8-195d843ca9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476348410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.476348410
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.2584131710
Short name T439
Test name
Test status
Simulation time 2624039334 ps
CPU time 37.73 seconds
Started Jul 01 12:51:36 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 242388 kb
Host smart-c4bc8934-1340-4d65-a20d-d3f04c58bc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584131710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2584131710
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.389418273
Short name T714
Test name
Test status
Simulation time 3085692606 ps
CPU time 7.7 seconds
Started Jul 01 12:51:42 PM PDT 24
Finished Jul 01 12:51:50 PM PDT 24
Peak memory 241896 kb
Host smart-89ccb8bd-45c1-4f0f-b123-74d2fdf02d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389418273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.389418273
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.1785748498
Short name T925
Test name
Test status
Simulation time 3081872721 ps
CPU time 24.57 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 248784 kb
Host smart-4bb6544c-378d-4824-a083-f60c2147b2a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785748498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1785748498
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.1384498540
Short name T851
Test name
Test status
Simulation time 511099527 ps
CPU time 4.91 seconds
Started Jul 01 12:51:42 PM PDT 24
Finished Jul 01 12:51:48 PM PDT 24
Peak memory 248764 kb
Host smart-5a96b048-9ebf-48cc-8215-56d4b8ddadc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1384498540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1384498540
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.2309996239
Short name T266
Test name
Test status
Simulation time 265451696 ps
CPU time 8.35 seconds
Started Jul 01 12:51:38 PM PDT 24
Finished Jul 01 12:51:48 PM PDT 24
Peak memory 248088 kb
Host smart-d78d22fc-7263-4bf8-83bd-ee5f80960fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309996239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2309996239
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.3616039253
Short name T950
Test name
Test status
Simulation time 132232446407 ps
CPU time 278.67 seconds
Started Jul 01 12:51:37 PM PDT 24
Finished Jul 01 12:56:17 PM PDT 24
Peak memory 260120 kb
Host smart-b70df4f7-b478-43c0-8245-d0b34a8aae00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616039253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.3616039253
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.2718456147
Short name T734
Test name
Test status
Simulation time 716568865 ps
CPU time 8.7 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:51:56 PM PDT 24
Peak memory 242080 kb
Host smart-278e0406-c8ef-4db4-8197-e6c2b11c4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718456147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.2718456147
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.3507517501
Short name T551
Test name
Test status
Simulation time 598553126 ps
CPU time 4.43 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:36 PM PDT 24
Peak memory 242040 kb
Host smart-e65f83f2-76f5-460c-92f0-6b13b26629c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507517501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.3507517501
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.3102866732
Short name T186
Test name
Test status
Simulation time 9884760567 ps
CPU time 29.06 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:55:00 PM PDT 24
Peak memory 242132 kb
Host smart-80403dc7-0de0-42a9-818c-fc5ffb3ad6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102866732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.3102866732
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.3959660276
Short name T180
Test name
Test status
Simulation time 282534611 ps
CPU time 5.12 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:36 PM PDT 24
Peak memory 241932 kb
Host smart-419f13e2-5283-44da-b52b-6e82909e9fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959660276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3959660276
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.321964695
Short name T729
Test name
Test status
Simulation time 211398766 ps
CPU time 5.25 seconds
Started Jul 01 12:54:30 PM PDT 24
Finished Jul 01 12:54:36 PM PDT 24
Peak memory 242164 kb
Host smart-f3639b86-ef88-44f3-84e5-63d11d6a8563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321964695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.321964695
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.2285272973
Short name T553
Test name
Test status
Simulation time 102341802 ps
CPU time 3.77 seconds
Started Jul 01 12:54:29 PM PDT 24
Finished Jul 01 12:54:34 PM PDT 24
Peak memory 241904 kb
Host smart-81baa260-cfac-4a9d-9085-4d364c8deb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285272973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2285272973
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.3942475159
Short name T604
Test name
Test status
Simulation time 513392267 ps
CPU time 16.73 seconds
Started Jul 01 12:54:31 PM PDT 24
Finished Jul 01 12:54:49 PM PDT 24
Peak memory 241780 kb
Host smart-46ea2242-452d-45ed-8273-929097f36819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942475159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.3942475159
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3980515411
Short name T953
Test name
Test status
Simulation time 530541746 ps
CPU time 3.56 seconds
Started Jul 01 12:54:29 PM PDT 24
Finished Jul 01 12:54:33 PM PDT 24
Peak memory 241852 kb
Host smart-67a6ad6e-2743-4168-8240-a859dbcb9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980515411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3980515411
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.1750282985
Short name T138
Test name
Test status
Simulation time 3562732549 ps
CPU time 30.53 seconds
Started Jul 01 12:54:35 PM PDT 24
Finished Jul 01 12:55:06 PM PDT 24
Peak memory 242120 kb
Host smart-22cfe768-99a1-4ab1-adde-b348adc9e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750282985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.1750282985
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2115378577
Short name T967
Test name
Test status
Simulation time 1735332194 ps
CPU time 15.65 seconds
Started Jul 01 12:54:36 PM PDT 24
Finished Jul 01 12:54:52 PM PDT 24
Peak memory 242252 kb
Host smart-9a03d153-5325-483e-abc9-37e5961bdacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115378577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2115378577
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.3658219007
Short name T158
Test name
Test status
Simulation time 189418272 ps
CPU time 3.73 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 242024 kb
Host smart-eadb93a8-5ef4-40df-b141-18ab54906a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658219007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3658219007
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.3320564708
Short name T514
Test name
Test status
Simulation time 274160399 ps
CPU time 4.36 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241836 kb
Host smart-0b2eeb8d-c158-4333-af1e-9abe203bf815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320564708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3320564708
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.2975922626
Short name T34
Test name
Test status
Simulation time 2555459334 ps
CPU time 7.36 seconds
Started Jul 01 12:54:35 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 242172 kb
Host smart-97b15686-b87f-49f2-b93c-eda0d5cf117c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975922626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2975922626
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1565241846
Short name T1037
Test name
Test status
Simulation time 498473671 ps
CPU time 7.13 seconds
Started Jul 01 12:54:32 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 242032 kb
Host smart-050c18ef-8500-44f9-b6e8-6e150a04632f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565241846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1565241846
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2682351623
Short name T717
Test name
Test status
Simulation time 1524251053 ps
CPU time 5.41 seconds
Started Jul 01 12:54:35 PM PDT 24
Finished Jul 01 12:54:41 PM PDT 24
Peak memory 242108 kb
Host smart-8398ee72-0b10-45e7-9848-dafad9632a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682351623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2682351623
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.889298720
Short name T882
Test name
Test status
Simulation time 15063949579 ps
CPU time 48.26 seconds
Started Jul 01 12:54:36 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 242000 kb
Host smart-a32e1355-1590-4871-9bb7-fb5106607c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889298720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.889298720
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.1352866019
Short name T585
Test name
Test status
Simulation time 2197650672 ps
CPU time 5.09 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 242448 kb
Host smart-6f06474e-4b15-4d9c-a16c-e7b4453c3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352866019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1352866019
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.4259038757
Short name T594
Test name
Test status
Simulation time 870245476 ps
CPU time 22.48 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:55:03 PM PDT 24
Peak memory 242156 kb
Host smart-b5ee98b9-75a3-4d53-a47b-491d818980eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259038757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.4259038757
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.3988866964
Short name T907
Test name
Test status
Simulation time 1703618187 ps
CPU time 6.8 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:50 PM PDT 24
Peak memory 242076 kb
Host smart-4c031e49-e66e-4276-866f-c174370873a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988866964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3988866964
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1301980103
Short name T701
Test name
Test status
Simulation time 545924301 ps
CPU time 14.3 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:55 PM PDT 24
Peak memory 241820 kb
Host smart-921f04eb-a4bb-4eb1-9e8d-c79fb522cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301980103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1301980103
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.993107152
Short name T1101
Test name
Test status
Simulation time 97434391 ps
CPU time 1.75 seconds
Started Jul 01 12:51:43 PM PDT 24
Finished Jul 01 12:51:46 PM PDT 24
Peak memory 240232 kb
Host smart-5df6f39a-9045-4e91-bf98-31fd96442841
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993107152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.993107152
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.126648251
Short name T86
Test name
Test status
Simulation time 6898533886 ps
CPU time 20.02 seconds
Started Jul 01 12:51:42 PM PDT 24
Finished Jul 01 12:52:03 PM PDT 24
Peak memory 242056 kb
Host smart-f355ed13-5dd9-4915-9b5e-f0c4c1eeaede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126648251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.126648251
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.2439765490
Short name T872
Test name
Test status
Simulation time 815707005 ps
CPU time 11.38 seconds
Started Jul 01 12:51:43 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 241996 kb
Host smart-28c68cbc-043c-41c2-9d52-a673e5f64e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439765490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2439765490
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.129257929
Short name T473
Test name
Test status
Simulation time 18277809892 ps
CPU time 30.79 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:52:18 PM PDT 24
Peak memory 242708 kb
Host smart-bcb3e704-1d84-40e3-847a-c8a44d760022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129257929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.129257929
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.2782470821
Short name T492
Test name
Test status
Simulation time 3168997618 ps
CPU time 7.1 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 242124 kb
Host smart-17cbe423-2ae3-4edf-8c7a-f6d613909712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782470821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.2782470821
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.3638468927
Short name T787
Test name
Test status
Simulation time 3346838373 ps
CPU time 47.5 seconds
Started Jul 01 12:51:45 PM PDT 24
Finished Jul 01 12:52:33 PM PDT 24
Peak memory 261176 kb
Host smart-72bdde0f-2e3a-4cf1-9dc2-f13cdbeb5a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638468927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3638468927
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.778554995
Short name T373
Test name
Test status
Simulation time 3385743733 ps
CPU time 22.5 seconds
Started Jul 01 12:51:42 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 242804 kb
Host smart-1416889a-3ae5-4c91-8099-a780f080551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778554995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.778554995
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.703913023
Short name T471
Test name
Test status
Simulation time 270036511 ps
CPU time 3.62 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:51:51 PM PDT 24
Peak memory 241948 kb
Host smart-cebbbb4b-2f56-4bc7-b810-5b26cbccd9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703913023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.703913023
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.4135524457
Short name T407
Test name
Test status
Simulation time 1419094142 ps
CPU time 10.87 seconds
Started Jul 01 12:51:37 PM PDT 24
Finished Jul 01 12:51:48 PM PDT 24
Peak memory 241808 kb
Host smart-bd14d448-2be1-44d2-9181-38284d7cf02c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4135524457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.4135524457
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.3291329088
Short name T749
Test name
Test status
Simulation time 184681139 ps
CPU time 5.71 seconds
Started Jul 01 12:51:43 PM PDT 24
Finished Jul 01 12:51:49 PM PDT 24
Peak memory 241872 kb
Host smart-1208b2b4-4125-4757-9520-7ced28efe10c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3291329088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.3291329088
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.4186968292
Short name T670
Test name
Test status
Simulation time 612897668 ps
CPU time 8.01 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 242168 kb
Host smart-ea5b6af4-0646-4eeb-b77b-979f31c38ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186968292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.4186968292
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.3856486514
Short name T101
Test name
Test status
Simulation time 453614219 ps
CPU time 15.19 seconds
Started Jul 01 12:51:49 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 242576 kb
Host smart-13fb58ea-58fd-48d4-ae48-10753656599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856486514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.3856486514
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.3935251789
Short name T1149
Test name
Test status
Simulation time 911713794 ps
CPU time 7.33 seconds
Started Jul 01 12:54:35 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 241856 kb
Host smart-c210e7c2-4c78-4ae0-a4a9-0880f387fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935251789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3935251789
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.3774204417
Short name T102
Test name
Test status
Simulation time 962440703 ps
CPU time 10.67 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 247704 kb
Host smart-61985ca3-42d0-4540-94ea-f5d50508cb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774204417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3774204417
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.447189564
Short name T305
Test name
Test status
Simulation time 507483905 ps
CPU time 4.47 seconds
Started Jul 01 12:54:41 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 241908 kb
Host smart-90086771-cf9a-46f7-8955-4bc66f7f7133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447189564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.447189564
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.640057485
Short name T403
Test name
Test status
Simulation time 347585031 ps
CPU time 4.74 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 241700 kb
Host smart-159ac026-4f69-4362-860a-1a7ae3adc390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640057485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.640057485
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.1114037449
Short name T616
Test name
Test status
Simulation time 525540839 ps
CPU time 4.28 seconds
Started Jul 01 12:54:36 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 241928 kb
Host smart-be60c6de-7edd-4633-bec5-da4a51cc8999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114037449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1114037449
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.3620526954
Short name T600
Test name
Test status
Simulation time 1125596329 ps
CPU time 9.13 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:52 PM PDT 24
Peak memory 242000 kb
Host smart-9f0e0820-52e2-43c9-b82c-74fc1541b6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620526954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3620526954
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.3679071110
Short name T1130
Test name
Test status
Simulation time 150503560 ps
CPU time 3.73 seconds
Started Jul 01 12:54:41 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 241896 kb
Host smart-e1b2aa7a-41cb-4b43-8a77-fffe1a589a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679071110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3679071110
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.475887839
Short name T548
Test name
Test status
Simulation time 129128715 ps
CPU time 3.91 seconds
Started Jul 01 12:54:33 PM PDT 24
Finished Jul 01 12:54:37 PM PDT 24
Peak memory 242192 kb
Host smart-8ecb20a4-708c-4436-96e6-970c3320e21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475887839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.475887839
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.138969739
Short name T1108
Test name
Test status
Simulation time 550578789 ps
CPU time 4.58 seconds
Started Jul 01 12:54:35 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 242132 kb
Host smart-31b21de1-756a-499d-992d-bdf9479e3d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138969739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.138969739
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1416711941
Short name T684
Test name
Test status
Simulation time 543305655 ps
CPU time 6.78 seconds
Started Jul 01 12:54:36 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 242032 kb
Host smart-fbead7af-ca6c-4e2f-933f-ce90dc189caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416711941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1416711941
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.1323520982
Short name T574
Test name
Test status
Simulation time 501763767 ps
CPU time 3.97 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241808 kb
Host smart-a92bedee-526c-4017-b76e-c4713220d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323520982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1323520982
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.446216104
Short name T1087
Test name
Test status
Simulation time 1766219389 ps
CPU time 5.2 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 241884 kb
Host smart-ee393564-0d42-4c65-8031-d7898b71790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446216104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.446216104
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.1906903782
Short name T789
Test name
Test status
Simulation time 484994530 ps
CPU time 14.64 seconds
Started Jul 01 12:54:41 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 241888 kb
Host smart-7b049018-da60-42e2-8355-b5b114877362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906903782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.1906903782
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.1203721030
Short name T1039
Test name
Test status
Simulation time 2151923070 ps
CPU time 4.63 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:44 PM PDT 24
Peak memory 242216 kb
Host smart-7d58b3c4-ee5e-4ac3-907f-e3da6ecb717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203721030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.1203721030
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.3644646600
Short name T141
Test name
Test status
Simulation time 176088372 ps
CPU time 8.74 seconds
Started Jul 01 12:54:41 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 242268 kb
Host smart-b2c9c181-bd6b-4307-bada-5b597f723ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644646600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.3644646600
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.1373057108
Short name T690
Test name
Test status
Simulation time 2409158408 ps
CPU time 4.97 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 242020 kb
Host smart-eb448644-8b8b-444f-8908-0b0f542fb459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373057108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1373057108
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.1355274411
Short name T737
Test name
Test status
Simulation time 825167741 ps
CPU time 11.78 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:53 PM PDT 24
Peak memory 241876 kb
Host smart-5d4f5c3e-afbc-40e1-bd7e-68b256d63632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355274411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1355274411
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3679800182
Short name T836
Test name
Test status
Simulation time 231115895 ps
CPU time 3.19 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:51:51 PM PDT 24
Peak memory 240120 kb
Host smart-3dc1d99e-30f1-4a6b-9bf4-7c8332186549
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679800182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3679800182
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.593625311
Short name T103
Test name
Test status
Simulation time 619448473 ps
CPU time 20.83 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242192 kb
Host smart-e58fbdac-c47d-474e-b8a1-400265fcbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593625311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.593625311
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.2954115868
Short name T840
Test name
Test status
Simulation time 510486888 ps
CPU time 15.22 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 242000 kb
Host smart-293bbede-3bba-4646-ba6a-ec89f33e59bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954115868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2954115868
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.534398552
Short name T997
Test name
Test status
Simulation time 5408497671 ps
CPU time 15.38 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:52:04 PM PDT 24
Peak memory 242408 kb
Host smart-46308791-28dd-4c11-928f-78e6d1208430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534398552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.534398552
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.329650529
Short name T1011
Test name
Test status
Simulation time 1443759373 ps
CPU time 4.44 seconds
Started Jul 01 12:51:43 PM PDT 24
Finished Jul 01 12:51:48 PM PDT 24
Peak memory 242328 kb
Host smart-61b9ed5d-96ff-40de-b44a-ef4d636685ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329650529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.329650529
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.2258108153
Short name T436
Test name
Test status
Simulation time 652297104 ps
CPU time 9.28 seconds
Started Jul 01 12:51:46 PM PDT 24
Finished Jul 01 12:51:56 PM PDT 24
Peak memory 242604 kb
Host smart-a6099d29-6f6b-4e5a-83b5-f8100e5e2b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258108153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.2258108153
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.846602943
Short name T712
Test name
Test status
Simulation time 2540036120 ps
CPU time 26.41 seconds
Started Jul 01 12:51:49 PM PDT 24
Finished Jul 01 12:52:16 PM PDT 24
Peak memory 242420 kb
Host smart-1ba71c7f-3a7f-4d0b-88e4-968a11420f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846602943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.846602943
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.1385858794
Short name T899
Test name
Test status
Simulation time 2990945824 ps
CPU time 6.47 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 241864 kb
Host smart-bd4fb18d-52d4-4b7d-bea0-c7e38a6a333b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385858794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.1385858794
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.864601215
Short name T94
Test name
Test status
Simulation time 1930851423 ps
CPU time 14.23 seconds
Started Jul 01 12:51:49 PM PDT 24
Finished Jul 01 12:52:04 PM PDT 24
Peak memory 242328 kb
Host smart-ce5a895e-bc45-4c1f-9af4-3ec006ba10bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864601215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.864601215
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.2594574984
Short name T699
Test name
Test status
Simulation time 409983019 ps
CPU time 6.7 seconds
Started Jul 01 12:51:42 PM PDT 24
Finished Jul 01 12:51:49 PM PDT 24
Peak memory 242016 kb
Host smart-f1d807c7-8af8-4c8f-bfc7-123f609346d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594574984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2594574984
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.114033252
Short name T588
Test name
Test status
Simulation time 8192047232 ps
CPU time 189.26 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:54:58 PM PDT 24
Peak memory 246072 kb
Host smart-4c0cf86b-1943-437d-b2cd-05364ee836bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114033252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.
114033252
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.272782342
Short name T257
Test name
Test status
Simulation time 2135612521 ps
CPU time 25.47 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:52:15 PM PDT 24
Peak memory 242356 kb
Host smart-3d310f2a-dc46-498b-8819-7275b86b5c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272782342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.272782342
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.672433512
Short name T56
Test name
Test status
Simulation time 146745482 ps
CPU time 5.15 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241992 kb
Host smart-83267805-7a1b-41fb-85c2-8358a8385e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672433512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.672433512
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.2403101891
Short name T422
Test name
Test status
Simulation time 2238109134 ps
CPU time 7.88 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:49 PM PDT 24
Peak memory 241884 kb
Host smart-7867a972-d498-4123-afaa-1d7cf892bb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403101891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2403101891
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.4020823985
Short name T154
Test name
Test status
Simulation time 2084934954 ps
CPU time 5.74 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 242384 kb
Host smart-6fa960f5-8528-4ac0-bdd7-5fedad4f0044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020823985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.4020823985
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.662609374
Short name T983
Test name
Test status
Simulation time 149761636 ps
CPU time 3.83 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:54:45 PM PDT 24
Peak memory 241960 kb
Host smart-d2c9134a-6e93-4cba-a92e-add916f333e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662609374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.662609374
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.2772745382
Short name T849
Test name
Test status
Simulation time 300201308 ps
CPU time 3.37 seconds
Started Jul 01 12:54:38 PM PDT 24
Finished Jul 01 12:54:41 PM PDT 24
Peak memory 241904 kb
Host smart-4c4afce0-4b18-4152-9637-ccc862deccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772745382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2772745382
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.573313895
Short name T716
Test name
Test status
Simulation time 468036310 ps
CPU time 13.15 seconds
Started Jul 01 12:54:38 PM PDT 24
Finished Jul 01 12:54:52 PM PDT 24
Peak memory 241940 kb
Host smart-83bec549-ab64-44c1-9cf4-0a8e49cd5ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573313895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.573313895
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.307601716
Short name T174
Test name
Test status
Simulation time 484171197 ps
CPU time 3.74 seconds
Started Jul 01 12:54:37 PM PDT 24
Finished Jul 01 12:54:41 PM PDT 24
Peak memory 241928 kb
Host smart-e7d2c604-2608-459c-a5c8-fd79eae3221c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307601716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.307601716
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.4166222713
Short name T823
Test name
Test status
Simulation time 1313125071 ps
CPU time 4.4 seconds
Started Jul 01 12:54:38 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 242272 kb
Host smart-a938b8a3-f27b-45d4-a65a-7933476984e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166222713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.4166222713
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.3066635730
Short name T460
Test name
Test status
Simulation time 2120061772 ps
CPU time 28.88 seconds
Started Jul 01 12:54:39 PM PDT 24
Finished Jul 01 12:55:09 PM PDT 24
Peak memory 241876 kb
Host smart-67982947-c50f-40a8-91e7-d7ec40688732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066635730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.3066635730
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.4056530832
Short name T715
Test name
Test status
Simulation time 211373439 ps
CPU time 4.72 seconds
Started Jul 01 12:54:40 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 241788 kb
Host smart-036f32b3-1a3a-4c33-8d18-bd5316a3d17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056530832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.4056530832
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.4161146444
Short name T2
Test name
Test status
Simulation time 139629204 ps
CPU time 6.01 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:52 PM PDT 24
Peak memory 241796 kb
Host smart-5ad1dc70-5fab-4394-b224-5139d063d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161146444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.4161146444
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.3210259817
Short name T284
Test name
Test status
Simulation time 242381143 ps
CPU time 3.44 seconds
Started Jul 01 12:54:47 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 241996 kb
Host smart-f686dd58-1ee2-4b98-bec4-8c14db6a45e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210259817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.3210259817
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.3445174088
Short name T543
Test name
Test status
Simulation time 441878547 ps
CPU time 7.7 seconds
Started Jul 01 12:54:44 PM PDT 24
Finished Jul 01 12:54:53 PM PDT 24
Peak memory 242280 kb
Host smart-11710405-c303-48b2-82f8-5a221e3e719d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445174088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.3445174088
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.2934564857
Short name T156
Test name
Test status
Simulation time 165179592 ps
CPU time 4.25 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:48 PM PDT 24
Peak memory 242160 kb
Host smart-2e19affe-374a-4527-9a55-998636e78e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934564857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2934564857
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.2571359379
Short name T1093
Test name
Test status
Simulation time 367060155 ps
CPU time 16.48 seconds
Started Jul 01 12:54:43 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 242372 kb
Host smart-bdaf7014-dc16-4f51-92c7-902ac01c1b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571359379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2571359379
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2877994133
Short name T819
Test name
Test status
Simulation time 245430553 ps
CPU time 3.39 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:46 PM PDT 24
Peak memory 241768 kb
Host smart-d36c5b43-90c7-45e0-b6ae-c416a17098bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877994133 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2877994133
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.1505846580
Short name T1185
Test name
Test status
Simulation time 1952686125 ps
CPU time 14.48 seconds
Started Jul 01 12:54:47 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 242236 kb
Host smart-cee777a1-2821-4ca5-a246-fc4fa0a4acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505846580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.1505846580
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.4094136229
Short name T486
Test name
Test status
Simulation time 42835252 ps
CPU time 1.64 seconds
Started Jul 01 12:51:56 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 240152 kb
Host smart-a154240e-3734-4cf2-bb4c-2003ebf89276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094136229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.4094136229
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1476100694
Short name T1158
Test name
Test status
Simulation time 187416014 ps
CPU time 4.43 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:51:53 PM PDT 24
Peak memory 248596 kb
Host smart-bc93907b-bc9c-4dfc-a94d-be47a70e6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476100694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1476100694
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.3362103757
Short name T980
Test name
Test status
Simulation time 220014679 ps
CPU time 8.53 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:51:57 PM PDT 24
Peak memory 242116 kb
Host smart-db693c09-cec1-4caf-9641-86fb781d573c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362103757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3362103757
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.1284058901
Short name T621
Test name
Test status
Simulation time 735148942 ps
CPU time 17.87 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 248824 kb
Host smart-429d91c0-4703-4108-9965-702603494aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284058901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1284058901
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.3703149954
Short name T635
Test name
Test status
Simulation time 220360066 ps
CPU time 5.13 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:04 PM PDT 24
Peak memory 241976 kb
Host smart-c3f6691b-d8de-4bd0-89ae-bc490fdf20af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703149954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3703149954
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.2457791335
Short name T922
Test name
Test status
Simulation time 5634555362 ps
CPU time 9.78 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242808 kb
Host smart-2211430d-1931-41d3-b57d-f84f1bfe9e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457791335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2457791335
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3958191643
Short name T932
Test name
Test status
Simulation time 1772770062 ps
CPU time 39.05 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:52:28 PM PDT 24
Peak memory 242164 kb
Host smart-976bb58a-eb23-43b3-830f-007d17cd9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958191643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3958191643
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.3586824494
Short name T425
Test name
Test status
Simulation time 127513137 ps
CPU time 5.3 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:51:54 PM PDT 24
Peak memory 241628 kb
Host smart-3c01aa23-7f5a-470e-9923-f4399026119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586824494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3586824494
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.2155084033
Short name T219
Test name
Test status
Simulation time 609991381 ps
CPU time 18.1 seconds
Started Jul 01 12:51:48 PM PDT 24
Finished Jul 01 12:52:07 PM PDT 24
Peak memory 248592 kb
Host smart-36348144-325b-4da0-bd22-086d047126ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155084033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.2155084033
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.1686642743
Short name T773
Test name
Test status
Simulation time 1911109210 ps
CPU time 6.25 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 242320 kb
Host smart-3cad5b12-55c9-45f2-815b-20653129908f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686642743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.1686642743
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.3851247742
Short name T1042
Test name
Test status
Simulation time 707646062 ps
CPU time 4.09 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:51:53 PM PDT 24
Peak memory 247664 kb
Host smart-87166a2a-4765-48f8-a94e-18bbb1820892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851247742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.3851247742
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.777371085
Short name T307
Test name
Test status
Simulation time 492477172284 ps
CPU time 3615.7 seconds
Started Jul 01 12:51:49 PM PDT 24
Finished Jul 01 01:52:06 PM PDT 24
Peak memory 759676 kb
Host smart-46786ed6-be28-49c5-a339-4b5f1ed3cec3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777371085 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.777371085
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.2634597205
Short name T351
Test name
Test status
Simulation time 3737486383 ps
CPU time 10.94 seconds
Started Jul 01 12:51:47 PM PDT 24
Finished Jul 01 12:52:00 PM PDT 24
Peak memory 243344 kb
Host smart-f37b3312-5fbb-49f0-8224-0a5469a80cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634597205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.2634597205
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.1391680670
Short name T995
Test name
Test status
Simulation time 1495187221 ps
CPU time 4.57 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 242148 kb
Host smart-855d06ae-603b-4559-ac0d-82a02c2a53a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391680670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.1391680670
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.15361866
Short name T1177
Test name
Test status
Simulation time 273465169 ps
CPU time 6.31 seconds
Started Jul 01 12:54:41 PM PDT 24
Finished Jul 01 12:54:49 PM PDT 24
Peak memory 241688 kb
Host smart-8c49353e-f859-4cdc-a5b6-f09c96248b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15361866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.15361866
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2540011585
Short name T48
Test name
Test status
Simulation time 463158114 ps
CPU time 4.15 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:50 PM PDT 24
Peak memory 241916 kb
Host smart-353ab09a-3fcc-48fd-99d5-c9b1085e4c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540011585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2540011585
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.1923561457
Short name T1061
Test name
Test status
Simulation time 1779194515 ps
CPU time 5.66 seconds
Started Jul 01 12:54:44 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 242544 kb
Host smart-db1e90c9-5cdb-45a9-b036-7d60b0ec17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923561457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1923561457
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3857449616
Short name T535
Test name
Test status
Simulation time 162644154 ps
CPU time 4.06 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:48 PM PDT 24
Peak memory 241840 kb
Host smart-6dbe3d19-e096-4314-b9d8-b93a3fd7dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857449616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3857449616
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.1049063920
Short name T1056
Test name
Test status
Simulation time 5609173326 ps
CPU time 14.06 seconds
Started Jul 01 12:54:42 PM PDT 24
Finished Jul 01 12:54:58 PM PDT 24
Peak memory 242412 kb
Host smart-becf3a42-ff80-44fd-a67d-2f4ccb44396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049063920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1049063920
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.2441025574
Short name T544
Test name
Test status
Simulation time 120391675 ps
CPU time 4.81 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 241780 kb
Host smart-393d0325-717f-43cd-abd3-7ff0232d7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441025574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2441025574
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3889962275
Short name T1165
Test name
Test status
Simulation time 116544988 ps
CPU time 4.38 seconds
Started Jul 01 12:54:43 PM PDT 24
Finished Jul 01 12:54:49 PM PDT 24
Peak memory 242280 kb
Host smart-e4437eca-7715-4d84-9662-24d400e2f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889962275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3889962275
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.1371933698
Short name T490
Test name
Test status
Simulation time 356499744 ps
CPU time 4.9 seconds
Started Jul 01 12:54:44 PM PDT 24
Finished Jul 01 12:54:50 PM PDT 24
Peak memory 241980 kb
Host smart-6ff40e3c-d078-4c00-a0d1-376e7189feb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371933698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.1371933698
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.359630253
Short name T650
Test name
Test status
Simulation time 205143860 ps
CPU time 4.6 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:51 PM PDT 24
Peak memory 242220 kb
Host smart-e0764e8c-8ec8-4e8a-a40b-0b5727d39407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359630253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.359630253
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.4161046380
Short name T582
Test name
Test status
Simulation time 504295985 ps
CPU time 4.03 seconds
Started Jul 01 12:54:45 PM PDT 24
Finished Jul 01 12:54:50 PM PDT 24
Peak memory 242084 kb
Host smart-d21b9b73-3018-4463-812f-7e1063fb3680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161046380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.4161046380
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.3629464186
Short name T941
Test name
Test status
Simulation time 517348660 ps
CPU time 14.94 seconds
Started Jul 01 12:54:49 PM PDT 24
Finished Jul 01 12:55:04 PM PDT 24
Peak memory 242260 kb
Host smart-7667d5de-c66a-43e8-b57a-4fc6f3fab8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629464186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3629464186
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.2975293902
Short name T728
Test name
Test status
Simulation time 207795573 ps
CPU time 3.72 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:56 PM PDT 24
Peak memory 241856 kb
Host smart-8074c080-bbed-4d96-92f4-a857ca07e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975293902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2975293902
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.2376014543
Short name T187
Test name
Test status
Simulation time 167785408 ps
CPU time 4.68 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 241896 kb
Host smart-1747e42a-9591-41cc-a33a-ef6865090807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376014543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2376014543
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.956362985
Short name T680
Test name
Test status
Simulation time 207409506 ps
CPU time 4.35 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 241864 kb
Host smart-4784b603-16e7-4c64-b721-5dfcb277571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956362985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.956362985
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1752021959
Short name T1088
Test name
Test status
Simulation time 596307419 ps
CPU time 4.7 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 242416 kb
Host smart-3fa5a499-6e23-4167-84fa-2709482a55c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752021959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1752021959
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.2646299734
Short name T815
Test name
Test status
Simulation time 140179679 ps
CPU time 3.62 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:54:54 PM PDT 24
Peak memory 242320 kb
Host smart-35f24986-a8b3-486f-98d1-848d72f29e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646299734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.2646299734
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.1533459002
Short name T1055
Test name
Test status
Simulation time 255151931 ps
CPU time 4.04 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:54:55 PM PDT 24
Peak memory 241912 kb
Host smart-361d34c1-8e12-4554-84e6-c9c98887aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533459002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.1533459002
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.2035468006
Short name T1080
Test name
Test status
Simulation time 152150094 ps
CPU time 6.47 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241908 kb
Host smart-8f07e06b-a8b6-4472-8870-398fe972a873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035468006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.2035468006
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.2600440771
Short name T653
Test name
Test status
Simulation time 124095191 ps
CPU time 1.83 seconds
Started Jul 01 12:51:54 PM PDT 24
Finished Jul 01 12:51:56 PM PDT 24
Peak memory 240136 kb
Host smart-ae3e658c-287f-4fc5-b984-3f7b4b241bb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600440771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2600440771
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.2075417528
Short name T106
Test name
Test status
Simulation time 881347993 ps
CPU time 17.46 seconds
Started Jul 01 12:51:56 PM PDT 24
Finished Jul 01 12:52:15 PM PDT 24
Peak memory 242640 kb
Host smart-1439a038-b0f8-4e50-b301-848f3551f29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075417528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2075417528
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.2365535376
Short name T150
Test name
Test status
Simulation time 431714562 ps
CPU time 11.88 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:10 PM PDT 24
Peak memory 242224 kb
Host smart-83b0d7be-fd55-45e4-a3a7-cfd978db5c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365535376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2365535376
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.1627252309
Short name T459
Test name
Test status
Simulation time 117403209 ps
CPU time 4.16 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:02 PM PDT 24
Peak memory 248632 kb
Host smart-9344455b-7841-475b-b8a0-feb4012feaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627252309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.1627252309
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.10309757
Short name T868
Test name
Test status
Simulation time 3333124828 ps
CPU time 21.53 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 242456 kb
Host smart-2ff13dde-0579-4654-85f9-e1c674bce029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10309757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.10309757
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.284664705
Short name T1012
Test name
Test status
Simulation time 1515840113 ps
CPU time 18.41 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:16 PM PDT 24
Peak memory 242536 kb
Host smart-3403acdf-6ddb-4180-adde-d0e110629baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284664705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.284664705
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.627076210
Short name T128
Test name
Test status
Simulation time 320326996 ps
CPU time 6.96 seconds
Started Jul 01 12:51:55 PM PDT 24
Finished Jul 01 12:52:03 PM PDT 24
Peak memory 241896 kb
Host smart-6070f58a-c459-48a8-b957-a13d7fb02a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627076210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.627076210
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.1679241498
Short name T361
Test name
Test status
Simulation time 268072937 ps
CPU time 8.89 seconds
Started Jul 01 12:51:59 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242348 kb
Host smart-b639805d-93b0-463b-a4bb-cacf21e1ed9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679241498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.1679241498
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.686206414
Short name T794
Test name
Test status
Simulation time 892376335 ps
CPU time 8.66 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:07 PM PDT 24
Peak memory 248196 kb
Host smart-fa7a68ba-f63e-4dd7-82cd-4fa38274660a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=686206414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.686206414
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.2756482431
Short name T400
Test name
Test status
Simulation time 653990518 ps
CPU time 6.96 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 242076 kb
Host smart-e86321c0-0d56-49fa-bdc1-d62bb26a0adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756482431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.2756482431
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2062175857
Short name T870
Test name
Test status
Simulation time 6643535140 ps
CPU time 12.71 seconds
Started Jul 01 12:52:01 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 241596 kb
Host smart-b7c0a2f7-37be-49b5-b032-d171daaea248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062175857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2062175857
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.3730637684
Short name T389
Test name
Test status
Simulation time 3817085164 ps
CPU time 9.43 seconds
Started Jul 01 12:51:56 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 242628 kb
Host smart-5594de68-ccd4-4b7b-aabe-947ee68e7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730637684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.3730637684
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.3375294018
Short name T801
Test name
Test status
Simulation time 86856801 ps
CPU time 3.39 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:56 PM PDT 24
Peak memory 241880 kb
Host smart-13a7fff6-32fd-4446-b735-8d128e9fc6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375294018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3375294018
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3036011452
Short name T854
Test name
Test status
Simulation time 4573726213 ps
CPU time 18.78 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:55:09 PM PDT 24
Peak memory 242292 kb
Host smart-4f626410-cd0c-4c61-b437-2cc95d9489b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036011452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3036011452
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.720068324
Short name T449
Test name
Test status
Simulation time 246224300 ps
CPU time 4 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 242144 kb
Host smart-5021ce29-ee8a-4b19-af82-0282d9d83d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720068324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.720068324
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.2074100515
Short name T659
Test name
Test status
Simulation time 259470440 ps
CPU time 5.57 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:54:56 PM PDT 24
Peak memory 242112 kb
Host smart-4ab57d91-3ec8-4c09-8acf-1e1cb512b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074100515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.2074100515
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.580510070
Short name T665
Test name
Test status
Simulation time 162345252 ps
CPU time 4.32 seconds
Started Jul 01 12:54:48 PM PDT 24
Finished Jul 01 12:54:53 PM PDT 24
Peak memory 242328 kb
Host smart-e141a832-bdd2-4244-9a9e-02306f6f61e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580510070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.580510070
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.1683141478
Short name T416
Test name
Test status
Simulation time 310310026 ps
CPU time 6.95 seconds
Started Jul 01 12:54:49 PM PDT 24
Finished Jul 01 12:54:57 PM PDT 24
Peak memory 241956 kb
Host smart-4d473706-6e0f-43e6-bf52-39c56cdd765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683141478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1683141478
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.2187072618
Short name T710
Test name
Test status
Simulation time 542098834 ps
CPU time 5.04 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:54:56 PM PDT 24
Peak memory 241784 kb
Host smart-984389b0-5330-49b0-a92e-452fe06ccddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187072618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2187072618
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.1797743874
Short name T542
Test name
Test status
Simulation time 379506383 ps
CPU time 8.51 seconds
Started Jul 01 12:54:51 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 241828 kb
Host smart-20bb4501-2ff5-4a8a-9586-f11305dea3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797743874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1797743874
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3541812778
Short name T649
Test name
Test status
Simulation time 362253247 ps
CPU time 4.22 seconds
Started Jul 01 12:54:50 PM PDT 24
Finished Jul 01 12:54:55 PM PDT 24
Peak memory 241788 kb
Host smart-9d4e0742-0bc4-46df-8ad6-6332f04745c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541812778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3541812778
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.1562661471
Short name T32
Test name
Test status
Simulation time 491074341 ps
CPU time 4.96 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 242356 kb
Host smart-2d854188-4e53-4cd7-bea9-6f92f3b9d552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562661471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.1562661471
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.3574369385
Short name T111
Test name
Test status
Simulation time 1460884720 ps
CPU time 5.78 seconds
Started Jul 01 12:54:54 PM PDT 24
Finished Jul 01 12:55:00 PM PDT 24
Peak memory 241820 kb
Host smart-cc07b393-a312-4c99-baaa-8bbcc544dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574369385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3574369385
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.1626493186
Short name T894
Test name
Test status
Simulation time 304841487 ps
CPU time 3.65 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 242036 kb
Host smart-a362b0f7-d2a5-49bf-9422-291d12289e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626493186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.1626493186
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.4285346694
Short name T646
Test name
Test status
Simulation time 245909983 ps
CPU time 10.84 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:08 PM PDT 24
Peak memory 241796 kb
Host smart-f58d6e67-9293-4ef9-8c33-d0bd690f349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285346694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4285346694
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2650650602
Short name T741
Test name
Test status
Simulation time 2147500144 ps
CPU time 4.32 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:00 PM PDT 24
Peak memory 242560 kb
Host smart-ba4d20c4-f61b-4c88-baa7-f9d5aa17af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650650602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2650650602
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.1579853183
Short name T1100
Test name
Test status
Simulation time 162964417 ps
CPU time 4.29 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241664 kb
Host smart-0f4c7617-a49c-46a6-9507-79aeeafd2c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579853183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1579853183
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.1690855405
Short name T994
Test name
Test status
Simulation time 160123548 ps
CPU time 3.68 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:00 PM PDT 24
Peak memory 241888 kb
Host smart-dccafd6b-e603-4734-b113-40bfbfc956ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690855405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.1690855405
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.3773202659
Short name T1036
Test name
Test status
Simulation time 324841791 ps
CPU time 6.93 seconds
Started Jul 01 12:54:54 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241872 kb
Host smart-78f188f0-be6f-4579-b977-598c8a1a1105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773202659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3773202659
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.2632577524
Short name T559
Test name
Test status
Simulation time 2387281249 ps
CPU time 6.22 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:03 PM PDT 24
Peak memory 241964 kb
Host smart-1bde1dae-5728-4091-8e1b-6a4b5cd399c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632577524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2632577524
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.1374813516
Short name T454
Test name
Test status
Simulation time 357069485 ps
CPU time 9.73 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:05 PM PDT 24
Peak memory 241768 kb
Host smart-b299c3c5-90aa-4d69-bd15-c87461abe9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374813516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1374813516
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.3497854870
Short name T89
Test name
Test status
Simulation time 566122646 ps
CPU time 1.72 seconds
Started Jul 01 12:51:55 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 240016 kb
Host smart-ca573a19-9343-4222-a290-2d484d3cccb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497854870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.3497854870
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.851288826
Short name T1107
Test name
Test status
Simulation time 377621229 ps
CPU time 12.77 seconds
Started Jul 01 12:52:00 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 248796 kb
Host smart-1741ac80-d578-4d06-a5b4-0feb85d20edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851288826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.851288826
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.728203251
Short name T570
Test name
Test status
Simulation time 5513530195 ps
CPU time 24.34 seconds
Started Jul 01 12:52:01 PM PDT 24
Finished Jul 01 12:52:26 PM PDT 24
Peak memory 242436 kb
Host smart-095a8cf7-0eb5-4096-8748-ea18ea2b7da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728203251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.728203251
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.3262354155
Short name T172
Test name
Test status
Simulation time 301195349 ps
CPU time 5.2 seconds
Started Jul 01 12:51:56 PM PDT 24
Finished Jul 01 12:52:02 PM PDT 24
Peak memory 242084 kb
Host smart-8ba02027-5f5a-4464-b3b8-f58af0809467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262354155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3262354155
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.1003184035
Short name T142
Test name
Test status
Simulation time 2065261206 ps
CPU time 5.09 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 241892 kb
Host smart-132b65c8-0c4e-46c6-bb2f-8187d912b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003184035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.1003184035
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.2384975486
Short name T663
Test name
Test status
Simulation time 370205413 ps
CPU time 9.62 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242260 kb
Host smart-d4313ee0-e289-4820-90a2-4f8c0239b2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384975486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.2384975486
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.743712300
Short name T428
Test name
Test status
Simulation time 126811534 ps
CPU time 5.29 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 241984 kb
Host smart-ee125b52-aaa6-468a-9be6-4f26786c800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743712300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.743712300
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.2541273550
Short name T356
Test name
Test status
Simulation time 10711546801 ps
CPU time 21.94 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 242200 kb
Host smart-a8222436-a22b-4af0-bc4f-8f4391613214
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541273550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2541273550
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.2947779160
Short name T992
Test name
Test status
Simulation time 360451221 ps
CPU time 10.76 seconds
Started Jul 01 12:51:57 PM PDT 24
Finished Jul 01 12:52:10 PM PDT 24
Peak memory 242296 kb
Host smart-6028576d-d576-4ead-a25f-9e2f577241d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2947779160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2947779160
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.564786149
Short name T919
Test name
Test status
Simulation time 727066744 ps
CPU time 6.32 seconds
Started Jul 01 12:51:55 PM PDT 24
Finished Jul 01 12:52:02 PM PDT 24
Peak memory 242096 kb
Host smart-691d1847-44b3-45c4-9004-9ab81eef974f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564786149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.564786149
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.4218156444
Short name T954
Test name
Test status
Simulation time 12363468383 ps
CPU time 230.66 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 258688 kb
Host smart-527a3165-c9af-4b11-84c8-853500c2efbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218156444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.4218156444
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.1643215688
Short name T1167
Test name
Test status
Simulation time 16450356835 ps
CPU time 386.51 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:58:26 PM PDT 24
Peak memory 251664 kb
Host smart-6482a963-3d5c-46e4-9e62-7f07bfaa5a92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643215688 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.1643215688
Directory /workspace/16.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.3823755762
Short name T554
Test name
Test status
Simulation time 1824874314 ps
CPU time 17.46 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:17 PM PDT 24
Peak memory 242304 kb
Host smart-0bcd45cb-6dea-4a15-9358-837934f391e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823755762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.3823755762
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3302471393
Short name T782
Test name
Test status
Simulation time 706539693 ps
CPU time 4.71 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 242304 kb
Host smart-6498085a-639b-4294-b3d5-ddc37fdbd5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302471393 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3302471393
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.1806202518
Short name T55
Test name
Test status
Simulation time 292308133 ps
CPU time 5.49 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241916 kb
Host smart-f015bb32-94ea-4af5-84fa-e5bff277cafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806202518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1806202518
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.733693406
Short name T884
Test name
Test status
Simulation time 103050559 ps
CPU time 4.58 seconds
Started Jul 01 12:54:52 PM PDT 24
Finished Jul 01 12:54:58 PM PDT 24
Peak memory 242284 kb
Host smart-c8c36731-5fa0-485b-a3f1-9ddd6de98187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733693406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.733693406
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.687240251
Short name T550
Test name
Test status
Simulation time 215514157 ps
CPU time 4.65 seconds
Started Jul 01 12:54:53 PM PDT 24
Finished Jul 01 12:54:59 PM PDT 24
Peak memory 242336 kb
Host smart-dc6fcc50-898e-41d6-84db-3e71cb3d2daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687240251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.687240251
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.1106157709
Short name T484
Test name
Test status
Simulation time 185731996 ps
CPU time 5.54 seconds
Started Jul 01 12:54:54 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 241748 kb
Host smart-c27d4d47-a73a-458a-9cd1-ff471f86e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106157709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1106157709
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.207621135
Short name T176
Test name
Test status
Simulation time 2416042868 ps
CPU time 8.78 seconds
Started Jul 01 12:54:55 PM PDT 24
Finished Jul 01 12:55:04 PM PDT 24
Peak memory 242120 kb
Host smart-1baae732-0606-4cfb-b9a2-b066f4b7d734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207621135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.207621135
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.3395347915
Short name T1110
Test name
Test status
Simulation time 191889337 ps
CPU time 5.71 seconds
Started Jul 01 12:54:52 PM PDT 24
Finished Jul 01 12:54:59 PM PDT 24
Peak memory 242352 kb
Host smart-e068fed5-0bff-4eff-8137-b1de317bbeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395347915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3395347915
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3308749786
Short name T615
Test name
Test status
Simulation time 378311350 ps
CPU time 4.18 seconds
Started Jul 01 12:54:56 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 241956 kb
Host smart-780beb75-b4fe-4bf1-ade8-c66f37fefa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308749786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3308749786
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.1110628239
Short name T215
Test name
Test status
Simulation time 278971012 ps
CPU time 6.86 seconds
Started Jul 01 12:54:53 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 242272 kb
Host smart-caaba435-f81d-4efa-913f-223a2b6b794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110628239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.1110628239
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.470096652
Short name T1171
Test name
Test status
Simulation time 915539693 ps
CPU time 27.83 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 241804 kb
Host smart-333b82fe-9030-49e2-b96d-edcfee4e3c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470096652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.470096652
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.3831637988
Short name T413
Test name
Test status
Simulation time 274922529 ps
CPU time 4.02 seconds
Started Jul 01 12:54:58 PM PDT 24
Finished Jul 01 12:55:03 PM PDT 24
Peak memory 242400 kb
Host smart-d5146f21-e0f5-4b6c-83e7-0d1a2be2ac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831637988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3831637988
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2590528969
Short name T603
Test name
Test status
Simulation time 202987467 ps
CPU time 6.69 seconds
Started Jul 01 12:54:59 PM PDT 24
Finished Jul 01 12:55:06 PM PDT 24
Peak memory 242376 kb
Host smart-aac79ac6-ee38-4bde-8801-49fcf70ed663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590528969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2590528969
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.4218818985
Short name T608
Test name
Test status
Simulation time 552111718 ps
CPU time 3.77 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:04 PM PDT 24
Peak memory 242204 kb
Host smart-3f174858-1a97-4fa2-afa8-434a2350b4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218818985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.4218818985
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.1981131921
Short name T824
Test name
Test status
Simulation time 381036337 ps
CPU time 5.07 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:06 PM PDT 24
Peak memory 242360 kb
Host smart-3e2df9bc-5121-4406-9286-86e8cec644e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981131921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1981131921
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1913342919
Short name T692
Test name
Test status
Simulation time 203413748 ps
CPU time 4.72 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:06 PM PDT 24
Peak memory 241908 kb
Host smart-4f661462-e116-44de-a069-0529fb36ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913342919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1913342919
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.1178512540
Short name T510
Test name
Test status
Simulation time 142543031 ps
CPU time 1.95 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 12:52:08 PM PDT 24
Peak memory 240004 kb
Host smart-5b521c6b-2b18-4e96-85c3-362057f15215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178512540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.1178512540
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.728899478
Short name T168
Test name
Test status
Simulation time 1134241046 ps
CPU time 20.89 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:29 PM PDT 24
Peak memory 242664 kb
Host smart-e7b43934-cd71-4b9a-83ee-e256c7d8b097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728899478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.728899478
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.499765995
Short name T779
Test name
Test status
Simulation time 316537480 ps
CPU time 18.67 seconds
Started Jul 01 12:52:01 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 241912 kb
Host smart-ab3d0b32-5a1f-4125-b780-9af496d4eb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499765995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.499765995
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.2103068838
Short name T392
Test name
Test status
Simulation time 743510035 ps
CPU time 21.08 seconds
Started Jul 01 12:52:02 PM PDT 24
Finished Jul 01 12:52:24 PM PDT 24
Peak memory 248768 kb
Host smart-6e6019ba-51bb-479a-b074-e5ec2c7ba7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103068838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2103068838
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.1583390789
Short name T963
Test name
Test status
Simulation time 257502553 ps
CPU time 4.11 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:04 PM PDT 24
Peak memory 242032 kb
Host smart-32a4c2d3-f93a-4e14-ba8b-e0cb3cfee5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583390789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1583390789
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.2185444579
Short name T1178
Test name
Test status
Simulation time 12939833335 ps
CPU time 40.77 seconds
Started Jul 01 12:52:05 PM PDT 24
Finished Jul 01 12:52:47 PM PDT 24
Peak memory 242904 kb
Host smart-21e05209-e0f9-40b2-a8f1-c9d3a9d66c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185444579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.2185444579
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.402586640
Short name T901
Test name
Test status
Simulation time 181694807 ps
CPU time 10.36 seconds
Started Jul 01 12:52:02 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 241764 kb
Host smart-884a8e1d-4ab3-4428-847c-6aba18adfead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402586640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.402586640
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.253015474
Short name T519
Test name
Test status
Simulation time 432917149 ps
CPU time 10.51 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:10 PM PDT 24
Peak memory 242424 kb
Host smart-ab8b4cc2-c307-45e8-970f-0ec4c05d8db0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253015474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.253015474
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.1689414657
Short name T338
Test name
Test status
Simulation time 345216949 ps
CPU time 4.05 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242080 kb
Host smart-f4f8fa12-4acf-407e-a690-7aaa86032143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1689414657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1689414657
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.3616776626
Short name T494
Test name
Test status
Simulation time 459362081 ps
CPU time 9.09 seconds
Started Jul 01 12:51:58 PM PDT 24
Finished Jul 01 12:52:09 PM PDT 24
Peak memory 242252 kb
Host smart-0402bb0b-007f-4aa2-86e1-8dd547e9f0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616776626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3616776626
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.3349571404
Short name T528
Test name
Test status
Simulation time 99060076307 ps
CPU time 279.02 seconds
Started Jul 01 12:52:02 PM PDT 24
Finished Jul 01 12:56:42 PM PDT 24
Peak memory 274220 kb
Host smart-9a916b85-55d2-4293-9024-078d112bd391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349571404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.3349571404
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2984284232
Short name T753
Test name
Test status
Simulation time 249606704526 ps
CPU time 3314.31 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 01:47:21 PM PDT 24
Peak memory 581920 kb
Host smart-1c525f8d-a402-4d87-9078-e964f61ad69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984284232 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2984284232
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.3463175302
Short name T398
Test name
Test status
Simulation time 2353206000 ps
CPU time 18.59 seconds
Started Jul 01 12:52:03 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 242776 kb
Host smart-0364731c-8ce1-4993-a6e1-c8bd1c397156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463175302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.3463175302
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.413469200
Short name T47
Test name
Test status
Simulation time 171647238 ps
CPU time 4.29 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:05 PM PDT 24
Peak memory 242116 kb
Host smart-c831c357-7b22-4d2a-9fd5-0341e61fa17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413469200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.413469200
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.3415651907
Short name T1035
Test name
Test status
Simulation time 1198983367 ps
CPU time 9.24 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 241852 kb
Host smart-3f35102a-6faa-47cb-a9b4-3792627538dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415651907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3415651907
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.3464811008
Short name T807
Test name
Test status
Simulation time 411247062 ps
CPU time 3.9 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:05 PM PDT 24
Peak memory 242184 kb
Host smart-bf79adb1-e744-44d5-be2a-f1c7f277534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464811008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3464811008
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2244411935
Short name T1086
Test name
Test status
Simulation time 255794381 ps
CPU time 3.72 seconds
Started Jul 01 12:54:59 PM PDT 24
Finished Jul 01 12:55:04 PM PDT 24
Peak memory 242344 kb
Host smart-36b29a9e-b609-4223-a633-af23a984682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244411935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2244411935
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.3284079997
Short name T802
Test name
Test status
Simulation time 287274513 ps
CPU time 4.11 seconds
Started Jul 01 12:55:00 PM PDT 24
Finished Jul 01 12:55:05 PM PDT 24
Peak memory 242384 kb
Host smart-825dcdc9-ee4c-4cc2-9441-d73a8f88d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284079997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.3284079997
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.1457184042
Short name T1114
Test name
Test status
Simulation time 1034680486 ps
CPU time 3.12 seconds
Started Jul 01 12:55:02 PM PDT 24
Finished Jul 01 12:55:06 PM PDT 24
Peak memory 241916 kb
Host smart-8f85f704-8f54-4811-8af8-588835ce0a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457184042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1457184042
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.3910637370
Short name T194
Test name
Test status
Simulation time 421478541 ps
CPU time 5.42 seconds
Started Jul 01 12:55:07 PM PDT 24
Finished Jul 01 12:55:13 PM PDT 24
Peak memory 242284 kb
Host smart-7c2a2bd7-8800-4173-8fed-72742b30f720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910637370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3910637370
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.4011014059
Short name T1136
Test name
Test status
Simulation time 191416637 ps
CPU time 3.85 seconds
Started Jul 01 12:55:07 PM PDT 24
Finished Jul 01 12:55:11 PM PDT 24
Peak memory 242144 kb
Host smart-d0bcba17-563c-42c7-93d3-51a04691b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011014059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.4011014059
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.3590701861
Short name T461
Test name
Test status
Simulation time 709724331 ps
CPU time 11.98 seconds
Started Jul 01 12:55:04 PM PDT 24
Finished Jul 01 12:55:17 PM PDT 24
Peak memory 241968 kb
Host smart-8ebd6ae8-9321-42f0-81b8-a7871a890b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590701861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.3590701861
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.3306332885
Short name T162
Test name
Test status
Simulation time 2427899165 ps
CPU time 4.09 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:08 PM PDT 24
Peak memory 241976 kb
Host smart-76f2741f-bd37-49d3-a98d-16f63add78cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306332885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3306332885
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.1942314682
Short name T227
Test name
Test status
Simulation time 511590571 ps
CPU time 11.68 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 242188 kb
Host smart-b9c89123-2354-4118-b34a-638eb8f862b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942314682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1942314682
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.118921740
Short name T161
Test name
Test status
Simulation time 2518126075 ps
CPU time 5.09 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:09 PM PDT 24
Peak memory 241960 kb
Host smart-f36a50c8-e556-4501-bd70-e06e55cd21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118921740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.118921740
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.1202913552
Short name T1111
Test name
Test status
Simulation time 254162892 ps
CPU time 5.46 seconds
Started Jul 01 12:55:04 PM PDT 24
Finished Jul 01 12:55:11 PM PDT 24
Peak memory 241916 kb
Host smart-cb9d99d5-56a8-46f2-a080-f541e3a07849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202913552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.1202913552
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2602482291
Short name T911
Test name
Test status
Simulation time 1868079631 ps
CPU time 6.41 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 242040 kb
Host smart-7496bfe1-7300-4928-a67c-625c762e85cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602482291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2602482291
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.221211620
Short name T987
Test name
Test status
Simulation time 246965602 ps
CPU time 4.21 seconds
Started Jul 01 12:55:05 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 241776 kb
Host smart-93bb1e40-ebe6-4341-9846-a5558e4cf56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221211620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.221211620
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.3659809435
Short name T633
Test name
Test status
Simulation time 179826428 ps
CPU time 4.52 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:08 PM PDT 24
Peak memory 241876 kb
Host smart-bd42afd9-a029-4b45-bb33-565244a8bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659809435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.3659809435
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.4033749795
Short name T151
Test name
Test status
Simulation time 136660873 ps
CPU time 3.59 seconds
Started Jul 01 12:55:07 PM PDT 24
Finished Jul 01 12:55:12 PM PDT 24
Peak memory 241820 kb
Host smart-4cfb605f-978e-4fdd-a933-ac555676497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033749795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.4033749795
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.2599646949
Short name T971
Test name
Test status
Simulation time 896115027 ps
CPU time 20.08 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:23 PM PDT 24
Peak memory 241972 kb
Host smart-108829c1-fd8e-43f8-84f2-6d5b06679b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599646949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2599646949
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.2643239089
Short name T456
Test name
Test status
Simulation time 124915064 ps
CPU time 1.81 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 240132 kb
Host smart-5952ca70-9a8c-4b1c-94a8-41c2bf9a698c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643239089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2643239089
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.212481210
Short name T1104
Test name
Test status
Simulation time 477985405 ps
CPU time 8.22 seconds
Started Jul 01 12:52:03 PM PDT 24
Finished Jul 01 12:52:12 PM PDT 24
Peak memory 242312 kb
Host smart-e8322553-7b07-4e2e-b507-f46acd76583f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212481210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.212481210
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.2200543092
Short name T404
Test name
Test status
Simulation time 196226911 ps
CPU time 8.29 seconds
Started Jul 01 12:52:06 PM PDT 24
Finished Jul 01 12:52:16 PM PDT 24
Peak memory 241720 kb
Host smart-ee199837-9196-4e8b-af2d-d9baa1d33769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200543092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2200543092
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2805964917
Short name T448
Test name
Test status
Simulation time 1420997670 ps
CPU time 24.29 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 12:52:30 PM PDT 24
Peak memory 242076 kb
Host smart-f4908135-7145-453f-b79c-39d6d8d45f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805964917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2805964917
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.2612904509
Short name T1122
Test name
Test status
Simulation time 224920598 ps
CPU time 4.17 seconds
Started Jul 01 12:52:05 PM PDT 24
Finished Jul 01 12:52:11 PM PDT 24
Peak memory 241940 kb
Host smart-6fcf89fd-0ac2-4fa7-8e81-3a4319bce54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612904509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2612904509
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.426177888
Short name T170
Test name
Test status
Simulation time 543792553 ps
CPU time 11.08 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 242532 kb
Host smart-1cf2963e-7517-4219-85c0-6b1384e549d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426177888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.426177888
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.1342519534
Short name T698
Test name
Test status
Simulation time 1787325692 ps
CPU time 3.86 seconds
Started Jul 01 12:52:08 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 242036 kb
Host smart-08e43916-9b6a-4ea7-8580-34827841ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342519534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.1342519534
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2031631250
Short name T1010
Test name
Test status
Simulation time 1011277145 ps
CPU time 26.04 seconds
Started Jul 01 12:52:04 PM PDT 24
Finished Jul 01 12:52:32 PM PDT 24
Peak memory 242256 kb
Host smart-6664a391-71be-4433-aa61-e84b77ee3488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031631250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2031631250
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.50545009
Short name T352
Test name
Test status
Simulation time 638214850 ps
CPU time 18.18 seconds
Started Jul 01 12:52:06 PM PDT 24
Finished Jul 01 12:52:25 PM PDT 24
Peak memory 242064 kb
Host smart-da1264f0-9e48-4fd0-9f02-00902101ddf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=50545009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.50545009
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.3054875646
Short name T867
Test name
Test status
Simulation time 111092176 ps
CPU time 4.82 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 241984 kb
Host smart-db7ef156-5e49-479f-a15d-e3a9f1defc38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054875646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3054875646
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.3751566512
Short name T903
Test name
Test status
Simulation time 1243354073 ps
CPU time 7.39 seconds
Started Jul 01 12:52:03 PM PDT 24
Finished Jul 01 12:52:12 PM PDT 24
Peak memory 242420 kb
Host smart-8a0b72f3-842e-407a-8c65-27de510e0e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751566512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.3751566512
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.510307018
Short name T498
Test name
Test status
Simulation time 49404791374 ps
CPU time 94.77 seconds
Started Jul 01 12:52:06 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 245652 kb
Host smart-786eb124-1bf7-474a-9138-6dae96c917ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510307018 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.
510307018
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.3744034898
Short name T90
Test name
Test status
Simulation time 719442760 ps
CPU time 14.66 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:25 PM PDT 24
Peak memory 242016 kb
Host smart-0fa14325-722d-4bb9-a8c0-d6b64c262f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744034898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.3744034898
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.2623901336
Short name T467
Test name
Test status
Simulation time 770623721 ps
CPU time 5.38 seconds
Started Jul 01 12:55:07 PM PDT 24
Finished Jul 01 12:55:13 PM PDT 24
Peak memory 242164 kb
Host smart-269a3c2b-4bc1-499d-824f-3fd70b3d6dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623901336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.2623901336
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.3771752428
Short name T213
Test name
Test status
Simulation time 1536956269 ps
CPU time 4.25 seconds
Started Jul 01 12:55:04 PM PDT 24
Finished Jul 01 12:55:09 PM PDT 24
Peak memory 242384 kb
Host smart-1470f641-1f91-4b76-8669-13955e584fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771752428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3771752428
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.3002376170
Short name T105
Test name
Test status
Simulation time 287714823 ps
CPU time 4.16 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:08 PM PDT 24
Peak memory 242388 kb
Host smart-c4afd41e-949c-4cf1-98ec-1811f957f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002376170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3002376170
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.2816328383
Short name T1142
Test name
Test status
Simulation time 1120407424 ps
CPU time 17.3 seconds
Started Jul 01 12:55:07 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 241820 kb
Host smart-1eb2cdc5-63cc-4bc1-9339-5c45e336a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816328383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.2816328383
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.675117443
Short name T80
Test name
Test status
Simulation time 128954642 ps
CPU time 3.54 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:07 PM PDT 24
Peak memory 241904 kb
Host smart-fc8b30fb-9bec-4aa3-a956-0ca421948969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675117443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.675117443
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.229865612
Short name T489
Test name
Test status
Simulation time 385221139 ps
CPU time 11.61 seconds
Started Jul 01 12:55:02 PM PDT 24
Finished Jul 01 12:55:14 PM PDT 24
Peak memory 242000 kb
Host smart-4c1414a8-4b86-4bff-bf0b-74bc558578e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229865612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.229865612
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.3630773403
Short name T775
Test name
Test status
Simulation time 105860698 ps
CPU time 3.86 seconds
Started Jul 01 12:55:05 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 242072 kb
Host smart-90877184-d4a2-4433-aacd-ad60392c070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630773403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3630773403
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.3792673353
Short name T1054
Test name
Test status
Simulation time 102642452 ps
CPU time 2.95 seconds
Started Jul 01 12:55:03 PM PDT 24
Finished Jul 01 12:55:07 PM PDT 24
Peak memory 241860 kb
Host smart-349d3db9-d093-41b9-8bb1-c43a2b91ad1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792673353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.3792673353
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.550075656
Short name T74
Test name
Test status
Simulation time 166973830 ps
CPU time 3.79 seconds
Started Jul 01 12:55:05 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 241920 kb
Host smart-fb6363e0-77bd-4edd-a435-356415db2d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550075656 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.550075656
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.2198590211
Short name T315
Test name
Test status
Simulation time 489657187 ps
CPU time 14.59 seconds
Started Jul 01 12:55:05 PM PDT 24
Finished Jul 01 12:55:21 PM PDT 24
Peak memory 242100 kb
Host smart-c0bbffa2-465c-4633-aacc-cd8a8db9e981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198590211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.2198590211
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.264064150
Short name T179
Test name
Test status
Simulation time 1730686243 ps
CPU time 4.66 seconds
Started Jul 01 12:55:04 PM PDT 24
Finished Jul 01 12:55:10 PM PDT 24
Peak memory 242416 kb
Host smart-c757da20-7e8f-424c-a6c4-50b8f1e87768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264064150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.264064150
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.2895758633
Short name T371
Test name
Test status
Simulation time 4428950856 ps
CPU time 13.54 seconds
Started Jul 01 12:55:06 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 242048 kb
Host smart-cfa8bf59-b15f-4ddf-ae0d-8dac2dc6329a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895758633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2895758633
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.1040293511
Short name T108
Test name
Test status
Simulation time 162907910 ps
CPU time 3.34 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:15 PM PDT 24
Peak memory 242408 kb
Host smart-bb0dd635-4450-42a1-b6a5-7501c5badf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040293511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1040293511
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.1638429843
Short name T726
Test name
Test status
Simulation time 202557046 ps
CPU time 6.31 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:15 PM PDT 24
Peak memory 241816 kb
Host smart-021b45ad-649a-43fc-b6e6-e5dfa69a868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638429843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1638429843
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.943000725
Short name T800
Test name
Test status
Simulation time 396990532 ps
CPU time 4.45 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:15 PM PDT 24
Peak memory 241920 kb
Host smart-ace6dcd4-b7bf-4441-88e9-f8d94cba0927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943000725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.943000725
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.127846910
Short name T774
Test name
Test status
Simulation time 397506368 ps
CPU time 4.99 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:14 PM PDT 24
Peak memory 241752 kb
Host smart-7864b401-a67c-44f3-bfbc-f55c65ffa507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127846910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.127846910
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.3932056620
Short name T733
Test name
Test status
Simulation time 599993942 ps
CPU time 4.88 seconds
Started Jul 01 12:55:10 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 242384 kb
Host smart-f24244b7-5e65-4511-9a82-098e52d8e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932056620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3932056620
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2047058831
Short name T488
Test name
Test status
Simulation time 618637931 ps
CPU time 8.56 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242320 kb
Host smart-5baa3e33-28ec-41d7-83d4-3e7465db38cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047058831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2047058831
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.2725712965
Short name T661
Test name
Test status
Simulation time 2505853885 ps
CPU time 5.19 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 242104 kb
Host smart-e631acda-1c89-443d-ae0a-d9eec532b814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725712965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2725712965
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1641591938
Short name T1041
Test name
Test status
Simulation time 1490462002 ps
CPU time 4.84 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:15 PM PDT 24
Peak memory 241876 kb
Host smart-00352397-db6c-4b4f-bb9c-a2bbd26023ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641591938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1641591938
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3205825394
Short name T513
Test name
Test status
Simulation time 178117185 ps
CPU time 1.51 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:10 PM PDT 24
Peak memory 240520 kb
Host smart-7f87e4e8-2eb4-4d71-b04d-b00cbda51eb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205825394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3205825394
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.1926560992
Short name T40
Test name
Test status
Simulation time 1435006819 ps
CPU time 25.97 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:37 PM PDT 24
Peak memory 244340 kb
Host smart-aba8a4a8-8edc-4233-a3aa-3cae2862ed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926560992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1926560992
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.1377257549
Short name T433
Test name
Test status
Simulation time 3264066240 ps
CPU time 27.39 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:36 PM PDT 24
Peak memory 242400 kb
Host smart-5a2f6137-2d04-44ae-83d0-815dcec87f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377257549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1377257549
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.298612649
Short name T857
Test name
Test status
Simulation time 103180186 ps
CPU time 3.23 seconds
Started Jul 01 12:52:10 PM PDT 24
Finished Jul 01 12:52:14 PM PDT 24
Peak memory 248776 kb
Host smart-c4a6af94-c558-45b4-b7a7-f1cba5d8fcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298612649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.298612649
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.4284316025
Short name T288
Test name
Test status
Simulation time 2464913904 ps
CPU time 8.02 seconds
Started Jul 01 12:52:08 PM PDT 24
Finished Jul 01 12:52:17 PM PDT 24
Peak memory 242184 kb
Host smart-8a8eb617-f6cf-40eb-8fed-842843681121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284316025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.4284316025
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.2867195046
Short name T673
Test name
Test status
Simulation time 2251549434 ps
CPU time 33.39 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 251256 kb
Host smart-3880df41-2ab3-4576-8e4f-eeb967bf40b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867195046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2867195046
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.3158436285
Short name T1096
Test name
Test status
Simulation time 2540694360 ps
CPU time 19.69 seconds
Started Jul 01 12:52:08 PM PDT 24
Finished Jul 01 12:52:29 PM PDT 24
Peak memory 242696 kb
Host smart-7e2848ff-006f-486c-8a69-9671035e12e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158436285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.3158436285
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.1265446172
Short name T974
Test name
Test status
Simulation time 328284408 ps
CPU time 8.88 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 242292 kb
Host smart-75280b6a-2545-4bb7-99e3-05280fe0bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265446172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1265446172
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.3053618403
Short name T655
Test name
Test status
Simulation time 602910047 ps
CPU time 11.8 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 241912 kb
Host smart-46c643f8-9006-4439-af83-cbb181cf163f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053618403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3053618403
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.3445764829
Short name T1174
Test name
Test status
Simulation time 641827088 ps
CPU time 8.46 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 248720 kb
Host smart-03220132-7c6f-4570-bc88-abb8ec139765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445764829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.3445764829
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.3125987720
Short name T167
Test name
Test status
Simulation time 108198019699 ps
CPU time 1175.12 seconds
Started Jul 01 12:52:10 PM PDT 24
Finished Jul 01 01:11:47 PM PDT 24
Peak memory 343140 kb
Host smart-c89e388b-e07e-401d-9e6f-fff8663d0461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125987720 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.3125987720
Directory /workspace/19.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.3191515042
Short name T1065
Test name
Test status
Simulation time 30031953624 ps
CPU time 47.84 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 242180 kb
Host smart-f5bae925-f8a1-4ecf-80fa-8f7dbac14cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191515042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.3191515042
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.4015450430
Short name T1183
Test name
Test status
Simulation time 1910031130 ps
CPU time 6.47 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:21 PM PDT 24
Peak memory 241852 kb
Host smart-663f67eb-19ba-432b-a957-909e134cbdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015450430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.4015450430
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.1746603288
Short name T358
Test name
Test status
Simulation time 125260331 ps
CPU time 3.07 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:13 PM PDT 24
Peak memory 242224 kb
Host smart-41ae2475-82b7-4a75-93fd-aa397dada64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746603288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1746603288
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.380144344
Short name T578
Test name
Test status
Simulation time 549911839 ps
CPU time 4.37 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:15 PM PDT 24
Peak memory 242260 kb
Host smart-7e2e2abc-52dd-48ab-a7b2-215dea97abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380144344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.380144344
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2871306725
Short name T552
Test name
Test status
Simulation time 158392463 ps
CPU time 4.25 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:13 PM PDT 24
Peak memory 241668 kb
Host smart-7882ee0b-4d3c-4043-8a76-ef5a3534183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871306725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2871306725
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.923958114
Short name T1169
Test name
Test status
Simulation time 632165032 ps
CPU time 5.36 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 242396 kb
Host smart-52a4d87d-c206-4ddb-a0ef-cf792879de23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923958114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.923958114
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.1224023318
Short name T192
Test name
Test status
Simulation time 158157840 ps
CPU time 7.14 seconds
Started Jul 01 12:55:10 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 241868 kb
Host smart-de0a7837-f690-425f-819c-e8bb20c1469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224023318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1224023318
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.3525613903
Short name T25
Test name
Test status
Simulation time 232999665 ps
CPU time 3.7 seconds
Started Jul 01 12:55:09 PM PDT 24
Finished Jul 01 12:55:13 PM PDT 24
Peak memory 242256 kb
Host smart-7b9bfa9b-a727-4802-a6c0-d3bd78027f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525613903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3525613903
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.827384640
Short name T251
Test name
Test status
Simulation time 1616942826 ps
CPU time 21.85 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 241848 kb
Host smart-7765978d-c946-4230-814b-f2b43dce3c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827384640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.827384640
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.3332585630
Short name T175
Test name
Test status
Simulation time 104094480 ps
CPU time 3.73 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:12 PM PDT 24
Peak memory 241844 kb
Host smart-1382cbf5-1c84-4752-9811-4ad3fed5fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332585630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3332585630
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.676937938
Short name T1049
Test name
Test status
Simulation time 358012440 ps
CPU time 7.5 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 241944 kb
Host smart-7bb6fbfd-70bd-4f26-922b-6e133b0e6dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676937938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.676937938
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.3897617497
Short name T614
Test name
Test status
Simulation time 677081462 ps
CPU time 4.49 seconds
Started Jul 01 12:55:10 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 241904 kb
Host smart-1364bb93-7780-4a55-a412-cd39432810f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897617497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.3897617497
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.2988493026
Short name T702
Test name
Test status
Simulation time 1306064374 ps
CPU time 10.96 seconds
Started Jul 01 12:55:08 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 242000 kb
Host smart-7d58eb37-3166-42b6-b03a-3db188403c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988493026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2988493026
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.308862198
Short name T49
Test name
Test status
Simulation time 587475385 ps
CPU time 4.89 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242160 kb
Host smart-37a7467e-b1d1-4898-bbc1-e75b26cd2bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308862198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.308862198
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.1163255765
Short name T1195
Test name
Test status
Simulation time 1024081837 ps
CPU time 29.04 seconds
Started Jul 01 12:55:12 PM PDT 24
Finished Jul 01 12:55:42 PM PDT 24
Peak memory 242120 kb
Host smart-58959317-cac3-4fed-96e6-760e1cc6073a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163255765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1163255765
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.799694582
Short name T1018
Test name
Test status
Simulation time 246233260 ps
CPU time 4.49 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 241996 kb
Host smart-eb5179b6-d456-41c4-af6e-7f0e429348d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799694582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.799694582
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.1242785799
Short name T939
Test name
Test status
Simulation time 280308205 ps
CPU time 4.3 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 241856 kb
Host smart-2551500b-b10e-40d3-ba32-ed03e8b7de59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242785799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1242785799
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.2680936885
Short name T709
Test name
Test status
Simulation time 463320481 ps
CPU time 3.49 seconds
Started Jul 01 12:55:15 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242380 kb
Host smart-73ae907c-bbd0-44a9-bcf8-2f052bfd6ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680936885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.2680936885
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.160456901
Short name T772
Test name
Test status
Simulation time 3144657261 ps
CPU time 16.14 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:31 PM PDT 24
Peak memory 241996 kb
Host smart-f9006313-50a6-46f2-a58c-6a68c04312e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160456901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.160456901
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.2845846180
Short name T43
Test name
Test status
Simulation time 120597932 ps
CPU time 3.93 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242080 kb
Host smart-16dfeeb7-16ba-4ec6-8115-791d0dcf8f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845846180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2845846180
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2368800647
Short name T739
Test name
Test status
Simulation time 995758300 ps
CPU time 19.13 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242216 kb
Host smart-51f989ec-7e0d-47e1-8ee0-451aa2a9f1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368800647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2368800647
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.2125290151
Short name T1163
Test name
Test status
Simulation time 139643103 ps
CPU time 1.59 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 12:51:09 PM PDT 24
Peak memory 240536 kb
Host smart-cc80a050-8a94-43a3-aa07-88b5c812af79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125290151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2125290151
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.2062823495
Short name T95
Test name
Test status
Simulation time 18741336445 ps
CPU time 28.81 seconds
Started Jul 01 12:51:04 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 243164 kb
Host smart-ab658a51-f2f6-43f0-b161-3003fc8fcbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062823495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2062823495
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.4012474615
Short name T78
Test name
Test status
Simulation time 3855719663 ps
CPU time 7.52 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 242444 kb
Host smart-7297c95b-b465-4019-937e-fef635d027c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012474615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.4012474615
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1018102344
Short name T956
Test name
Test status
Simulation time 393992706 ps
CPU time 11.8 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:21 PM PDT 24
Peak memory 242020 kb
Host smart-7adc47bf-9fb5-487a-9d22-8a9dc87943c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018102344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1018102344
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.4236888477
Short name T355
Test name
Test status
Simulation time 20654906211 ps
CPU time 32.85 seconds
Started Jul 01 12:51:03 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 243380 kb
Host smart-1f4d3d31-45e8-45cb-be12-c5a7fac2efe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236888477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.4236888477
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.3150506432
Short name T1151
Test name
Test status
Simulation time 359751423 ps
CPU time 4.89 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 241900 kb
Host smart-3defb68c-412b-426d-98a5-1ee476cf1865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150506432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3150506432
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.3925133982
Short name T887
Test name
Test status
Simulation time 2302714161 ps
CPU time 31.02 seconds
Started Jul 01 12:51:00 PM PDT 24
Finished Jul 01 12:51:32 PM PDT 24
Peak memory 242212 kb
Host smart-90783fe9-7924-45fa-b91f-eba5c8d25bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925133982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.3925133982
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.3131670981
Short name T417
Test name
Test status
Simulation time 316432458 ps
CPU time 8.66 seconds
Started Jul 01 12:51:03 PM PDT 24
Finished Jul 01 12:51:14 PM PDT 24
Peak memory 242256 kb
Host smart-f262ce3f-bcf7-4d75-aacf-847981e52e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131670981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.3131670981
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.4162210102
Short name T476
Test name
Test status
Simulation time 287498657 ps
CPU time 3.99 seconds
Started Jul 01 12:51:01 PM PDT 24
Finished Jul 01 12:51:06 PM PDT 24
Peak memory 242084 kb
Host smart-adc3bd28-6497-44df-8252-04e3597d4aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162210102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.4162210102
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.793776061
Short name T946
Test name
Test status
Simulation time 706683103 ps
CPU time 20.7 seconds
Started Jul 01 12:51:02 PM PDT 24
Finished Jul 01 12:51:23 PM PDT 24
Peak memory 241956 kb
Host smart-231a1d7a-ea3b-4c4d-8f7d-f775d06fe5bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=793776061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.793776061
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.398272315
Short name T340
Test name
Test status
Simulation time 213653331 ps
CPU time 7.2 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:16 PM PDT 24
Peak memory 242192 kb
Host smart-b5de109c-15e0-4f33-978b-5870f8310258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398272315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.398272315
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.499425118
Short name T21
Test name
Test status
Simulation time 154648393266 ps
CPU time 328.09 seconds
Started Jul 01 12:51:04 PM PDT 24
Finished Jul 01 12:56:35 PM PDT 24
Peak memory 270272 kb
Host smart-11db1993-569d-4f4e-aeb8-5702236e27b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499425118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.499425118
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.3717965345
Short name T828
Test name
Test status
Simulation time 1076470522 ps
CPU time 6.42 seconds
Started Jul 01 12:51:04 PM PDT 24
Finished Jul 01 12:51:12 PM PDT 24
Peak memory 242068 kb
Host smart-1e0e99b7-6896-4242-9c4d-7f6045f6ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717965345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.3717965345
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.3652295200
Short name T964
Test name
Test status
Simulation time 127276562370 ps
CPU time 209.61 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 257076 kb
Host smart-55d9a0af-a459-4e5d-a239-a4aec2c63971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652295200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
3652295200
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.4292031840
Short name T306
Test name
Test status
Simulation time 79829688780 ps
CPU time 1018.51 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 01:08:07 PM PDT 24
Peak memory 257192 kb
Host smart-ae04e66c-b553-4f6e-b739-e78a318b1b6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292031840 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.4292031840
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.3395002132
Short name T499
Test name
Test status
Simulation time 566763642 ps
CPU time 12.48 seconds
Started Jul 01 12:51:07 PM PDT 24
Finished Jul 01 12:51:22 PM PDT 24
Peak memory 242560 kb
Host smart-b5937a41-8fee-4395-8834-7c75e1aad3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395002132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.3395002132
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.3326858924
Short name T678
Test name
Test status
Simulation time 253171921 ps
CPU time 2 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:17 PM PDT 24
Peak memory 240408 kb
Host smart-793c04a8-9934-4b7a-9cf6-b1fc2b4fe64b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326858924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3326858924
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1293106894
Short name T79
Test name
Test status
Simulation time 401370699 ps
CPU time 5.54 seconds
Started Jul 01 12:52:10 PM PDT 24
Finished Jul 01 12:52:17 PM PDT 24
Peak memory 248780 kb
Host smart-2077c4aa-5caa-48c1-8118-ee6dea132699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293106894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1293106894
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2157738398
Short name T1173
Test name
Test status
Simulation time 5602362208 ps
CPU time 52.45 seconds
Started Jul 01 12:52:09 PM PDT 24
Finished Jul 01 12:53:03 PM PDT 24
Peak memory 256660 kb
Host smart-1e76742d-214d-4cc3-aa9b-c8e14aa14d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157738398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2157738398
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.203428526
Short name T683
Test name
Test status
Simulation time 7329466141 ps
CPU time 39.34 seconds
Started Jul 01 12:52:10 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 242516 kb
Host smart-8b6ec834-84f9-43e3-885c-a5ee60ee5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203428526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.203428526
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.2374717593
Short name T755
Test name
Test status
Simulation time 404911586 ps
CPU time 4.63 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:13 PM PDT 24
Peak memory 242304 kb
Host smart-b45fb1bf-3403-4ab3-ad41-00766039412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374717593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.2374717593
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.3390503184
Short name T905
Test name
Test status
Simulation time 453071864 ps
CPU time 5.07 seconds
Started Jul 01 12:52:16 PM PDT 24
Finished Jul 01 12:52:23 PM PDT 24
Peak memory 242420 kb
Host smart-32685b93-9693-40b1-bdf1-7a9f1cfb7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390503184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.3390503184
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.3954368087
Short name T290
Test name
Test status
Simulation time 243391696 ps
CPU time 5.48 seconds
Started Jul 01 12:52:14 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 241880 kb
Host smart-c0617c90-088f-4801-942c-97d77036bd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954368087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.3954368087
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.1715310750
Short name T1097
Test name
Test status
Simulation time 1377700043 ps
CPU time 18.95 seconds
Started Jul 01 12:52:07 PM PDT 24
Finished Jul 01 12:52:27 PM PDT 24
Peak memory 241956 kb
Host smart-98cfff97-f205-43ba-ba15-c11028fd77dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715310750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.1715310750
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.1679094548
Short name T668
Test name
Test status
Simulation time 489127417 ps
CPU time 13.32 seconds
Started Jul 01 12:52:10 PM PDT 24
Finished Jul 01 12:52:25 PM PDT 24
Peak memory 242012 kb
Host smart-af9232c0-50cf-427b-9bcc-82f025962b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679094548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.1679094548
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.4133473938
Short name T1000
Test name
Test status
Simulation time 927543061 ps
CPU time 9.21 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:24 PM PDT 24
Peak memory 242112 kb
Host smart-aaee7052-7cb2-444f-afab-549db00ff84f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133473938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.4133473938
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3645955527
Short name T830
Test name
Test status
Simulation time 252208578 ps
CPU time 8.02 seconds
Started Jul 01 12:52:05 PM PDT 24
Finished Jul 01 12:52:15 PM PDT 24
Peak memory 241752 kb
Host smart-94be0eef-3518-40f5-84a6-149a9c1d6086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645955527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3645955527
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.1546423253
Short name T374
Test name
Test status
Simulation time 31148015610 ps
CPU time 258.88 seconds
Started Jul 01 12:52:12 PM PDT 24
Finished Jul 01 12:56:32 PM PDT 24
Peak memory 264252 kb
Host smart-39d20d61-87f4-43a5-951d-cbb8eb402ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546423253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.1546423253
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.2703420547
Short name T283
Test name
Test status
Simulation time 59059705710 ps
CPU time 1039.41 seconds
Started Jul 01 12:52:12 PM PDT 24
Finished Jul 01 01:09:33 PM PDT 24
Peak memory 332060 kb
Host smart-71bc4548-8a0c-4b90-b175-14c12339a0fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703420547 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.2703420547
Directory /workspace/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.141824611
Short name T1043
Test name
Test status
Simulation time 427537291 ps
CPU time 4.6 seconds
Started Jul 01 12:52:15 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 242092 kb
Host smart-984cee11-0065-454d-a896-7ea288fe0741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141824611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.141824611
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.4000874238
Short name T526
Test name
Test status
Simulation time 2232076555 ps
CPU time 3.78 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242360 kb
Host smart-0bec7e81-4f47-4445-b42b-8cb033c5fbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000874238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.4000874238
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.860694749
Short name T441
Test name
Test status
Simulation time 1827001400 ps
CPU time 5.65 seconds
Started Jul 01 12:55:13 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 242292 kb
Host smart-c8178bfb-d1c4-40ed-86ed-2ae56140d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860694749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.860694749
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.2704969348
Short name T866
Test name
Test status
Simulation time 110279419 ps
CPU time 4.23 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:19 PM PDT 24
Peak memory 241972 kb
Host smart-37dadb1f-2eaa-432f-8a89-29d6a488b665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704969348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2704969348
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.2146277878
Short name T509
Test name
Test status
Simulation time 181757008 ps
CPU time 4.59 seconds
Started Jul 01 12:55:15 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 242144 kb
Host smart-36050bff-96f7-4272-8ff3-24ad27158fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146277878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2146277878
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.3062743460
Short name T805
Test name
Test status
Simulation time 601419877 ps
CPU time 4.1 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 241920 kb
Host smart-4c2d3b58-f730-4996-8b8e-e3581fddfd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062743460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3062743460
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.2064928182
Short name T767
Test name
Test status
Simulation time 2571163830 ps
CPU time 6.96 seconds
Started Jul 01 12:55:12 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 241976 kb
Host smart-c0755a9a-180d-4d9b-ae58-3c1aa1bcc428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064928182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2064928182
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.3260428561
Short name T479
Test name
Test status
Simulation time 454560603 ps
CPU time 5.39 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:21 PM PDT 24
Peak memory 241904 kb
Host smart-dbaca2df-1604-4e9d-a45b-7b80df053b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260428561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.3260428561
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2250365980
Short name T159
Test name
Test status
Simulation time 204049740 ps
CPU time 3.06 seconds
Started Jul 01 12:55:14 PM PDT 24
Finished Jul 01 12:55:18 PM PDT 24
Peak memory 242080 kb
Host smart-a192a2bc-696d-4ef8-9b30-5857413d72f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250365980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2250365980
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.3606389705
Short name T893
Test name
Test status
Simulation time 164471883 ps
CPU time 3.49 seconds
Started Jul 01 12:55:13 PM PDT 24
Finished Jul 01 12:55:18 PM PDT 24
Peak memory 242020 kb
Host smart-ba7f9599-76b4-4e63-bd9a-4d29d3a6fe83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606389705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.3606389705
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3093599800
Short name T1070
Test name
Test status
Simulation time 2322856920 ps
CPU time 5.95 seconds
Started Jul 01 12:55:13 PM PDT 24
Finished Jul 01 12:55:20 PM PDT 24
Peak memory 241988 kb
Host smart-d1a836c7-dbd5-4842-878e-2cd5963835cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093599800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3093599800
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.3618052978
Short name T1044
Test name
Test status
Simulation time 224665645 ps
CPU time 2.16 seconds
Started Jul 01 12:52:15 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 240264 kb
Host smart-7008b373-47cd-4a03-a1b0-2ddf38bb4c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618052978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.3618052978
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.4181223368
Short name T677
Test name
Test status
Simulation time 1823506966 ps
CPU time 4.92 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:19 PM PDT 24
Peak memory 242204 kb
Host smart-0ef67176-f22d-4205-8f7b-18bc50262593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181223368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.4181223368
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.3894262622
Short name T1034
Test name
Test status
Simulation time 348968844 ps
CPU time 20.19 seconds
Started Jul 01 12:52:14 PM PDT 24
Finished Jul 01 12:52:36 PM PDT 24
Peak memory 242132 kb
Host smart-f0f47a8e-7036-4720-9775-95a71a43136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894262622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3894262622
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.3856422581
Short name T812
Test name
Test status
Simulation time 979517935 ps
CPU time 34.18 seconds
Started Jul 01 12:52:15 PM PDT 24
Finished Jul 01 12:52:51 PM PDT 24
Peak memory 242592 kb
Host smart-ff263824-137a-4a85-b3e4-81436fd3d38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856422581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.3856422581
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1710945598
Short name T975
Test name
Test status
Simulation time 568205650 ps
CPU time 4.63 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:20 PM PDT 24
Peak memory 241848 kb
Host smart-969bb798-f4bd-4e44-970a-47b5633cacae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710945598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1710945598
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.1738797898
Short name T626
Test name
Test status
Simulation time 252988527 ps
CPU time 7.96 seconds
Started Jul 01 12:52:14 PM PDT 24
Finished Jul 01 12:52:24 PM PDT 24
Peak memory 242456 kb
Host smart-28c68198-a064-46b5-adda-50f93456a953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738797898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.1738797898
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.3174664871
Short name T768
Test name
Test status
Simulation time 703316688 ps
CPU time 17.24 seconds
Started Jul 01 12:52:17 PM PDT 24
Finished Jul 01 12:52:35 PM PDT 24
Peak memory 248780 kb
Host smart-917e6be8-9b25-4b36-bab5-f16ef500d05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174664871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.3174664871
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.1873424641
Short name T904
Test name
Test status
Simulation time 6628347663 ps
CPU time 21.48 seconds
Started Jul 01 12:52:12 PM PDT 24
Finished Jul 01 12:52:35 PM PDT 24
Peak memory 241828 kb
Host smart-9c2ce005-1391-459e-a6d5-d4ecbfa60b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873424641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.1873424641
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.3355824860
Short name T434
Test name
Test status
Simulation time 281789584 ps
CPU time 10.52 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:26 PM PDT 24
Peak memory 242232 kb
Host smart-ef76ed25-7fbf-40a9-8bd8-40fe1e7bb15c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355824860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.3355824860
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.2656194139
Short name T335
Test name
Test status
Simulation time 487121412 ps
CPU time 7.67 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:23 PM PDT 24
Peak memory 242448 kb
Host smart-ba00b643-1732-4f81-840f-b46dc1a3984d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2656194139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2656194139
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.3056545962
Short name T474
Test name
Test status
Simulation time 172431566 ps
CPU time 5.53 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 242348 kb
Host smart-255f009a-22fd-4583-a05e-fffa4563e460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056545962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.3056545962
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.467093523
Short name T747
Test name
Test status
Simulation time 14259308066 ps
CPU time 219.3 seconds
Started Jul 01 12:52:16 PM PDT 24
Finished Jul 01 12:55:57 PM PDT 24
Peak memory 258192 kb
Host smart-3db0db00-29ad-4c92-ad9f-4af65dfc1389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467093523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.
467093523
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2589536457
Short name T265
Test name
Test status
Simulation time 147615748966 ps
CPU time 2757.11 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 01:38:13 PM PDT 24
Peak memory 416176 kb
Host smart-75fcb77a-c1cf-4353-95ba-f755ed54d529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589536457 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.2589536457
Directory /workspace/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.4129040832
Short name T732
Test name
Test status
Simulation time 227988291 ps
CPU time 7.44 seconds
Started Jul 01 12:52:14 PM PDT 24
Finished Jul 01 12:52:23 PM PDT 24
Peak memory 248012 kb
Host smart-e4c3cd90-801d-4800-90ef-d93397e4cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129040832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.4129040832
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.3248508161
Short name T778
Test name
Test status
Simulation time 141309078 ps
CPU time 4.35 seconds
Started Jul 01 12:55:13 PM PDT 24
Finished Jul 01 12:55:18 PM PDT 24
Peak memory 241800 kb
Host smart-4c8f3638-b3b2-4bb8-bcae-0432e7ac4a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248508161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.3248508161
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3263813905
Short name T976
Test name
Test status
Simulation time 615561148 ps
CPU time 4.23 seconds
Started Jul 01 12:55:11 PM PDT 24
Finished Jul 01 12:55:16 PM PDT 24
Peak memory 242452 kb
Host smart-c22e2cd8-a3f5-4632-ac34-4e632d329744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263813905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3263813905
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.699000622
Short name T786
Test name
Test status
Simulation time 1562664544 ps
CPU time 4.89 seconds
Started Jul 01 12:55:12 PM PDT 24
Finished Jul 01 12:55:18 PM PDT 24
Peak memory 242304 kb
Host smart-18a87576-f159-4b0f-81b7-47b4332aded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699000622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.699000622
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.1262643169
Short name T206
Test name
Test status
Simulation time 125411910 ps
CPU time 4.62 seconds
Started Jul 01 12:55:16 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 241816 kb
Host smart-4f5757d1-7192-45b1-b382-90e9bcc75769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262643169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1262643169
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.452438869
Short name T209
Test name
Test status
Simulation time 146990813 ps
CPU time 4.51 seconds
Started Jul 01 12:55:17 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 242152 kb
Host smart-1b890f63-cb42-4594-98d9-8caebbc01128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452438869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.452438869
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3744919087
Short name T833
Test name
Test status
Simulation time 417415416 ps
CPU time 4.68 seconds
Started Jul 01 12:55:16 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 242120 kb
Host smart-d5888a7e-d3fb-4224-86d6-2b9127d7df97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744919087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3744919087
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.539991936
Short name T622
Test name
Test status
Simulation time 2591868212 ps
CPU time 5.44 seconds
Started Jul 01 12:55:16 PM PDT 24
Finished Jul 01 12:55:23 PM PDT 24
Peak memory 242420 kb
Host smart-04210694-7a03-4a42-b9cb-ff39039029eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539991936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.539991936
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.4208883790
Short name T607
Test name
Test status
Simulation time 132417749 ps
CPU time 4.03 seconds
Started Jul 01 12:55:21 PM PDT 24
Finished Jul 01 12:55:26 PM PDT 24
Peak memory 241968 kb
Host smart-2dd84a68-c2de-4440-81e8-f19b5e20ed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208883790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.4208883790
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.4170977850
Short name T252
Test name
Test status
Simulation time 64600350 ps
CPU time 1.64 seconds
Started Jul 01 12:52:19 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 240544 kb
Host smart-2e28b13a-1665-4999-bd28-54c9a9563870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170977850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.4170977850
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.72495338
Short name T41
Test name
Test status
Simulation time 18868593349 ps
CPU time 55.1 seconds
Started Jul 01 12:52:21 PM PDT 24
Finished Jul 01 12:53:18 PM PDT 24
Peak memory 246368 kb
Host smart-8f5f25f5-a364-4a64-a3ca-14a0ac2b6f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72495338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.72495338
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.1467228622
Short name T1154
Test name
Test status
Simulation time 5489486236 ps
CPU time 24.92 seconds
Started Jul 01 12:52:19 PM PDT 24
Finished Jul 01 12:52:45 PM PDT 24
Peak memory 242444 kb
Host smart-ad0466a5-04f7-47d9-b11e-18a0dea3c275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467228622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1467228622
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.314097896
Short name T1144
Test name
Test status
Simulation time 806809682 ps
CPU time 18.36 seconds
Started Jul 01 12:52:18 PM PDT 24
Finished Jul 01 12:52:37 PM PDT 24
Peak memory 242012 kb
Host smart-a004137d-6c3c-4987-a98b-4e4a16e786ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314097896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.314097896
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.452284385
Short name T121
Test name
Test status
Simulation time 2342104096 ps
CPU time 5.72 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:21 PM PDT 24
Peak memory 242248 kb
Host smart-99d2035c-5419-4b02-8168-4bc72a282edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452284385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.452284385
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.1705143758
Short name T501
Test name
Test status
Simulation time 879496288 ps
CPU time 18.37 seconds
Started Jul 01 12:52:20 PM PDT 24
Finished Jul 01 12:52:39 PM PDT 24
Peak memory 242144 kb
Host smart-cbd78eac-249a-4245-9644-2a6e8d1a90f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705143758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1705143758
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.2754901946
Short name T384
Test name
Test status
Simulation time 514647542 ps
CPU time 5.9 seconds
Started Jul 01 12:52:19 PM PDT 24
Finished Jul 01 12:52:26 PM PDT 24
Peak memory 242284 kb
Host smart-6ee5f880-991e-4208-9896-ccd53b0211d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754901946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2754901946
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.56855180
Short name T1181
Test name
Test status
Simulation time 782020622 ps
CPU time 10.79 seconds
Started Jul 01 12:52:12 PM PDT 24
Finished Jul 01 12:52:25 PM PDT 24
Peak memory 247364 kb
Host smart-55d8b266-8b68-4e81-85ce-e68d14518cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56855180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.56855180
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.4215690304
Short name T986
Test name
Test status
Simulation time 248042058 ps
CPU time 6.79 seconds
Started Jul 01 12:52:13 PM PDT 24
Finished Jul 01 12:52:22 PM PDT 24
Peak memory 242236 kb
Host smart-b1816179-1cc5-4e8c-9948-19110a730606
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215690304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.4215690304
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.1943607634
Short name T959
Test name
Test status
Simulation time 273313045 ps
CPU time 7.49 seconds
Started Jul 01 12:52:23 PM PDT 24
Finished Jul 01 12:52:31 PM PDT 24
Peak memory 242088 kb
Host smart-bf63e847-0500-41c1-945b-a028436a5989
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1943607634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1943607634
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.2160868763
Short name T1046
Test name
Test status
Simulation time 2586073962 ps
CPU time 4.17 seconds
Started Jul 01 12:52:14 PM PDT 24
Finished Jul 01 12:52:20 PM PDT 24
Peak memory 242580 kb
Host smart-890a5b60-9a68-491e-9555-f014fc6d4081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160868763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2160868763
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.149879740
Short name T220
Test name
Test status
Simulation time 12057543312 ps
CPU time 161.73 seconds
Started Jul 01 12:52:19 PM PDT 24
Finished Jul 01 12:55:01 PM PDT 24
Peak memory 248956 kb
Host smart-09008d9c-9ef7-4572-828b-ac985363eb85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149879740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.
149879740
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.3986163150
Short name T481
Test name
Test status
Simulation time 772555276 ps
CPU time 15.89 seconds
Started Jul 01 12:52:22 PM PDT 24
Finished Jul 01 12:52:39 PM PDT 24
Peak memory 242796 kb
Host smart-34108de8-041f-413d-a57d-fbe6a1cec1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986163150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.3986163150
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.1194116853
Short name T163
Test name
Test status
Simulation time 120012243 ps
CPU time 4.05 seconds
Started Jul 01 12:55:19 PM PDT 24
Finished Jul 01 12:55:23 PM PDT 24
Peak memory 242344 kb
Host smart-70690f42-4d65-4f27-a45c-42e978f4f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194116853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1194116853
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.2951300246
Short name T1076
Test name
Test status
Simulation time 1316221628 ps
CPU time 5.17 seconds
Started Jul 01 12:55:17 PM PDT 24
Finished Jul 01 12:55:23 PM PDT 24
Peak memory 242264 kb
Host smart-d2e45353-1d8a-4396-be51-f4e309e5c6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951300246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.2951300246
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.2144054640
Short name T177
Test name
Test status
Simulation time 299350643 ps
CPU time 3.83 seconds
Started Jul 01 12:55:20 PM PDT 24
Finished Jul 01 12:55:24 PM PDT 24
Peak memory 242180 kb
Host smart-28406994-2f7e-4a97-8637-e97e37f25e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144054640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2144054640
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.2180606677
Short name T124
Test name
Test status
Simulation time 302057151 ps
CPU time 3.93 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:28 PM PDT 24
Peak memory 242220 kb
Host smart-0d7dd5bc-fcbd-487b-99ae-675fa253fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180606677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2180606677
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3842943571
Short name T169
Test name
Test status
Simulation time 1625775601 ps
CPU time 4.51 seconds
Started Jul 01 12:55:20 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 242072 kb
Host smart-4361a097-7b1e-4659-aa6e-b7c75a4e6685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842943571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3842943571
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.1892544347
Short name T522
Test name
Test status
Simulation time 506910825 ps
CPU time 4.25 seconds
Started Jul 01 12:55:18 PM PDT 24
Finished Jul 01 12:55:23 PM PDT 24
Peak memory 242136 kb
Host smart-8985e6b3-4d92-4c33-8062-f2abecd9354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892544347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.1892544347
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2152540256
Short name T750
Test name
Test status
Simulation time 1782181475 ps
CPU time 6.01 seconds
Started Jul 01 12:55:18 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 241924 kb
Host smart-ff80ecad-214a-491b-8499-baed8f43a36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152540256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2152540256
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.1481837729
Short name T502
Test name
Test status
Simulation time 157902737 ps
CPU time 4.3 seconds
Started Jul 01 12:55:16 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 242056 kb
Host smart-fadc6d54-f1ee-4eff-829b-90f7bb6d7b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481837729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.1481837729
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.1884541768
Short name T660
Test name
Test status
Simulation time 324271794 ps
CPU time 3.66 seconds
Started Jul 01 12:55:18 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 241928 kb
Host smart-9db7db01-205c-4024-b25b-ee0987a564b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884541768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.1884541768
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.2805152292
Short name T996
Test name
Test status
Simulation time 45562514 ps
CPU time 1.54 seconds
Started Jul 01 12:52:27 PM PDT 24
Finished Jul 01 12:52:29 PM PDT 24
Peak memory 240192 kb
Host smart-0d9d6ed1-db20-4243-98ee-cbc4a79b4eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805152292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.2805152292
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.4180208936
Short name T572
Test name
Test status
Simulation time 816224679 ps
CPU time 21.44 seconds
Started Jul 01 12:52:21 PM PDT 24
Finished Jul 01 12:52:43 PM PDT 24
Peak memory 242148 kb
Host smart-f5f1a27f-f17b-40d8-b44d-126d18afc776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180208936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.4180208936
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.2866092087
Short name T579
Test name
Test status
Simulation time 2256517194 ps
CPU time 19.47 seconds
Started Jul 01 12:52:21 PM PDT 24
Finished Jul 01 12:52:42 PM PDT 24
Peak memory 248804 kb
Host smart-353321d8-feb0-4f37-8836-b4291bf674b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866092087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2866092087
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.2585331111
Short name T965
Test name
Test status
Simulation time 142079250 ps
CPU time 4.3 seconds
Started Jul 01 12:52:21 PM PDT 24
Finished Jul 01 12:52:27 PM PDT 24
Peak memory 242152 kb
Host smart-2d2a7e40-7f67-40f2-8aec-a573f63cd739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585331111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2585331111
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3133902683
Short name T898
Test name
Test status
Simulation time 2724569809 ps
CPU time 18.98 seconds
Started Jul 01 12:52:20 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 245584 kb
Host smart-50f672b3-db9d-4401-9862-c10edca636e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133902683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3133902683
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.2159933687
Short name T268
Test name
Test status
Simulation time 1295676900 ps
CPU time 8.89 seconds
Started Jul 01 12:52:20 PM PDT 24
Finished Jul 01 12:52:30 PM PDT 24
Peak memory 242520 kb
Host smart-1977cecd-eb5c-4263-b764-8cfabfa986ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159933687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.2159933687
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.2861246831
Short name T228
Test name
Test status
Simulation time 105636161 ps
CPU time 4.61 seconds
Started Jul 01 12:52:20 PM PDT 24
Finished Jul 01 12:52:26 PM PDT 24
Peak memory 242000 kb
Host smart-b82d2655-168e-4087-b3d2-138d3fa06925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861246831 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2861246831
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.4131975436
Short name T1016
Test name
Test status
Simulation time 708053059 ps
CPU time 17.91 seconds
Started Jul 01 12:52:20 PM PDT 24
Finished Jul 01 12:52:39 PM PDT 24
Peak memory 248724 kb
Host smart-85626182-ffd5-4ea0-b043-3fea4fd0b4b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4131975436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.4131975436
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3461604723
Short name T339
Test name
Test status
Simulation time 516182789 ps
CPU time 9.21 seconds
Started Jul 01 12:52:19 PM PDT 24
Finished Jul 01 12:52:30 PM PDT 24
Peak memory 242436 kb
Host smart-931079ec-6b2c-4e0b-bfe5-51de7c782920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461604723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3461604723
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.644006471
Short name T880
Test name
Test status
Simulation time 276999320 ps
CPU time 8.14 seconds
Started Jul 01 12:52:22 PM PDT 24
Finished Jul 01 12:52:31 PM PDT 24
Peak memory 242012 kb
Host smart-8584e6a9-063f-4b70-8372-3af9e8cdbf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644006471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.644006471
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.4143852016
Short name T353
Test name
Test status
Simulation time 48870674029 ps
CPU time 174.92 seconds
Started Jul 01 12:52:22 PM PDT 24
Finished Jul 01 12:55:18 PM PDT 24
Peak memory 249568 kb
Host smart-c3881fa5-8655-4745-a62f-57f2d78866c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143852016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.4143852016
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.641777436
Short name T259
Test name
Test status
Simulation time 56305552278 ps
CPU time 1454.92 seconds
Started Jul 01 12:52:23 PM PDT 24
Finished Jul 01 01:16:39 PM PDT 24
Peak memory 446576 kb
Host smart-16d3a09a-5848-4e05-86fd-0d2d2b65caab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641777436 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.641777436
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3254806796
Short name T396
Test name
Test status
Simulation time 1643742178 ps
CPU time 9.39 seconds
Started Jul 01 12:52:21 PM PDT 24
Finished Jul 01 12:52:31 PM PDT 24
Peak memory 242556 kb
Host smart-15c14d20-7f93-4787-be4b-68657b2e44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254806796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3254806796
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.2232310920
Short name T1164
Test name
Test status
Simulation time 214339334 ps
CPU time 4.32 seconds
Started Jul 01 12:55:21 PM PDT 24
Finished Jul 01 12:55:26 PM PDT 24
Peak memory 241752 kb
Host smart-40027122-1eb1-4915-b00a-39089b2c5ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232310920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2232310920
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3917323327
Short name T507
Test name
Test status
Simulation time 169345117 ps
CPU time 3.37 seconds
Started Jul 01 12:55:17 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 242380 kb
Host smart-97983d8b-7ada-4c8a-aa96-32515599f086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917323327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3917323327
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.1468843473
Short name T784
Test name
Test status
Simulation time 356990311 ps
CPU time 3.43 seconds
Started Jul 01 12:55:18 PM PDT 24
Finished Jul 01 12:55:22 PM PDT 24
Peak memory 242344 kb
Host smart-3a0030f1-6aa4-4fe1-8b9f-777bab87c206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468843473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.1468843473
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.2543717117
Short name T1124
Test name
Test status
Simulation time 247545070 ps
CPU time 3.72 seconds
Started Jul 01 12:55:17 PM PDT 24
Finished Jul 01 12:55:21 PM PDT 24
Peak memory 242076 kb
Host smart-429a9287-6dc0-4b1a-88e6-a151757af5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543717117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2543717117
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.2158221600
Short name T1075
Test name
Test status
Simulation time 119525628 ps
CPU time 4.69 seconds
Started Jul 01 12:55:20 PM PDT 24
Finished Jul 01 12:55:26 PM PDT 24
Peak memory 242072 kb
Host smart-8a5eef0c-b8fe-4463-a83a-d127526f2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158221600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2158221600
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.2340583227
Short name T969
Test name
Test status
Simulation time 102883380 ps
CPU time 3.44 seconds
Started Jul 01 12:55:24 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242148 kb
Host smart-a1b8c6f8-b16b-4380-af03-5ecb354b980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340583227 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.2340583227
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2217739688
Short name T493
Test name
Test status
Simulation time 139911345 ps
CPU time 3.88 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:28 PM PDT 24
Peak memory 241732 kb
Host smart-b06a1fc3-631a-4b0d-8779-53b54a65ac8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217739688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2217739688
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.1231715721
Short name T1060
Test name
Test status
Simulation time 104178652 ps
CPU time 3.4 seconds
Started Jul 01 12:55:20 PM PDT 24
Finished Jul 01 12:55:24 PM PDT 24
Peak memory 241776 kb
Host smart-ef1768d6-8563-4e98-9a7e-5020e379aee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231715721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.1231715721
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3999764864
Short name T546
Test name
Test status
Simulation time 116227955 ps
CPU time 4.54 seconds
Started Jul 01 12:55:20 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 242108 kb
Host smart-4092e0df-956d-4e7c-af5e-285e26b8bc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999764864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3999764864
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.4001362555
Short name T999
Test name
Test status
Simulation time 348972575 ps
CPU time 4.86 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242392 kb
Host smart-0d9d6ed7-8ae1-47f3-8f42-d6a89f45863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001362555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4001362555
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.102292732
Short name T480
Test name
Test status
Simulation time 83782172 ps
CPU time 1.67 seconds
Started Jul 01 12:52:27 PM PDT 24
Finished Jul 01 12:52:29 PM PDT 24
Peak memory 240244 kb
Host smart-87ef8db4-ecc8-479f-be9e-082d64950dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102292732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.102292732
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.299835522
Short name T45
Test name
Test status
Simulation time 2988782571 ps
CPU time 18.87 seconds
Started Jul 01 12:52:25 PM PDT 24
Finished Jul 01 12:52:45 PM PDT 24
Peak memory 242884 kb
Host smart-eeab0bed-b8e7-4402-99b5-d8b1845505be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299835522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.299835522
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.3518236553
Short name T320
Test name
Test status
Simulation time 1076483068 ps
CPU time 29.3 seconds
Started Jul 01 12:52:24 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 242292 kb
Host smart-ddd57fb7-48f6-4edd-b0b6-e320327a9f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518236553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.3518236553
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.2704491677
Short name T92
Test name
Test status
Simulation time 1570216896 ps
CPU time 35.43 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:53:05 PM PDT 24
Peak memory 242468 kb
Host smart-9f26818e-55dd-46ca-a65a-c9737703cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704491677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2704491677
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.2066159797
Short name T719
Test name
Test status
Simulation time 2027785182 ps
CPU time 4.96 seconds
Started Jul 01 12:52:27 PM PDT 24
Finished Jul 01 12:52:33 PM PDT 24
Peak memory 242080 kb
Host smart-33b9acc6-6d28-4e83-a153-1b8024101d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066159797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2066159797
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.2196024491
Short name T464
Test name
Test status
Simulation time 5078459002 ps
CPU time 73.14 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 248988 kb
Host smart-fbe27364-55f1-4ceb-8c3a-1d8e680f35ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196024491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2196024491
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.3268165066
Short name T647
Test name
Test status
Simulation time 468472565 ps
CPU time 21.06 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 242620 kb
Host smart-406f1244-6be5-4f71-94c3-eee9ed566c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268165066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.3268165066
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.3336382461
Short name T135
Test name
Test status
Simulation time 2628136881 ps
CPU time 5.41 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:35 PM PDT 24
Peak memory 242032 kb
Host smart-d26a256f-d64a-48ca-9511-46b105895c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336382461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3336382461
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2490571136
Short name T1135
Test name
Test status
Simulation time 472976160 ps
CPU time 7.76 seconds
Started Jul 01 12:52:23 PM PDT 24
Finished Jul 01 12:52:32 PM PDT 24
Peak memory 248784 kb
Host smart-f97df985-8b08-4bb6-9772-6d212fa8927c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490571136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2490571136
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.3258930457
Short name T382
Test name
Test status
Simulation time 317997891 ps
CPU time 4.81 seconds
Started Jul 01 12:52:25 PM PDT 24
Finished Jul 01 12:52:31 PM PDT 24
Peak memory 242444 kb
Host smart-40e44703-93a0-49ef-9608-a5d52422b387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258930457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3258930457
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.53844535
Short name T685
Test name
Test status
Simulation time 9283072780 ps
CPU time 18.72 seconds
Started Jul 01 12:52:23 PM PDT 24
Finished Jul 01 12:52:43 PM PDT 24
Peak memory 242048 kb
Host smart-2a0b92f9-5574-4db0-923c-c491e474dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53844535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.53844535
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.3658806588
Short name T1148
Test name
Test status
Simulation time 41933404899 ps
CPU time 195.96 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:55:47 PM PDT 24
Peak memory 257060 kb
Host smart-9fa28f85-768a-4cc8-bd1c-87c427a6c61d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658806588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.3658806588
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.2799541615
Short name T549
Test name
Test status
Simulation time 246940818230 ps
CPU time 1452.16 seconds
Started Jul 01 12:52:30 PM PDT 24
Finished Jul 01 01:16:43 PM PDT 24
Peak memory 357968 kb
Host smart-90ac1756-0c47-48a4-803c-c234ae24a12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799541615 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.2799541615
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.3601832729
Short name T991
Test name
Test status
Simulation time 1255449887 ps
CPU time 11.36 seconds
Started Jul 01 12:52:24 PM PDT 24
Finished Jul 01 12:52:36 PM PDT 24
Peak memory 248760 kb
Host smart-57d9d6cd-2682-4ff0-95c9-e36beaa0c011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601832729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.3601832729
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3094922537
Short name T1190
Test name
Test status
Simulation time 110217733 ps
CPU time 4.22 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:35 PM PDT 24
Peak memory 241752 kb
Host smart-27137398-4b4f-4508-9de0-ce0b4ebf56a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094922537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3094922537
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.1242044771
Short name T181
Test name
Test status
Simulation time 2313268538 ps
CPU time 5.1 seconds
Started Jul 01 12:55:22 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242460 kb
Host smart-b932978f-3811-4924-9599-7d287240db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242044771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1242044771
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.2449165272
Short name T875
Test name
Test status
Simulation time 2265772947 ps
CPU time 6.15 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:35 PM PDT 24
Peak memory 242148 kb
Host smart-a6a2bcb4-9783-4cc6-9a31-1a6e92368a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449165272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2449165272
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1015420609
Short name T876
Test name
Test status
Simulation time 279573923 ps
CPU time 3.72 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242076 kb
Host smart-c3eb7a79-8e8f-4e05-909b-c2a98af3d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015420609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1015420609
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.869968200
Short name T1004
Test name
Test status
Simulation time 210351521 ps
CPU time 3.98 seconds
Started Jul 01 12:55:24 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 241928 kb
Host smart-563b9fd0-f867-4977-90f7-5587662a7765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869968200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.869968200
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1523547572
Short name T861
Test name
Test status
Simulation time 532981439 ps
CPU time 4.42 seconds
Started Jul 01 12:55:22 PM PDT 24
Finished Jul 01 12:55:28 PM PDT 24
Peak memory 242152 kb
Host smart-ff2caccb-c135-4b8e-abd0-f85f35d47a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523547572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1523547572
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.1340881137
Short name T674
Test name
Test status
Simulation time 355529614 ps
CPU time 3.71 seconds
Started Jul 01 12:55:22 PM PDT 24
Finished Jul 01 12:55:27 PM PDT 24
Peak memory 241900 kb
Host smart-cd49f040-d1f6-446f-8420-3f8ec4ddc3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340881137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1340881137
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.113753756
Short name T914
Test name
Test status
Simulation time 132538937 ps
CPU time 3.71 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 241932 kb
Host smart-9fabd2a5-889d-4375-bd0a-5fefc69250ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113753756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.113753756
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.3043999571
Short name T455
Test name
Test status
Simulation time 277340727 ps
CPU time 4.6 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 242068 kb
Host smart-1e5d8acb-ee16-445d-989c-394c14685e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043999571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3043999571
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.3642690892
Short name T682
Test name
Test status
Simulation time 308931622 ps
CPU time 3.92 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242316 kb
Host smart-ac584e2e-7fef-4427-b0e5-e44785fde0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642690892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.3642690892
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.738974794
Short name T936
Test name
Test status
Simulation time 68470934 ps
CPU time 1.91 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:52:33 PM PDT 24
Peak memory 240500 kb
Host smart-6bf4fc90-f13c-4f9e-8d0f-4b74e4ea40d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738974794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.738974794
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.2647918437
Short name T115
Test name
Test status
Simulation time 1480964489 ps
CPU time 23.16 seconds
Started Jul 01 12:52:26 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 242444 kb
Host smart-6c4d2d9e-c62f-4596-8e22-f8b57d4e6f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647918437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2647918437
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.2343039045
Short name T1179
Test name
Test status
Simulation time 307831505 ps
CPU time 17.17 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:47 PM PDT 24
Peak memory 241936 kb
Host smart-164e8e3e-4845-4f1f-8ba2-67519716088b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343039045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.2343039045
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.4289596883
Short name T1147
Test name
Test status
Simulation time 2647378157 ps
CPU time 20.49 seconds
Started Jul 01 12:52:24 PM PDT 24
Finished Jul 01 12:52:46 PM PDT 24
Peak memory 242640 kb
Host smart-a490d81a-cc11-469c-9138-8d2666e77210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289596883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.4289596883
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.3525745543
Short name T1026
Test name
Test status
Simulation time 411668794 ps
CPU time 3.5 seconds
Started Jul 01 12:52:25 PM PDT 24
Finished Jul 01 12:52:30 PM PDT 24
Peak memory 242404 kb
Host smart-81dd6e20-da39-4dde-8819-9c84f7c8b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525745543 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3525745543
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.1912877445
Short name T88
Test name
Test status
Simulation time 700011647 ps
CPU time 14.32 seconds
Started Jul 01 12:52:26 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 248768 kb
Host smart-616d73d6-8a15-4937-a1d3-dae00119bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912877445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1912877445
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.3267314806
Short name T491
Test name
Test status
Simulation time 10793266608 ps
CPU time 31.03 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 243568 kb
Host smart-4526e568-324b-4f35-81fd-f6845d676864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267314806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3267314806
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.579766030
Short name T895
Test name
Test status
Simulation time 178751186 ps
CPU time 5.13 seconds
Started Jul 01 12:52:24 PM PDT 24
Finished Jul 01 12:52:30 PM PDT 24
Peak memory 241732 kb
Host smart-15099536-7569-4c4c-a705-71d32f1e6e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579766030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.579766030
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.4133728695
Short name T667
Test name
Test status
Simulation time 2661520744 ps
CPU time 22.51 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:52 PM PDT 24
Peak memory 242584 kb
Host smart-4afb3114-afe7-43d0-a51a-ae4066aa8425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133728695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.4133728695
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.1165270435
Short name T424
Test name
Test status
Simulation time 461899759 ps
CPU time 3.63 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:52:34 PM PDT 24
Peak memory 242172 kb
Host smart-1e03499c-aaac-4e87-83ae-1b4f9d78c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165270435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1165270435
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2585704200
Short name T1189
Test name
Test status
Simulation time 199038029145 ps
CPU time 782.11 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 01:05:32 PM PDT 24
Peak memory 257156 kb
Host smart-e3c68496-7d23-439b-af63-6e21184722b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585704200 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.2585704200
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.738179111
Short name T988
Test name
Test status
Simulation time 1264671330 ps
CPU time 13.06 seconds
Started Jul 01 12:52:30 PM PDT 24
Finished Jul 01 12:52:44 PM PDT 24
Peak memory 242320 kb
Host smart-6342abae-93a1-4783-9763-269e5ffff778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738179111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.738179111
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.3871665132
Short name T555
Test name
Test status
Simulation time 151056817 ps
CPU time 4.2 seconds
Started Jul 01 12:55:26 PM PDT 24
Finished Jul 01 12:55:32 PM PDT 24
Peak memory 242088 kb
Host smart-44340936-967b-4db0-b1e4-b7df6cd57d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871665132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3871665132
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.3274277730
Short name T760
Test name
Test status
Simulation time 2340522833 ps
CPU time 6.42 seconds
Started Jul 01 12:55:25 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242504 kb
Host smart-241957b8-42d4-4506-bd2f-1a5444b12e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274277730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.3274277730
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3904220752
Short name T537
Test name
Test status
Simulation time 111273863 ps
CPU time 4.12 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242140 kb
Host smart-cb23c129-90b0-46b0-b6ff-d80745c9b33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904220752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3904220752
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.3650228689
Short name T538
Test name
Test status
Simulation time 2127994298 ps
CPU time 6.05 seconds
Started Jul 01 12:55:26 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242076 kb
Host smart-3c0cbc11-c6a5-48be-8e90-9dc72d77513d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650228689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3650228689
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.4140035121
Short name T118
Test name
Test status
Simulation time 210308610 ps
CPU time 3.87 seconds
Started Jul 01 12:55:24 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 241996 kb
Host smart-ae949d02-e842-43cd-a8db-f1f871883ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140035121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.4140035121
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.1966275489
Short name T951
Test name
Test status
Simulation time 328295511 ps
CPU time 5.3 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242484 kb
Host smart-18967b4f-2c3a-4326-b7d1-479fd3c45881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966275489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.1966275489
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.3819168092
Short name T411
Test name
Test status
Simulation time 539931897 ps
CPU time 4.84 seconds
Started Jul 01 12:55:25 PM PDT 24
Finished Jul 01 12:55:32 PM PDT 24
Peak memory 241888 kb
Host smart-dd3afffc-2869-4fc5-8d3b-275196ba166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819168092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.3819168092
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.916569802
Short name T966
Test name
Test status
Simulation time 140033842 ps
CPU time 3.4 seconds
Started Jul 01 12:55:21 PM PDT 24
Finished Jul 01 12:55:25 PM PDT 24
Peak memory 242236 kb
Host smart-86ff0d5c-3f87-4e96-9a24-5a8c33b082c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916569802 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.916569802
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.3555469213
Short name T178
Test name
Test status
Simulation time 314022917 ps
CPU time 5.05 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 241912 kb
Host smart-cd8bd3a7-0f6a-4489-95fd-31b9d517778b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555469213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.3555469213
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2186769280
Short name T691
Test name
Test status
Simulation time 520898102 ps
CPU time 4.21 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242076 kb
Host smart-524e5904-cabd-4f9c-9677-b6cf0dbc859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186769280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2186769280
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.3087765166
Short name T98
Test name
Test status
Simulation time 99954361 ps
CPU time 1.86 seconds
Started Jul 01 12:52:35 PM PDT 24
Finished Jul 01 12:52:37 PM PDT 24
Peak memory 240148 kb
Host smart-d02e3ad0-b550-410e-95f2-ad53966511fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087765166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3087765166
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.3022372737
Short name T63
Test name
Test status
Simulation time 10815117767 ps
CPU time 19.56 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 242696 kb
Host smart-79fc1a4c-8b70-4712-8738-91ab7b973051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022372737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.3022372737
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.3370561475
Short name T1
Test name
Test status
Simulation time 668469622 ps
CPU time 18.33 seconds
Started Jul 01 12:52:31 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 242072 kb
Host smart-ea2062cb-fde6-4c6c-87f0-ea2f83516425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370561475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3370561475
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.4237873599
Short name T395
Test name
Test status
Simulation time 2161473690 ps
CPU time 13.07 seconds
Started Jul 01 12:52:30 PM PDT 24
Finished Jul 01 12:52:44 PM PDT 24
Peak memory 242532 kb
Host smart-50e298a5-f76f-4170-90d9-7ce2404ee32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237873599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.4237873599
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.556533062
Short name T1077
Test name
Test status
Simulation time 151211830 ps
CPU time 3.82 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:33 PM PDT 24
Peak memory 242392 kb
Host smart-044e36fc-5826-4f4d-bab8-212763ce43f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556533062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.556533062
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.4192077629
Short name T207
Test name
Test status
Simulation time 14362824853 ps
CPU time 33.42 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:53:04 PM PDT 24
Peak memory 245888 kb
Host smart-2f5390be-b31c-47fb-99f9-ad43a3ae8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192077629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.4192077629
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.3490338790
Short name T369
Test name
Test status
Simulation time 626017120 ps
CPU time 22.43 seconds
Started Jul 01 12:52:28 PM PDT 24
Finished Jul 01 12:52:51 PM PDT 24
Peak memory 248744 kb
Host smart-ad39e7b9-0591-4b03-95ae-6cd5c8cfaa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490338790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3490338790
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.312264799
Short name T697
Test name
Test status
Simulation time 144969001 ps
CPU time 4.27 seconds
Started Jul 01 12:52:30 PM PDT 24
Finished Jul 01 12:52:35 PM PDT 24
Peak memory 241984 kb
Host smart-a580913e-77d9-4a34-9b14-8d966d202100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312264799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.312264799
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2505735475
Short name T930
Test name
Test status
Simulation time 934228001 ps
CPU time 24.36 seconds
Started Jul 01 12:52:29 PM PDT 24
Finished Jul 01 12:52:55 PM PDT 24
Peak memory 248644 kb
Host smart-de9dd0db-0703-467a-875e-de0cb1edad48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2505735475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2505735475
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.3175422042
Short name T871
Test name
Test status
Simulation time 925418592 ps
CPU time 8.59 seconds
Started Jul 01 12:52:36 PM PDT 24
Finished Jul 01 12:52:45 PM PDT 24
Peak memory 242096 kb
Host smart-30efb80c-b58b-433e-89f1-be70c0b6ecd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3175422042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.3175422042
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.4053392173
Short name T597
Test name
Test status
Simulation time 3671721285 ps
CPU time 10.83 seconds
Started Jul 01 12:52:30 PM PDT 24
Finished Jul 01 12:52:42 PM PDT 24
Peak memory 241916 kb
Host smart-9200b1d9-cd07-4c94-96a9-96d7623eb6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053392173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.4053392173
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.713323169
Short name T71
Test name
Test status
Simulation time 20733363453 ps
CPU time 132.54 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 248724 kb
Host smart-a716a209-a79d-4114-aa64-00ba607409f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713323169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
713323169
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1088070593
Short name T165
Test name
Test status
Simulation time 181270248330 ps
CPU time 1084.83 seconds
Started Jul 01 12:52:36 PM PDT 24
Finished Jul 01 01:10:42 PM PDT 24
Peak memory 314320 kb
Host smart-c6570cb5-fc0f-4359-9f2a-a05e2e8eb2b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088070593 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1088070593
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.2915423004
Short name T1161
Test name
Test status
Simulation time 1180395807 ps
CPU time 14.77 seconds
Started Jul 01 12:52:33 PM PDT 24
Finished Jul 01 12:52:48 PM PDT 24
Peak memory 242696 kb
Host smart-c84c0e01-96d2-418c-a716-4c6628717b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915423004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.2915423004
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.1248736422
Short name T547
Test name
Test status
Simulation time 188707268 ps
CPU time 3.64 seconds
Started Jul 01 12:55:24 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 242052 kb
Host smart-415adfcc-f19c-4ebb-9f43-bd43236eeefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248736422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.1248736422
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.2367936208
Short name T110
Test name
Test status
Simulation time 2134276472 ps
CPU time 5.83 seconds
Started Jul 01 12:55:25 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 241720 kb
Host smart-06067e3d-c083-4d39-aae7-08537c3a4a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367936208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.2367936208
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1188117458
Short name T803
Test name
Test status
Simulation time 306238874 ps
CPU time 4.83 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:36 PM PDT 24
Peak memory 242004 kb
Host smart-0c95a817-5464-4fd9-9b0e-8d705885ba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188117458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1188117458
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2009162960
Short name T960
Test name
Test status
Simulation time 125394973 ps
CPU time 3.86 seconds
Started Jul 01 12:55:23 PM PDT 24
Finished Jul 01 12:55:29 PM PDT 24
Peak memory 242592 kb
Host smart-44c0af24-9482-4d39-9a6a-79bc68a76f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009162960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2009162960
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.646354928
Short name T831
Test name
Test status
Simulation time 2090555233 ps
CPU time 3.93 seconds
Started Jul 01 12:55:24 PM PDT 24
Finished Jul 01 12:55:30 PM PDT 24
Peak memory 241920 kb
Host smart-4a08ca39-227c-416b-bba4-1da62b517120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646354928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.646354928
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.3763378991
Short name T806
Test name
Test status
Simulation time 122821474 ps
CPU time 4.64 seconds
Started Jul 01 12:55:25 PM PDT 24
Finished Jul 01 12:55:32 PM PDT 24
Peak memory 242180 kb
Host smart-ffb55128-b2be-4dc4-aa89-179c18785fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763378991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3763378991
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.546769706
Short name T609
Test name
Test status
Simulation time 688317806 ps
CPU time 5.02 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 241828 kb
Host smart-c6dded64-bcd0-4bf4-9bde-9c575921cbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546769706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.546769706
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.408709191
Short name T1192
Test name
Test status
Simulation time 218660482 ps
CPU time 3.58 seconds
Started Jul 01 12:55:31 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 241936 kb
Host smart-8379c680-e717-479f-9161-a793bb1f497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408709191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.408709191
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1439542632
Short name T1072
Test name
Test status
Simulation time 117836705 ps
CPU time 3.94 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242380 kb
Host smart-f2f0d1ec-db77-4d6e-b19b-7a6c398a6486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439542632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1439542632
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.600745788
Short name T387
Test name
Test status
Simulation time 154186435 ps
CPU time 1.71 seconds
Started Jul 01 12:52:38 PM PDT 24
Finished Jul 01 12:52:42 PM PDT 24
Peak memory 240088 kb
Host smart-113f30ee-9354-4d27-ad36-7b981f3f9b27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600745788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.600745788
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.204763876
Short name T64
Test name
Test status
Simulation time 163254953 ps
CPU time 5.4 seconds
Started Jul 01 12:52:35 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 242180 kb
Host smart-6be046eb-d005-4403-856b-9618b415a5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204763876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.204763876
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.1416410920
Short name T1057
Test name
Test status
Simulation time 7650268928 ps
CPU time 21.55 seconds
Started Jul 01 12:52:38 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 242204 kb
Host smart-42729025-88e2-4d69-aa71-52098675f7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416410920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1416410920
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.2014367199
Short name T952
Test name
Test status
Simulation time 1188035489 ps
CPU time 22.85 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 248784 kb
Host smart-58a2a349-7f58-48d0-a216-ab6f50367b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014367199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2014367199
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.1621872273
Short name T201
Test name
Test status
Simulation time 458981479 ps
CPU time 3.31 seconds
Started Jul 01 12:52:33 PM PDT 24
Finished Jul 01 12:52:37 PM PDT 24
Peak memory 242264 kb
Host smart-c9903518-3949-4232-9d8a-6503d5cdb6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621872273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1621872273
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2703952282
Short name T435
Test name
Test status
Simulation time 10162634258 ps
CPU time 18.09 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:52:53 PM PDT 24
Peak memory 245972 kb
Host smart-63af0e97-b3a6-4996-bed9-4fad36d7f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703952282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2703952282
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.833153719
Short name T721
Test name
Test status
Simulation time 5751552020 ps
CPU time 44.2 seconds
Started Jul 01 12:52:38 PM PDT 24
Finished Jul 01 12:53:23 PM PDT 24
Peak memory 242244 kb
Host smart-70e7a756-8b41-430d-8a72-4d2009b7b4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833153719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.833153719
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2639278854
Short name T883
Test name
Test status
Simulation time 9495432948 ps
CPU time 17.18 seconds
Started Jul 01 12:52:33 PM PDT 24
Finished Jul 01 12:52:51 PM PDT 24
Peak memory 242380 kb
Host smart-0aa3adeb-4e25-4459-941a-79aeed513108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639278854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2639278854
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.2043832015
Short name T1058
Test name
Test status
Simulation time 556526162 ps
CPU time 5.85 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:52:41 PM PDT 24
Peak memory 242124 kb
Host smart-edc9a89a-ba04-457e-985f-8156f5cd4825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043832015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2043832015
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.2826590099
Short name T372
Test name
Test status
Simulation time 408890842 ps
CPU time 9.08 seconds
Started Jul 01 12:52:38 PM PDT 24
Finished Jul 01 12:52:48 PM PDT 24
Peak memory 242356 kb
Host smart-1b6a3482-91ff-4522-b082-262520182d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826590099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.2826590099
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2198931528
Short name T485
Test name
Test status
Simulation time 37337778725 ps
CPU time 146.6 seconds
Started Jul 01 12:52:35 PM PDT 24
Finished Jul 01 12:55:02 PM PDT 24
Peak memory 259116 kb
Host smart-f5cc2c12-64c0-4606-a8ec-760a3bee389a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198931528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2198931528
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.470984633
Short name T639
Test name
Test status
Simulation time 98170334152 ps
CPU time 589.66 seconds
Started Jul 01 12:52:33 PM PDT 24
Finished Jul 01 01:02:23 PM PDT 24
Peak memory 268492 kb
Host smart-5a92ab01-ba4d-4e43-a472-6eaebcf86011
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470984633 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.470984633
Directory /workspace/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.640330136
Short name T584
Test name
Test status
Simulation time 591177370 ps
CPU time 9.86 seconds
Started Jul 01 12:52:35 PM PDT 24
Finished Jul 01 12:52:46 PM PDT 24
Peak memory 242176 kb
Host smart-07f25f2f-2802-468d-b4c6-2a818e0bb245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640330136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.640330136
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2645035452
Short name T432
Test name
Test status
Simulation time 174206641 ps
CPU time 3.44 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242100 kb
Host smart-bec11d9e-3c01-4b06-a848-3c24d85fe040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645035452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2645035452
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.3347274875
Short name T896
Test name
Test status
Simulation time 98151605 ps
CPU time 3.5 seconds
Started Jul 01 12:55:31 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 241928 kb
Host smart-ffa44a82-9cc5-4e98-b5a4-958f38d8aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347274875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3347274875
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.1904440513
Short name T185
Test name
Test status
Simulation time 262440716 ps
CPU time 4.88 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242404 kb
Host smart-a8c3aea7-e9b5-4efb-8053-61ab705a88f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904440513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1904440513
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.2893971848
Short name T518
Test name
Test status
Simulation time 2313592598 ps
CPU time 4.88 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242324 kb
Host smart-234601dd-a110-4907-9f91-43afa31ebfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893971848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2893971848
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1286281847
Short name T1022
Test name
Test status
Simulation time 177178204 ps
CPU time 4.87 seconds
Started Jul 01 12:55:26 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242364 kb
Host smart-5712dddf-3782-43fe-82b7-6869151a4b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286281847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1286281847
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.3928688517
Short name T463
Test name
Test status
Simulation time 189064452 ps
CPU time 4.51 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:34 PM PDT 24
Peak memory 242008 kb
Host smart-71cd9c30-ed5a-42b0-904d-37a5d0208c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928688517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.3928688517
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.316291508
Short name T1175
Test name
Test status
Simulation time 1691504179 ps
CPU time 3.79 seconds
Started Jul 01 12:55:31 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242072 kb
Host smart-f575cf45-57fb-402b-8e5a-63b4bf313770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316291508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.316291508
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.2236899450
Short name T76
Test name
Test status
Simulation time 223714519 ps
CPU time 3.42 seconds
Started Jul 01 12:55:28 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242156 kb
Host smart-0190fd89-fbe4-44aa-8047-f5d9df806053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236899450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2236899450
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.2522806501
Short name T304
Test name
Test status
Simulation time 285447024 ps
CPU time 2.04 seconds
Started Jul 01 12:52:40 PM PDT 24
Finished Jul 01 12:52:43 PM PDT 24
Peak memory 240444 kb
Host smart-8fa0c6d7-d825-4d89-976c-ad57598a5297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522806501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.2522806501
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.2836728817
Short name T1062
Test name
Test status
Simulation time 449050599 ps
CPU time 22.32 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:53:09 PM PDT 24
Peak memory 241960 kb
Host smart-66fda504-b603-4ecd-b7a4-86617684943c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836728817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.2836728817
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.3526218916
Short name T804
Test name
Test status
Simulation time 536756926 ps
CPU time 6.23 seconds
Started Jul 01 12:52:42 PM PDT 24
Finished Jul 01 12:52:51 PM PDT 24
Peak memory 242028 kb
Host smart-04065402-16ab-487e-93d6-22040aa7fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526218916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.3526218916
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.25973642
Short name T813
Test name
Test status
Simulation time 498621211 ps
CPU time 5.24 seconds
Started Jul 01 12:52:34 PM PDT 24
Finished Jul 01 12:52:40 PM PDT 24
Peak memory 242184 kb
Host smart-c6429b44-12b1-4a5a-9658-d4cf2f060e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25973642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.25973642
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.3885010799
Short name T495
Test name
Test status
Simulation time 3309484286 ps
CPU time 37.94 seconds
Started Jul 01 12:52:40 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 246952 kb
Host smart-df5f3df4-3abd-4fd2-b39a-b94a410bc185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885010799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3885010799
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1685104348
Short name T517
Test name
Test status
Simulation time 1302017787 ps
CPU time 27.73 seconds
Started Jul 01 12:52:40 PM PDT 24
Finished Jul 01 12:53:09 PM PDT 24
Peak memory 242228 kb
Host smart-48f0f762-626c-4401-bc57-64bc6e4ffee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685104348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1685104348
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.4102513369
Short name T359
Test name
Test status
Simulation time 2809805245 ps
CPU time 20.87 seconds
Started Jul 01 12:52:39 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 248788 kb
Host smart-0f53b8da-00f8-4358-804f-2367c2859bf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4102513369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.4102513369
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2397897330
Short name T869
Test name
Test status
Simulation time 539400887 ps
CPU time 4.91 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:52:49 PM PDT 24
Peak memory 242184 kb
Host smart-dc9edcc5-7a06-4ce8-b20a-ed8e0198f8b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2397897330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2397897330
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.1195074812
Short name T736
Test name
Test status
Simulation time 10790153387 ps
CPU time 25.57 seconds
Started Jul 01 12:52:36 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 242116 kb
Host smart-b53749c3-12d6-4d06-8d40-9d26c906944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195074812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1195074812
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.4025728693
Short name T323
Test name
Test status
Simulation time 4551167229 ps
CPU time 63.26 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:53:50 PM PDT 24
Peak memory 248864 kb
Host smart-be367fd4-38e0-4489-9be1-f3ac1695cabe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025728693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all
.4025728693
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.3969915487
Short name T223
Test name
Test status
Simulation time 1731675318225 ps
CPU time 3306.81 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 01:47:51 PM PDT 24
Peak memory 370260 kb
Host smart-d9492a69-be7f-44a1-b877-c792427b747c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969915487 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3969915487
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.2434766689
Short name T990
Test name
Test status
Simulation time 3120776284 ps
CPU time 23.58 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:53:07 PM PDT 24
Peak memory 242468 kb
Host smart-750b492e-c30f-4d69-b486-60c98c330b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434766689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.2434766689
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.3065442023
Short name T897
Test name
Test status
Simulation time 179009316 ps
CPU time 4.34 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 242472 kb
Host smart-c490a4b2-16d6-47e5-826b-3f6166057a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065442023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.3065442023
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.165220496
Short name T624
Test name
Test status
Simulation time 302659044 ps
CPU time 4.76 seconds
Started Jul 01 12:55:26 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 241848 kb
Host smart-1155302b-6abd-452e-b963-a78c82c891df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165220496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.165220496
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.244917478
Short name T955
Test name
Test status
Simulation time 218801540 ps
CPU time 3.65 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:35 PM PDT 24
Peak memory 242040 kb
Host smart-eba6a25b-027c-4fe2-b3a7-94f23c08250b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244917478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.244917478
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.484949748
Short name T738
Test name
Test status
Simulation time 233474099 ps
CPU time 3.79 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 241836 kb
Host smart-f50f7bf9-6aee-4f5e-9c3d-994d4afd97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484949748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.484949748
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.900137579
Short name T24
Test name
Test status
Simulation time 1904845761 ps
CPU time 4.79 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242072 kb
Host smart-b370bb0a-a71f-4516-bcd4-aba300aab6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900137579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.900137579
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1718870677
Short name T1068
Test name
Test status
Simulation time 299178394 ps
CPU time 3.39 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:48 PM PDT 24
Peak memory 242028 kb
Host smart-48cedb94-f1ea-4ac3-b882-a7f9e3889b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718870677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1718870677
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3180817218
Short name T1191
Test name
Test status
Simulation time 721733249 ps
CPU time 5.02 seconds
Started Jul 01 12:55:32 PM PDT 24
Finished Jul 01 12:55:52 PM PDT 24
Peak memory 242412 kb
Host smart-cdee9678-30c9-45dd-90e2-58abb2ea49ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180817218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3180817218
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.642951806
Short name T182
Test name
Test status
Simulation time 402571131 ps
CPU time 4.19 seconds
Started Jul 01 12:55:31 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 241840 kb
Host smart-5c8226a0-1166-4501-a1a0-0329ae039f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642951806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.642951806
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.731464405
Short name T1003
Test name
Test status
Simulation time 104580360 ps
CPU time 4.03 seconds
Started Jul 01 12:55:27 PM PDT 24
Finished Jul 01 12:55:33 PM PDT 24
Peak memory 241936 kb
Host smart-0f52ad1c-b3c5-4058-a1e3-cff6f9de7c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731464405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.731464405
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.1016567595
Short name T107
Test name
Test status
Simulation time 449416901 ps
CPU time 4.36 seconds
Started Jul 01 12:55:31 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 241976 kb
Host smart-efc348f9-3680-44da-b5ef-e2030200a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016567595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1016567595
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.2137200083
Short name T696
Test name
Test status
Simulation time 104585821 ps
CPU time 2.36 seconds
Started Jul 01 12:52:42 PM PDT 24
Finished Jul 01 12:52:46 PM PDT 24
Peak memory 240312 kb
Host smart-10c3ca6d-2243-4a8f-8b13-eefa758c4be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137200083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.2137200083
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.2571549378
Short name T944
Test name
Test status
Simulation time 4959365394 ps
CPU time 10.45 seconds
Started Jul 01 12:52:39 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 244672 kb
Host smart-7772361d-5997-42d0-a3c2-c2af2cab2c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571549378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2571549378
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.1936478330
Short name T821
Test name
Test status
Simulation time 439048552 ps
CPU time 9.78 seconds
Started Jul 01 12:52:42 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 241892 kb
Host smart-88eae67f-2eba-40ed-a111-abbbbbe69d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936478330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1936478330
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.3576081481
Short name T781
Test name
Test status
Simulation time 8196884579 ps
CPU time 37.35 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 242444 kb
Host smart-2b020fe1-5baa-4603-8ca8-c6f072d65b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576081481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3576081481
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.3203169262
Short name T1081
Test name
Test status
Simulation time 235973064 ps
CPU time 3.56 seconds
Started Jul 01 12:52:40 PM PDT 24
Finished Jul 01 12:52:46 PM PDT 24
Peak memory 242012 kb
Host smart-1942e641-759d-4086-ad3a-b70bbecfb735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203169262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3203169262
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.3417808449
Short name T324
Test name
Test status
Simulation time 99108984 ps
CPU time 3.18 seconds
Started Jul 01 12:52:40 PM PDT 24
Finished Jul 01 12:52:44 PM PDT 24
Peak memory 248648 kb
Host smart-97965775-2689-49b2-b84b-7e2123a86c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417808449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.3417808449
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.1456853505
Short name T593
Test name
Test status
Simulation time 780852570 ps
CPU time 11.37 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:52:55 PM PDT 24
Peak memory 242456 kb
Host smart-ebe053e6-4a87-40da-ba06-7a3948df80b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456853505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.1456853505
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.2749316742
Short name T1038
Test name
Test status
Simulation time 197082560 ps
CPU time 5.71 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:52:49 PM PDT 24
Peak memory 242548 kb
Host smart-3264c294-6962-405d-8144-38dcf1da4b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749316742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.2749316742
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.376128178
Short name T606
Test name
Test status
Simulation time 1024320048 ps
CPU time 14.48 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:52:57 PM PDT 24
Peak memory 242324 kb
Host smart-52cb6017-7ca5-4e3c-b932-dfdf537f0000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=376128178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.376128178
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.2541106649
Short name T1150
Test name
Test status
Simulation time 448519994 ps
CPU time 7.88 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:52:55 PM PDT 24
Peak memory 242112 kb
Host smart-8feb3020-9e9b-449a-a2c1-43f22d87a538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2541106649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.2541106649
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.1270348481
Short name T457
Test name
Test status
Simulation time 450367827 ps
CPU time 4.58 seconds
Started Jul 01 12:52:39 PM PDT 24
Finished Jul 01 12:52:45 PM PDT 24
Peak memory 241960 kb
Host smart-ad3bf060-ff4d-4031-9727-83df9d3ce25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270348481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1270348481
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.617091098
Short name T506
Test name
Test status
Simulation time 50947215172 ps
CPU time 324.41 seconds
Started Jul 01 12:52:42 PM PDT 24
Finished Jul 01 12:58:09 PM PDT 24
Peak memory 294196 kb
Host smart-8101725c-6164-4756-8894-b6bcb2b1e251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617091098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.
617091098
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.3124401920
Short name T1115
Test name
Test status
Simulation time 47459842485 ps
CPU time 439.68 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 01:00:03 PM PDT 24
Peak memory 257144 kb
Host smart-f40b7044-dcf7-4767-9901-7ca4c60a7260
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124401920 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.3124401920
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.1343001046
Short name T863
Test name
Test status
Simulation time 6533728875 ps
CPU time 20.35 seconds
Started Jul 01 12:52:41 PM PDT 24
Finished Jul 01 12:53:03 PM PDT 24
Peak memory 248832 kb
Host smart-3751d764-f87a-4633-8d0f-882838811e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343001046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1343001046
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.2441629520
Short name T610
Test name
Test status
Simulation time 122113846 ps
CPU time 3.71 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:35 PM PDT 24
Peak memory 242164 kb
Host smart-35769024-1d81-4285-836b-8ff74c19f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441629520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.2441629520
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2821252992
Short name T72
Test name
Test status
Simulation time 144446370 ps
CPU time 3.7 seconds
Started Jul 01 12:55:40 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242100 kb
Host smart-81b581d4-8c6a-439d-a8da-4b24c1ae1ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821252992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2821252992
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3514483990
Short name T672
Test name
Test status
Simulation time 180605192 ps
CPU time 4.03 seconds
Started Jul 01 12:55:34 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 242116 kb
Host smart-37617ba9-8538-44ed-a71f-a8966dae08d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514483990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3514483990
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.598258048
Short name T576
Test name
Test status
Simulation time 254366774 ps
CPU time 3.31 seconds
Started Jul 01 12:55:33 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242320 kb
Host smart-3e9ffe3d-a577-4f58-8738-7dbf5829ce00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598258048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.598258048
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.791165673
Short name T888
Test name
Test status
Simulation time 207145656 ps
CPU time 4.49 seconds
Started Jul 01 12:55:40 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 241836 kb
Host smart-bb2bec90-d887-4a90-9825-ca43ac1867ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791165673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.791165673
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.3756516476
Short name T909
Test name
Test status
Simulation time 302893075 ps
CPU time 3.29 seconds
Started Jul 01 12:55:35 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242152 kb
Host smart-fd68256e-08ad-4f71-8cda-0f98e7396fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756516476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3756516476
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.1094011665
Short name T406
Test name
Test status
Simulation time 2320802259 ps
CPU time 4.19 seconds
Started Jul 01 12:55:30 PM PDT 24
Finished Jul 01 12:55:49 PM PDT 24
Peak memory 242428 kb
Host smart-54279909-6902-4268-b59d-2e19915d0146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094011665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.1094011665
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.3864460732
Short name T205
Test name
Test status
Simulation time 120166377 ps
CPU time 3.03 seconds
Started Jul 01 12:55:40 PM PDT 24
Finished Jul 01 12:55:50 PM PDT 24
Peak memory 242000 kb
Host smart-aefae413-9338-4d1b-b0da-06692aa745a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864460732 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3864460732
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.3238644305
Short name T912
Test name
Test status
Simulation time 1500256421 ps
CPU time 4.81 seconds
Started Jul 01 12:55:35 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 241976 kb
Host smart-402930c6-81e6-40d1-a719-32fa3b678857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238644305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.3238644305
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.3795739639
Short name T1027
Test name
Test status
Simulation time 345577251 ps
CPU time 2.08 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:10 PM PDT 24
Peak memory 240160 kb
Host smart-20186830-43bb-46ed-ace2-7a0ea872282d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795739639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.3795739639
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.395246037
Short name T642
Test name
Test status
Simulation time 1497119517 ps
CPU time 13.02 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 12:51:21 PM PDT 24
Peak memory 242488 kb
Host smart-64fe19ba-e02b-44d2-a399-4712d6342f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395246037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.395246037
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1503238790
Short name T114
Test name
Test status
Simulation time 2184838406 ps
CPU time 28.66 seconds
Started Jul 01 12:51:03 PM PDT 24
Finished Jul 01 12:51:34 PM PDT 24
Peak memory 242376 kb
Host smart-c435942e-666a-4349-b83a-3afb7d90ad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503238790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1503238790
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.2991098159
Short name T979
Test name
Test status
Simulation time 2586955729 ps
CPU time 38.54 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 12:51:46 PM PDT 24
Peak memory 250308 kb
Host smart-8056ee6d-92e7-44e5-8163-65a1f7695698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991098159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2991098159
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.3561595485
Short name T835
Test name
Test status
Simulation time 593323847 ps
CPU time 13.95 seconds
Started Jul 01 12:51:04 PM PDT 24
Finished Jul 01 12:51:21 PM PDT 24
Peak memory 242108 kb
Host smart-eb449dc8-15ec-48cc-8017-df2bf75b9d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561595485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3561595485
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.1580788501
Short name T119
Test name
Test status
Simulation time 156640612 ps
CPU time 3.79 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:13 PM PDT 24
Peak memory 241900 kb
Host smart-a6256732-8ab2-4547-a798-182dc0d9e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580788501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1580788501
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.900074860
Short name T1071
Test name
Test status
Simulation time 6121306306 ps
CPU time 14.98 seconds
Started Jul 01 12:51:08 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 244676 kb
Host smart-3c38fc45-8578-4377-8270-73da40777790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900074860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.900074860
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.2915367121
Short name T431
Test name
Test status
Simulation time 1530478551 ps
CPU time 18.09 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:27 PM PDT 24
Peak memory 242140 kb
Host smart-298dff6e-0609-48c1-97c4-7c6f5676d04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915367121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2915367121
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.3682902784
Short name T1074
Test name
Test status
Simulation time 171192536 ps
CPU time 7.62 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 12:51:16 PM PDT 24
Peak memory 242292 kb
Host smart-d7f25a98-f139-483a-a8e3-9edd3e198f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682902784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.3682902784
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.1125792775
Short name T765
Test name
Test status
Simulation time 2229041086 ps
CPU time 21.75 seconds
Started Jul 01 12:51:07 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 242048 kb
Host smart-56901309-28e9-4938-88cd-e58284540bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1125792775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.1125792775
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.4032176976
Short name T216
Test name
Test status
Simulation time 505414790 ps
CPU time 8.61 seconds
Started Jul 01 12:51:05 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 242232 kb
Host smart-06b5e03a-ea0b-40f3-8e16-4c6bb3c3541e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032176976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4032176976
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3300876320
Short name T22
Test name
Test status
Simulation time 9336260384 ps
CPU time 178.14 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:54:06 PM PDT 24
Peak memory 278408 kb
Host smart-9ecf035e-a5c6-429d-9140-b34621a1b05b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300876320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3300876320
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.379785078
Short name T286
Test name
Test status
Simulation time 311813445 ps
CPU time 4.07 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:13 PM PDT 24
Peak memory 241980 kb
Host smart-7d2aaf9c-0057-482f-98f0-760604632681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379785078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.379785078
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.2472476638
Short name T109
Test name
Test status
Simulation time 8043305539 ps
CPU time 28.51 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:51:37 PM PDT 24
Peak memory 242940 kb
Host smart-64a828f8-ea3c-439c-889d-a70999bc11aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472476638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.
2472476638
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.2255769390
Short name T415
Test name
Test status
Simulation time 11377723598 ps
CPU time 88.56 seconds
Started Jul 01 12:51:06 PM PDT 24
Finished Jul 01 12:52:38 PM PDT 24
Peak memory 242668 kb
Host smart-e1ac6681-815a-4a61-8a66-84ba44575aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255769390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2255769390
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.2689232517
Short name T973
Test name
Test status
Simulation time 67735563 ps
CPU time 1.72 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:48 PM PDT 24
Peak memory 240356 kb
Host smart-5f311e2c-d628-404f-b598-2e2f075d9ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689232517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.2689232517
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.1915135176
Short name T742
Test name
Test status
Simulation time 10582228667 ps
CPU time 28.69 seconds
Started Jul 01 12:52:46 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 243956 kb
Host smart-f5be3e57-1e9a-4654-9ec2-c12e3a2cfc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915135176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1915135176
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.3181133688
Short name T401
Test name
Test status
Simulation time 644405707 ps
CPU time 16.33 seconds
Started Jul 01 12:52:46 PM PDT 24
Finished Jul 01 12:53:04 PM PDT 24
Peak memory 242048 kb
Host smart-b3c9e667-e987-4fc9-8cb1-8526f639898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181133688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3181133688
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.2691038219
Short name T390
Test name
Test status
Simulation time 643855798 ps
CPU time 7.99 seconds
Started Jul 01 12:52:48 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 242484 kb
Host smart-3492f710-e562-4fa1-8c29-eae9d35f6112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691038219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2691038219
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.2391599486
Short name T539
Test name
Test status
Simulation time 2509933727 ps
CPU time 4.59 seconds
Started Jul 01 12:52:43 PM PDT 24
Finished Jul 01 12:52:50 PM PDT 24
Peak memory 241836 kb
Host smart-3a9bd204-69df-440f-a427-1b7e7473ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391599486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.2391599486
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.2517418148
Short name T381
Test name
Test status
Simulation time 394924150 ps
CPU time 9.8 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 242152 kb
Host smart-98cacfc9-f58b-4d7f-aceb-c3df163ef3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517418148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2517418148
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3129184747
Short name T713
Test name
Test status
Simulation time 736099353 ps
CPU time 16.83 seconds
Started Jul 01 12:52:43 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 242300 kb
Host smart-82ee5f32-13c0-4fcf-ba77-2dbf39b07d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129184747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3129184747
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.3524713096
Short name T817
Test name
Test status
Simulation time 298807225 ps
CPU time 6.85 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:53 PM PDT 24
Peak memory 241972 kb
Host smart-2f578dc5-6c62-4f58-b7ab-2a9ab05a9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524713096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3524713096
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.1711575550
Short name T1193
Test name
Test status
Simulation time 507678729 ps
CPU time 11.06 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 241976 kb
Host smart-5be5b3b3-f9d1-473f-9b99-f01d55af3ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711575550 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.1711575550
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.338925344
Short name T375
Test name
Test status
Simulation time 539527010 ps
CPU time 7.02 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 242324 kb
Host smart-579e3d18-cf94-468c-afcd-d6a0ace2487e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338925344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.338925344
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.3507160136
Short name T587
Test name
Test status
Simulation time 842389111 ps
CPU time 11.96 seconds
Started Jul 01 12:52:42 PM PDT 24
Finished Jul 01 12:52:57 PM PDT 24
Peak memory 242108 kb
Host smart-b90e3655-3a99-4490-bf6c-2e64593f782d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507160136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.3507160136
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.2740989371
Short name T923
Test name
Test status
Simulation time 27425125404 ps
CPU time 251.63 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:56:59 PM PDT 24
Peak memory 291808 kb
Host smart-84e36457-c3ac-411f-88db-94530baeb097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740989371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.2740989371
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.771756986
Short name T569
Test name
Test status
Simulation time 87601050163 ps
CPU time 2605.92 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 01:36:14 PM PDT 24
Peak memory 551788 kb
Host smart-313dc209-2895-4934-997e-b6876a90d01c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771756986 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.771756986
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.619881373
Short name T303
Test name
Test status
Simulation time 4509079853 ps
CPU time 21.19 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:53:08 PM PDT 24
Peak memory 241976 kb
Host smart-453d570d-bbcb-4c09-b861-7591ffd0046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619881373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.619881373
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.1020450800
Short name T1029
Test name
Test status
Simulation time 59764934 ps
CPU time 1.74 seconds
Started Jul 01 12:52:51 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 240420 kb
Host smart-3e9c6db1-f922-4ff2-8a6d-ea1e79cf362f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020450800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1020450800
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.3413023150
Short name T29
Test name
Test status
Simulation time 3798696754 ps
CPU time 12.18 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 242544 kb
Host smart-b3767556-057f-4b0f-a6db-bf14e980462d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413023150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3413023150
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.56734909
Short name T798
Test name
Test status
Simulation time 13127729112 ps
CPU time 50.05 seconds
Started Jul 01 12:52:44 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 244972 kb
Host smart-728b9328-9003-4905-9e7b-872f12f58d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56734909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.56734909
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.1379109464
Short name T940
Test name
Test status
Simulation time 846169547 ps
CPU time 14.3 seconds
Started Jul 01 12:52:47 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 242388 kb
Host smart-3671ddf6-b55a-4ff3-8002-00bb15fa5f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379109464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.1379109464
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.285976388
Short name T756
Test name
Test status
Simulation time 106567455 ps
CPU time 4.03 seconds
Started Jul 01 12:52:47 PM PDT 24
Finished Jul 01 12:52:52 PM PDT 24
Peak memory 242324 kb
Host smart-5543f061-9cb8-47c6-bc5a-a1478f80477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285976388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.285976388
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.3537426356
Short name T920
Test name
Test status
Simulation time 7600088069 ps
CPU time 16.37 seconds
Started Jul 01 12:52:43 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 248588 kb
Host smart-7cddac29-6ea6-4b75-b5ba-bc630136446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537426356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.3537426356
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.2938940136
Short name T560
Test name
Test status
Simulation time 9144622741 ps
CPU time 18.74 seconds
Started Jul 01 12:52:52 PM PDT 24
Finished Jul 01 12:53:12 PM PDT 24
Peak memory 242016 kb
Host smart-6c82889b-2b48-4a19-ad6a-fcdc09de62f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938940136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.2938940136
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.2658109149
Short name T628
Test name
Test status
Simulation time 279036036 ps
CPU time 6.65 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 242388 kb
Host smart-e9a21c43-251b-4308-bc13-410c695526ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658109149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2658109149
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.2170191012
Short name T521
Test name
Test status
Simulation time 1273525754 ps
CPU time 13.84 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 242496 kb
Host smart-86aadbb1-5fb9-4482-b837-56bb86b78fac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170191012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.2170191012
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.3829077252
Short name T1085
Test name
Test status
Simulation time 512642364 ps
CPU time 4.77 seconds
Started Jul 01 12:52:50 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 242348 kb
Host smart-708391b5-4710-4a70-9bf3-40913c25bbee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829077252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3829077252
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.689422183
Short name T541
Test name
Test status
Simulation time 4487534536 ps
CPU time 13.84 seconds
Started Jul 01 12:52:45 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 242380 kb
Host smart-930a2642-54db-48dd-bc6b-e48f2555bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689422183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.689422183
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.336204428
Short name T982
Test name
Test status
Simulation time 24282644875 ps
CPU time 545.01 seconds
Started Jul 01 12:52:49 PM PDT 24
Finished Jul 01 01:01:55 PM PDT 24
Peak memory 305596 kb
Host smart-6d8d141e-4ef4-4a7a-8bdd-f146791c5be6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336204428 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.336204428
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.1171450183
Short name T745
Test name
Test status
Simulation time 560202690 ps
CPU time 14.19 seconds
Started Jul 01 12:52:49 PM PDT 24
Finished Jul 01 12:53:04 PM PDT 24
Peak memory 242556 kb
Host smart-a8cf0168-2187-411b-afca-4492e4c5874d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171450183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1171450183
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.3487982164
Short name T725
Test name
Test status
Simulation time 97332220 ps
CPU time 2.06 seconds
Started Jul 01 12:52:52 PM PDT 24
Finished Jul 01 12:52:55 PM PDT 24
Peak memory 240136 kb
Host smart-eb5b980c-6bb5-4015-850a-293603d2f62c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487982164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.3487982164
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.108761189
Short name T67
Test name
Test status
Simulation time 1434863615 ps
CPU time 9.83 seconds
Started Jul 01 12:52:49 PM PDT 24
Finished Jul 01 12:52:59 PM PDT 24
Peak memory 248756 kb
Host smart-a4194f3c-1c0d-4c07-86d3-d1fabfd2d3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108761189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.108761189
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.1321861615
Short name T567
Test name
Test status
Simulation time 1316037904 ps
CPU time 20.22 seconds
Started Jul 01 12:52:56 PM PDT 24
Finished Jul 01 12:53:17 PM PDT 24
Peak memory 241764 kb
Host smart-a9f69747-0940-4157-b397-57b2853e4fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321861615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.1321861615
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.1907280907
Short name T705
Test name
Test status
Simulation time 1434191313 ps
CPU time 22.98 seconds
Started Jul 01 12:52:52 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 242376 kb
Host smart-7ae2c14a-dffc-4f33-b738-ecad5468c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907280907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1907280907
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3317690706
Short name T1157
Test name
Test status
Simulation time 139211820 ps
CPU time 4.86 seconds
Started Jul 01 12:52:49 PM PDT 24
Finished Jul 01 12:52:54 PM PDT 24
Peak memory 241924 kb
Host smart-574b87a9-3b8b-40fc-a745-d1c6b5e885f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317690706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3317690706
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.985435534
Short name T1099
Test name
Test status
Simulation time 1963475516 ps
CPU time 19.95 seconds
Started Jul 01 12:52:52 PM PDT 24
Finished Jul 01 12:53:13 PM PDT 24
Peak memory 242228 kb
Host smart-2a7940f2-819c-45de-8ed5-ffcea7466f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985435534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.985435534
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2340493716
Short name T602
Test name
Test status
Simulation time 2744396584 ps
CPU time 34.24 seconds
Started Jul 01 12:52:49 PM PDT 24
Finished Jul 01 12:53:24 PM PDT 24
Peak memory 242436 kb
Host smart-62d5d32d-57ce-4294-95ba-3f199bed6011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340493716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2340493716
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.502001275
Short name T645
Test name
Test status
Simulation time 577389854 ps
CPU time 4.45 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:01 PM PDT 24
Peak memory 242116 kb
Host smart-4fa952cd-3f8d-44c7-b7bd-51231b15e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502001275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.502001275
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.608571627
Short name T666
Test name
Test status
Simulation time 204832862 ps
CPU time 6.52 seconds
Started Jul 01 12:52:50 PM PDT 24
Finished Jul 01 12:52:58 PM PDT 24
Peak memory 248292 kb
Host smart-29cc25c8-09cd-47b2-81fc-50cd92629447
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=608571627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.608571627
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.2388659336
Short name T589
Test name
Test status
Simulation time 262401073 ps
CPU time 4.43 seconds
Started Jul 01 12:52:51 PM PDT 24
Finished Jul 01 12:52:57 PM PDT 24
Peak memory 242096 kb
Host smart-29cf2c4d-7e91-4d32-9d48-2daca9a21aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388659336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.2388659336
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.1188686044
Short name T462
Test name
Test status
Simulation time 4323629070 ps
CPU time 9.02 seconds
Started Jul 01 12:52:51 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 242428 kb
Host smart-fadf0fb9-c120-4d53-8116-dce45a60962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188686044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1188686044
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2929745119
Short name T39
Test name
Test status
Simulation time 251956078817 ps
CPU time 1240.3 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 01:13:38 PM PDT 24
Peak memory 337360 kb
Host smart-34ee6c90-a6f3-4e14-9f5f-5669593145c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929745119 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.2929745119
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.2025675035
Short name T264
Test name
Test status
Simulation time 2184585848 ps
CPU time 15.82 seconds
Started Jul 01 12:52:51 PM PDT 24
Finished Jul 01 12:53:08 PM PDT 24
Peak memory 242484 kb
Host smart-d69cf4cd-9aa9-48c4-afd4-27e2db7fd9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025675035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.2025675035
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.1553556752
Short name T524
Test name
Test status
Simulation time 121197796 ps
CPU time 1.87 seconds
Started Jul 01 12:52:53 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 239988 kb
Host smart-3ac2d1fa-63b4-422f-bba7-82e352bd55ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553556752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.1553556752
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.3009522613
Short name T780
Test name
Test status
Simulation time 924084808 ps
CPU time 29.69 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 242144 kb
Host smart-87d924de-0a51-47c0-b1ac-e8fd94733765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009522613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3009522613
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.1992280665
Short name T612
Test name
Test status
Simulation time 981542548 ps
CPU time 19.23 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 242216 kb
Host smart-f8b6e69a-3ef2-40a9-9e59-2d853c640c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992280665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.1992280665
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.2365880498
Short name T740
Test name
Test status
Simulation time 2155680399 ps
CPU time 4.92 seconds
Started Jul 01 12:52:53 PM PDT 24
Finished Jul 01 12:52:59 PM PDT 24
Peak memory 242240 kb
Host smart-8fa8067c-386b-4b94-b732-d06ce76ff7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365880498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.2365880498
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.3794553889
Short name T1033
Test name
Test status
Simulation time 2453448753 ps
CPU time 18.82 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 248792 kb
Host smart-d71109ed-2f1a-46ca-9f4f-84b67c83da7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794553889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.3794553889
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.4257767708
Short name T468
Test name
Test status
Simulation time 804051117 ps
CPU time 33.17 seconds
Started Jul 01 12:52:56 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 242316 kb
Host smart-9e7cf31b-028b-4d64-989d-3b43a5f23f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257767708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.4257767708
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.891475279
Short name T641
Test name
Test status
Simulation time 1705716391 ps
CPU time 14.36 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:53:10 PM PDT 24
Peak memory 241832 kb
Host smart-f7332d5a-87c9-43af-b124-940285e41958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891475279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.891475279
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1050592709
Short name T864
Test name
Test status
Simulation time 499604387 ps
CPU time 13.38 seconds
Started Jul 01 12:52:56 PM PDT 24
Finished Jul 01 12:53:11 PM PDT 24
Peak memory 242076 kb
Host smart-09455d45-ebf5-4409-a7e6-93355e6a1016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050592709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1050592709
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.2657695740
Short name T344
Test name
Test status
Simulation time 1156867415 ps
CPU time 11.89 seconds
Started Jul 01 12:52:58 PM PDT 24
Finished Jul 01 12:53:11 PM PDT 24
Peak memory 242028 kb
Host smart-e262357e-4dd5-4678-9603-dbed0aa4fed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2657695740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.2657695740
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.887758195
Short name T906
Test name
Test status
Simulation time 2142697215 ps
CPU time 5.76 seconds
Started Jul 01 12:52:50 PM PDT 24
Finished Jul 01 12:52:56 PM PDT 24
Peak memory 242288 kb
Host smart-f756f5dc-0abb-4145-a123-ac9773b7bd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887758195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.887758195
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.2320885767
Short name T232
Test name
Test status
Simulation time 320074638 ps
CPU time 6.63 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:03 PM PDT 24
Peak memory 242396 kb
Host smart-3e0d9e61-5f31-4944-beb6-b1137fb92e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320885767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2320885767
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.903934544
Short name T1109
Test name
Test status
Simulation time 608048497 ps
CPU time 1.6 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:00 PM PDT 24
Peak memory 240104 kb
Host smart-8d43c711-6cd9-45b8-bc1f-385a74154f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903934544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.903934544
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.4270179612
Short name T429
Test name
Test status
Simulation time 1659949344 ps
CPU time 19.2 seconds
Started Jul 01 12:52:53 PM PDT 24
Finished Jul 01 12:53:13 PM PDT 24
Peak memory 244104 kb
Host smart-aa22656c-ce7b-444a-998d-ea0eb8553c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270179612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.4270179612
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3507294295
Short name T886
Test name
Test status
Simulation time 1830385182 ps
CPU time 44.84 seconds
Started Jul 01 12:52:56 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 255444 kb
Host smart-1029b5bd-546a-4de3-84e5-64520f64e4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507294295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3507294295
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3877822509
Short name T816
Test name
Test status
Simulation time 1963853463 ps
CPU time 22.84 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 242280 kb
Host smart-288c95f8-93d6-4c47-93e5-11c1d15e7daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877822509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3877822509
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.2236953833
Short name T285
Test name
Test status
Simulation time 116405276 ps
CPU time 3.8 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:52:59 PM PDT 24
Peak memory 242172 kb
Host smart-eb1f1703-cc79-4e9f-b2e8-f6184012f99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236953833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2236953833
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.3252686586
Short name T671
Test name
Test status
Simulation time 484803660 ps
CPU time 4.82 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:04 PM PDT 24
Peak memory 242500 kb
Host smart-eba2be48-0c1d-47c5-9a3d-81ab6ae704da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252686586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3252686586
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3302753712
Short name T759
Test name
Test status
Simulation time 2933686244 ps
CPU time 30.09 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:53:26 PM PDT 24
Peak memory 242380 kb
Host smart-965a7313-d6a2-4e44-8c93-535cfea1006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302753712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3302753712
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.3642652553
Short name T419
Test name
Test status
Simulation time 225802046 ps
CPU time 3.9 seconds
Started Jul 01 12:52:55 PM PDT 24
Finished Jul 01 12:53:00 PM PDT 24
Peak memory 241772 kb
Host smart-62b703ae-9a90-4f94-b811-368240abe0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642652553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.3642652553
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.1698874391
Short name T1145
Test name
Test status
Simulation time 349705660 ps
CPU time 4.42 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:03 PM PDT 24
Peak memory 241808 kb
Host smart-631fc45c-2749-497f-a64f-e13422abe63f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1698874391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.1698874391
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.1248133887
Short name T1152
Test name
Test status
Simulation time 172673971 ps
CPU time 3.38 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:52:59 PM PDT 24
Peak memory 242056 kb
Host smart-aa95e468-e365-43b8-b039-2af1f7c07dcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1248133887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.1248133887
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.2957225813
Short name T379
Test name
Test status
Simulation time 452932689 ps
CPU time 6.44 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:05 PM PDT 24
Peak memory 241924 kb
Host smart-8c36b73a-39de-4fab-b687-43e583385045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957225813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2957225813
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3231572688
Short name T316
Test name
Test status
Simulation time 15491702403 ps
CPU time 41.64 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 247116 kb
Host smart-3da35978-5aa3-46ab-bcbe-ff69e814f17a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231572688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3231572688
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.1612841865
Short name T573
Test name
Test status
Simulation time 4040814686 ps
CPU time 26.88 seconds
Started Jul 01 12:52:54 PM PDT 24
Finished Jul 01 12:53:23 PM PDT 24
Peak memory 243220 kb
Host smart-5cbaee4f-6b94-4ebf-9d6d-05e83c7babef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612841865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1612841865
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2907615149
Short name T844
Test name
Test status
Simulation time 939742204 ps
CPU time 2.05 seconds
Started Jul 01 12:53:01 PM PDT 24
Finished Jul 01 12:53:05 PM PDT 24
Peak memory 240488 kb
Host smart-5989992d-2a32-4047-9387-24e16ef7fc6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907615149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2907615149
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.2478279787
Short name T267
Test name
Test status
Simulation time 952269129 ps
CPU time 7.05 seconds
Started Jul 01 12:53:00 PM PDT 24
Finished Jul 01 12:53:09 PM PDT 24
Peak memory 248712 kb
Host smart-b5b76c59-cee2-44c9-9032-16d0f6635e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478279787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2478279787
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.2140236152
Short name T453
Test name
Test status
Simulation time 729405985 ps
CPU time 15.21 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 242168 kb
Host smart-af94c0eb-4a72-4381-a486-005caf356e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140236152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2140236152
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.2576047522
Short name T852
Test name
Test status
Simulation time 11348981977 ps
CPU time 27.15 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 242100 kb
Host smart-040a7d1f-9fab-47d6-9fb9-a253aab79c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576047522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2576047522
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.3896402947
Short name T200
Test name
Test status
Simulation time 353064873 ps
CPU time 4.54 seconds
Started Jul 01 12:52:56 PM PDT 24
Finished Jul 01 12:53:02 PM PDT 24
Peak memory 242176 kb
Host smart-c0c4fa00-41ea-45c4-83ed-ac8411de9e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896402947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3896402947
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.3974746352
Short name T1155
Test name
Test status
Simulation time 10029578966 ps
CPU time 31.17 seconds
Started Jul 01 12:53:00 PM PDT 24
Finished Jul 01 12:53:33 PM PDT 24
Peak memory 248856 kb
Host smart-a04bdc71-be0a-4a3d-a1f0-3fc7f8c07df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974746352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3974746352
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.2301037624
Short name T377
Test name
Test status
Simulation time 811793782 ps
CPU time 9.68 seconds
Started Jul 01 12:53:02 PM PDT 24
Finished Jul 01 12:53:13 PM PDT 24
Peak memory 242072 kb
Host smart-1727e67d-3d74-4e5a-a972-074db9972c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301037624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.2301037624
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.3744761306
Short name T312
Test name
Test status
Simulation time 149964424 ps
CPU time 4.27 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 12:53:06 PM PDT 24
Peak memory 241872 kb
Host smart-3b8557d4-832f-42a3-a926-f096441ff1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744761306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3744761306
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2871586889
Short name T1139
Test name
Test status
Simulation time 495104429 ps
CPU time 12.24 seconds
Started Jul 01 12:53:02 PM PDT 24
Finished Jul 01 12:53:15 PM PDT 24
Peak memory 242008 kb
Host smart-e600c565-233d-4c67-b616-89d7b6cb19ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871586889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2871586889
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.692828247
Short name T656
Test name
Test status
Simulation time 2392650403 ps
CPU time 8.57 seconds
Started Jul 01 12:53:00 PM PDT 24
Finished Jul 01 12:53:10 PM PDT 24
Peak memory 242096 kb
Host smart-9fadb7a5-827e-40f3-8704-6d70b00f6342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692828247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.692828247
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.1192751897
Short name T414
Test name
Test status
Simulation time 230808045 ps
CPU time 4.04 seconds
Started Jul 01 12:52:57 PM PDT 24
Finished Jul 01 12:53:03 PM PDT 24
Peak memory 241940 kb
Host smart-ee76e834-5d1e-4eab-bdd6-d8af920009f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192751897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.1192751897
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.2998819596
Short name T596
Test name
Test status
Simulation time 69646986697 ps
CPU time 266.38 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 12:57:27 PM PDT 24
Peak memory 250152 kb
Host smart-3c939969-21a6-468f-a37f-c269e6d02429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998819596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all
.2998819596
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1572335649
Short name T1025
Test name
Test status
Simulation time 25628013220 ps
CPU time 619.81 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 01:03:21 PM PDT 24
Peak memory 266376 kb
Host smart-cd903609-2fd6-4241-8033-ae2a42630072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572335649 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1572335649
Directory /workspace/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.2674263704
Short name T1007
Test name
Test status
Simulation time 1861906932 ps
CPU time 13.93 seconds
Started Jul 01 12:52:59 PM PDT 24
Finished Jul 01 12:53:15 PM PDT 24
Peak memory 242748 kb
Host smart-4505935a-566b-44f7-8b31-c6dee12e7f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674263704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2674263704
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.4219397157
Short name T399
Test name
Test status
Simulation time 48670026 ps
CPU time 1.72 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:08 PM PDT 24
Peak memory 240200 kb
Host smart-256d7ca4-8acc-4ad9-85d1-9dba5406ead3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219397157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.4219397157
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.1591808078
Short name T1172
Test name
Test status
Simulation time 2150410832 ps
CPU time 26.03 seconds
Started Jul 01 12:53:03 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 245112 kb
Host smart-37a69b98-741c-42d7-9d1b-c5c8cc2e2f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591808078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1591808078
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.4272654693
Short name T687
Test name
Test status
Simulation time 780812448 ps
CPU time 21.77 seconds
Started Jul 01 12:53:01 PM PDT 24
Finished Jul 01 12:53:24 PM PDT 24
Peak memory 241916 kb
Host smart-3c3e35e6-05e6-4f85-ac7c-1ba9d5c30890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272654693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.4272654693
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.1184733635
Short name T530
Test name
Test status
Simulation time 1373807707 ps
CPU time 25.82 seconds
Started Jul 01 12:53:04 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 242688 kb
Host smart-87766bc6-a86d-4e7f-8660-3005637beb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184733635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1184733635
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.401836399
Short name T620
Test name
Test status
Simulation time 230768029 ps
CPU time 4.78 seconds
Started Jul 01 12:52:58 PM PDT 24
Finished Jul 01 12:53:04 PM PDT 24
Peak memory 241872 kb
Host smart-1a011266-48e9-4c00-b1b2-2083a7442b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401836399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.401836399
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.3504689776
Short name T711
Test name
Test status
Simulation time 4602726006 ps
CPU time 12.73 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:19 PM PDT 24
Peak memory 242508 kb
Host smart-3ab01a79-9b5c-4bbd-b8c0-04db2af50bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504689776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3504689776
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.3879224872
Short name T1050
Test name
Test status
Simulation time 681699716 ps
CPU time 15.57 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:23 PM PDT 24
Peak memory 242136 kb
Host smart-3323f538-1675-4a3b-9374-0ef0b0d1310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879224872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3879224872
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.2993698923
Short name T191
Test name
Test status
Simulation time 6203179761 ps
CPU time 17.05 seconds
Started Jul 01 12:53:00 PM PDT 24
Finished Jul 01 12:53:19 PM PDT 24
Peak memory 242100 kb
Host smart-1ed69861-c844-4d7f-b881-660ebbd83da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993698923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.2993698923
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.2054823074
Short name T402
Test name
Test status
Simulation time 454952695 ps
CPU time 6.01 seconds
Started Jul 01 12:52:58 PM PDT 24
Finished Jul 01 12:53:05 PM PDT 24
Peak memory 242324 kb
Host smart-9c987442-397a-4007-9f97-d93a68c706bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054823074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2054823074
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.473483331
Short name T832
Test name
Test status
Simulation time 993339506 ps
CPU time 9.13 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 242484 kb
Host smart-c5f33d87-de99-4cb9-92ed-34eb9a32c491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=473483331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.473483331
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.3887145767
Short name T408
Test name
Test status
Simulation time 251116877 ps
CPU time 6.36 seconds
Started Jul 01 12:52:58 PM PDT 24
Finished Jul 01 12:53:06 PM PDT 24
Peak memory 242072 kb
Host smart-03c41652-ce49-450b-b05f-7345d061b3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887145767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3887145767
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.3075388745
Short name T900
Test name
Test status
Simulation time 22671989924 ps
CPU time 47.71 seconds
Started Jul 01 12:53:08 PM PDT 24
Finished Jul 01 12:53:57 PM PDT 24
Peak memory 248728 kb
Host smart-e3cc80e3-e6b9-4b54-8fa8-afa51a643a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075388745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.3075388745
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.1793089380
Short name T260
Test name
Test status
Simulation time 1328669551694 ps
CPU time 2094.85 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 01:28:02 PM PDT 24
Peak memory 346312 kb
Host smart-ed754280-fa5b-422e-b5f5-9c3094251480
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793089380 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.1793089380
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.493555321
Short name T984
Test name
Test status
Simulation time 746248872 ps
CPU time 26.6 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:34 PM PDT 24
Peak memory 242340 kb
Host smart-3c6fd320-1b04-4658-8aec-6ba255efad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493555321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.493555321
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.251712411
Short name T1020
Test name
Test status
Simulation time 141625419 ps
CPU time 2.02 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:09 PM PDT 24
Peak memory 240420 kb
Host smart-556d7ac3-b83b-4069-9808-e7d72df6cf07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251712411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.251712411
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.2253241286
Short name T746
Test name
Test status
Simulation time 5091623317 ps
CPU time 32.03 seconds
Started Jul 01 12:53:08 PM PDT 24
Finished Jul 01 12:53:42 PM PDT 24
Peak memory 248828 kb
Host smart-c252d15c-e9b2-4a60-b2a9-62daf9a19a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253241286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2253241286
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.2823799106
Short name T1014
Test name
Test status
Simulation time 361243175 ps
CPU time 21.85 seconds
Started Jul 01 12:53:07 PM PDT 24
Finished Jul 01 12:53:29 PM PDT 24
Peak memory 241924 kb
Host smart-420adb4e-ab67-46da-a385-7ec28a40bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823799106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.2823799106
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1542821627
Short name T405
Test name
Test status
Simulation time 2520506488 ps
CPU time 15.72 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:22 PM PDT 24
Peak memory 241912 kb
Host smart-2cc515c7-2c98-467b-a3c1-7dba6effc502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542821627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1542821627
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.4261876566
Short name T523
Test name
Test status
Simulation time 561413948 ps
CPU time 4.61 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:11 PM PDT 24
Peak memory 242264 kb
Host smart-862cdc23-d8cf-4d1c-a2ef-9fb5d0a17a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261876566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.4261876566
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.779361183
Short name T247
Test name
Test status
Simulation time 1641389498 ps
CPU time 44.07 seconds
Started Jul 01 12:53:08 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 258456 kb
Host smart-b707cdf0-a99c-4f85-81bb-08817c16089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779361183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.779361183
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.3922281939
Short name T796
Test name
Test status
Simulation time 2460357554 ps
CPU time 20.58 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 248856 kb
Host smart-c4c50190-0beb-4c2a-886f-56b4adf4b859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922281939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.3922281939
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.510915928
Short name T1069
Test name
Test status
Simulation time 412827922 ps
CPU time 10.67 seconds
Started Jul 01 12:53:04 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 241976 kb
Host smart-ac8e8143-435b-4438-a0d6-cd1c18037d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510915928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.510915928
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.552621046
Short name T527
Test name
Test status
Simulation time 1484167355 ps
CPU time 11.64 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:18 PM PDT 24
Peak memory 242092 kb
Host smart-5f09e46c-2a69-4633-84b4-2b3444c38d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552621046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.552621046
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.80517321
Short name T623
Test name
Test status
Simulation time 104960026 ps
CPU time 4.15 seconds
Started Jul 01 12:53:05 PM PDT 24
Finished Jul 01 12:53:10 PM PDT 24
Peak memory 241928 kb
Host smart-59b28a9e-b066-4a8b-ba0b-61d99836d3a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80517321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.80517321
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.4261353601
Short name T1079
Test name
Test status
Simulation time 117146395 ps
CPU time 3.31 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:53:10 PM PDT 24
Peak memory 242152 kb
Host smart-75dd809b-762f-4282-992d-76a8243a6388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261353601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.4261353601
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.1683246383
Short name T1105
Test name
Test status
Simulation time 14697863055 ps
CPU time 226.01 seconds
Started Jul 01 12:53:06 PM PDT 24
Finished Jul 01 12:56:53 PM PDT 24
Peak memory 257016 kb
Host smart-7d93786a-141c-4ce0-b71a-0d8cc0bc4c17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683246383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.1683246383
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.1566965668
Short name T19
Test name
Test status
Simulation time 198210396334 ps
CPU time 1266.11 seconds
Started Jul 01 12:53:04 PM PDT 24
Finished Jul 01 01:14:11 PM PDT 24
Peak memory 259828 kb
Host smart-b5ffdc94-1f8c-481c-9e41-dc2dbdefbb84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566965668 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.1566965668
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3720134899
Short name T648
Test name
Test status
Simulation time 407367577 ps
CPU time 9.79 seconds
Started Jul 01 12:53:03 PM PDT 24
Finished Jul 01 12:53:14 PM PDT 24
Peak memory 241940 kb
Host smart-61c8c874-3f9c-48a7-a529-77de64d555c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720134899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3720134899
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.4002855319
Short name T525
Test name
Test status
Simulation time 63168915 ps
CPU time 1.82 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:53:17 PM PDT 24
Peak memory 240544 kb
Host smart-d5787078-71d3-41cf-839f-11b76065e26a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002855319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.4002855319
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3322185722
Short name T122
Test name
Test status
Simulation time 11725301071 ps
CPU time 27.19 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:53:42 PM PDT 24
Peak memory 243716 kb
Host smart-218e1294-e125-4911-bf77-f61ee9785c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322185722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3322185722
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.5223041
Short name T1028
Test name
Test status
Simulation time 3748230191 ps
CPU time 34.71 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 245860 kb
Host smart-632e3284-3904-4687-b610-8ede5adedcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5223041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.5223041
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.3875745839
Short name T972
Test name
Test status
Simulation time 8784237030 ps
CPU time 19.52 seconds
Started Jul 01 12:53:11 PM PDT 24
Finished Jul 01 12:53:32 PM PDT 24
Peak memory 242492 kb
Host smart-43f53f61-6558-4048-a7e8-ecba3fd6ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875745839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3875745839
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.1619153620
Short name T482
Test name
Test status
Simulation time 231435684 ps
CPU time 3.13 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:53:17 PM PDT 24
Peak memory 241788 kb
Host smart-ecf7d891-efd7-42b5-a854-fd64a8521488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619153620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1619153620
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.2252771604
Short name T935
Test name
Test status
Simulation time 21961371678 ps
CPU time 51.28 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 248880 kb
Host smart-e9e3a7ab-1b48-462b-bd3c-4bb474f02941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252771604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.2252771604
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.1544774606
Short name T799
Test name
Test status
Simulation time 735676881 ps
CPU time 8.74 seconds
Started Jul 01 12:53:10 PM PDT 24
Finished Jul 01 12:53:21 PM PDT 24
Peak memory 242356 kb
Host smart-e72713d9-b792-461f-a50c-c7f527418793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544774606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.1544774606
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.3990337192
Short name T934
Test name
Test status
Simulation time 165183761 ps
CPU time 3.08 seconds
Started Jul 01 12:53:12 PM PDT 24
Finished Jul 01 12:53:17 PM PDT 24
Peak memory 241724 kb
Host smart-29a22bb7-c596-4785-b0b8-ea817bc6f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990337192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3990337192
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.4089883089
Short name T394
Test name
Test status
Simulation time 768160432 ps
CPU time 19.08 seconds
Started Jul 01 12:53:09 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 241740 kb
Host smart-1923210b-a0ce-49c4-80c8-ab3f4291e126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089883089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.4089883089
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.1369031610
Short name T397
Test name
Test status
Simulation time 1852405669 ps
CPU time 6.35 seconds
Started Jul 01 12:53:11 PM PDT 24
Finished Jul 01 12:53:19 PM PDT 24
Peak memory 241948 kb
Host smart-06095157-3cb7-4aae-8854-63dff1cdc7a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1369031610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1369031610
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.1924836421
Short name T790
Test name
Test status
Simulation time 446021117 ps
CPU time 5 seconds
Started Jul 01 12:53:08 PM PDT 24
Finished Jul 01 12:53:15 PM PDT 24
Peak memory 242068 kb
Host smart-d5af6687-db84-437e-b1be-e6bd7b6b2329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924836421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.1924836421
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3852726920
Short name T503
Test name
Test status
Simulation time 158132550 ps
CPU time 3.66 seconds
Started Jul 01 12:53:10 PM PDT 24
Finished Jul 01 12:53:16 PM PDT 24
Peak memory 248548 kb
Host smart-18e74450-cfa4-4ded-a5fb-c430144a813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852726920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3852726920
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.3885661705
Short name T83
Test name
Test status
Simulation time 5902185862 ps
CPU time 18.94 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 12:53:38 PM PDT 24
Peak memory 242296 kb
Host smart-a79f693a-4ef4-4fa4-84e2-309b7952f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885661705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3885661705
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.3823218907
Short name T754
Test name
Test status
Simulation time 556504433 ps
CPU time 14.34 seconds
Started Jul 01 12:53:15 PM PDT 24
Finished Jul 01 12:53:33 PM PDT 24
Peak memory 242392 kb
Host smart-433da106-c084-411a-970b-54543f55a1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823218907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3823218907
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.636887746
Short name T561
Test name
Test status
Simulation time 2756295565 ps
CPU time 29.75 seconds
Started Jul 01 12:53:10 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242296 kb
Host smart-fa9a482a-acfd-4ef6-89bb-e850158fee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636887746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.636887746
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.2156913519
Short name T818
Test name
Test status
Simulation time 403647426 ps
CPU time 4.28 seconds
Started Jul 01 12:53:11 PM PDT 24
Finished Jul 01 12:53:18 PM PDT 24
Peak memory 242136 kb
Host smart-0ea059b5-10f4-49e5-9ac7-5a0f77bb76f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156913519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2156913519
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.1225937512
Short name T1092
Test name
Test status
Simulation time 1985111769 ps
CPU time 31.78 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 12:53:51 PM PDT 24
Peak memory 242560 kb
Host smart-c41e8521-4946-4a13-a4c6-70f6278c1d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225937512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1225937512
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2815340691
Short name T475
Test name
Test status
Simulation time 1093373871 ps
CPU time 24.06 seconds
Started Jul 01 12:53:17 PM PDT 24
Finished Jul 01 12:53:44 PM PDT 24
Peak memory 241948 kb
Host smart-8ba5cec1-d752-424b-bf8b-51064464d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815340691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2815340691
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3790727630
Short name T133
Test name
Test status
Simulation time 522895664 ps
CPU time 5.14 seconds
Started Jul 01 12:53:09 PM PDT 24
Finished Jul 01 12:53:15 PM PDT 24
Peak memory 241684 kb
Host smart-8d94a406-b4df-46d0-91bb-e780be828da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790727630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3790727630
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.1250900204
Short name T512
Test name
Test status
Simulation time 739958622 ps
CPU time 5.03 seconds
Started Jul 01 12:53:13 PM PDT 24
Finished Jul 01 12:53:20 PM PDT 24
Peak memory 241984 kb
Host smart-0057ceec-262c-496b-976c-826ec1f95d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1250900204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.1250900204
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3834538175
Short name T637
Test name
Test status
Simulation time 139872047 ps
CPU time 4.56 seconds
Started Jul 01 12:53:18 PM PDT 24
Finished Jul 01 12:53:26 PM PDT 24
Peak memory 242012 kb
Host smart-f5ec5511-926c-4a85-a12c-acd93d21f9f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834538175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3834538175
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1439170174
Short name T1082
Test name
Test status
Simulation time 3059984255 ps
CPU time 9.6 seconds
Started Jul 01 12:53:10 PM PDT 24
Finished Jul 01 12:53:21 PM PDT 24
Peak memory 242216 kb
Host smart-648bbccc-0050-4181-a3f6-781723abe66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439170174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1439170174
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.2028404610
Short name T949
Test name
Test status
Simulation time 17844213365 ps
CPU time 478.67 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 01:01:18 PM PDT 24
Peak memory 314484 kb
Host smart-13704619-1887-449e-9b03-51768ebc164f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028404610 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2028404610
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.4252148157
Short name T255
Test name
Test status
Simulation time 1785586834 ps
CPU time 15.92 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 12:53:35 PM PDT 24
Peak memory 242320 kb
Host smart-6b190523-1a8b-4a32-8047-261fef4b15c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252148157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.4252148157
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.1496488095
Short name T1112
Test name
Test status
Simulation time 69951119 ps
CPU time 1.74 seconds
Started Jul 01 12:51:14 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 240004 kb
Host smart-db755177-f4d8-4463-91fa-26b6687de063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496488095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.1496488095
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.3354459110
Short name T862
Test name
Test status
Simulation time 1688335501 ps
CPU time 12.76 seconds
Started Jul 01 12:51:12 PM PDT 24
Finished Jul 01 12:51:26 PM PDT 24
Peak memory 242432 kb
Host smart-27936e66-0f3b-474a-aa04-06492d2382fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354459110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.3354459110
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.417752508
Short name T322
Test name
Test status
Simulation time 22187796466 ps
CPU time 76.99 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 12:52:32 PM PDT 24
Peak memory 250384 kb
Host smart-668ee79d-f7f0-41f1-af04-536c0e863c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417752508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.417752508
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.3387337661
Short name T391
Test name
Test status
Simulation time 7431452920 ps
CPU time 13.7 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 12:51:28 PM PDT 24
Peak memory 242712 kb
Host smart-c4b0ed45-053e-45f3-83db-53862a58f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387337661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.3387337661
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.1808142001
Short name T199
Test name
Test status
Simulation time 1210726582 ps
CPU time 17 seconds
Started Jul 01 12:51:12 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 248692 kb
Host smart-bbcee9d8-28dc-452f-83eb-0e5a3c520778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808142001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1808142001
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3643058750
Short name T367
Test name
Test status
Simulation time 1896548479 ps
CPU time 21.24 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 242112 kb
Host smart-a69e678e-0cd0-47ea-bbac-8ab2a00a8ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643058750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3643058750
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.569534527
Short name T846
Test name
Test status
Simulation time 130431389 ps
CPU time 3.72 seconds
Started Jul 01 12:51:10 PM PDT 24
Finished Jul 01 12:51:15 PM PDT 24
Peak memory 241680 kb
Host smart-7dc85470-f691-4383-94b4-e95e2c9cd4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569534527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.569534527
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.459703172
Short name T757
Test name
Test status
Simulation time 6220302255 ps
CPU time 12.38 seconds
Started Jul 01 12:51:11 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 248796 kb
Host smart-31174634-58d4-45ed-97c0-d70a4b141e31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459703172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.459703172
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.3678095210
Short name T601
Test name
Test status
Simulation time 271719812 ps
CPU time 8.7 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 12:51:23 PM PDT 24
Peak memory 242120 kb
Host smart-81645913-a14f-44d4-9d70-0e159efebfb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678095210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3678095210
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.2298674695
Short name T211
Test name
Test status
Simulation time 10834072370 ps
CPU time 190.58 seconds
Started Jul 01 12:51:12 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 278376 kb
Host smart-99e453b6-2dd4-4d6c-a4e1-00a19efb9fc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298674695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.2298674695
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.1098085899
Short name T477
Test name
Test status
Simulation time 531766841 ps
CPU time 6.48 seconds
Started Jul 01 12:51:07 PM PDT 24
Finished Jul 01 12:51:16 PM PDT 24
Peak memory 242084 kb
Host smart-8eb47fdb-f43a-4173-9cd1-7be4f62ec099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098085899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1098085899
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.23890863
Short name T748
Test name
Test status
Simulation time 69359553055 ps
CPU time 139.89 seconds
Started Jul 01 12:51:11 PM PDT 24
Finished Jul 01 12:53:32 PM PDT 24
Peak memory 248764 kb
Host smart-9636786e-5123-46cc-8a71-c85c6038a140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23890863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.23890863
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.50629528
Short name T945
Test name
Test status
Simulation time 91043056738 ps
CPU time 666.86 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 01:02:22 PM PDT 24
Peak memory 296712 kb
Host smart-49f72220-2a9b-4aa6-9ace-8e900cc4e9c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50629528 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.50629528
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.4076796815
Short name T938
Test name
Test status
Simulation time 2476110339 ps
CPU time 18.26 seconds
Started Jul 01 12:51:12 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 242540 kb
Host smart-7657c022-b3a0-4421-8c49-eaab7c3c86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076796815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.4076796815
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.3026272877
Short name T921
Test name
Test status
Simulation time 188075850 ps
CPU time 2.04 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:53:27 PM PDT 24
Peak memory 240496 kb
Host smart-3cde0c23-2193-4437-b40c-2733cc6f5a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026272877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3026272877
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.1078507670
Short name T822
Test name
Test status
Simulation time 1907183511 ps
CPU time 20.2 seconds
Started Jul 01 12:53:19 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242312 kb
Host smart-9d73c74c-59f6-452e-9bb2-32a852ddad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078507670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1078507670
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.2106446170
Short name T917
Test name
Test status
Simulation time 15548194868 ps
CPU time 35.54 seconds
Started Jul 01 12:53:14 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 245840 kb
Host smart-37a6c4bc-0193-48b4-b5d8-3fa95ff7c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106446170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2106446170
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.1779248205
Short name T814
Test name
Test status
Simulation time 800146252 ps
CPU time 5.85 seconds
Started Jul 01 12:53:15 PM PDT 24
Finished Jul 01 12:53:24 PM PDT 24
Peak memory 242612 kb
Host smart-a9a15bea-9a1b-407a-b99e-ab477648e31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779248205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.1779248205
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1257227103
Short name T160
Test name
Test status
Simulation time 132296997 ps
CPU time 3.29 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 12:53:22 PM PDT 24
Peak memory 241996 kb
Host smart-718afcb0-85e1-424f-9667-c179ae53eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257227103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1257227103
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.530212868
Short name T325
Test name
Test status
Simulation time 3862200026 ps
CPU time 26.21 seconds
Started Jul 01 12:53:15 PM PDT 24
Finished Jul 01 12:53:44 PM PDT 24
Peak memory 248648 kb
Host smart-9a8c64e5-5ab1-4915-8997-4f5f82177d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530212868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.530212868
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.656030282
Short name T1008
Test name
Test status
Simulation time 1324219586 ps
CPU time 9.93 seconds
Started Jul 01 12:53:17 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 248804 kb
Host smart-4058cd96-d32b-448a-ba0d-1927c2745b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656030282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.656030282
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.2585145037
Short name T144
Test name
Test status
Simulation time 2413090938 ps
CPU time 4.58 seconds
Started Jul 01 12:53:16 PM PDT 24
Finished Jul 01 12:53:24 PM PDT 24
Peak memory 242340 kb
Host smart-6f9f713a-c10e-42a7-a0bb-1ee8d74a3677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585145037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.2585145037
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.3407537092
Short name T1023
Test name
Test status
Simulation time 2280029789 ps
CPU time 21.18 seconds
Started Jul 01 12:53:19 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 241956 kb
Host smart-df37f34f-b209-49e4-ae80-abcf66a8d6a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407537092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3407537092
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.1040616930
Short name T348
Test name
Test status
Simulation time 1811008244 ps
CPU time 4.55 seconds
Started Jul 01 12:53:14 PM PDT 24
Finished Jul 01 12:53:21 PM PDT 24
Peak memory 242076 kb
Host smart-14d375c7-d22d-428f-b797-cfd6ebfb417d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040616930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1040616930
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.1909914254
Short name T1143
Test name
Test status
Simulation time 2018535192 ps
CPU time 11.48 seconds
Started Jul 01 12:53:15 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 242224 kb
Host smart-d775af03-9843-4f6e-9d01-dcabb39e0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909914254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1909914254
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.975009518
Short name T14
Test name
Test status
Simulation time 12986852964 ps
CPU time 379.86 seconds
Started Jul 01 12:53:23 PM PDT 24
Finished Jul 01 12:59:45 PM PDT 24
Peak memory 334824 kb
Host smart-0f5debd3-b7f7-4f3a-bf18-0b90c54e1454
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975009518 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.975009518
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2547078997
Short name T1045
Test name
Test status
Simulation time 392538468 ps
CPU time 6.24 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 242056 kb
Host smart-c4efa557-583e-482e-89b2-e3a561d1bebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547078997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2547078997
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.3061638698
Short name T450
Test name
Test status
Simulation time 936668419 ps
CPU time 2.09 seconds
Started Jul 01 12:53:21 PM PDT 24
Finished Jul 01 12:53:25 PM PDT 24
Peak memory 240404 kb
Host smart-91e9decc-2a13-45c2-81e8-737a46fce44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061638698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3061638698
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.2316969717
Short name T164
Test name
Test status
Simulation time 2075188191 ps
CPU time 12.86 seconds
Started Jul 01 12:53:22 PM PDT 24
Finished Jul 01 12:53:36 PM PDT 24
Peak memory 242456 kb
Host smart-b4130464-66cd-4230-88a6-983c52920180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316969717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2316969717
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.905989071
Short name T577
Test name
Test status
Simulation time 731178183 ps
CPU time 24.47 seconds
Started Jul 01 12:53:21 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 241876 kb
Host smart-0e1ec5cb-95a5-4c7a-948c-d213d92f96b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905989071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.905989071
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.3907426863
Short name T536
Test name
Test status
Simulation time 412362532 ps
CPU time 8.09 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:53:31 PM PDT 24
Peak memory 241976 kb
Host smart-438b6e9c-f5bd-4449-8164-2aff3f980681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907426863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3907426863
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.133415174
Short name T855
Test name
Test status
Simulation time 452847148 ps
CPU time 5.8 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 242120 kb
Host smart-c6c7e191-4102-4540-b371-730576f3809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133415174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.133415174
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.612099525
Short name T1059
Test name
Test status
Simulation time 24011453300 ps
CPU time 42.46 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:54:04 PM PDT 24
Peak memory 257104 kb
Host smart-61aaa58f-3270-4482-8939-e4cc53e46f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612099525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.612099525
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.3880661286
Short name T393
Test name
Test status
Simulation time 836495404 ps
CPU time 8.68 seconds
Started Jul 01 12:53:25 PM PDT 24
Finished Jul 01 12:53:35 PM PDT 24
Peak memory 242216 kb
Host smart-23369133-8d0a-46ee-9d25-353a0d258ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880661286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3880661286
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.7409958
Short name T776
Test name
Test status
Simulation time 595559222 ps
CPU time 10 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:53:32 PM PDT 24
Peak memory 242360 kb
Host smart-776628f3-8947-4645-a8bb-0f7e670c1555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7409958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.7409958
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.185695315
Short name T28
Test name
Test status
Simulation time 1136930665 ps
CPU time 16 seconds
Started Jul 01 12:53:19 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 248760 kb
Host smart-afd9a267-48c9-4329-818b-354fd0dea02a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185695315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.185695315
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.3364330275
Short name T629
Test name
Test status
Simulation time 645995394 ps
CPU time 6.34 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:53:31 PM PDT 24
Peak memory 242036 kb
Host smart-eaafc59b-8457-404d-9605-9f4838cd2f44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3364330275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.3364330275
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.945584580
Short name T1052
Test name
Test status
Simulation time 2028751054 ps
CPU time 6.61 seconds
Started Jul 01 12:53:23 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 248496 kb
Host smart-e604e9ed-f854-4941-921b-61232601a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945584580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.945584580
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.56967531
Short name T236
Test name
Test status
Simulation time 7657472204 ps
CPU time 20.4 seconds
Started Jul 01 12:53:20 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 241608 kb
Host smart-fde2ec1a-9941-4d97-8744-3d57669836b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56967531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.56967531
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.296858875
Short name T837
Test name
Test status
Simulation time 13832271790 ps
CPU time 35.48 seconds
Started Jul 01 12:53:22 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 242068 kb
Host smart-81557894-c1f4-4ea1-93d1-e00b8c2d5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296858875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.296858875
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.1385038961
Short name T378
Test name
Test status
Simulation time 195216581 ps
CPU time 2.27 seconds
Started Jul 01 12:53:25 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 240120 kb
Host smart-4eed0b17-d53c-4820-9037-7121b6a6e068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385038961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1385038961
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.1067842117
Short name T1030
Test name
Test status
Simulation time 1971780050 ps
CPU time 11.62 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:39 PM PDT 24
Peak memory 242744 kb
Host smart-56588809-54d0-4687-beee-33daeb7fc918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067842117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1067842117
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.2717965298
Short name T970
Test name
Test status
Simulation time 516796730 ps
CPU time 16.4 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 242104 kb
Host smart-0da04687-ee83-4118-8569-cb5524c75eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717965298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2717965298
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.1670391596
Short name T445
Test name
Test status
Simulation time 7625592864 ps
CPU time 19.2 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:53 PM PDT 24
Peak memory 242632 kb
Host smart-8ca62312-577b-4c43-9f2b-8e9787c654f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670391596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1670391596
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.2040650655
Short name T104
Test name
Test status
Simulation time 381789130 ps
CPU time 3.82 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 242184 kb
Host smart-e0d5bff8-74ef-4f5a-829d-f54dfb8f97cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040650655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.2040650655
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.436986265
Short name T148
Test name
Test status
Simulation time 579801920 ps
CPU time 8.26 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:53:34 PM PDT 24
Peak memory 242408 kb
Host smart-f220b687-fd61-4054-bd3f-8494709d0b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436986265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.436986265
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2746495594
Short name T421
Test name
Test status
Simulation time 416007314 ps
CPU time 9.6 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 242572 kb
Host smart-49a872ba-ffaa-4b9a-ae11-005025d0f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746495594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2746495594
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.4116417268
Short name T764
Test name
Test status
Simulation time 232142658 ps
CPU time 5.43 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:32 PM PDT 24
Peak memory 241896 kb
Host smart-5bed3e0b-7735-4d74-889d-1f134db2813e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116417268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.4116417268
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1928662916
Short name T766
Test name
Test status
Simulation time 2961617646 ps
CPU time 7.35 seconds
Started Jul 01 12:53:25 PM PDT 24
Finished Jul 01 12:53:33 PM PDT 24
Peak memory 242004 kb
Host smart-fb573db0-7897-4e68-8169-0b077bcb94fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1928662916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1928662916
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.878905405
Short name T1128
Test name
Test status
Simulation time 130265384 ps
CPU time 5.16 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:53:30 PM PDT 24
Peak memory 241944 kb
Host smart-c1d648aa-9e47-4d58-a2b5-680be4675827
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878905405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.878905405
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.3983490893
Short name T700
Test name
Test status
Simulation time 387088459 ps
CPU time 6.89 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:34 PM PDT 24
Peak memory 241904 kb
Host smart-1e27cc2b-036a-4b58-b28e-03fcf3fc77d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983490893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.3983490893
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.3406074599
Short name T452
Test name
Test status
Simulation time 617557187 ps
CPU time 14.03 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 241684 kb
Host smart-0e6587e6-7039-4f28-9f54-82147d07d326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406074599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.3406074599
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.4233141736
Short name T595
Test name
Test status
Simulation time 37413982077 ps
CPU time 738.94 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 01:05:45 PM PDT 24
Peak memory 298040 kb
Host smart-6017a05c-a58a-47ef-9886-67baf9bc8f91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233141736 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.4233141736
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3430608454
Short name T652
Test name
Test status
Simulation time 3152432937 ps
CPU time 30.47 seconds
Started Jul 01 12:53:23 PM PDT 24
Finished Jul 01 12:53:55 PM PDT 24
Peak memory 242520 kb
Host smart-22c32dd5-113f-4f37-8080-50e5748ef491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430608454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3430608454
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.851638666
Short name T444
Test name
Test status
Simulation time 62217827 ps
CPU time 1.99 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:53:33 PM PDT 24
Peak memory 240400 kb
Host smart-2ccbc042-84d9-430d-a575-31bedf0b3f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851638666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.851638666
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.3986592396
Short name T289
Test name
Test status
Simulation time 227905458 ps
CPU time 4.57 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242124 kb
Host smart-4221bf93-0862-401e-b2fb-3081ebc3323d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986592396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.3986592396
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.4245872846
Short name T998
Test name
Test status
Simulation time 1468399241 ps
CPU time 44.04 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:54:09 PM PDT 24
Peak memory 247772 kb
Host smart-3a040a7d-d4c6-4a0c-a283-37d08f5cb1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245872846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.4245872846
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.2391350152
Short name T718
Test name
Test status
Simulation time 2166486818 ps
CPU time 21.84 seconds
Started Jul 01 12:53:25 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 242628 kb
Host smart-b703a2ae-3b38-41e5-9992-7719482d067e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391350152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.2391350152
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.1227220728
Short name T928
Test name
Test status
Simulation time 376029195 ps
CPU time 4.59 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:32 PM PDT 24
Peak memory 241948 kb
Host smart-3f9ab587-9caf-408d-b800-f57ada9f3ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227220728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.1227220728
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1695898305
Short name T210
Test name
Test status
Simulation time 16183356426 ps
CPU time 30.69 seconds
Started Jul 01 12:53:29 PM PDT 24
Finished Jul 01 12:54:01 PM PDT 24
Peak memory 247292 kb
Host smart-c1735ad0-3fda-4000-b078-4e5118148f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695898305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1695898305
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.3484713194
Short name T1116
Test name
Test status
Simulation time 3687403950 ps
CPU time 28.1 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:54:00 PM PDT 24
Peak memory 243400 kb
Host smart-ae504e5d-6c71-480b-81eb-bcdbf42aaf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484713194 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3484713194
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.2161553675
Short name T214
Test name
Test status
Simulation time 1187569544 ps
CPU time 3.4 seconds
Started Jul 01 12:53:24 PM PDT 24
Finished Jul 01 12:53:28 PM PDT 24
Peak memory 241972 kb
Host smart-eb3eba6d-2490-4f4e-8a20-d900bcdc7010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161553675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2161553675
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.2808489907
Short name T540
Test name
Test status
Simulation time 2427615739 ps
CPU time 6.85 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242200 kb
Host smart-20cb50ec-7e20-438a-8a6e-d52d6f99939d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2808489907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.2808489907
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1342680158
Short name T341
Test name
Test status
Simulation time 523772323 ps
CPU time 8.62 seconds
Started Jul 01 12:53:34 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 242076 kb
Host smart-9b91d6cd-535c-4853-99ae-6bb8c1b7608d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342680158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1342680158
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.2234335010
Short name T1127
Test name
Test status
Simulation time 278818632 ps
CPU time 9.71 seconds
Started Jul 01 12:53:26 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 242320 kb
Host smart-58ee5117-852e-45b6-b0e0-dcb1dc2dae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234335010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.2234335010
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.3910212322
Short name T575
Test name
Test status
Simulation time 11392371518 ps
CPU time 112.64 seconds
Started Jul 01 12:53:28 PM PDT 24
Finished Jul 01 12:55:21 PM PDT 24
Peak memory 260032 kb
Host smart-d64a60e1-b459-4951-9d8c-35ff6e0c68cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910212322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all
.3910212322
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.2545153252
Short name T632
Test name
Test status
Simulation time 365901669600 ps
CPU time 728.4 seconds
Started Jul 01 12:53:32 PM PDT 24
Finished Jul 01 01:05:41 PM PDT 24
Peak memory 265124 kb
Host smart-d5ed91fd-086e-4268-812e-8bf53e3fa9d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545153252 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2545153252
Directory /workspace/43.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.3596476443
Short name T418
Test name
Test status
Simulation time 22304522748 ps
CPU time 44.61 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:54:16 PM PDT 24
Peak memory 243328 kb
Host smart-442b5507-b72a-4cf0-8efc-5248ae4549f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596476443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.3596476443
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.941998677
Short name T386
Test name
Test status
Simulation time 107611464 ps
CPU time 1.93 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:36 PM PDT 24
Peak memory 240108 kb
Host smart-df58b0cc-e8a7-4d33-8ad0-8d3ec90545da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941998677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.941998677
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.142966755
Short name T82
Test name
Test status
Simulation time 2474990637 ps
CPU time 22.37 seconds
Started Jul 01 12:53:29 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 245736 kb
Host smart-32be72f2-c93a-40ad-a217-b19dde4a0a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142966755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.142966755
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.1657884373
Short name T743
Test name
Test status
Simulation time 2042295525 ps
CPU time 25.85 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:53:57 PM PDT 24
Peak memory 242212 kb
Host smart-16f07d7b-ba81-4370-9187-32b39b532d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657884373 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1657884373
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.924435286
Short name T827
Test name
Test status
Simulation time 1333964325 ps
CPU time 20.05 seconds
Started Jul 01 12:53:32 PM PDT 24
Finished Jul 01 12:53:53 PM PDT 24
Peak memory 242168 kb
Host smart-ae7982ea-e4d8-4307-84df-ca0f81ee1cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924435286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.924435286
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.630867996
Short name T892
Test name
Test status
Simulation time 147700982 ps
CPU time 4.65 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242328 kb
Host smart-d730dde7-b125-4292-9e53-cbc50bac041c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630867996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.630867996
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.58731481
Short name T771
Test name
Test status
Simulation time 1793341411 ps
CPU time 11.93 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:46 PM PDT 24
Peak memory 242460 kb
Host smart-c656f499-fa43-4284-9f9e-03085e0aecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58731481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.58731481
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2850261974
Short name T1184
Test name
Test status
Simulation time 15381047934 ps
CPU time 34.65 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:54:06 PM PDT 24
Peak memory 242584 kb
Host smart-26e15c66-34a2-4cf3-9cab-886995d8d7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850261974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2850261974
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.3379684076
Short name T664
Test name
Test status
Simulation time 157131816 ps
CPU time 6.47 seconds
Started Jul 01 12:53:29 PM PDT 24
Finished Jul 01 12:53:36 PM PDT 24
Peak memory 241836 kb
Host smart-ca82dbe1-3e9a-4b97-b2c7-09cacdd9b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379684076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.3379684076
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3251771843
Short name T442
Test name
Test status
Simulation time 701716849 ps
CPU time 21.8 seconds
Started Jul 01 12:53:29 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 242020 kb
Host smart-3ce93e07-165b-4770-bed5-1fc9531ed764
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3251771843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3251771843
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.4143117295
Short name T342
Test name
Test status
Simulation time 269295197 ps
CPU time 8.46 seconds
Started Jul 01 12:53:31 PM PDT 24
Finished Jul 01 12:53:40 PM PDT 24
Peak memory 242060 kb
Host smart-1e4de8d6-ec4f-4e07-829e-b97a9f8081c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4143117295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.4143117295
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1433750687
Short name T1015
Test name
Test status
Simulation time 513009955 ps
CPU time 11.1 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:45 PM PDT 24
Peak memory 242360 kb
Host smart-37d08f24-02d9-4814-91da-a6fa41d444ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433750687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1433750687
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3012319899
Short name T558
Test name
Test status
Simulation time 1054161049810 ps
CPU time 2080.95 seconds
Started Jul 01 12:53:28 PM PDT 24
Finished Jul 01 01:28:10 PM PDT 24
Peak memory 343476 kb
Host smart-2f097277-3319-474b-b034-78fa102c29a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012319899 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.3012319899
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.3268993440
Short name T947
Test name
Test status
Simulation time 481576921 ps
CPU time 5.41 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:53:37 PM PDT 24
Peak memory 242068 kb
Host smart-4123c7e9-9166-4a02-87eb-262f2cad7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268993440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3268993440
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.2872065588
Short name T592
Test name
Test status
Simulation time 47512887 ps
CPU time 1.64 seconds
Started Jul 01 12:53:37 PM PDT 24
Finished Jul 01 12:53:40 PM PDT 24
Peak memory 240356 kb
Host smart-d767feb1-d97b-4807-b1d6-35270fc6f7a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872065588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.2872065588
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.741636686
Short name T1125
Test name
Test status
Simulation time 588621012 ps
CPU time 13.05 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:50 PM PDT 24
Peak memory 242104 kb
Host smart-6e045992-88ee-4244-bb3e-ea8b42097453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741636686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.741636686
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.1892389362
Short name T826
Test name
Test status
Simulation time 1079435136 ps
CPU time 18.14 seconds
Started Jul 01 12:53:37 PM PDT 24
Finished Jul 01 12:53:56 PM PDT 24
Peak memory 242216 kb
Host smart-818777ef-df31-49e9-9362-eb84144f0d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892389362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.1892389362
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1219885713
Short name T1133
Test name
Test status
Simulation time 126450199 ps
CPU time 4.53 seconds
Started Jul 01 12:53:30 PM PDT 24
Finished Jul 01 12:53:36 PM PDT 24
Peak memory 242324 kb
Host smart-fa78a407-53b0-45d1-bb02-9ecad0ce71da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219885713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1219885713
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.1963538221
Short name T1166
Test name
Test status
Simulation time 1052555884 ps
CPU time 19.81 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:57 PM PDT 24
Peak memory 243464 kb
Host smart-45998575-8d32-41e4-8741-6f1d80be506b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963538221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1963538221
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.1387618766
Short name T842
Test name
Test status
Simulation time 17493980322 ps
CPU time 41.85 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 248848 kb
Host smart-24ea3e49-7733-4171-bafa-7405c2a0dcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387618766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1387618766
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.1412152045
Short name T136
Test name
Test status
Simulation time 155382834 ps
CPU time 6.71 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:44 PM PDT 24
Peak memory 242268 kb
Host smart-6e96d7e1-b337-4f59-8f86-d9c138b17d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412152045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.1412152045
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2182509303
Short name T534
Test name
Test status
Simulation time 698173525 ps
CPU time 11.6 seconds
Started Jul 01 12:53:33 PM PDT 24
Finished Jul 01 12:53:46 PM PDT 24
Peak memory 242492 kb
Host smart-d3c91029-a666-46bc-88f9-25313495d0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182509303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2182509303
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.774078198
Short name T847
Test name
Test status
Simulation time 79188897826 ps
CPU time 136.4 seconds
Started Jul 01 12:53:34 PM PDT 24
Finished Jul 01 12:55:51 PM PDT 24
Peak memory 246604 kb
Host smart-8c8d16c2-b227-4d81-adc9-5244f07c18e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774078198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.
774078198
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2648425246
Short name T686
Test name
Test status
Simulation time 297876030626 ps
CPU time 1715.55 seconds
Started Jul 01 12:53:36 PM PDT 24
Finished Jul 01 01:22:14 PM PDT 24
Peak memory 271484 kb
Host smart-f4ed0521-b574-4553-bae8-6c034755ef27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648425246 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.2648425246
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.1413273603
Short name T13
Test name
Test status
Simulation time 7850105319 ps
CPU time 17.41 seconds
Started Jul 01 12:53:34 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 242100 kb
Host smart-88641609-8f4e-4143-a8bb-9ac0a72bf557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413273603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1413273603
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.975582531
Short name T1156
Test name
Test status
Simulation time 84054566 ps
CPU time 1.57 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 240168 kb
Host smart-c0931b5a-4881-4a3b-ae10-3afa4fe5f170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975582531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.975582531
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.911187902
Short name T62
Test name
Test status
Simulation time 853714556 ps
CPU time 10.34 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 248772 kb
Host smart-27c629a6-f279-4621-9d20-c2cc58d0c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911187902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.911187902
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.914167155
Short name T640
Test name
Test status
Simulation time 1155803608 ps
CPU time 10.23 seconds
Started Jul 01 12:53:36 PM PDT 24
Finished Jul 01 12:53:48 PM PDT 24
Peak memory 242036 kb
Host smart-6b16d2bb-2ea4-49ba-880f-87aa7e61a41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914167155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.914167155
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.357430742
Short name T958
Test name
Test status
Simulation time 787938299 ps
CPU time 12.73 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:50 PM PDT 24
Peak memory 242428 kb
Host smart-49a6577d-83e0-4091-946e-fed951d8b5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357430742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.357430742
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.2855476264
Short name T37
Test name
Test status
Simulation time 441423838 ps
CPU time 4.35 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242084 kb
Host smart-321db826-b521-48e4-9e28-d81c3bdee0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855476264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.2855476264
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3015243006
Short name T446
Test name
Test status
Simulation time 832934743 ps
CPU time 7.47 seconds
Started Jul 01 12:53:37 PM PDT 24
Finished Jul 01 12:53:46 PM PDT 24
Peak memory 242440 kb
Host smart-2a1a90d0-162b-4faa-b05b-6c1a253db3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015243006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3015243006
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.2106200931
Short name T466
Test name
Test status
Simulation time 2618496719 ps
CPU time 15.73 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:53 PM PDT 24
Peak memory 242300 kb
Host smart-21ea55c3-aef2-4533-82bf-d0817c9f6497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106200931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2106200931
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1865701238
Short name T1120
Test name
Test status
Simulation time 123273972 ps
CPU time 5.03 seconds
Started Jul 01 12:53:36 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 242236 kb
Host smart-d54ae2b7-8c6a-458f-9a81-45c972a941af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865701238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1865701238
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.1712113791
Short name T116
Test name
Test status
Simulation time 9874850970 ps
CPU time 27.4 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:54:04 PM PDT 24
Peak memory 248800 kb
Host smart-dd99cf54-06a7-40b9-888b-e9973d870847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712113791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1712113791
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.470450587
Short name T720
Test name
Test status
Simulation time 919029962 ps
CPU time 9.54 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 242084 kb
Host smart-bdeb780c-7f81-4033-8503-4c42b922c200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470450587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.470450587
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.2710724500
Short name T839
Test name
Test status
Simulation time 242485747 ps
CPU time 5.03 seconds
Started Jul 01 12:53:35 PM PDT 24
Finished Jul 01 12:53:41 PM PDT 24
Peak memory 242244 kb
Host smart-d231abd7-ba9e-4bb4-bc7a-e8a918669e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710724500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.2710724500
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.150238735
Short name T15
Test name
Test status
Simulation time 542983501304 ps
CPU time 2439.42 seconds
Started Jul 01 12:53:41 PM PDT 24
Finished Jul 01 01:34:22 PM PDT 24
Peak memory 371840 kb
Host smart-0ba9e974-c013-4fb4-b803-57c726a1dbae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150238735 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.150238735
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.664018008
Short name T1160
Test name
Test status
Simulation time 1679462003 ps
CPU time 17.81 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 242600 kb
Host smart-c41ba79d-6313-4edd-a231-17df2400ea63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664018008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.664018008
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2977758870
Short name T658
Test name
Test status
Simulation time 740357068 ps
CPU time 2.61 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 240236 kb
Host smart-37392e7a-f436-4d99-8d9b-cf74429ea038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977758870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2977758870
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.1135285081
Short name T1021
Test name
Test status
Simulation time 193793537 ps
CPU time 4.6 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:53:46 PM PDT 24
Peak memory 242540 kb
Host smart-30c845fc-b3fd-4bba-af98-f3a548810f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135285081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1135285081
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.1530976414
Short name T762
Test name
Test status
Simulation time 14180331879 ps
CPU time 52.77 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:54:35 PM PDT 24
Peak memory 246244 kb
Host smart-49eb37c3-ec4d-49f4-a3de-643012780d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530976414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1530976414
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.551208365
Short name T981
Test name
Test status
Simulation time 2683323020 ps
CPU time 28.95 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:54:09 PM PDT 24
Peak memory 248876 kb
Host smart-25668b08-28ef-4b63-b5b8-e9f4949f671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551208365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.551208365
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.1678555717
Short name T617
Test name
Test status
Simulation time 317723507 ps
CPU time 3.72 seconds
Started Jul 01 12:53:43 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 242152 kb
Host smart-c51282b2-69b4-49e8-ba86-d2b8fb4ad81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678555717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1678555717
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2452023139
Short name T152
Test name
Test status
Simulation time 7870123061 ps
CPU time 27.61 seconds
Started Jul 01 12:53:41 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 245820 kb
Host smart-56ca7897-5d4c-4fab-9b26-995ca954e3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452023139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2452023139
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.3354470270
Short name T791
Test name
Test status
Simulation time 2166666090 ps
CPU time 29.04 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:54:11 PM PDT 24
Peak memory 242236 kb
Host smart-fcad118b-dbec-4afc-92a9-b70f103f8aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354470270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3354470270
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.4078216140
Short name T310
Test name
Test status
Simulation time 467875586 ps
CPU time 5.4 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:53:47 PM PDT 24
Peak memory 241816 kb
Host smart-3aa35ccd-158b-4574-9e2e-e7cc2b0be88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078216140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.4078216140
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.939151608
Short name T1083
Test name
Test status
Simulation time 896267470 ps
CPU time 8.29 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 241888 kb
Host smart-8c1f6a88-b22a-41f7-9e16-09ef9d58aeb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939151608 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.939151608
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.2140721549
Short name T343
Test name
Test status
Simulation time 107954440 ps
CPU time 3.36 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:44 PM PDT 24
Peak memory 247596 kb
Host smart-160bf95b-2f15-447f-918e-1c72e1d034f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140721549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2140721549
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.1573285693
Short name T918
Test name
Test status
Simulation time 1404603908 ps
CPU time 12.37 seconds
Started Jul 01 12:53:43 PM PDT 24
Finished Jul 01 12:53:56 PM PDT 24
Peak memory 241960 kb
Host smart-d42cea90-0525-43c0-a97e-f9fd104e6c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573285693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1573285693
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2596731581
Short name T1091
Test name
Test status
Simulation time 81196609588 ps
CPU time 267.85 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 12:58:09 PM PDT 24
Peak memory 261292 kb
Host smart-1633ca92-b51b-44ad-ba4e-455d809a3e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596731581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2596731581
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.387222653
Short name T810
Test name
Test status
Simulation time 140903549094 ps
CPU time 382.4 seconds
Started Jul 01 12:53:40 PM PDT 24
Finished Jul 01 01:00:04 PM PDT 24
Peak memory 257012 kb
Host smart-6b803345-f764-4d35-b7c6-18bfd55e2a6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387222653 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.387222653
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.904925116
Short name T675
Test name
Test status
Simulation time 742871509 ps
CPU time 7.97 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 242232 kb
Host smart-b2ed5a03-721d-477f-920b-5ec1921f7d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904925116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.904925116
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.414163415
Short name T410
Test name
Test status
Simulation time 852274079 ps
CPU time 1.99 seconds
Started Jul 01 12:53:46 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 240392 kb
Host smart-5ca43f44-c8ed-4ca9-ad9e-c17f88877c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414163415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.414163415
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.1345488030
Short name T54
Test name
Test status
Simulation time 2292888941 ps
CPU time 15.9 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:54:02 PM PDT 24
Peak memory 248872 kb
Host smart-11c32cda-893d-47d5-bd40-90b2b7aa9b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345488030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1345488030
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.2898985315
Short name T321
Test name
Test status
Simulation time 4286288450 ps
CPU time 18.74 seconds
Started Jul 01 12:53:44 PM PDT 24
Finished Jul 01 12:54:03 PM PDT 24
Peak memory 241784 kb
Host smart-88953a8d-fc0c-4b01-83c2-3f1feac07c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898985315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.2898985315
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.845749797
Short name T744
Test name
Test status
Simulation time 1882337990 ps
CPU time 21.93 seconds
Started Jul 01 12:53:41 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 242300 kb
Host smart-d2cd2034-2017-45ce-9ca4-e345bc7e127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845749797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.845749797
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1566389007
Short name T563
Test name
Test status
Simulation time 128604996 ps
CPU time 4.67 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:45 PM PDT 24
Peak memory 242112 kb
Host smart-9cf71921-2fbe-410b-a8d9-6ef5a023b4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566389007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1566389007
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1417953662
Short name T568
Test name
Test status
Simulation time 19077343739 ps
CPU time 53.15 seconds
Started Jul 01 12:53:44 PM PDT 24
Finished Jul 01 12:54:38 PM PDT 24
Peak memory 247600 kb
Host smart-20a5f807-2f2a-40c9-9599-7d59b00a2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417953662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1417953662
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.2281525889
Short name T1126
Test name
Test status
Simulation time 2689186868 ps
CPU time 31.82 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:54:18 PM PDT 24
Peak memory 242548 kb
Host smart-059c6b7e-e5d0-459a-8874-cac05fe6be5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281525889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2281525889
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2735279944
Short name T504
Test name
Test status
Simulation time 165168404 ps
CPU time 2.9 seconds
Started Jul 01 12:53:38 PM PDT 24
Finished Jul 01 12:53:43 PM PDT 24
Peak memory 241636 kb
Host smart-43f9e634-26e4-4672-9a91-928dcd9fa5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735279944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2735279944
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.1395397949
Short name T1187
Test name
Test status
Simulation time 600924149 ps
CPU time 18.51 seconds
Started Jul 01 12:53:41 PM PDT 24
Finished Jul 01 12:54:01 PM PDT 24
Peak memory 241668 kb
Host smart-151c4eed-0319-4c3b-a84f-a337d0100655
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395397949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.1395397949
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.875765033
Short name T1153
Test name
Test status
Simulation time 265377726 ps
CPU time 4.71 seconds
Started Jul 01 12:53:44 PM PDT 24
Finished Jul 01 12:53:49 PM PDT 24
Peak memory 242104 kb
Host smart-8a76d2fa-8bd8-4cde-9d6f-8fb6e71a6a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875765033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.875765033
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1005056251
Short name T797
Test name
Test status
Simulation time 684935360 ps
CPU time 5.76 seconds
Started Jul 01 12:53:39 PM PDT 24
Finished Jul 01 12:53:46 PM PDT 24
Peak memory 248800 kb
Host smart-39e164a2-096e-4903-8fc9-af5578e25d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005056251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1005056251
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2513903714
Short name T117
Test name
Test status
Simulation time 71175712956 ps
CPU time 324.47 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:59:11 PM PDT 24
Peak memory 264884 kb
Host smart-91f51672-bac9-4352-839e-91d7ce443fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513903714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2513903714
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.420096645
Short name T253
Test name
Test status
Simulation time 715746800805 ps
CPU time 2203.74 seconds
Started Jul 01 12:53:46 PM PDT 24
Finished Jul 01 01:30:31 PM PDT 24
Peak memory 292296 kb
Host smart-0f547685-a235-493b-9bc6-8e7f25a98856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420096645 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.420096645
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.2956887931
Short name T795
Test name
Test status
Simulation time 432594510 ps
CPU time 12.44 seconds
Started Jul 01 12:53:46 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 248768 kb
Host smart-9470050d-35cb-4936-bcae-ef078d01a71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956887931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.2956887931
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.420898376
Short name T511
Test name
Test status
Simulation time 46183147 ps
CPU time 1.76 seconds
Started Jul 01 12:53:57 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 240020 kb
Host smart-ca82becf-bf5e-48d7-a1fa-794c2055cd24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420898376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.420898376
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.2426986556
Short name T59
Test name
Test status
Simulation time 3462098898 ps
CPU time 39.39 seconds
Started Jul 01 12:53:44 PM PDT 24
Finished Jul 01 12:54:24 PM PDT 24
Peak memory 248856 kb
Host smart-7662eb31-ccd4-45bf-8fd9-5e3b47e184bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426986556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2426986556
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.366069551
Short name T125
Test name
Test status
Simulation time 3930887954 ps
CPU time 36.87 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 246552 kb
Host smart-d125ee6f-af9a-481c-9a44-7e16f1d23586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366069551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.366069551
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.4211578535
Short name T989
Test name
Test status
Simulation time 3340792864 ps
CPU time 33.96 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:54:20 PM PDT 24
Peak memory 242328 kb
Host smart-382ff418-48f4-428e-ae49-1d3412e3052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211578535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.4211578535
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.2012901124
Short name T1066
Test name
Test status
Simulation time 544509252 ps
CPU time 4.59 seconds
Started Jul 01 12:53:47 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 242016 kb
Host smart-b764d834-d758-42a1-a360-c031b9518843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012901124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.2012901124
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.1550154128
Short name T465
Test name
Test status
Simulation time 638604228 ps
CPU time 8.38 seconds
Started Jul 01 12:53:49 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 242516 kb
Host smart-f19ab1a3-3144-4144-89bb-981793add9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550154128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.1550154128
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.654358437
Short name T845
Test name
Test status
Simulation time 1082615810 ps
CPU time 27.75 seconds
Started Jul 01 12:53:50 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 242224 kb
Host smart-5bdcdf71-0228-4f9d-9829-c7db2bd0887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654358437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.654358437
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.251862911
Short name T1017
Test name
Test status
Simulation time 266217314 ps
CPU time 6.38 seconds
Started Jul 01 12:53:47 PM PDT 24
Finished Jul 01 12:53:54 PM PDT 24
Peak memory 242216 kb
Host smart-47cef0b2-57c3-48f5-a580-284aaad659f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251862911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.251862911
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.195740491
Short name T916
Test name
Test status
Simulation time 980973381 ps
CPU time 19.53 seconds
Started Jul 01 12:53:45 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 241812 kb
Host smart-0ecaddf2-657c-40e4-b829-6b513979133c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195740491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.195740491
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.3875825746
Short name T346
Test name
Test status
Simulation time 196520631 ps
CPU time 6.13 seconds
Started Jul 01 12:53:50 PM PDT 24
Finished Jul 01 12:53:56 PM PDT 24
Peak memory 242340 kb
Host smart-29e6daf5-ad4b-41f5-8d05-4808b344a118
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875825746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3875825746
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.1173214408
Short name T388
Test name
Test status
Simulation time 3653075189 ps
CPU time 6.21 seconds
Started Jul 01 12:53:44 PM PDT 24
Finished Jul 01 12:53:52 PM PDT 24
Peak memory 242224 kb
Host smart-57033bed-feae-40e7-80c3-de7078004a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173214408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1173214408
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.21016503
Short name T948
Test name
Test status
Simulation time 7786901862 ps
CPU time 85.04 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:55:17 PM PDT 24
Peak memory 248760 kb
Host smart-8c063a0f-194f-42cf-9ede-3a039527ab53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21016503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.21016503
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.2931880400
Short name T365
Test name
Test status
Simulation time 22123320165 ps
CPU time 49.59 seconds
Started Jul 01 12:53:57 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 243124 kb
Host smart-af1fc8f5-d5e3-4868-a73d-88a38901d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931880400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2931880400
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.3204762737
Short name T669
Test name
Test status
Simulation time 140952102 ps
CPU time 2.01 seconds
Started Jul 01 12:51:20 PM PDT 24
Finished Jul 01 12:51:23 PM PDT 24
Peak memory 240468 kb
Host smart-9b926e21-bd16-4fe7-b6a1-d671e2ff3f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204762737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.3204762737
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.3828652105
Short name T811
Test name
Test status
Simulation time 248867104 ps
CPU time 8.69 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:28 PM PDT 24
Peak memory 242244 kb
Host smart-f0590a55-bdcf-4e57-a6e1-3bcc79635507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828652105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3828652105
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2173006509
Short name T193
Test name
Test status
Simulation time 459513103 ps
CPU time 8.52 seconds
Started Jul 01 12:51:21 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 242324 kb
Host smart-259b2f90-efef-4d6c-9254-e5405c1c9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173006509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2173006509
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.1651829859
Short name T469
Test name
Test status
Simulation time 2078009463 ps
CPU time 26.21 seconds
Started Jul 01 12:51:22 PM PDT 24
Finished Jul 01 12:51:50 PM PDT 24
Peak memory 242988 kb
Host smart-065117bb-2029-4a67-a9c9-b3bcead89eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651829859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1651829859
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.4058300551
Short name T1168
Test name
Test status
Simulation time 1196430005 ps
CPU time 17.89 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:37 PM PDT 24
Peak memory 242584 kb
Host smart-c834fceb-a58d-4208-b576-5f7bdedbe615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058300551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4058300551
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3066659251
Short name T203
Test name
Test status
Simulation time 363433319 ps
CPU time 3.73 seconds
Started Jul 01 12:51:12 PM PDT 24
Finished Jul 01 12:51:17 PM PDT 24
Peak memory 242060 kb
Host smart-7ff1dc18-d0e0-4726-9734-15a884bdf80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066659251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3066659251
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.152042653
Short name T147
Test name
Test status
Simulation time 5028833685 ps
CPU time 33.67 seconds
Started Jul 01 12:51:22 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 257084 kb
Host smart-842cbc9c-425c-476d-941b-60db9665e60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152042653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.152042653
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.2873182609
Short name T769
Test name
Test status
Simulation time 633729266 ps
CPU time 9.29 seconds
Started Jul 01 12:51:25 PM PDT 24
Finished Jul 01 12:51:36 PM PDT 24
Peak memory 242076 kb
Host smart-2d4e7f30-e455-4857-8858-7e54ba61f518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873182609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2873182609
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.4127765317
Short name T140
Test name
Test status
Simulation time 2118730220 ps
CPU time 6.86 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 241936 kb
Host smart-214597fd-cf1a-4e4f-9eb1-408e2443304b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127765317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4127765317
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.1405473847
Short name T1095
Test name
Test status
Simulation time 5613012628 ps
CPU time 12.64 seconds
Started Jul 01 12:51:16 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 241912 kb
Host smart-f9b11376-a973-42b5-b6ad-e217e5615ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405473847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1405473847
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.2733870734
Short name T1032
Test name
Test status
Simulation time 690982020 ps
CPU time 11.67 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 242020 kb
Host smart-78fd0158-08d5-41af-b7cd-7e77924ccb16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733870734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2733870734
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1427547949
Short name T763
Test name
Test status
Simulation time 312856225 ps
CPU time 4.51 seconds
Started Jul 01 12:51:13 PM PDT 24
Finished Jul 01 12:51:19 PM PDT 24
Peak memory 242184 kb
Host smart-f7c1b75c-12bd-41f8-b3a3-e5d3b7ffe0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427547949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1427547949
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1166746590
Short name T752
Test name
Test status
Simulation time 10009656768 ps
CPU time 269.59 seconds
Started Jul 01 12:51:18 PM PDT 24
Finished Jul 01 12:55:49 PM PDT 24
Peak memory 257112 kb
Host smart-61ef8327-c7e5-4ce1-8c14-74554e31a6b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166746590 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1166746590
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.2560779536
Short name T613
Test name
Test status
Simulation time 430528047 ps
CPU time 13.75 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:32 PM PDT 24
Peak memory 242296 kb
Host smart-1c01758a-9ccc-41f3-a25b-8f7a4e566d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560779536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2560779536
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.792613258
Short name T961
Test name
Test status
Simulation time 291042975 ps
CPU time 3.71 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:53:57 PM PDT 24
Peak memory 241904 kb
Host smart-b53cb72a-a9bf-4aa5-9b3b-93a0df9d4db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792613258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.792613258
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.3391829197
Short name T873
Test name
Test status
Simulation time 212420261 ps
CPU time 5.39 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 241960 kb
Host smart-03dadb3a-eaa6-4664-b386-463c4ece8d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391829197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.3391829197
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.2659503542
Short name T1180
Test name
Test status
Simulation time 106905385888 ps
CPU time 404.45 seconds
Started Jul 01 12:53:49 PM PDT 24
Finished Jul 01 01:00:35 PM PDT 24
Peak memory 257080 kb
Host smart-a0530af2-d254-4cd2-bac9-7a80acec1dcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659503542 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.2659503542
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.2822720002
Short name T808
Test name
Test status
Simulation time 244958891 ps
CPU time 5.47 seconds
Started Jul 01 12:53:49 PM PDT 24
Finished Jul 01 12:53:55 PM PDT 24
Peak memory 242144 kb
Host smart-2bcbf1ea-00b2-4308-938f-59064bb131d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822720002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2822720002
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.2104032094
Short name T235
Test name
Test status
Simulation time 362331603 ps
CPU time 7.4 seconds
Started Jul 01 12:53:51 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 241648 kb
Host smart-d1c21a6f-8810-48bb-a234-2a3a7c81da94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104032094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.2104032094
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.2894190409
Short name T12
Test name
Test status
Simulation time 1163005916430 ps
CPU time 2084.06 seconds
Started Jul 01 12:53:50 PM PDT 24
Finished Jul 01 01:28:35 PM PDT 24
Peak memory 478900 kb
Host smart-94f56588-77b9-44bc-bfb3-edb3ba61a85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894190409 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.2894190409
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.3569474007
Short name T703
Test name
Test status
Simulation time 107866462 ps
CPU time 4.02 seconds
Started Jul 01 12:53:49 PM PDT 24
Finished Jul 01 12:53:53 PM PDT 24
Peak memory 241932 kb
Host smart-f2b686c6-721f-4843-ba62-0f6260297cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569474007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3569474007
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.3996453025
Short name T557
Test name
Test status
Simulation time 271699691 ps
CPU time 6.58 seconds
Started Jul 01 12:53:51 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 242176 kb
Host smart-bd8eb023-c23c-4413-adc7-ce5efe28e707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996453025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3996453025
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.566948334
Short name T985
Test name
Test status
Simulation time 51348006426 ps
CPU time 724.39 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 01:05:58 PM PDT 24
Peak memory 295328 kb
Host smart-5d146c7b-f154-4396-b017-b52ad92f179d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566948334 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.566948334
Directory /workspace/52.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.2527763206
Short name T380
Test name
Test status
Simulation time 229297985 ps
CPU time 4.66 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 241876 kb
Host smart-a60b803f-3ceb-4142-92f2-909178919097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527763206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.2527763206
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.893591058
Short name T529
Test name
Test status
Simulation time 261544399 ps
CPU time 13.56 seconds
Started Jul 01 12:53:50 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 242372 kb
Host smart-723da998-6c17-4f2c-8ff8-1e00e6b2ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893591058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.893591058
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3610467140
Short name T1048
Test name
Test status
Simulation time 106398771682 ps
CPU time 642.42 seconds
Started Jul 01 12:53:48 PM PDT 24
Finished Jul 01 01:04:31 PM PDT 24
Peak memory 265256 kb
Host smart-35280968-3f99-41b9-8398-cf76e3b566dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610467140 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.3610467140
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.3222438441
Short name T792
Test name
Test status
Simulation time 142138382 ps
CPU time 4.3 seconds
Started Jul 01 12:53:50 PM PDT 24
Finished Jul 01 12:53:55 PM PDT 24
Peak memory 242152 kb
Host smart-b52d0b3a-b516-4899-9ede-b147ef8ca794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222438441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.3222438441
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.3737103191
Short name T820
Test name
Test status
Simulation time 240199086 ps
CPU time 7.45 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:54:00 PM PDT 24
Peak memory 241952 kb
Host smart-5588641c-1b04-4e34-b9a2-2480e10a5e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737103191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3737103191
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.826890792
Short name T497
Test name
Test status
Simulation time 153437413 ps
CPU time 4.02 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 241836 kb
Host smart-7edfec95-7900-4eda-a0b7-9dd20db5d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826890792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.826890792
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.4269056247
Short name T1141
Test name
Test status
Simulation time 1134841119 ps
CPU time 14.37 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:54:08 PM PDT 24
Peak memory 242120 kb
Host smart-7b3f53b7-a53d-43c4-a3ff-1e2e918c95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269056247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.4269056247
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.2908072466
Short name T693
Test name
Test status
Simulation time 154754897 ps
CPU time 3.39 seconds
Started Jul 01 12:53:56 PM PDT 24
Finished Jul 01 12:54:00 PM PDT 24
Peak memory 241924 kb
Host smart-368c014a-5cd0-4bc0-bcee-39f5c59d3aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908072466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.2908072466
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.653778257
Short name T566
Test name
Test status
Simulation time 214472741 ps
CPU time 5.77 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:54:01 PM PDT 24
Peak memory 241840 kb
Host smart-f9067865-e78f-4962-afdd-3c71f5772044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653778257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.653778257
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.63510690
Short name T1090
Test name
Test status
Simulation time 2186144036 ps
CPU time 6.05 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:54:01 PM PDT 24
Peak memory 242552 kb
Host smart-814390db-15bc-4a15-874c-1546f4ab32b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63510690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.63510690
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.2331030281
Short name T627
Test name
Test status
Simulation time 364602578 ps
CPU time 9.53 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 242272 kb
Host smart-613b55d0-954e-491f-be8c-baf70ad262d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331030281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2331030281
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3758406951
Short name T318
Test name
Test status
Simulation time 64649952465 ps
CPU time 379.4 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 01:00:15 PM PDT 24
Peak memory 273736 kb
Host smart-b5c72f23-9699-4af0-862e-8d164879560f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758406951 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3758406951
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.4162212253
Short name T1006
Test name
Test status
Simulation time 469384634 ps
CPU time 3.37 seconds
Started Jul 01 12:53:52 PM PDT 24
Finished Jul 01 12:53:57 PM PDT 24
Peak memory 242120 kb
Host smart-7f5847a1-8670-4c25-aa56-a5ec4fd7add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162212253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.4162212253
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2733365111
Short name T515
Test name
Test status
Simulation time 430651824 ps
CPU time 10.23 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:54:04 PM PDT 24
Peak memory 242052 kb
Host smart-74f3c553-86fb-4668-8c36-c761f278dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733365111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2733365111
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.3494970117
Short name T858
Test name
Test status
Simulation time 736895451717 ps
CPU time 1588.54 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 01:20:29 PM PDT 24
Peak memory 452088 kb
Host smart-d3a76df9-644d-42cf-a195-19bcb34a9121
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494970117 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.3494970117
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2100451058
Short name T556
Test name
Test status
Simulation time 272785688 ps
CPU time 4.52 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:53:59 PM PDT 24
Peak memory 241936 kb
Host smart-b1eebcfd-0b33-4226-98c4-8224a6cadbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100451058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2100451058
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.1631669157
Short name T704
Test name
Test status
Simulation time 5117783340 ps
CPU time 14.43 seconds
Started Jul 01 12:53:55 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 241916 kb
Host smart-a3e2309f-e68f-406c-b4ef-433314c21256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631669157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.1631669157
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3596295806
Short name T313
Test name
Test status
Simulation time 927949012979 ps
CPU time 2305.34 seconds
Started Jul 01 12:53:55 PM PDT 24
Finished Jul 01 01:32:21 PM PDT 24
Peak memory 517252 kb
Host smart-fd4703b8-11a7-4f1a-908b-4e0510af119e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596295806 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3596295806
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.3616323705
Short name T1040
Test name
Test status
Simulation time 166417395 ps
CPU time 1.73 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:29 PM PDT 24
Peak memory 240100 kb
Host smart-1c2e62f9-7719-4c2c-b280-66ff23186ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616323705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3616323705
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.2777719607
Short name T364
Test name
Test status
Simulation time 3274919226 ps
CPU time 22.46 seconds
Started Jul 01 12:51:18 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 248864 kb
Host smart-bd8766f4-62bb-49ba-b2b2-88d54b012e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777719607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2777719607
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.2267748253
Short name T196
Test name
Test status
Simulation time 584206722 ps
CPU time 8.95 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 242276 kb
Host smart-6f345b18-c655-4d98-998b-6382956ee543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267748253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.2267748253
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.344307170
Short name T651
Test name
Test status
Simulation time 747234743 ps
CPU time 11.72 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:30 PM PDT 24
Peak memory 241848 kb
Host smart-8f531b4e-b089-4cd7-b778-d592b5d74802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344307170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.344307170
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.635110421
Short name T1001
Test name
Test status
Simulation time 1026384116 ps
CPU time 12.3 seconds
Started Jul 01 12:51:20 PM PDT 24
Finished Jul 01 12:51:34 PM PDT 24
Peak memory 242140 kb
Host smart-7b1b3e80-1f3d-46b3-9b6d-ff413baed7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635110421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.635110421
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.892198208
Short name T809
Test name
Test status
Simulation time 246715053 ps
CPU time 2.95 seconds
Started Jul 01 12:51:19 PM PDT 24
Finished Jul 01 12:51:24 PM PDT 24
Peak memory 241992 kb
Host smart-05f3f66c-20d1-416d-900d-53b064929e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892198208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.892198208
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.892718523
Short name T183
Test name
Test status
Simulation time 7873853445 ps
CPU time 66.98 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:52:33 PM PDT 24
Peak memory 256904 kb
Host smart-e29386c5-1a01-4e41-ba1f-c11296017f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892718523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.892718523
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.3001042776
Short name T189
Test name
Test status
Simulation time 9974771060 ps
CPU time 35.6 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:52:01 PM PDT 24
Peak memory 248796 kb
Host smart-b79930ed-0e19-4485-95f1-1aae54cdc774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001042776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.3001042776
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.527556459
Short name T770
Test name
Test status
Simulation time 539227283 ps
CPU time 5.24 seconds
Started Jul 01 12:51:18 PM PDT 24
Finished Jul 01 12:51:25 PM PDT 24
Peak memory 241772 kb
Host smart-5220e885-e4a4-442c-90e6-cd069962be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527556459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.527556459
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.3017609724
Short name T500
Test name
Test status
Simulation time 272985335 ps
CPU time 9.46 seconds
Started Jul 01 12:51:17 PM PDT 24
Finished Jul 01 12:51:28 PM PDT 24
Peak memory 241996 kb
Host smart-6cb3a898-da72-4b1a-9dda-4ed4c315c528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3017609724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3017609724
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3854369491
Short name T1182
Test name
Test status
Simulation time 634032936 ps
CPU time 8.94 seconds
Started Jul 01 12:51:23 PM PDT 24
Finished Jul 01 12:51:33 PM PDT 24
Peak memory 242012 kb
Host smart-d0bd99b3-928b-4e84-af13-3291fd99d46c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854369491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3854369491
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.3332089906
Short name T412
Test name
Test status
Simulation time 733743181 ps
CPU time 6.33 seconds
Started Jul 01 12:51:15 PM PDT 24
Finished Jul 01 12:51:23 PM PDT 24
Peak memory 242416 kb
Host smart-d1341561-62c7-4776-ae87-c004eb721971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332089906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.3332089906
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.620374150
Short name T908
Test name
Test status
Simulation time 4730730519 ps
CPU time 73.56 seconds
Started Jul 01 12:51:23 PM PDT 24
Finished Jul 01 12:52:38 PM PDT 24
Peak memory 248732 kb
Host smart-37d0a8cc-93d8-4435-8d4d-be9368755ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620374150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.620374150
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.1747119540
Short name T877
Test name
Test status
Simulation time 334740596967 ps
CPU time 825.65 seconds
Started Jul 01 12:51:22 PM PDT 24
Finished Jul 01 01:05:10 PM PDT 24
Peak memory 295144 kb
Host smart-2722eee0-fc1f-4b79-aed3-ed5e52ab79ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747119540 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.1747119540
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1690378745
Short name T262
Test name
Test status
Simulation time 1607994560 ps
CPU time 29.24 seconds
Started Jul 01 12:51:25 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 248800 kb
Host smart-67731159-4f58-4e42-91b2-f46c4a130c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690378745 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1690378745
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.4284768866
Short name T859
Test name
Test status
Simulation time 168146018 ps
CPU time 3.38 seconds
Started Jul 01 12:53:54 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 241820 kb
Host smart-21bc3427-fe2b-41e0-8c1d-03a7b1ce9742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284768866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.4284768866
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.741380616
Short name T226
Test name
Test status
Simulation time 8847515954 ps
CPU time 18.26 seconds
Started Jul 01 12:53:53 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 242380 kb
Host smart-dd012119-4e08-48cc-ad29-71e35a34bc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741380616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.741380616
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1923853605
Short name T520
Test name
Test status
Simulation time 1842411555 ps
CPU time 4.24 seconds
Started Jul 01 12:53:53 PM PDT 24
Finished Jul 01 12:53:58 PM PDT 24
Peak memory 242128 kb
Host smart-8b9ebb0e-cba6-4911-a9d8-e6eecac380bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923853605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1923853605
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.520805767
Short name T1013
Test name
Test status
Simulation time 168843727 ps
CPU time 4.45 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 241728 kb
Host smart-3b401816-4b8d-4698-9cb2-c5665b4906e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520805767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.520805767
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2160740862
Short name T751
Test name
Test status
Simulation time 694257967912 ps
CPU time 3444.34 seconds
Started Jul 01 12:53:58 PM PDT 24
Finished Jul 01 01:51:23 PM PDT 24
Peak memory 524052 kb
Host smart-4a653332-0c19-49bc-ae68-8e26f8f48eb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160740862 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2160740862
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1817403396
Short name T590
Test name
Test status
Simulation time 522002244 ps
CPU time 4.92 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 242076 kb
Host smart-a2e028fd-39cb-496d-ad3a-dfbaf70e2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817403396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1817403396
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.1497055605
Short name T225
Test name
Test status
Simulation time 409419535 ps
CPU time 7.71 seconds
Started Jul 01 12:54:10 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 242104 kb
Host smart-16de12ed-5579-48ff-9185-49d7269c2ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497055605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1497055605
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.2683980655
Short name T848
Test name
Test status
Simulation time 59807670877 ps
CPU time 1891.46 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 01:25:32 PM PDT 24
Peak memory 363640 kb
Host smart-13c53699-d10b-4698-882a-2b7e053e2b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683980655 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2683980655
Directory /workspace/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.3915029561
Short name T605
Test name
Test status
Simulation time 143666436 ps
CPU time 3.82 seconds
Started Jul 01 12:54:00 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 242164 kb
Host smart-6da7f417-6ee3-4a8b-8638-9a8ec7e4e4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915029561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3915029561
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.92000185
Short name T902
Test name
Test status
Simulation time 2050286253 ps
CPU time 7.68 seconds
Started Jul 01 12:54:02 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 241704 kb
Host smart-a339f461-dd29-48e1-880e-7809109063c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92000185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.92000185
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1065341395
Short name T564
Test name
Test status
Simulation time 46385414371 ps
CPU time 681.5 seconds
Started Jul 01 12:53:59 PM PDT 24
Finished Jul 01 01:05:22 PM PDT 24
Peak memory 295900 kb
Host smart-7008164f-0f94-4745-bb63-d9300c733a4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065341395 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1065341395
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.1745982473
Short name T1009
Test name
Test status
Simulation time 1599229670 ps
CPU time 4.45 seconds
Started Jul 01 12:53:57 PM PDT 24
Finished Jul 01 12:54:03 PM PDT 24
Peak memory 242160 kb
Host smart-630346b6-3e50-4c7b-b0fb-e6780bed8a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745982473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1745982473
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.3043513936
Short name T385
Test name
Test status
Simulation time 1775231140 ps
CPU time 12.08 seconds
Started Jul 01 12:53:58 PM PDT 24
Finished Jul 01 12:54:11 PM PDT 24
Peak memory 242448 kb
Host smart-b515f4b7-9bd9-4370-91f9-3cbc497cd7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043513936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3043513936
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.2327586325
Short name T447
Test name
Test status
Simulation time 132668846 ps
CPU time 5.29 seconds
Started Jul 01 12:54:11 PM PDT 24
Finished Jul 01 12:54:18 PM PDT 24
Peak memory 242004 kb
Host smart-f8e7d88d-6547-43f8-b918-350ffbc49b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327586325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2327586325
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.1929726885
Short name T843
Test name
Test status
Simulation time 580837302 ps
CPU time 7.48 seconds
Started Jul 01 12:53:58 PM PDT 24
Finished Jul 01 12:54:06 PM PDT 24
Peak memory 241772 kb
Host smart-7997d22c-b665-42c4-a15c-1f591111f790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929726885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.1929726885
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1148089096
Short name T618
Test name
Test status
Simulation time 458765281330 ps
CPU time 1035.19 seconds
Started Jul 01 12:54:10 PM PDT 24
Finished Jul 01 01:11:27 PM PDT 24
Peak memory 376596 kb
Host smart-9ac03826-ff1c-4e2c-8507-15da935d62bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148089096 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1148089096
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.2297165176
Short name T937
Test name
Test status
Simulation time 214978066 ps
CPU time 4.34 seconds
Started Jul 01 12:54:00 PM PDT 24
Finished Jul 01 12:54:05 PM PDT 24
Peak memory 241940 kb
Host smart-a546b57f-7111-48b4-b5a5-eb223a4cc685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297165176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2297165176
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3616727013
Short name T1176
Test name
Test status
Simulation time 800515837 ps
CPU time 13.06 seconds
Started Jul 01 12:53:56 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 241760 kb
Host smart-fc3625fd-3800-4c77-8b10-ccf0be5d761c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616727013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3616727013
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2209568029
Short name T631
Test name
Test status
Simulation time 497119185706 ps
CPU time 1203.3 seconds
Started Jul 01 12:54:00 PM PDT 24
Finished Jul 01 01:14:04 PM PDT 24
Peak memory 383528 kb
Host smart-dec9a874-5c60-4451-bdf5-a14c7cb464ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209568029 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2209568029
Directory /workspace/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.3177767780
Short name T10
Test name
Test status
Simulation time 358569204 ps
CPU time 4.42 seconds
Started Jul 01 12:54:05 PM PDT 24
Finished Jul 01 12:54:11 PM PDT 24
Peak memory 242388 kb
Host smart-296f85a7-7a1c-46c3-b72c-b3486c492b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177767780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3177767780
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.2815915918
Short name T619
Test name
Test status
Simulation time 1884243947 ps
CPU time 27.09 seconds
Started Jul 01 12:54:06 PM PDT 24
Finished Jul 01 12:54:34 PM PDT 24
Peak memory 241900 kb
Host smart-06074c92-7bc0-43e1-ae8c-71f35563c2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815915918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.2815915918
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.638590157
Short name T127
Test name
Test status
Simulation time 192383831155 ps
CPU time 1453.1 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 01:18:26 PM PDT 24
Peak memory 482228 kb
Host smart-f42c72a8-a87e-48ec-a7b8-05d44e5f4e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638590157 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.638590157
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.3339425145
Short name T52
Test name
Test status
Simulation time 175301137 ps
CPU time 3.91 seconds
Started Jul 01 12:54:01 PM PDT 24
Finished Jul 01 12:54:06 PM PDT 24
Peak memory 242260 kb
Host smart-91eb7e38-104a-4dea-8d19-86d09bcfeeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339425145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.3339425145
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.3362814748
Short name T478
Test name
Test status
Simulation time 235577973 ps
CPU time 12.9 seconds
Started Jul 01 12:54:03 PM PDT 24
Finished Jul 01 12:54:16 PM PDT 24
Peak memory 242152 kb
Host smart-ae36020c-2e41-45cc-b9fb-6d0abebd7dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362814748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.3362814748
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.589939637
Short name T261
Test name
Test status
Simulation time 83887057026 ps
CPU time 1078.8 seconds
Started Jul 01 12:54:03 PM PDT 24
Finished Jul 01 01:12:02 PM PDT 24
Peak memory 319704 kb
Host smart-34e2cbeb-d1da-46f3-8527-2f68389c2fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589939637 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.589939637
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.725178821
Short name T533
Test name
Test status
Simulation time 2461084891 ps
CPU time 5.9 seconds
Started Jul 01 12:54:04 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 242464 kb
Host smart-b609790f-3f18-4d8c-8b46-c4edcab2479d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725178821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.725178821
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.2738651162
Short name T1132
Test name
Test status
Simulation time 53997118759 ps
CPU time 1093.28 seconds
Started Jul 01 12:54:04 PM PDT 24
Finished Jul 01 01:12:19 PM PDT 24
Peak memory 401808 kb
Host smart-37f3ac07-636e-492d-9639-32644a3bb4df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738651162 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.2738651162
Directory /workspace/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.3996239834
Short name T1170
Test name
Test status
Simulation time 598445591 ps
CPU time 2.39 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 240380 kb
Host smart-90dd2e45-3f33-4927-9b94-9bc989d99857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996239834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3996239834
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3868681161
Short name T366
Test name
Test status
Simulation time 1663213288 ps
CPU time 13.6 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:42 PM PDT 24
Peak memory 248788 kb
Host smart-69b9b9e9-b892-4ca3-8343-a8583cd542e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868681161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3868681161
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.2920356330
Short name T929
Test name
Test status
Simulation time 185279133 ps
CPU time 2.81 seconds
Started Jul 01 12:51:21 PM PDT 24
Finished Jul 01 12:51:26 PM PDT 24
Peak memory 241980 kb
Host smart-f6bba9cf-08c8-4da1-b060-f3e440ba4d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920356330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2920356330
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.1410120344
Short name T250
Test name
Test status
Simulation time 808421425 ps
CPU time 11.99 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 242396 kb
Host smart-73484e81-dd23-465e-9c38-25811db9b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410120344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1410120344
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.673040645
Short name T531
Test name
Test status
Simulation time 1146002432 ps
CPU time 23.42 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:51:49 PM PDT 24
Peak memory 242636 kb
Host smart-8b127d0b-37a0-4683-b447-c1d260a7cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673040645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.673040645
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1329948335
Short name T202
Test name
Test status
Simulation time 1520947931 ps
CPU time 6.7 seconds
Started Jul 01 12:51:25 PM PDT 24
Finished Jul 01 12:51:33 PM PDT 24
Peak memory 242104 kb
Host smart-6a45c754-f593-4159-be40-1dc74e2d88d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329948335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1329948335
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.2698786885
Short name T363
Test name
Test status
Simulation time 3166661567 ps
CPU time 31.12 seconds
Started Jul 01 12:51:22 PM PDT 24
Finished Jul 01 12:51:55 PM PDT 24
Peak memory 248792 kb
Host smart-8d79d905-12eb-4bda-83d2-ba2bc4563996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698786885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2698786885
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.1397336110
Short name T1078
Test name
Test status
Simulation time 1588598181 ps
CPU time 41.14 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:52:06 PM PDT 24
Peak memory 243092 kb
Host smart-7f4f4abc-41a0-4a55-8534-a4498fddf4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397336110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.1397336110
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.415641489
Short name T881
Test name
Test status
Simulation time 1361943540 ps
CPU time 3.21 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:32 PM PDT 24
Peak memory 241672 kb
Host smart-062cfbf7-6500-4f14-bf56-1ef6e03a0455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415641489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.415641489
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.4227136216
Short name T96
Test name
Test status
Simulation time 2978872108 ps
CPU time 21.63 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:51:47 PM PDT 24
Peak memory 242256 kb
Host smart-d1f5a746-62fd-44b9-bbcc-921294e91677
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227136216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.4227136216
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.3597160256
Short name T913
Test name
Test status
Simulation time 154671283 ps
CPU time 5.49 seconds
Started Jul 01 12:51:25 PM PDT 24
Finished Jul 01 12:51:32 PM PDT 24
Peak memory 242188 kb
Host smart-91cb38cf-6523-46d3-a5fe-fa096672bef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3597160256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3597160256
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.3674354840
Short name T430
Test name
Test status
Simulation time 4645246630 ps
CPU time 8.63 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:36 PM PDT 24
Peak memory 242196 kb
Host smart-38fbb6c1-4d8b-4309-a677-1a08f288bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674354840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3674354840
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.1566357621
Short name T1137
Test name
Test status
Simulation time 10241300209 ps
CPU time 27.45 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 248736 kb
Host smart-8e198432-3a90-487f-8055-27004128546a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566357621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
1566357621
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.3839071874
Short name T308
Test name
Test status
Simulation time 335632667474 ps
CPU time 3525.5 seconds
Started Jul 01 12:51:22 PM PDT 24
Finished Jul 01 01:50:10 PM PDT 24
Peak memory 382656 kb
Host smart-aceeff3b-783e-445d-8210-bfe6eaf7b66c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839071874 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3839071874
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.1962297738
Short name T1051
Test name
Test status
Simulation time 1120446794 ps
CPU time 13.86 seconds
Started Jul 01 12:51:24 PM PDT 24
Finished Jul 01 12:51:40 PM PDT 24
Peak memory 248800 kb
Host smart-79993c2e-7128-49e5-aedb-81f0a55a3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962297738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1962297738
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.1736155012
Short name T1106
Test name
Test status
Simulation time 1696827995 ps
CPU time 4.58 seconds
Started Jul 01 12:54:04 PM PDT 24
Finished Jul 01 12:54:10 PM PDT 24
Peak memory 242016 kb
Host smart-6c7eba41-cd0a-4af1-9264-3e265c443bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736155012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.1736155012
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3528553319
Short name T586
Test name
Test status
Simulation time 232808896 ps
CPU time 5.81 seconds
Started Jul 01 12:54:11 PM PDT 24
Finished Jul 01 12:54:18 PM PDT 24
Peak memory 241820 kb
Host smart-2f84c098-de61-4f8b-b4aa-7f8d55f13474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528553319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3528553319
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1667001037
Short name T910
Test name
Test status
Simulation time 93837205076 ps
CPU time 2545.44 seconds
Started Jul 01 12:54:05 PM PDT 24
Finished Jul 01 01:36:32 PM PDT 24
Peak memory 339880 kb
Host smart-93664de3-b44e-481a-9ff3-08fd2811a4ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667001037 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1667001037
Directory /workspace/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.145569792
Short name T874
Test name
Test status
Simulation time 102923971 ps
CPU time 3.45 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:11 PM PDT 24
Peak memory 242288 kb
Host smart-601bec2a-9efa-479b-9dab-5a24626af4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145569792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.145569792
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.2965550088
Short name T879
Test name
Test status
Simulation time 266355079 ps
CPU time 6.14 seconds
Started Jul 01 12:54:04 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 241936 kb
Host smart-93d7cb13-8cc2-4655-a876-24ddc72752d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965550088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2965550088
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2136401629
Short name T246
Test name
Test status
Simulation time 265590362951 ps
CPU time 748.09 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 01:06:41 PM PDT 24
Peak memory 355988 kb
Host smart-bacfc60b-b45e-4e35-aca1-894a00662c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136401629 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.2136401629
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.30044503
Short name T591
Test name
Test status
Simulation time 135387734 ps
CPU time 3.92 seconds
Started Jul 01 12:54:03 PM PDT 24
Finished Jul 01 12:54:08 PM PDT 24
Peak memory 241944 kb
Host smart-2b7c1d6e-0dbe-4d75-858f-472265c58fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30044503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.30044503
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.3751145174
Short name T137
Test name
Test status
Simulation time 2054480391 ps
CPU time 6.72 seconds
Started Jul 01 12:54:04 PM PDT 24
Finished Jul 01 12:54:11 PM PDT 24
Peak memory 242040 kb
Host smart-0b03e8fc-4a64-4440-9a88-5c6a8f8d6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751145174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3751145174
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.3784833908
Short name T1047
Test name
Test status
Simulation time 105983760283 ps
CPU time 2390.85 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 01:34:04 PM PDT 24
Peak memory 553112 kb
Host smart-fc1327bd-f99f-4cb2-9f8d-8152432bc8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784833908 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.3784833908
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.840915773
Short name T841
Test name
Test status
Simulation time 236948867 ps
CPU time 5.09 seconds
Started Jul 01 12:54:03 PM PDT 24
Finished Jul 01 12:54:09 PM PDT 24
Peak memory 242392 kb
Host smart-0a01b65c-6796-408a-bb42-9095953eac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840915773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.840915773
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2959071394
Short name T229
Test name
Test status
Simulation time 3442183815 ps
CPU time 29.97 seconds
Started Jul 01 12:54:05 PM PDT 24
Finished Jul 01 12:54:36 PM PDT 24
Peak memory 241924 kb
Host smart-731c6281-a76d-4e65-82ee-e03e171dc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959071394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2959071394
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.1778357346
Short name T166
Test name
Test status
Simulation time 110879550640 ps
CPU time 774.15 seconds
Started Jul 01 12:54:05 PM PDT 24
Finished Jul 01 01:07:01 PM PDT 24
Peak memory 273480 kb
Host smart-507b20eb-2630-4cd6-8604-80801bbd7722
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778357346 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.1778357346
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.644057435
Short name T51
Test name
Test status
Simulation time 189927718 ps
CPU time 5.29 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:14 PM PDT 24
Peak memory 242208 kb
Host smart-d25e4635-d527-465a-a44f-c4c310f638a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644057435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.644057435
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.3552704870
Short name T516
Test name
Test status
Simulation time 1552046696 ps
CPU time 13.46 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:21 PM PDT 24
Peak memory 241960 kb
Host smart-21f9bf49-a96b-48fa-8549-f45909eee29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552704870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.3552704870
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.1112754579
Short name T309
Test name
Test status
Simulation time 44793300900 ps
CPU time 532.33 seconds
Started Jul 01 12:54:09 PM PDT 24
Finished Jul 01 01:03:02 PM PDT 24
Peak memory 314504 kb
Host smart-9cb281e4-d5a8-4803-947c-b3bbad9c198a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112754579 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.1112754579
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.2239396413
Short name T50
Test name
Test status
Simulation time 347525256 ps
CPU time 4.62 seconds
Started Jul 01 12:54:11 PM PDT 24
Finished Jul 01 12:54:16 PM PDT 24
Peak memory 241964 kb
Host smart-60a5e2c8-7022-4d08-af2f-f45b710b74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239396413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2239396413
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.2160974740
Short name T1053
Test name
Test status
Simulation time 8302525763 ps
CPU time 21.8 seconds
Started Jul 01 12:54:08 PM PDT 24
Finished Jul 01 12:54:31 PM PDT 24
Peak memory 241696 kb
Host smart-ea00d17f-750b-42b4-871b-9e9f3a5a7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160974740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.2160974740
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.4143713298
Short name T644
Test name
Test status
Simulation time 1700731400 ps
CPU time 5.04 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:13 PM PDT 24
Peak memory 241876 kb
Host smart-1e7b2766-1613-4577-b447-710c7d61dfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143713298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.4143713298
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.3973239721
Short name T132
Test name
Test status
Simulation time 723078422 ps
CPU time 5.47 seconds
Started Jul 01 12:54:08 PM PDT 24
Finished Jul 01 12:54:15 PM PDT 24
Peak memory 241956 kb
Host smart-f0453954-85f2-46c5-945f-2e9a693ff464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973239721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3973239721
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.3537891517
Short name T694
Test name
Test status
Simulation time 197172486071 ps
CPU time 2328.77 seconds
Started Jul 01 12:54:08 PM PDT 24
Finished Jul 01 01:32:58 PM PDT 24
Peak memory 550264 kb
Host smart-3f1bdd12-ed3d-47a2-b783-91f422b57dda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537891517 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.3537891517
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.745207657
Short name T580
Test name
Test status
Simulation time 451292569 ps
CPU time 4.19 seconds
Started Jul 01 12:54:08 PM PDT 24
Finished Jul 01 12:54:14 PM PDT 24
Peak memory 241872 kb
Host smart-61742ac9-d39d-46cc-84d8-38a2fc94fa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745207657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.745207657
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.1063058558
Short name T1089
Test name
Test status
Simulation time 1852390363 ps
CPU time 22.74 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:31 PM PDT 24
Peak memory 242216 kb
Host smart-c9aa05ee-9341-4146-ac30-c8af20cb5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063058558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.1063058558
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2951474843
Short name T505
Test name
Test status
Simulation time 106162743 ps
CPU time 3.54 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 242160 kb
Host smart-13e2e653-56f0-4da1-94f6-3a347c3f8f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951474843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2951474843
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1708840079
Short name T317
Test name
Test status
Simulation time 254020432 ps
CPU time 5.6 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:14 PM PDT 24
Peak memory 241928 kb
Host smart-3b01ffdb-8828-40a9-ad4c-0983f513453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708840079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1708840079
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.2628131465
Short name T856
Test name
Test status
Simulation time 144446964 ps
CPU time 3.79 seconds
Started Jul 01 12:54:07 PM PDT 24
Finished Jul 01 12:54:12 PM PDT 24
Peak memory 242060 kb
Host smart-4ffb914b-c850-4333-bd2b-3c29c821986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628131465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.2628131465
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.3057810467
Short name T145
Test name
Test status
Simulation time 4848054312 ps
CPU time 9.23 seconds
Started Jul 01 12:54:09 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 241860 kb
Host smart-e808a17c-a298-421b-a74f-f149e2a1cbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057810467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.3057810467
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.3175017454
Short name T357
Test name
Test status
Simulation time 43197960176 ps
CPU time 515.14 seconds
Started Jul 01 12:54:08 PM PDT 24
Finished Jul 01 01:02:45 PM PDT 24
Peak memory 297724 kb
Host smart-0ebe53b0-a7ea-4e64-80ab-c1bae20cb57c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175017454 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3175017454
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.4050854174
Short name T437
Test name
Test status
Simulation time 192069945 ps
CPU time 1.95 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:31 PM PDT 24
Peak memory 240220 kb
Host smart-e075a652-5ba6-4e20-9b13-df3787617104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050854174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.4050854174
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.833805671
Short name T112
Test name
Test status
Simulation time 374572656 ps
CPU time 5.81 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:33 PM PDT 24
Peak memory 241840 kb
Host smart-a783ceb0-017a-4979-867c-125a6fec7261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833805671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.833805671
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.1202719878
Short name T30
Test name
Test status
Simulation time 646428966 ps
CPU time 9.04 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:51:40 PM PDT 24
Peak memory 242116 kb
Host smart-68fd4318-3749-49ef-8f49-69b307e28721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202719878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.1202719878
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2163168247
Short name T1063
Test name
Test status
Simulation time 967376444 ps
CPU time 14.89 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 241828 kb
Host smart-b46b41c3-32b7-41ab-9cc3-4bf9b35049aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163168247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2163168247
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.817700513
Short name T1138
Test name
Test status
Simulation time 4599705387 ps
CPU time 32.47 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 12:52:07 PM PDT 24
Peak memory 243780 kb
Host smart-02a114f0-8337-410d-b81e-0d600062e6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817700513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.817700513
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.3604235380
Short name T968
Test name
Test status
Simulation time 415855888 ps
CPU time 10.21 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 243648 kb
Host smart-9d0f1393-2ff7-435b-8092-2f7a2e0bb17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604235380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.3604235380
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.1984822265
Short name T1102
Test name
Test status
Simulation time 710365812 ps
CPU time 28.95 seconds
Started Jul 01 12:51:28 PM PDT 24
Finished Jul 01 12:51:59 PM PDT 24
Peak memory 242792 kb
Host smart-69e42a73-d7e1-4e28-97a5-1486dfe2d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984822265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1984822265
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.29110178
Short name T1129
Test name
Test status
Simulation time 858218900 ps
CPU time 10.04 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:39 PM PDT 24
Peak memory 241940 kb
Host smart-f8e8186c-0e05-4f25-9b3b-3f32e21ae50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29110178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.29110178
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3505706295
Short name T707
Test name
Test status
Simulation time 1690125266 ps
CPU time 23.98 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:53 PM PDT 24
Peak memory 241900 kb
Host smart-381d2174-090a-4ec0-ab3d-d72f3253022a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505706295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3505706295
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3211933596
Short name T345
Test name
Test status
Simulation time 974720407 ps
CPU time 9.06 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:37 PM PDT 24
Peak memory 248740 kb
Host smart-b98b7959-b653-494e-a8b2-cc58f96ba2a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3211933596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3211933596
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.2082204843
Short name T695
Test name
Test status
Simulation time 145751094 ps
CPU time 4.97 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:33 PM PDT 24
Peak memory 242080 kb
Host smart-209bd0d5-ed2f-41ea-aa19-3bad298e0528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082204843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.2082204843
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.2103396864
Short name T70
Test name
Test status
Simulation time 81986128401 ps
CPU time 277.62 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 12:56:12 PM PDT 24
Peak memory 273400 kb
Host smart-a2da868a-52b5-4e0d-8596-cbbd7fb77862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103396864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
2103396864
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.2904111488
Short name T931
Test name
Test status
Simulation time 146919099808 ps
CPU time 1478.39 seconds
Started Jul 01 12:51:34 PM PDT 24
Finished Jul 01 01:16:13 PM PDT 24
Peak memory 458604 kb
Host smart-78884b3c-f693-4809-81be-8a5c62c573fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904111488 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.2904111488
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.1447337287
Short name T834
Test name
Test status
Simulation time 578089149 ps
CPU time 13.88 seconds
Started Jul 01 12:51:28 PM PDT 24
Finished Jul 01 12:51:44 PM PDT 24
Peak memory 242500 kb
Host smart-102cf61a-7640-4334-bfc0-4222742c44a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447337287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1447337287
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3458291746
Short name T81
Test name
Test status
Simulation time 192335131 ps
CPU time 4.24 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 12:54:17 PM PDT 24
Peak memory 241872 kb
Host smart-27fe2f70-a7b9-4d44-8a58-d8ebdf5bdf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458291746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3458291746
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2644646711
Short name T1098
Test name
Test status
Simulation time 383711122 ps
CPU time 4.48 seconds
Started Jul 01 12:54:14 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 241768 kb
Host smart-1384399a-31e8-4596-a367-25b65a4d8a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644646711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2644646711
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.1043890966
Short name T758
Test name
Test status
Simulation time 8638793496 ps
CPU time 254.91 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 12:58:28 PM PDT 24
Peak memory 257120 kb
Host smart-536a036a-057e-47bd-ab9a-13d02b95ad4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043890966 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1043890966
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1616978354
Short name T1123
Test name
Test status
Simulation time 424559804 ps
CPU time 3.91 seconds
Started Jul 01 12:54:13 PM PDT 24
Finished Jul 01 12:54:18 PM PDT 24
Peak memory 241996 kb
Host smart-19e24854-02dd-4add-a5bf-ce1bcac44ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616978354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1616978354
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.716203782
Short name T487
Test name
Test status
Simulation time 748740130 ps
CPU time 9.13 seconds
Started Jul 01 12:54:11 PM PDT 24
Finished Jul 01 12:54:22 PM PDT 24
Peak memory 241860 kb
Host smart-2f97f6fe-0ad3-43dd-b0fc-6b6b17ccfe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716203782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.716203782
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1075406520
Short name T256
Test name
Test status
Simulation time 80046463498 ps
CPU time 1201.53 seconds
Started Jul 01 12:54:15 PM PDT 24
Finished Jul 01 01:14:17 PM PDT 24
Peak memory 298080 kb
Host smart-f96e1341-c188-450f-a80f-fadd60abeca7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075406520 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1075406520
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.2573662564
Short name T287
Test name
Test status
Simulation time 128832630 ps
CPU time 3.31 seconds
Started Jul 01 12:54:10 PM PDT 24
Finished Jul 01 12:54:14 PM PDT 24
Peak memory 242512 kb
Host smart-5d4bf9e6-15fb-4287-82b2-afcac00bf75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573662564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.2573662564
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.2924034911
Short name T583
Test name
Test status
Simulation time 93316119 ps
CPU time 3.35 seconds
Started Jul 01 12:54:13 PM PDT 24
Finished Jul 01 12:54:17 PM PDT 24
Peak memory 241952 kb
Host smart-04166f93-9c92-4144-8407-1214a4fd1062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924034911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2924034911
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.906083755
Short name T722
Test name
Test status
Simulation time 154806641 ps
CPU time 3.7 seconds
Started Jul 01 12:54:14 PM PDT 24
Finished Jul 01 12:54:18 PM PDT 24
Peak memory 241908 kb
Host smart-9562911e-77fe-4e01-af03-6a58a5482dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906083755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.906083755
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3636481875
Short name T1162
Test name
Test status
Simulation time 3410190840 ps
CPU time 13.4 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 242012 kb
Host smart-fbe5c293-8e1a-4df2-a3a7-1c7a195b7a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636481875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3636481875
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3495848114
Short name T993
Test name
Test status
Simulation time 123548139232 ps
CPU time 1489.39 seconds
Started Jul 01 12:54:13 PM PDT 24
Finished Jul 01 01:19:03 PM PDT 24
Peak memory 271708 kb
Host smart-8b9a2661-a717-4e87-bb1c-7efb6d869384
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495848114 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3495848114
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3690433748
Short name T66
Test name
Test status
Simulation time 265576658 ps
CPU time 3.87 seconds
Started Jul 01 12:54:12 PM PDT 24
Finished Jul 01 12:54:17 PM PDT 24
Peak memory 242300 kb
Host smart-60d09160-64b2-419f-9689-75d35418a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690433748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3690433748
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.1989838292
Short name T598
Test name
Test status
Simulation time 448030201 ps
CPU time 5.89 seconds
Started Jul 01 12:54:13 PM PDT 24
Finished Jul 01 12:54:19 PM PDT 24
Peak memory 241828 kb
Host smart-bd968e29-7e91-432d-9b62-0a769ac71f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989838292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1989838292
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.1471322912
Short name T788
Test name
Test status
Simulation time 147688163011 ps
CPU time 1645.25 seconds
Started Jul 01 12:54:11 PM PDT 24
Finished Jul 01 01:21:38 PM PDT 24
Peak memory 254028 kb
Host smart-e0064e0c-2737-44b7-9740-b00aaad7577c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471322912 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.1471322912
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.2827312449
Short name T850
Test name
Test status
Simulation time 511351453 ps
CPU time 4.46 seconds
Started Jul 01 12:54:22 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 242132 kb
Host smart-621c3b5d-9806-406e-b17c-6fb61195c83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827312449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2827312449
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.300624473
Short name T370
Test name
Test status
Simulation time 2815049852 ps
CPU time 24.7 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:47 PM PDT 24
Peak memory 242000 kb
Host smart-786517d5-c187-445d-b204-2cc4b850c1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300624473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.300624473
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.220220888
Short name T878
Test name
Test status
Simulation time 155032416 ps
CPU time 4.4 seconds
Started Jul 01 12:54:18 PM PDT 24
Finished Jul 01 12:54:23 PM PDT 24
Peak memory 242076 kb
Host smart-65e0b83a-848b-49ab-b219-0e43f0f8b7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220220888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.220220888
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1211849465
Short name T1024
Test name
Test status
Simulation time 542482938 ps
CPU time 15.87 seconds
Started Jul 01 12:54:23 PM PDT 24
Finished Jul 01 12:54:39 PM PDT 24
Peak memory 242352 kb
Host smart-6742bae0-411c-4fa9-bddf-f4fee6cadc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211849465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1211849465
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.279213168
Short name T681
Test name
Test status
Simulation time 329181842 ps
CPU time 4.22 seconds
Started Jul 01 12:54:17 PM PDT 24
Finished Jul 01 12:54:22 PM PDT 24
Peak memory 241760 kb
Host smart-48178354-5d70-4a56-8a1b-745376b10420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279213168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.279213168
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.633834339
Short name T689
Test name
Test status
Simulation time 1254315919 ps
CPU time 12.72 seconds
Started Jul 01 12:54:17 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 241848 kb
Host smart-1dc0fcff-3b5a-4458-bb20-cbc03f8bc3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633834339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.633834339
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1032344208
Short name T248
Test name
Test status
Simulation time 1991716867313 ps
CPU time 4846.69 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 02:15:08 PM PDT 24
Peak memory 484172 kb
Host smart-395d33cb-f392-49ca-b777-57e535db4d96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032344208 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1032344208
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.1064961237
Short name T1031
Test name
Test status
Simulation time 2299370345 ps
CPU time 4.92 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 242448 kb
Host smart-ca16bc38-71a5-4686-8176-0e39cc95d859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064961237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.1064961237
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3455285573
Short name T1094
Test name
Test status
Simulation time 882231810 ps
CPU time 6.85 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 241760 kb
Host smart-c00f1f4b-e0a0-4123-bd14-fefa89052660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455285573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3455285573
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3324941183
Short name T360
Test name
Test status
Simulation time 301820853321 ps
CPU time 2417.76 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 01:34:44 PM PDT 24
Peak memory 288304 kb
Host smart-a78ab157-f1af-41f5-801d-72e67607b495
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324941183 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3324941183
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.1510036647
Short name T184
Test name
Test status
Simulation time 284144175 ps
CPU time 3.92 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 12:54:25 PM PDT 24
Peak memory 242044 kb
Host smart-8b1f5c0f-5f40-4ad1-aad1-001edc2c4f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510036647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.1510036647
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.1397549592
Short name T423
Test name
Test status
Simulation time 316717790 ps
CPU time 8.09 seconds
Started Jul 01 12:54:19 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 241884 kb
Host smart-a492de7a-9761-401a-a27a-314c8a1e518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397549592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.1397549592
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2785750356
Short name T838
Test name
Test status
Simulation time 1002270522657 ps
CPU time 1565.39 seconds
Started Jul 01 12:54:17 PM PDT 24
Finished Jul 01 01:20:24 PM PDT 24
Peak memory 321344 kb
Host smart-d898e0e1-5620-4405-9fbc-74642e59dff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785750356 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2785750356
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.3817770084
Short name T1084
Test name
Test status
Simulation time 110132991 ps
CPU time 2.54 seconds
Started Jul 01 12:51:31 PM PDT 24
Finished Jul 01 12:51:35 PM PDT 24
Peak memory 240212 kb
Host smart-d3eafd7f-206f-4e10-b8d2-1e0fba65df79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817770084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.3817770084
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.533098568
Short name T829
Test name
Test status
Simulation time 734126162 ps
CPU time 17.05 seconds
Started Jul 01 12:51:25 PM PDT 24
Finished Jul 01 12:51:43 PM PDT 24
Peak memory 242488 kb
Host smart-72c07f03-6bf4-40df-b9fc-c5cec1377599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533098568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.533098568
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.2274771309
Short name T3
Test name
Test status
Simulation time 237226994 ps
CPU time 4.82 seconds
Started Jul 01 12:51:33 PM PDT 24
Finished Jul 01 12:51:39 PM PDT 24
Peak memory 242324 kb
Host smart-4aa37af3-9c6c-433f-9382-08711150f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274771309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2274771309
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.2266260418
Short name T783
Test name
Test status
Simulation time 929798618 ps
CPU time 26.82 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:51:58 PM PDT 24
Peak memory 242064 kb
Host smart-01f90ada-0fff-4618-af78-b72ace9600ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266260418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.2266260418
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.1594399286
Short name T1113
Test name
Test status
Simulation time 8139809170 ps
CPU time 24.38 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:54 PM PDT 24
Peak memory 243624 kb
Host smart-626c60f6-120e-4893-bb77-8edf621a285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594399286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.1594399286
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.1236325357
Short name T1103
Test name
Test status
Simulation time 146582771 ps
CPU time 3.54 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:33 PM PDT 24
Peak memory 241936 kb
Host smart-3a95d030-46fc-4f06-aa84-f8af64d1f6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236325357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1236325357
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.2757214493
Short name T198
Test name
Test status
Simulation time 1902353665 ps
CPU time 46.47 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:52:18 PM PDT 24
Peak memory 251992 kb
Host smart-a6f70a87-6d7f-443b-9760-a02baa0f79eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757214493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2757214493
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.1827303506
Short name T99
Test name
Test status
Simulation time 2337932242 ps
CPU time 33.59 seconds
Started Jul 01 12:51:29 PM PDT 24
Finished Jul 01 12:52:05 PM PDT 24
Peak memory 242540 kb
Host smart-35a1772b-5275-4e91-bfab-c7a044161db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827303506 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1827303506
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.4281274889
Short name T735
Test name
Test status
Simulation time 2214968199 ps
CPU time 9.96 seconds
Started Jul 01 12:51:27 PM PDT 24
Finished Jul 01 12:51:39 PM PDT 24
Peak memory 242196 kb
Host smart-52e92e32-f233-4d50-90cd-fa80400029cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281274889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.4281274889
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.172238508
Short name T35
Test name
Test status
Simulation time 360484825 ps
CPU time 11.02 seconds
Started Jul 01 12:51:28 PM PDT 24
Finished Jul 01 12:51:41 PM PDT 24
Peak memory 242356 kb
Host smart-e213d02b-69e4-4b26-ae1e-a7073c225871
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=172238508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.172238508
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.1679918124
Short name T347
Test name
Test status
Simulation time 221720465 ps
CPU time 6.39 seconds
Started Jul 01 12:51:30 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 242156 kb
Host smart-9f54a8d1-fefa-42db-9e89-882e221d2eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679918124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1679918124
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.3925811000
Short name T1194
Test name
Test status
Simulation time 1723839009 ps
CPU time 9.49 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:38 PM PDT 24
Peak memory 242548 kb
Host smart-6cc396fd-753c-41f8-8166-c07b4b5f2c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925811000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3925811000
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.596752386
Short name T927
Test name
Test status
Simulation time 13289746615 ps
CPU time 198.23 seconds
Started Jul 01 12:51:32 PM PDT 24
Finished Jul 01 12:54:52 PM PDT 24
Peak memory 273388 kb
Host smart-965ad3b7-fe72-47b5-ba35-446db8dc56ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596752386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.596752386
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.3446445728
Short name T865
Test name
Test status
Simulation time 91958402705 ps
CPU time 659.72 seconds
Started Jul 01 12:51:30 PM PDT 24
Finished Jul 01 01:02:32 PM PDT 24
Peak memory 291484 kb
Host smart-d27ab64f-d2b4-4430-ad21-5c8a8a53068a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446445728 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.3446445728
Directory /workspace/9.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.3180615612
Short name T269
Test name
Test status
Simulation time 1389621607 ps
CPU time 21.95 seconds
Started Jul 01 12:51:26 PM PDT 24
Finished Jul 01 12:51:50 PM PDT 24
Peak memory 242080 kb
Host smart-09718bdf-7b05-4de6-bee1-57084350119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180615612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3180615612
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.4109641461
Short name T383
Test name
Test status
Simulation time 150326342 ps
CPU time 4.7 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 242008 kb
Host smart-2c4f19b3-771d-4e2b-90db-645a21cc6302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109641461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.4109641461
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.2432319602
Short name T362
Test name
Test status
Simulation time 672325687 ps
CPU time 21.86 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 12:54:43 PM PDT 24
Peak memory 241832 kb
Host smart-a8f91e25-7476-4303-b85b-74b42a467a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432319602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2432319602
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3086718994
Short name T314
Test name
Test status
Simulation time 157444409890 ps
CPU time 2359.16 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 01:33:45 PM PDT 24
Peak memory 420868 kb
Host smart-ead036c6-0f61-448d-9d82-b18bb0bb0d7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086718994 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.3086718994
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.3412118847
Short name T679
Test name
Test status
Simulation time 145688802 ps
CPU time 3.9 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 12:54:24 PM PDT 24
Peak memory 242168 kb
Host smart-6d50f31a-c0b7-4b4b-870f-3c0b7f4d97cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412118847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3412118847
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.2283452291
Short name T1064
Test name
Test status
Simulation time 111769229 ps
CPU time 5.02 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 241692 kb
Host smart-5d30df68-489b-414a-92b1-9f74501005f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283452291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.2283452291
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.3274902779
Short name T723
Test name
Test status
Simulation time 2560890926 ps
CPU time 6.79 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 12:54:28 PM PDT 24
Peak memory 241912 kb
Host smart-5970567a-f968-41fb-a29b-b7e5c8a5c3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274902779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.3274902779
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.707462617
Short name T943
Test name
Test status
Simulation time 2561282769 ps
CPU time 7.1 seconds
Started Jul 01 12:54:19 PM PDT 24
Finished Jul 01 12:54:26 PM PDT 24
Peak memory 241792 kb
Host smart-a22f46bb-5fc6-4f17-a3da-25eb8c9f6d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707462617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.707462617
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3480326567
Short name T636
Test name
Test status
Simulation time 435551531 ps
CPU time 5.67 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:27 PM PDT 24
Peak memory 242400 kb
Host smart-dfb59f4b-2a64-47e1-8cc1-506b0e755961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480326567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3480326567
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.3264371429
Short name T761
Test name
Test status
Simulation time 2164473724 ps
CPU time 7.63 seconds
Started Jul 01 12:54:21 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 242064 kb
Host smart-bcd2b433-dc8e-4236-9bf0-57ba5f1215bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264371429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.3264371429
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1010816634
Short name T263
Test name
Test status
Simulation time 61966548963 ps
CPU time 811.2 seconds
Started Jul 01 12:54:19 PM PDT 24
Finished Jul 01 01:07:51 PM PDT 24
Peak memory 265312 kb
Host smart-7b797135-9729-422a-b600-b73be5d972f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010816634 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1010816634
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.470701368
Short name T1119
Test name
Test status
Simulation time 272542006 ps
CPU time 3.24 seconds
Started Jul 01 12:54:20 PM PDT 24
Finished Jul 01 12:54:24 PM PDT 24
Peak memory 241816 kb
Host smart-b94a2797-2798-4106-83d0-96d54611339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470701368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.470701368
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.1042641462
Short name T891
Test name
Test status
Simulation time 477210968 ps
CPU time 8.02 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 12:54:35 PM PDT 24
Peak memory 241856 kb
Host smart-57f4d929-89d1-4a27-bf82-6a8f684f93ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042641462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1042641462
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.310174902
Short name T230
Test name
Test status
Simulation time 47256893087 ps
CPU time 1229.92 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 01:14:55 PM PDT 24
Peak memory 285796 kb
Host smart-08f41954-1c9a-4dd9-b6c8-093579b89b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310174902 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.310174902
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.3227192438
Short name T599
Test name
Test status
Simulation time 247010295 ps
CPU time 3.88 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 241872 kb
Host smart-3a016f98-0bca-461a-96d0-988396e0ad96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227192438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3227192438
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.3660335248
Short name T545
Test name
Test status
Simulation time 1104683312 ps
CPU time 14.36 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:40 PM PDT 24
Peak memory 242192 kb
Host smart-4ef80016-4f0a-4cd4-bbd6-586f72951a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660335248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3660335248
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.308759773
Short name T915
Test name
Test status
Simulation time 276223529570 ps
CPU time 1493.65 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 01:19:20 PM PDT 24
Peak memory 260192 kb
Host smart-f82499a3-987f-4231-a870-ae9aed94dda5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308759773 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.308759773
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.53471654
Short name T785
Test name
Test status
Simulation time 2939450960 ps
CPU time 6.52 seconds
Started Jul 01 12:54:23 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 241944 kb
Host smart-eff56313-dcc7-434b-958d-716f0912b94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53471654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.53471654
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.4038096091
Short name T426
Test name
Test status
Simulation time 181716285 ps
CPU time 8.89 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:34 PM PDT 24
Peak memory 242240 kb
Host smart-a8bec615-9f92-4dc1-9f52-3ed40eb24ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038096091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.4038096091
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.2390919630
Short name T75
Test name
Test status
Simulation time 504444356 ps
CPU time 4.82 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 242228 kb
Host smart-b2ea166b-7eb8-45fc-bebc-26b297ff9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390919630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2390919630
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.2355024414
Short name T727
Test name
Test status
Simulation time 873009385 ps
CPU time 6.27 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 242124 kb
Host smart-c97a4a1b-7418-4ac9-9143-63c7aa8432e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355024414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2355024414
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.1114163316
Short name T258
Test name
Test status
Simulation time 230707121753 ps
CPU time 1407.78 seconds
Started Jul 01 12:54:23 PM PDT 24
Finished Jul 01 01:17:52 PM PDT 24
Peak memory 291684 kb
Host smart-15833e16-c37f-48a8-8adc-8dae1e245f3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114163316 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.1114163316
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.105628120
Short name T470
Test name
Test status
Simulation time 527365702 ps
CPU time 3.92 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 12:54:30 PM PDT 24
Peak memory 242028 kb
Host smart-bf08ca01-25fd-4ad3-8bd3-7f895324f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105628120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.105628120
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.1586844976
Short name T129
Test name
Test status
Simulation time 132625552 ps
CPU time 5.21 seconds
Started Jul 01 12:54:22 PM PDT 24
Finished Jul 01 12:54:28 PM PDT 24
Peak memory 241980 kb
Host smart-b237efb5-1a86-46b7-9118-3b54bf16b06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586844976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1586844976
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4037676137
Short name T17
Test name
Test status
Simulation time 62484424129 ps
CPU time 741.34 seconds
Started Jul 01 12:54:25 PM PDT 24
Finished Jul 01 01:06:48 PM PDT 24
Peak memory 316768 kb
Host smart-b4ca0e77-dc85-4d5e-8dc0-7fe040ce5667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037676137 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.4037676137
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.2495219533
Short name T724
Test name
Test status
Simulation time 128417449 ps
CPU time 3.31 seconds
Started Jul 01 12:54:26 PM PDT 24
Finished Jul 01 12:54:31 PM PDT 24
Peak memory 242208 kb
Host smart-247c6d88-9b66-4ed9-85a6-dc3fd7cefdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495219533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.2495219533
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.3836944357
Short name T1005
Test name
Test status
Simulation time 213801739 ps
CPU time 4.81 seconds
Started Jul 01 12:54:27 PM PDT 24
Finished Jul 01 12:54:32 PM PDT 24
Peak memory 241828 kb
Host smart-0b077db7-b2de-4fcb-b03d-34b075c73b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836944357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3836944357
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.2280337906
Short name T6
Test name
Test status
Simulation time 773387914222 ps
CPU time 1956.86 seconds
Started Jul 01 12:54:24 PM PDT 24
Finished Jul 01 01:27:03 PM PDT 24
Peak memory 347240 kb
Host smart-ce3a58c8-e758-423b-8ba4-3396219d8b6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280337906 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.2280337906
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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