SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 0 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
sram_0_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_flash_data_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
sram_0_req_during_otbn_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
sram_0_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13785 | 1 | T5 | 16 | T6 | 4 | T7 | 36 | ||||
auto[1] | 1159 | 1 | T16 | 5 | T8 | 12 | T91 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13721 | 1 | T5 | 16 | T6 | 4 | T7 | 36 | ||||
auto[1] | 1223 | 1 | T16 | 5 | T8 | 6 | T91 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 14918 | 1 | T5 | 16 | T6 | 4 | T7 | 36 | ||||
lc_esc_on | 26 | 1 | T171 | 1 | T133 | 1 | T18 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13923 | 1 | T5 | 16 | T6 | 4 | T7 | 36 | ||||
auto[1] | 1021 | 1 | T16 | 4 | T8 | 7 | T91 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2352 | 1 | T7 | 10 | T16 | 3 | T8 | 12 | ||||
auto[1] | 12592 | 1 | T5 | 16 | T6 | 4 | T7 | 26 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 12392 | 1 | T5 | 16 | T6 | 3 | T7 | 36 | ||||
auto[1] | 2552 | 1 | T6 | 1 | T12 | 2 | T16 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |