Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
sram_1_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_flash_data_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_lc_esc	2	0	2	100.00	100	1	1	0
sram_1_req_during_otbn_req	2	0	2	100.00	100	1	1	2
sram_1_req_during_otp_idle	2	0	2	100.00	100	1	1	2
sram_1_req_during_sram_0_req	2	0	2	100.00	100	1	1	2

Summary for Variable sram_1_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13481

1

T5

16

T6

4

T7

38

auto[1]

1111

1

T16

3

T8

5

T91

1

---

Summary for Variable sram_1_req_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13590

1

T5

16

T6

4

T7

38

auto[1]

1002

1

T16

3

T8

2

T91

1

---

Summary for Variable sram_1_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sram_1_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

14566

1

T5

16

T6

4

T7

38

lc_esc_on

26

1

T171

1

T133

1

T18

1

---

Summary for Variable sram_1_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13803

1

T5

16

T6

4

T7

38

auto[1]

789

1

T16

4

T8

1

T91

2

---

Summary for Variable sram_1_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2057

1

T7

11

T16

7

T8

12

auto[1]

12535

1

T5

16

T6

4

T7

27

---

Summary for Variable sram_1_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14193

1

T5

16

T6

4

T7

38

auto[1]

399

1

T198

1

T171

1

T24

133