Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
181737 |
1 |
|
|
T1 |
34 |
|
T2 |
66 |
|
T3 |
68 |
all_pins[1] |
181737 |
1 |
|
|
T1 |
34 |
|
T2 |
66 |
|
T3 |
68 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
301622 |
1 |
|
|
T1 |
35 |
|
T2 |
66 |
|
T3 |
68 |
values[0x1] |
61852 |
1 |
|
|
T1 |
33 |
|
T2 |
66 |
|
T3 |
68 |
transitions[0x0=>0x1] |
45563 |
1 |
|
|
T1 |
33 |
|
T2 |
66 |
|
T3 |
68 |
transitions[0x1=>0x0] |
45473 |
1 |
|
|
T1 |
33 |
|
T2 |
65 |
|
T3 |
67 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
136183 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
74 |
all_pins[0] |
values[0x1] |
45554 |
1 |
|
|
T1 |
33 |
|
T2 |
66 |
|
T3 |
68 |
all_pins[0] |
transitions[0x0=>0x1] |
37462 |
1 |
|
|
T1 |
33 |
|
T2 |
66 |
|
T3 |
68 |
all_pins[0] |
transitions[0x1=>0x0] |
8206 |
1 |
|
|
T5 |
30 |
|
T7 |
28 |
|
T12 |
19 |
all_pins[1] |
values[0x0] |
165439 |
1 |
|
|
T1 |
34 |
|
T2 |
66 |
|
T3 |
68 |
all_pins[1] |
values[0x1] |
16298 |
1 |
|
|
T5 |
40 |
|
T7 |
35 |
|
T12 |
64 |
all_pins[1] |
transitions[0x0=>0x1] |
8101 |
1 |
|
|
T5 |
30 |
|
T7 |
28 |
|
T12 |
19 |
all_pins[1] |
transitions[0x1=>0x0] |
37267 |
1 |
|
|
T1 |
33 |
|
T2 |
65 |
|
T3 |
67 |