Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
84.44 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv



Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 1 17 94.44
Crosses 72 13 59 81.94


Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
err_code_vals 7 1 6 85.71 100 1 1 0
partition 11 0 11 100.00 100 1 1 0


Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
dai_err_code_for_all_partitions 72 13 59 81.94 100 1 1 0


Summary for Variable err_code_vals

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for err_code_vals

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
macro_err 0 1 1


Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_err 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err 47046 1 T1 156 T5 41 T16 474
access_err 60479 1 T1 14 T5 77 T7 82
write_blank_err 440 1 T7 1 T89 1 T14 7
ecc_uncorr_err 74995 1 T7 449 T88 16 T89 716
ecc_corr_err 1377 1 T5 14 T88 4 T66 11
no_err 91762 1 T1 35 T4 62 T5 55



Summary for Variable partition

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 11 0 11 100.00


User Defined Bins for partition

Excluded/Illegal bins
NAMECOUNTSTATUS
illegal_idx 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
life_cycle 873 1 T7 2 T14 6 T15 2
secret2 24943 1 T1 10 T4 14 T5 19
secret1 29554 1 T4 9 T5 20 T6 15
secret0 38348 1 T4 6 T5 21 T6 14
hw_cfg1 36449 1 T1 4 T4 3 T5 4
hw_cfg0 25567 1 T1 7 T4 6 T5 21
rot_creator_auth_state 25077 1 T1 11 T4 2 T5 13
rot_creator_auth_codesign 22744 1 T1 3 T4 10 T5 12
owner_sw_cfg 19646 1 T1 9 T4 5 T5 6
creator_sw_cfg 22006 1 T1 5 T4 3 T5 13
vendor_test 30892 1 T1 156 T4 4 T5 58



Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 72 13 59 81.94 13
Automatically Generated Cross Bins 72 13 59 81.94 13
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins
err_code_valspartitionCOUNTAT LEASTNUMBERSTATUS
[fsm_err] [life_cycle] 0 1 1
[ecc_corr_err] [vendor_test] 0 1 1
[macro_err] [secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test] -- -- 10
[no_err] [life_cycle] 0 1 1


Covered bins
err_code_valspartitionCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fsm_err secret2 2885 1 T133 189 T223 184 T309 59
fsm_err secret1 3505 1 T224 187 T19 325 T139 357
fsm_err secret0 4517 1 T170 446 T18 503 T266 479
fsm_err hw_cfg1 2559 1 T16 474 T146 272 T115 21
fsm_err hw_cfg0 4631 1 T248 97 T137 462 T134 102
fsm_err rot_creator_auth_state 3701 1 T165 53 T322 56 T323 180
fsm_err rot_creator_auth_codesign 4334 1 T228 190 T19 71 T167 42
fsm_err owner_sw_cfg 2184 1 T229 46 T166 28 T324 283
fsm_err creator_sw_cfg 5164 1 T227 22 T325 495 T225 272
fsm_err vendor_test 13566 1 T1 156 T5 41 T198 131
access_err life_cycle 873 1 T7 2 T14 6 T15 2
access_err secret2 10423 1 T1 10 T5 13 T7 17
access_err secret1 5886 1 T5 12 T7 7 T12 23
access_err secret0 4454 1 T5 17 T7 7 T12 13
access_err hw_cfg1 1237 1 T5 1 T7 7 T12 2
access_err hw_cfg0 2325 1 T5 10 T7 1 T12 15
access_err rot_creator_auth_state 5931 1 T1 2 T5 1 T7 11
access_err rot_creator_auth_codesign 7670 1 T5 10 T7 11 T12 32
access_err owner_sw_cfg 6874 1 T1 2 T5 1 T7 4
access_err creator_sw_cfg 7412 1 T5 7 T7 5 T12 12
access_err vendor_test 7394 1 T5 5 T7 10 T12 15
write_blank_err secret2 12 1 T120 1 T139 1 T326 1
write_blank_err secret1 28 1 T7 1 T14 1 T156 1
write_blank_err secret0 62 1 T89 1 T15 1 T157 1
write_blank_err hw_cfg1 75 1 T14 1 T155 2 T127 1
write_blank_err hw_cfg0 14 1 T18 1 T223 1 T327 1
write_blank_err rot_creator_auth_state 131 1 T14 3 T19 7 T20 1
write_blank_err rot_creator_auth_codesign 58 1 T14 1 T98 3 T223 1
write_blank_err owner_sw_cfg 24 1 T328 1 T98 6 T128 1
write_blank_err creator_sw_cfg 16 1 T155 1 T329 1 T330 2
write_blank_err vendor_test 20 1 T14 1 T18 1 T223 1
ecc_uncorr_err secret2 5845 1 T88 4 T120 268 T139 719
ecc_uncorr_err secret1 10759 1 T7 449 T156 126 T331 408
ecc_uncorr_err secret0 20683 1 T89 716 T15 675 T157 159
ecc_uncorr_err hw_cfg1 21456 1 T88 2 T14 294 T155 426
ecc_uncorr_err hw_cfg0 6301 1 T88 7 T18 620 T165 60
ecc_uncorr_err rot_creator_auth_state 6587 1 T166 30 T332 63 T20 492
ecc_uncorr_err rot_creator_auth_codesign 1185 1 T166 31 T167 34 T150 30
ecc_uncorr_err owner_sw_cfg 1211 1 T328 192 T166 57 T167 30
ecc_uncorr_err creator_sw_cfg 968 1 T88 3 T333 49 T332 31
ecc_corr_err secret2 72 1 T5 1 T66 1 T70 1
ecc_corr_err secret1 133 1 T5 4 T66 1 T14 3
ecc_corr_err secret0 139 1 T5 1 T70 1 T71 3
ecc_corr_err hw_cfg1 258 1 T66 3 T155 2 T246 3
ecc_corr_err hw_cfg0 244 1 T5 4 T88 2 T66 5
ecc_corr_err rot_creator_auth_state 127 1 T5 4 T88 1 T165 2
ecc_corr_err rot_creator_auth_codesign 137 1 T88 1 T70 5 T71 3
ecc_corr_err owner_sw_cfg 110 1 T66 1 T70 3 T71 7
ecc_corr_err creator_sw_cfg 157 1 T71 3 T163 3 T46 3
no_err secret2 5706 1 T4 14 T5 5 T6 21
no_err secret1 9243 1 T4 9 T5 4 T6 15
no_err secret0 8493 1 T4 6 T5 3 T6 14
no_err hw_cfg1 10864 1 T1 4 T4 3 T5 3
no_err hw_cfg0 12052 1 T1 7 T4 6 T5 7
no_err rot_creator_auth_state 8600 1 T1 9 T4 2 T5 8
no_err rot_creator_auth_codesign 9360 1 T1 3 T4 10 T5 2
no_err owner_sw_cfg 9243 1 T1 7 T4 5 T5 5
no_err creator_sw_cfg 8289 1 T1 5 T4 3 T5 6
no_err vendor_test 9912 1 T4 4 T5 12 T6 13


User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins
NAMECOUNTSTATUS
vendor_test_ecc_uncorrectable_err 0 Illegal
life_cycle_ignore 0 Excluded

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