Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_addr_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_addr_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_addr_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_addr_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_addr_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11432 1 T4 23 T5 9 T6 6
auto[1] 1730 1 T4 1 T5 9 T6 6



Summary for Variable flash_addr_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_addr_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13124 1 T4 24 T5 18 T6 12
lc_esc_on 38 1 T8 1 T266 1 T279 1



Summary for Variable flash_addr_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12415 1 T4 24 T5 18 T6 12
auto[1] 747 1 T7 5 T9 3 T90 4



Summary for Variable flash_addr_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1872 1 T5 5 T7 2 T8 10
auto[1] 11290 1 T4 24 T5 13 T6 12



Summary for Variable flash_addr_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12391 1 T4 24 T5 18 T6 12
auto[1] 771 1 T7 15 T9 1 T90 3



Summary for Variable flash_addr_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_addr_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12811 1 T4 24 T5 18 T6 12
auto[1] 351 1 T7 6 T95 9 T159 2

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