Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
lc_esc_during_flash_addr_req 2 0 2 100.00 100 1 1 2
lc_esc_during_flash_data_req 2 0 2 100.00 100 1 1 2
lc_esc_during_lc_otp_prog_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otbn_req 2 0 2 100.00 100 1 1 2
lc_esc_during_otp_idle 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_0_req 2 0 2 100.00 100 1 1 2
lc_esc_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable lc_esc_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 298 1 T7 2 T8 5 T107 2
auto[1] 46 1 T8 1 T266 1 T279 1



Summary for Variable lc_esc_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301 1 T7 2 T8 5 T107 2
auto[1] 43 1 T8 1 T61 1 T98 1



Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312 1 T7 1 T8 6 T107 2
auto[1] 32 1 T7 1 T365 1 T230 1



Summary for Variable lc_esc_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312 1 T7 2 T8 6 T107 2
auto[1] 32 1 T14 1 T15 1 T274 2



Summary for Variable lc_esc_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32 1 T107 1 T61 1 T152 1
auto[1] 312 1 T7 2 T8 6 T107 1



Summary for Variable lc_esc_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 311 1 T7 2 T8 6 T107 1
auto[1] 33 1 T107 1 T134 1 T16 1



Summary for Variable lc_esc_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for lc_esc_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312 1 T7 2 T8 6 T107 1
auto[1] 32 1 T107 1 T134 1 T16 1

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