Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	48206	1			T6	5		T97	52		T128	49
access_err	62306	1			T4	21		T5	20		T6	4
write_blank_err	426	1			T8	3		T14	9		T94	1
ecc_uncorr_err	63100	1			T97	151		T128	167		T129	77
ecc_corr_err	1347	1			T97	9		T128	7		T129	1
no_err	90871	1			T4	35		T5	17		T6	7

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	801	1			T8	3		T14	8		T15	10
secret2	27525	1			T4	10		T5	2		T6	2
secret1	27506	1			T4	4		T5	4		T6	1
secret0	29649	1			T4	2		T5	4		T6	2
hw_cfg1	34514	1			T4	4		T5	2		T12	11
hw_cfg0	25596	1			T4	3		T5	5		T6	1
rot_creator_auth_state	22384	1			T4	6		T5	5		T12	14
rot_creator_auth_codesign	21303	1			T4	8		T5	6		T6	2
owner_sw_cfg	20208	1			T4	7		T5	3		T12	9
creator_sw_cfg	20488	1			T4	4		T12	20		T27	15
vendor_test	36282	1			T4	8		T5	6		T6	8

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	4460	1			T155	297		T117	151		T268	25
fsm_err	secret1	3933	1			T8	40		T266	27		T98	135
fsm_err	secret0	3627	1			T14	97		T156	22		T231	93
fsm_err	hw_cfg1	2314	1			T8	132		T94	47		T376	102
fsm_err	hw_cfg0	5912	1			T377	441		T378	115		T146	69
fsm_err	rot_creator_auth_state	2302	1			T97	25		T121	36		T157	78
fsm_err	rot_creator_auth_codesign	3399	1			T271	326		T192	59		T194	24
fsm_err	owner_sw_cfg	1426	1			T97	27		T274	55		T194	22
fsm_err	creator_sw_cfg	2147	1			T156	48		T249	45		T379	144
fsm_err	vendor_test	18686	1			T6	5		T128	49		T26	218
access_err	life_cycle	801	1			T8	3		T14	8		T15	10
access_err	secret2	10955	1			T4	9		T5	2		T6	1
access_err	secret1	5779	1			T4	4		T5	4		T6	1
access_err	secret0	4560	1			T4	2		T5	4		T6	2
access_err	hw_cfg1	1265	1			T4	2		T7	3		T8	10
access_err	hw_cfg0	2171	1			T4	1		T5	3		T8	1
access_err	rot_creator_auth_state	6012	1			T4	2		T7	22		T128	2
access_err	rot_creator_auth_codesign	7991	1			T4	1		T5	2		T7	10
access_err	owner_sw_cfg	7197	1			T5	2		T7	20		T8	15
access_err	creator_sw_cfg	7941	1			T7	7		T8	19		T26	36
access_err	vendor_test	7634	1			T5	3		T7	13		T128	1
write_blank_err	secret2	15	1			T8	1		T215	1		T380	1
write_blank_err	secret1	23	1			T131	1		T248	1		T231	1
write_blank_err	secret0	34	1			T14	1		T94	1		T15	1
write_blank_err	hw_cfg1	70	1			T14	1		T381	1		T249	1
write_blank_err	hw_cfg0	16	1			T215	1		T258	1		T262	1
write_blank_err	rot_creator_auth_state	153	1			T8	2		T14	6		T15	2
write_blank_err	rot_creator_auth_codesign	42	1			T137	1		T382	5		T383	1
write_blank_err	owner_sw_cfg	23	1			T137	2		T383	1		T269	1
write_blank_err	creator_sw_cfg	18	1			T215	3		T381	2		T380	3
write_blank_err	vendor_test	32	1			T14	1		T96	1		T215	3
ecc_uncorr_err	secret2	6597	1			T97	51		T8	414		T162	70
ecc_uncorr_err	secret1	8470	1			T162	70		T131	244		T248	263
ecc_uncorr_err	secret0	12983	1			T128	41		T161	55		T14	175
ecc_uncorr_err	hw_cfg1	19926	1			T97	55		T129	37		T14	4
ecc_uncorr_err	hw_cfg0	4995	1			T97	24		T128	32		T162	70
ecc_uncorr_err	rot_creator_auth_state	5226	1			T129	40		T162	74		T156	19
ecc_uncorr_err	rot_creator_auth_codesign	481	1			T161	94		T384	42		T385	6
ecc_uncorr_err	owner_sw_cfg	2187	1			T97	21		T128	41		T192	56
ecc_uncorr_err	creator_sw_cfg	2235	1			T128	53		T192	35		T213	29
ecc_corr_err	secret2	76	1			T128	1		T26	2		T162	4
ecc_corr_err	secret1	115	1			T26	2		T156	2		T64	6
ecc_corr_err	secret0	138	1			T128	4		T26	4		T162	1
ecc_corr_err	hw_cfg1	268	1			T97	1		T128	1		T26	3
ecc_corr_err	hw_cfg0	240	1			T26	15		T161	1		T156	1
ecc_corr_err	rot_creator_auth_state	104	1			T97	3		T129	1		T26	2
ecc_corr_err	rot_creator_auth_codesign	135	1			T97	2		T26	6		T161	5
ecc_corr_err	owner_sw_cfg	141	1			T97	2		T128	1		T26	7
ecc_corr_err	creator_sw_cfg	130	1			T97	1		T26	1		T162	3
no_err	secret2	5422	1			T4	1		T6	1		T12	9
no_err	secret1	9186	1			T12	13		T27	14		T7	24
no_err	secret0	8307	1			T12	16		T27	14		T7	21
no_err	hw_cfg1	10671	1			T4	2		T5	2		T12	11
no_err	hw_cfg0	12262	1			T4	2		T5	2		T6	1
no_err	rot_creator_auth_state	8587	1			T4	4		T5	5		T12	14
no_err	rot_creator_auth_codesign	9255	1			T4	7		T5	4		T6	2
no_err	owner_sw_cfg	9234	1			T4	7		T5	1		T12	9
no_err	creator_sw_cfg	8017	1			T4	4		T12	20		T27	15
no_err	vendor_test	9930	1			T4	8		T5	3		T6	3

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded