SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 0 | 12 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
otbn_req_during_flash_addr_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_flash_data_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_lc_esc | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
otbn_req_during_otp_idle | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_0_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
otbn_req_during_sram_1_req | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13147 | 1 | T3 | 46 | T4 | 4 | T5 | 12 | ||||
auto[1] | 815 | 1 | T12 | 2 | T28 | 14 | T9 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13022 | 1 | T3 | 46 | T4 | 4 | T5 | 12 | ||||
auto[1] | 940 | 1 | T12 | 2 | T28 | 19 | T9 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
lc_esc_off | 13913 | 1 | T3 | 46 | T4 | 4 | T5 | 12 | ||||
lc_esc_on | 49 | 1 | T37 | 1 | T354 | 1 | T400 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2709 | 1 | T3 | 6 | T5 | 2 | T28 | 19 | ||||
auto[1] | 11253 | 1 | T3 | 40 | T4 | 4 | T5 | 10 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13017 | 1 | T3 | 46 | T4 | 4 | T5 | 12 | ||||
auto[1] | 945 | 1 | T12 | 2 | T28 | 16 | T9 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 13603 | 1 | T3 | 46 | T4 | 4 | T5 | 12 | ||||
auto[1] | 359 | 1 | T12 | 1 | T28 | 3 | T9 | 1 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |