Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::sram_1_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
sram_1_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_flash_data_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_lc_esc 2 0 2 100.00 100 1 1 0
sram_1_req_during_otbn_req 2 0 2 100.00 100 1 1 2
sram_1_req_during_otp_idle 2 0 2 100.00 100 1 1 2
sram_1_req_during_sram_0_req 2 0 2 100.00 100 1 1 2


Summary for Variable sram_1_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13198 1 T3 46 T4 4 T5 12
auto[1] 700 1 T12 1 T28 13 T9 2



Summary for Variable sram_1_req_during_flash_data_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_flash_data_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13125 1 T3 46 T4 4 T5 12
auto[1] 773 1 T12 1 T28 5 T9 2



Summary for Variable sram_1_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for sram_1_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13862 1 T3 46 T4 4 T5 12
lc_esc_on 36 1 T99 1 T16 1 T258 1



Summary for Variable sram_1_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13217 1 T3 46 T4 4 T5 12
auto[1] 681 1 T12 1 T28 3 T9 1



Summary for Variable sram_1_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2216 1 T3 8 T12 2 T28 6
auto[1] 11682 1 T3 38 T4 4 T5 12



Summary for Variable sram_1_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sram_1_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13654 1 T3 46 T4 4 T5 12
auto[1] 244 1 T99 1 T258 1 T391 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%