Summary for Variable dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for dai_access_cmd
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
dai_digest |
2449 |
1 |
|
|
T3 |
13 |
|
T5 |
3 |
|
T12 |
1 |
dai_wr |
4281 |
1 |
|
|
T3 |
14 |
|
T6 |
2 |
|
T7 |
3 |
dai_rd |
7444 |
1 |
|
|
T3 |
27 |
|
T6 |
2 |
|
T7 |
1 |
Summary for Variable lc_creator_seed_sw_rw_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6760 |
1 |
|
|
T3 |
54 |
|
T5 |
19 |
|
T12 |
3 |
auto[1] |
7414 |
1 |
|
|
T6 |
4 |
|
T7 |
4 |
|
T4 |
4 |
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins for dai_access_secret2
Bins
lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
dai_digest |
1410 |
1 |
|
|
T3 |
13 |
|
T5 |
3 |
|
T12 |
1 |
auto[0] |
dai_wr |
1650 |
1 |
|
|
T3 |
14 |
|
T5 |
6 |
|
T12 |
1 |
auto[0] |
dai_rd |
3700 |
1 |
|
|
T3 |
27 |
|
T5 |
10 |
|
T12 |
1 |
auto[1] |
dai_digest |
1039 |
1 |
|
|
T28 |
2 |
|
T38 |
1 |
|
T31 |
1 |
auto[1] |
dai_wr |
2631 |
1 |
|
|
T6 |
2 |
|
T7 |
3 |
|
T4 |
2 |
auto[1] |
dai_rd |
3744 |
1 |
|
|
T6 |
2 |
|
T7 |
1 |
|
T4 |
2 |