Unified Coverage Report :: Group :: otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

Group : otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
84.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_env_0.1/otp_ctrl_env_cov.sv

---

Summary for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	1	17	94.44
Crosses	72	13	59	81.94

Variables for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
err_code_vals	7	1	6	85.71	100	1	1	0
partition	11	0	11	100.00	100	1	1	0

Crosses for Group otp_ctrl_env_pkg::otp_ctrl_env_cov::dai_err_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
dai_err_code_for_all_partitions	72	13	59	81.94	100	1	1	0

Summary for Variable err_code_vals

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for err_code_vals

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
macro_err	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_err	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	51011	1			T7	590		T27	256		T38	84
access_err	62851	1			T3	147		T7	17		T4	4
write_blank_err	567	1			T3	8		T8	10		T14	1
ecc_uncorr_err	77054	1			T3	1231		T4	132		T8	144
ecc_corr_err	1395	1			T4	7		T27	20		T38	20
no_err	92923	1			T3	267		T6	14		T7	49

---

Summary for Variable partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for partition

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal_idx	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
life_cycle	857	1			T3	19		T8	13		T14	14
secret2	25308	1			T3	63		T6	7		T7	6
secret1	32500	1			T3	50		T6	1		T7	1
secret0	41608	1			T3	1262		T7	599		T4	2
hw_cfg1	39655	1			T3	25		T6	4		T7	4
hw_cfg0	25521	1			T3	31		T7	6		T5	21
rot_creator_auth_state	22227	1			T3	49		T7	11		T4	2
rot_creator_auth_codesign	21834	1			T3	34		T7	5		T4	56
owner_sw_cfg	23920	1			T3	38		T6	2		T7	8
creator_sw_cfg	21176	1			T3	42		T7	11		T4	3
vendor_test	31195	1			T3	40		T7	5		T4	6

---

Summary for Cross dai_err_code_for_all_partitions

Samples crossed: err_code_vals partition

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	72	13	59	81.94	13
Automatically Generated Cross Bins	72	13	59	81.94	13
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for dai_err_code_for_all_partitions

Uncovered bins

err_code_vals	partition	COUNT	AT LEAST	NUMBER	STATUS
[fsm_err]	[life_cycle]	0	1	1
[ecc_corr_err]	[vendor_test]	0	1	1
[macro_err]	[secret2 , secret1 , secret0 , hw_cfg1 , hw_cfg0 , rot_creator_auth_state , rot_creator_auth_codesign , owner_sw_cfg , creator_sw_cfg , vendor_test]	--	--	10
[no_err]	[life_cycle]	0	1	1

Covered bins

err_code_vals	partition	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fsm_err	secret2	3293	1			T152	266		T258	138		T17	89
fsm_err	secret1	5400	1			T16	335		T224	452		T351	293
fsm_err	secret0	3771	1			T7	590		T13	180		T137	7
fsm_err	hw_cfg1	2761	1			T113	96		T18	117		T252	400
fsm_err	hw_cfg0	6684	1			T99	289		T123	441		T352	480
fsm_err	rot_creator_auth_state	2917	1			T37	84		T165	59		T353	474
fsm_err	rot_creator_auth_codesign	4126	1			T354	200		T355	245		T356	82
fsm_err	owner_sw_cfg	5256	1			T260	115		T132	102		T167	32
fsm_err	creator_sw_cfg	3418	1			T105	193		T357	218		T358	216
fsm_err	vendor_test	13385	1			T27	256		T38	84		T122	607
access_err	life_cycle	857	1			T3	19		T8	13		T14	14
access_err	secret2	11289	1			T3	63		T5	34		T12	3
access_err	secret1	5788	1			T5	70		T28	42		T39	17
access_err	secret0	4777	1			T3	2		T5	16		T28	19
access_err	hw_cfg1	1280	1			T3	3		T7	3		T5	3
access_err	hw_cfg0	2262	1			T5	1		T27	2		T28	18
access_err	rot_creator_auth_state	5983	1			T3	16		T7	5		T5	5
access_err	rot_creator_auth_codesign	7644	1			T3	4		T7	2		T5	13
access_err	owner_sw_cfg	7251	1			T3	12		T4	1		T5	20
access_err	creator_sw_cfg	8032	1			T3	13		T7	7		T4	2
access_err	vendor_test	7688	1			T3	15		T4	1		T5	15
write_blank_err	secret2	11	1			T214	1		T132	1		T359	1
write_blank_err	secret1	32	1			T16	1		T105	1		T360	2
write_blank_err	secret0	62	1			T3	3		T8	1		T13	1
write_blank_err	hw_cfg1	98	1			T14	1		T16	2		T160	1
write_blank_err	hw_cfg0	11	1			T361	1		T312	1		T285	1
write_blank_err	rot_creator_auth_state	168	1			T3	3		T16	1		T160	1
write_blank_err	rot_creator_auth_codesign	85	1			T8	4		T160	3		T213	1
write_blank_err	owner_sw_cfg	25	1			T3	1		T213	4		T101	1
write_blank_err	creator_sw_cfg	33	1			T8	4		T160	2		T113	1
write_blank_err	vendor_test	42	1			T3	1		T8	1		T213	1
ecc_uncorr_err	secret2	5330	1			T214	644		T166	41		T132	345
ecc_uncorr_err	secret1	11580	1			T16	278		T105	539		T261	72
ecc_uncorr_err	secret0	23806	1			T3	1231		T8	144		T13	360
ecc_uncorr_err	hw_cfg1	24320	1			T14	375		T157	50		T158	51
ecc_uncorr_err	hw_cfg0	4108	1			T158	51		T165	50		T167	32
ecc_uncorr_err	rot_creator_auth_state	4170	1			T159	46		T16	483		T362	48
ecc_uncorr_err	rot_creator_auth_codesign	877	1			T4	51		T158	52		T159	93
ecc_uncorr_err	owner_sw_cfg	1767	1			T4	81		T158	52		T159	97
ecc_uncorr_err	creator_sw_cfg	1096	1			T167	29		T363	506		T318	3
ecc_corr_err	secret2	88	1			T4	2		T27	2		T62	8
ecc_corr_err	secret1	141	1			T27	5		T38	10		T163	1
ecc_corr_err	secret0	154	1			T4	2		T27	3		T38	4
ecc_corr_err	hw_cfg1	258	1			T27	4		T38	2		T163	1
ecc_corr_err	hw_cfg0	233	1			T27	2		T38	3		T163	2
ecc_corr_err	rot_creator_auth_state	145	1			T4	2		T27	2		T159	1
ecc_corr_err	rot_creator_auth_codesign	128	1			T4	1		T27	1		T38	1
ecc_corr_err	owner_sw_cfg	115	1			T163	3		T158	1		T67	5
ecc_corr_err	creator_sw_cfg	133	1			T27	1		T157	1		T158	1
no_err	secret2	5297	1			T6	7		T7	6		T4	2
no_err	secret1	9559	1			T3	50		T6	1		T7	1
no_err	secret0	9038	1			T3	26		T7	9		T5	17
no_err	hw_cfg1	10938	1			T3	22		T6	4		T7	1
no_err	hw_cfg0	12223	1			T3	31		T7	6		T5	20
no_err	rot_creator_auth_state	8844	1			T3	30		T7	6		T5	17
no_err	rot_creator_auth_codesign	8974	1			T3	30		T7	3		T4	4
no_err	owner_sw_cfg	9506	1			T3	25		T6	2		T7	8
no_err	creator_sw_cfg	8464	1			T3	29		T7	4		T4	1
no_err	vendor_test	10080	1			T3	24		T7	5		T4	5

User Defined Cross Bins for dai_err_code_for_all_partitions

Excluded/Illegal bins

NAME	COUNT	STATUS
vendor_test_ecc_uncorrectable_err	0	Illegal
life_cycle_ignore	0	Excluded