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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.88 93.76 96.57 96.06 90.93 97.19 96.34 93.28


Total test records in report: 1328
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T1269 /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2397978922 Jul 03 06:26:29 PM PDT 24 Jul 03 06:26:31 PM PDT 24 44926104 ps
T1270 /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.169126318 Jul 03 06:26:06 PM PDT 24 Jul 03 06:26:08 PM PDT 24 38779893 ps
T1271 /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.9529004 Jul 03 06:26:29 PM PDT 24 Jul 03 06:26:31 PM PDT 24 67472339 ps
T1272 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2292921676 Jul 03 06:26:28 PM PDT 24 Jul 03 06:26:34 PM PDT 24 1391268045 ps
T306 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.226113241 Jul 03 06:25:47 PM PDT 24 Jul 03 06:25:54 PM PDT 24 530875356 ps
T1273 /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1878830193 Jul 03 06:26:31 PM PDT 24 Jul 03 06:26:32 PM PDT 24 147233468 ps
T307 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2136737302 Jul 03 06:25:41 PM PDT 24 Jul 03 06:25:44 PM PDT 24 712816609 ps
T308 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2683280323 Jul 03 06:25:54 PM PDT 24 Jul 03 06:25:56 PM PDT 24 187913713 ps
T1274 /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2089840370 Jul 03 06:26:21 PM PDT 24 Jul 03 06:26:23 PM PDT 24 114537785 ps
T1275 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.327238466 Jul 03 06:26:05 PM PDT 24 Jul 03 06:26:17 PM PDT 24 1504551573 ps
T376 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4250360216 Jul 03 06:26:20 PM PDT 24 Jul 03 06:26:40 PM PDT 24 5388096005 ps
T372 /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2204610912 Jul 03 06:26:28 PM PDT 24 Jul 03 06:26:48 PM PDT 24 2491363334 ps
T1276 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.37533277 Jul 03 06:25:56 PM PDT 24 Jul 03 06:25:58 PM PDT 24 72109446 ps
T368 /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.598370758 Jul 03 06:26:00 PM PDT 24 Jul 03 06:26:41 PM PDT 24 20090276396 ps
T370 /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3505789713 Jul 03 06:26:02 PM PDT 24 Jul 03 06:26:22 PM PDT 24 3846112208 ps
T1277 /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2001710320 Jul 03 06:26:08 PM PDT 24 Jul 03 06:26:09 PM PDT 24 132193260 ps
T1278 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1133002185 Jul 03 06:26:10 PM PDT 24 Jul 03 06:26:12 PM PDT 24 554528284 ps
T309 /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1698119628 Jul 03 06:26:09 PM PDT 24 Jul 03 06:26:11 PM PDT 24 40147502 ps
T374 /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.962827152 Jul 03 06:26:07 PM PDT 24 Jul 03 06:26:27 PM PDT 24 2479043614 ps
T1279 /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.89827683 Jul 03 06:26:29 PM PDT 24 Jul 03 06:26:30 PM PDT 24 45012026 ps
T326 /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1752587077 Jul 03 06:26:26 PM PDT 24 Jul 03 06:26:28 PM PDT 24 88992153 ps
T1280 /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2670558970 Jul 03 06:26:28 PM PDT 24 Jul 03 06:26:30 PM PDT 24 77196174 ps
T1281 /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3875115186 Jul 03 06:25:55 PM PDT 24 Jul 03 06:25:57 PM PDT 24 73051307 ps
T1282 /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2934371982 Jul 03 06:26:23 PM PDT 24 Jul 03 06:26:29 PM PDT 24 1453181263 ps
T1283 /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2222571121 Jul 03 06:26:12 PM PDT 24 Jul 03 06:26:16 PM PDT 24 804896285 ps
T1284 /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1271350884 Jul 03 06:26:31 PM PDT 24 Jul 03 06:26:33 PM PDT 24 142428688 ps
T369 /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2509756747 Jul 03 06:25:44 PM PDT 24 Jul 03 06:26:09 PM PDT 24 4784653110 ps
T1285 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.4157630330 Jul 03 06:25:55 PM PDT 24 Jul 03 06:25:57 PM PDT 24 520916294 ps
T1286 /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1442749600 Jul 03 06:26:36 PM PDT 24 Jul 03 06:26:38 PM PDT 24 43332481 ps
T1287 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1657945671 Jul 03 06:26:04 PM PDT 24 Jul 03 06:26:14 PM PDT 24 638891116 ps
T1288 /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.186093510 Jul 03 06:26:22 PM PDT 24 Jul 03 06:26:25 PM PDT 24 66886958 ps
T1289 /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2504475204 Jul 03 06:26:22 PM PDT 24 Jul 03 06:26:24 PM PDT 24 129176149 ps
T1290 /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2585962444 Jul 03 06:26:00 PM PDT 24 Jul 03 06:26:03 PM PDT 24 1101335654 ps
T1291 /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.388267971 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:36 PM PDT 24 142366223 ps
T1292 /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.218906748 Jul 03 06:25:52 PM PDT 24 Jul 03 06:25:54 PM PDT 24 38408518 ps
T310 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1032890232 Jul 03 06:26:24 PM PDT 24 Jul 03 06:26:26 PM PDT 24 655461979 ps
T1293 /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2351587267 Jul 03 06:25:59 PM PDT 24 Jul 03 06:26:02 PM PDT 24 55749506 ps
T1294 /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4190700145 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:37 PM PDT 24 38250539 ps
T1295 /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3794543686 Jul 03 06:26:22 PM PDT 24 Jul 03 06:26:24 PM PDT 24 60108878 ps
T1296 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.996846450 Jul 03 06:25:49 PM PDT 24 Jul 03 06:25:52 PM PDT 24 107438809 ps
T1297 /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.116296109 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:37 PM PDT 24 45769357 ps
T1298 /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3840782000 Jul 03 06:25:44 PM PDT 24 Jul 03 06:25:47 PM PDT 24 510526585 ps
T1299 /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.190522903 Jul 03 06:26:34 PM PDT 24 Jul 03 06:26:36 PM PDT 24 551796270 ps
T1300 /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3212923065 Jul 03 06:26:36 PM PDT 24 Jul 03 06:26:38 PM PDT 24 72238653 ps
T1301 /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2193388420 Jul 03 06:26:06 PM PDT 24 Jul 03 06:26:09 PM PDT 24 70090412 ps
T327 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3010173371 Jul 03 06:25:54 PM PDT 24 Jul 03 06:26:00 PM PDT 24 1202768984 ps
T1302 /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2349420648 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:37 PM PDT 24 570942962 ps
T1303 /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2140683159 Jul 03 06:25:51 PM PDT 24 Jul 03 06:25:55 PM PDT 24 458041378 ps
T1304 /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1008945639 Jul 03 06:26:10 PM PDT 24 Jul 03 06:26:14 PM PDT 24 302740023 ps
T1305 /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.694001807 Jul 03 06:26:28 PM PDT 24 Jul 03 06:26:32 PM PDT 24 435384982 ps
T1306 /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1534943212 Jul 03 06:25:53 PM PDT 24 Jul 03 06:25:58 PM PDT 24 72695964 ps
T1307 /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2886788987 Jul 03 06:25:55 PM PDT 24 Jul 03 06:25:57 PM PDT 24 44181807 ps
T1308 /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1929181757 Jul 03 06:26:32 PM PDT 24 Jul 03 06:26:33 PM PDT 24 128088765 ps
T1309 /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4093229810 Jul 03 06:26:19 PM PDT 24 Jul 03 06:26:22 PM PDT 24 1149441291 ps
T1310 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.781287427 Jul 03 06:26:20 PM PDT 24 Jul 03 06:26:26 PM PDT 24 180560114 ps
T328 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3351791522 Jul 03 06:25:41 PM PDT 24 Jul 03 06:25:47 PM PDT 24 151615546 ps
T366 /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2538852368 Jul 03 06:25:45 PM PDT 24 Jul 03 06:26:12 PM PDT 24 9749539921 ps
T1311 /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2926732891 Jul 03 06:26:08 PM PDT 24 Jul 03 06:26:11 PM PDT 24 367445942 ps
T329 /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2353681874 Jul 03 06:26:08 PM PDT 24 Jul 03 06:26:10 PM PDT 24 567192558 ps
T330 /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.121794096 Jul 03 06:26:00 PM PDT 24 Jul 03 06:26:02 PM PDT 24 51524183 ps
T1312 /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.153344081 Jul 03 06:26:28 PM PDT 24 Jul 03 06:26:31 PM PDT 24 136826651 ps
T1313 /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.180549522 Jul 03 06:25:37 PM PDT 24 Jul 03 06:25:39 PM PDT 24 137938085 ps
T1314 /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3647107779 Jul 03 06:25:47 PM PDT 24 Jul 03 06:25:50 PM PDT 24 95064732 ps
T1315 /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3172809696 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:37 PM PDT 24 155211702 ps
T1316 /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3589373851 Jul 03 06:25:50 PM PDT 24 Jul 03 06:25:52 PM PDT 24 72679720 ps
T1317 /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.662065556 Jul 03 06:26:22 PM PDT 24 Jul 03 06:26:26 PM PDT 24 66907785 ps
T1318 /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1034581658 Jul 03 06:25:56 PM PDT 24 Jul 03 06:26:02 PM PDT 24 243489924 ps
T1319 /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2716542735 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:37 PM PDT 24 49934776 ps
T1320 /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3366486718 Jul 03 06:25:53 PM PDT 24 Jul 03 06:25:55 PM PDT 24 107118901 ps
T1321 /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.967857495 Jul 03 06:25:47 PM PDT 24 Jul 03 06:25:53 PM PDT 24 150913673 ps
T1322 /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.572173686 Jul 03 06:25:57 PM PDT 24 Jul 03 06:25:59 PM PDT 24 38835142 ps
T1323 /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1484625286 Jul 03 06:25:56 PM PDT 24 Jul 03 06:26:00 PM PDT 24 451839551 ps
T1324 /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1869862369 Jul 03 06:26:16 PM PDT 24 Jul 03 06:26:20 PM PDT 24 102589142 ps
T1325 /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3235201814 Jul 03 06:25:49 PM PDT 24 Jul 03 06:25:56 PM PDT 24 313108997 ps
T1326 /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.586727871 Jul 03 06:26:08 PM PDT 24 Jul 03 06:26:16 PM PDT 24 3211977658 ps
T271 /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3970835197 Jul 03 06:26:22 PM PDT 24 Jul 03 06:26:42 PM PDT 24 2675197568 ps
T1327 /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1162590857 Jul 03 06:25:55 PM PDT 24 Jul 03 06:26:00 PM PDT 24 1636970533 ps
T1328 /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.938894821 Jul 03 06:26:23 PM PDT 24 Jul 03 06:26:25 PM PDT 24 269079113 ps

Test location /workspace/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2693426121
Short name T3
Test name
Test status
Simulation time 117437655230 ps
CPU time 2225.02 seconds
Started Jul 03 07:16:56 PM PDT 24
Finished Jul 03 07:54:08 PM PDT 24
Peak memory 278892 kb
Host smart-05b4852a-7911-41ad-acf8-c900573e7b2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693426121 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2693426121
Directory /workspace/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all.2161655984
Short name T101
Test name
Test status
Simulation time 37625409290 ps
CPU time 229.33 seconds
Started Jul 03 07:15:31 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 263120 kb
Host smart-e143e342-3821-4933-a963-f2eb08fd26e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161655984 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all
.2161655984
Directory /workspace/11.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_check_fail.4172404269
Short name T27
Test name
Test status
Simulation time 1979713886 ps
CPU time 20.3 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:17:30 PM PDT 24
Peak memory 242436 kb
Host smart-1a5a8620-52e9-4b10-892a-fca2c1d8396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172404269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4172404269
Directory /workspace/43.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all.3204349290
Short name T113
Test name
Test status
Simulation time 39901576111 ps
CPU time 340.28 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:21:14 PM PDT 24
Peak memory 298044 kb
Host smart-35df261f-c5b0-437c-bc6d-f1dc8d01bea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204349290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all
.3204349290
Directory /workspace/12.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.1425883731
Short name T16
Test name
Test status
Simulation time 288276686778 ps
CPU time 3433.38 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 08:12:57 PM PDT 24
Peak memory 516576 kb
Host smart-d6a4cba4-bf17-4dc1-bca9-1403143c01b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425883731 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.1425883731
Directory /workspace/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.otp_ctrl_sec_cm.1976633993
Short name T23
Test name
Test status
Simulation time 21781200512 ps
CPU time 185.47 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 278388 kb
Host smart-a9a7a2e9-1944-4711-bd55-081562f99ec3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976633993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.1976633993
Directory /workspace/1.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_init_fail.262298003
Short name T148
Test name
Test status
Simulation time 2304438972 ps
CPU time 4.6 seconds
Started Jul 03 07:15:03 PM PDT 24
Finished Jul 03 07:15:13 PM PDT 24
Peak memory 241972 kb
Host smart-f1275ae8-b9f4-4c83-b13b-c9468b1de3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262298003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.262298003
Directory /workspace/3.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_check_fail.3490286324
Short name T38
Test name
Test status
Simulation time 868954070 ps
CPU time 13.13 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:40 PM PDT 24
Peak memory 248744 kb
Host smart-837e3292-2004-4f87-b6a8-e7f1af93c388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490286324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3490286324
Directory /workspace/10.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_init_fail.1659956096
Short name T81
Test name
Test status
Simulation time 198870949 ps
CPU time 3.25 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:17:55 PM PDT 24
Peak memory 242188 kb
Host smart-01038ae1-7760-4626-8dc8-272a87e260ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659956096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1659956096
Directory /workspace/81.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all.2594437043
Short name T255
Test name
Test status
Simulation time 25145642848 ps
CPU time 163.81 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:19:31 PM PDT 24
Peak memory 250260 kb
Host smart-e7e8de8d-e16e-473d-b1c4-da25c6c79ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594437043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all
.2594437043
Directory /workspace/37.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3734691075
Short name T266
Test name
Test status
Simulation time 2570506549 ps
CPU time 19.59 seconds
Started Jul 03 06:26:23 PM PDT 24
Finished Jul 03 06:26:43 PM PDT 24
Peak memory 239336 kb
Host smart-4ba80a37-3ed9-48e3-9d7b-b14dc5e5adda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734691075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_i
ntg_err.3734691075
Directory /workspace/17.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/141.otp_ctrl_init_fail.2697125589
Short name T57
Test name
Test status
Simulation time 114563552 ps
CPU time 3.41 seconds
Started Jul 03 07:18:09 PM PDT 24
Finished Jul 03 07:18:16 PM PDT 24
Peak memory 242084 kb
Host smart-d25b514e-888a-463e-8a99-4046b2d75be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697125589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2697125589
Directory /workspace/141.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/127.otp_ctrl_init_fail.165758420
Short name T10
Test name
Test status
Simulation time 119892371 ps
CPU time 3.26 seconds
Started Jul 03 07:18:01 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 242020 kb
Host smart-7c356c9f-cf9d-47ee-adb6-9f4adf71bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165758420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.165758420
Directory /workspace/127.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all.759944783
Short name T278
Test name
Test status
Simulation time 76163207904 ps
CPU time 210.49 seconds
Started Jul 03 07:16:25 PM PDT 24
Finished Jul 03 07:20:01 PM PDT 24
Peak memory 259212 kb
Host smart-be4501b8-3ded-4f77-a089-afa762e318f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759944783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.
759944783
Directory /workspace/28.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_check_fail.3258425604
Short name T67
Test name
Test status
Simulation time 7802965220 ps
CPU time 32.7 seconds
Started Jul 03 07:16:53 PM PDT 24
Finished Jul 03 07:17:32 PM PDT 24
Peak memory 248864 kb
Host smart-36a4e78c-cd77-4c14-b9fb-76b4fe49177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258425604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.3258425604
Directory /workspace/40.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/63.otp_ctrl_init_fail.801944699
Short name T161
Test name
Test status
Simulation time 453879357 ps
CPU time 3.5 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:34 PM PDT 24
Peak memory 242264 kb
Host smart-c2c8b2b7-dd9b-4c0f-a520-eae46c9b26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801944699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.801944699
Directory /workspace/63.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/295.otp_ctrl_init_fail.1864478475
Short name T31
Test name
Test status
Simulation time 192126578 ps
CPU time 4.6 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242052 kb
Host smart-09bcf3de-0755-4ea7-b9b8-65dfab97489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864478475 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.1864478475
Directory /workspace/295.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.2775790079
Short name T284
Test name
Test status
Simulation time 136433658676 ps
CPU time 1275.59 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:36:54 PM PDT 24
Peak memory 252940 kb
Host smart-93379fe7-1832-4887-b08d-7055205c462a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775790079 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.2775790079
Directory /workspace/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/260.otp_ctrl_init_fail.2106754485
Short name T59
Test name
Test status
Simulation time 162178199 ps
CPU time 3.13 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 241928 kb
Host smart-49acb3b2-b414-4b30-9ad4-65b40ecf107e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106754485 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2106754485
Directory /workspace/260.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_macro_errs.1438579938
Short name T167
Test name
Test status
Simulation time 1806461146 ps
CPU time 26.97 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 246444 kb
Host smart-4183ecbd-b079-41ff-a932-5bac3cc70cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438579938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.1438579938
Directory /workspace/42.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/191.otp_ctrl_init_fail.1148841761
Short name T34
Test name
Test status
Simulation time 317554293 ps
CPU time 5.19 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 242072 kb
Host smart-e9140e81-f482-4ef6-a883-ddafdd24f80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148841761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.1148841761
Directory /workspace/191.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.816115646
Short name T254
Test name
Test status
Simulation time 62410279767 ps
CPU time 418.37 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:24:35 PM PDT 24
Peak memory 343636 kb
Host smart-27094480-0413-46c6-bd1c-ae21883562de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816115646 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.816115646
Directory /workspace/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.otp_ctrl_alert_test.1508367159
Short name T221
Test name
Test status
Simulation time 182935279 ps
CPU time 2.54 seconds
Started Jul 03 07:16:00 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 240580 kb
Host smart-02f41cec-8b78-4bf5-8e08-176b1c63e74d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508367159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1508367159
Directory /workspace/22.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_init_fail.1045797128
Short name T65
Test name
Test status
Simulation time 191728853 ps
CPU time 4.57 seconds
Started Jul 03 07:17:13 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 241772 kb
Host smart-3eb4e595-973f-436a-b0b2-044508855488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045797128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1045797128
Directory /workspace/49.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all.3582636132
Short name T349
Test name
Test status
Simulation time 143937959648 ps
CPU time 378.88 seconds
Started Jul 03 07:14:57 PM PDT 24
Finished Jul 03 07:21:18 PM PDT 24
Peak memory 297812 kb
Host smart-92c0377e-f7ea-4e6e-bc9f-72e595f2ab9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582636132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.
3582636132
Directory /workspace/0.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.otp_ctrl_macro_errs.2480555054
Short name T154
Test name
Test status
Simulation time 1169127346 ps
CPU time 18.83 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 242456 kb
Host smart-bcd557dd-ec62-4030-b3d1-8d27f8b1be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480555054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2480555054
Directory /workspace/28.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/197.otp_ctrl_init_fail.3344057894
Short name T53
Test name
Test status
Simulation time 272386908 ps
CPU time 3.97 seconds
Started Jul 03 07:18:30 PM PDT 24
Finished Jul 03 07:18:39 PM PDT 24
Peak memory 241964 kb
Host smart-e2151833-bc7b-401e-9d8b-b03257e8b6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344057894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3344057894
Directory /workspace/197.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.3551309588
Short name T15
Test name
Test status
Simulation time 150355543459 ps
CPU time 982.5 seconds
Started Jul 03 07:17:17 PM PDT 24
Finished Jul 03 07:33:48 PM PDT 24
Peak memory 312248 kb
Host smart-17ae283d-ca61-4cec-a9ff-2b8c6c931893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551309588 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.3551309588
Directory /workspace/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_stress_all.2118553124
Short name T105
Test name
Test status
Simulation time 33502280744 ps
CPU time 208.8 seconds
Started Jul 03 07:15:23 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 256944 kb
Host smart-f2932b4b-0196-44f2-b478-87576baa7fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118553124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.
2118553124
Directory /workspace/9.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.3648808028
Short name T37
Test name
Test status
Simulation time 35774971092 ps
CPU time 744.8 seconds
Started Jul 03 07:17:44 PM PDT 24
Finished Jul 03 07:30:15 PM PDT 24
Peak memory 402872 kb
Host smart-e97aa0d5-eadc-4062-990e-984d4b27da41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648808028 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.3648808028
Directory /workspace/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/202.otp_ctrl_init_fail.65785008
Short name T215
Test name
Test status
Simulation time 127449368 ps
CPU time 3.36 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 242352 kb
Host smart-66513ce3-226a-497a-b997-0a4e9e5bf4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65785008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.65785008
Directory /workspace/202.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/106.otp_ctrl_init_fail.1519889905
Short name T47
Test name
Test status
Simulation time 164838220 ps
CPU time 4.49 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 242136 kb
Host smart-0923d4ee-b0dc-4965-9f8a-062f3ad1842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519889905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1519889905
Directory /workspace/106.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/175.otp_ctrl_init_fail.1150425882
Short name T42
Test name
Test status
Simulation time 393160140 ps
CPU time 4.5 seconds
Started Jul 03 07:18:24 PM PDT 24
Finished Jul 03 07:18:34 PM PDT 24
Peak memory 242040 kb
Host smart-5dcc7a1b-0c4f-4168-99a6-48d59c201165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150425882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1150425882
Directory /workspace/175.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all.1153219877
Short name T151
Test name
Test status
Simulation time 118406188218 ps
CPU time 268.2 seconds
Started Jul 03 07:16:04 PM PDT 24
Finished Jul 03 07:20:38 PM PDT 24
Peak memory 257536 kb
Host smart-093a273c-9eeb-427f-bad8-9f39779c01e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153219877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all
.1153219877
Directory /workspace/23.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.1521706100
Short name T281
Test name
Test status
Simulation time 184856552701 ps
CPU time 2921.38 seconds
Started Jul 03 07:16:00 PM PDT 24
Finished Jul 03 08:04:47 PM PDT 24
Peak memory 396400 kb
Host smart-86300eee-2deb-4b91-9e8d-f59553a788b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521706100 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.1521706100
Directory /workspace/22.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.otp_ctrl_check_fail.810229549
Short name T51
Test name
Test status
Simulation time 1470816937 ps
CPU time 18.89 seconds
Started Jul 03 07:16:33 PM PDT 24
Finished Jul 03 07:16:57 PM PDT 24
Peak memory 245332 kb
Host smart-9fc36297-d584-42a5-9911-21348b76d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810229549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.810229549
Directory /workspace/35.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/81.otp_ctrl_parallel_lc_esc.2319214973
Short name T136
Test name
Test status
Simulation time 1410506025 ps
CPU time 10.41 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 242456 kb
Host smart-f5835eff-4763-4bcf-bf8d-44350fd88a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319214973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2319214973
Directory /workspace/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_key_req.822142052
Short name T96
Test name
Test status
Simulation time 1374451786 ps
CPU time 23.61 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 248820 kb
Host smart-2faaaccc-a9c6-421b-a466-66776b28bcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822142052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.822142052
Directory /workspace/25.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_init_fail.1018901600
Short name T90
Test name
Test status
Simulation time 289386227 ps
CPU time 4.22 seconds
Started Jul 03 07:16:16 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 241764 kb
Host smart-ad0f652c-bec0-4a2f-9515-b4f051fb9cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018901600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1018901600
Directory /workspace/30.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/70.otp_ctrl_parallel_lc_esc.3553331763
Short name T137
Test name
Test status
Simulation time 126672023 ps
CPU time 4.79 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 241836 kb
Host smart-5f6cdf61-0921-4cb1-ba29-e67bcc8af460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553331763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3553331763
Directory /workspace/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_regwen.3283195722
Short name T382
Test name
Test status
Simulation time 548142631 ps
CPU time 10.25 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 242064 kb
Host smart-0ce08d93-9dcc-4baf-a6e1-3ad06b8f6f46
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283195722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3283195722
Directory /workspace/13.otp_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_rw.3335891589
Short name T299
Test name
Test status
Simulation time 39933172 ps
CPU time 1.57 seconds
Started Jul 03 06:25:56 PM PDT 24
Finished Jul 03 06:25:58 PM PDT 24
Peak memory 241396 kb
Host smart-e5e32c43-f8af-49c5-a014-f700672634ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335891589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.3335891589
Directory /workspace/4.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.4179746079
Short name T140
Test name
Test status
Simulation time 253345334788 ps
CPU time 1579.86 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:42:14 PM PDT 24
Peak memory 390008 kb
Host smart-cb194d58-a915-4c99-b79d-4193343b3e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179746079 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.4179746079
Directory /workspace/18.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_check_fail.456734830
Short name T30
Test name
Test status
Simulation time 2113106158 ps
CPU time 14.87 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 242436 kb
Host smart-1889ed9c-f589-480b-9f1a-a76e024ebebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456734830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.456734830
Directory /workspace/25.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_esc.3729584300
Short name T145
Test name
Test status
Simulation time 594874801 ps
CPU time 15.69 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 241784 kb
Host smart-af00b597-8137-4d7e-8a0c-027412bd5bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729584300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3729584300
Directory /workspace/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/200.otp_ctrl_init_fail.1691375120
Short name T26
Test name
Test status
Simulation time 598420901 ps
CPU time 4.45 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 242000 kb
Host smart-9859df17-d125-42ee-a5b8-4d76793b299e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691375120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.1691375120
Directory /workspace/200.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/138.otp_ctrl_init_fail.3642469028
Short name T85
Test name
Test status
Simulation time 2880268978 ps
CPU time 6.84 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:25 PM PDT 24
Peak memory 242612 kb
Host smart-34eb2491-b131-4c5f-a3cb-a032da6b4dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642469028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3642469028
Directory /workspace/138.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all.4054917467
Short name T982
Test name
Test status
Simulation time 21177015520 ps
CPU time 185.62 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:20:18 PM PDT 24
Peak memory 273472 kb
Host smart-d10d8d33-7049-4b72-8936-57acd9fdc8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054917467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all
.4054917467
Directory /workspace/44.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.1316817059
Short name T347
Test name
Test status
Simulation time 259074799973 ps
CPU time 781.99 seconds
Started Jul 03 07:15:24 PM PDT 24
Finished Jul 03 07:28:28 PM PDT 24
Peak memory 333776 kb
Host smart-e2578d1d-3541-491a-ae47-8ca6eb165c08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316817059 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.1316817059
Directory /workspace/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/103.otp_ctrl_parallel_lc_esc.2760372191
Short name T251
Test name
Test status
Simulation time 149554758 ps
CPU time 7.15 seconds
Started Jul 03 07:17:49 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 241800 kb
Host smart-5ab1107f-4b2b-4a50-9863-db4668352ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760372191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.2760372191
Directory /workspace/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_parallel_lc_esc.1979541476
Short name T71
Test name
Test status
Simulation time 1033859340 ps
CPU time 9.57 seconds
Started Jul 03 07:17:56 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 241880 kb
Host smart-61d5f73c-ec1a-4e78-b4ab-7b83d316fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979541476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1979541476
Directory /workspace/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/180.otp_ctrl_parallel_lc_esc.1750226029
Short name T1052
Test name
Test status
Simulation time 347020223 ps
CPU time 8.8 seconds
Started Jul 03 07:18:31 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 241948 kb
Host smart-3a985b04-f125-4944-b345-c4aff9ffcaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750226029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.1750226029
Directory /workspace/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_stress_all.114464139
Short name T359
Test name
Test status
Simulation time 126452684000 ps
CPU time 247.11 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 273396 kb
Host smart-34d3a830-c22b-45ce-81e9-1d05e5aa21b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114464139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.
114464139
Directory /workspace/10.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.2538852368
Short name T366
Test name
Test status
Simulation time 9749539921 ps
CPU time 26.49 seconds
Started Jul 03 06:25:45 PM PDT 24
Finished Jul 03 06:26:12 PM PDT 24
Peak memory 244588 kb
Host smart-80f895ff-023d-4eca-9d3d-692dc6fe2226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538852368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_in
tg_err.2538852368
Directory /workspace/0.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.2422912819
Short name T267
Test name
Test status
Simulation time 2641228331 ps
CPU time 20.76 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:26:19 PM PDT 24
Peak memory 244844 kb
Host smart-6d8ff0aa-bbe8-40f1-9296-2ff9a067807f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422912819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_in
tg_err.2422912819
Directory /workspace/6.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.otp_ctrl_regwen.2525275507
Short name T783
Test name
Test status
Simulation time 289321523 ps
CPU time 9.82 seconds
Started Jul 03 07:16:10 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 241936 kb
Host smart-03311dfd-6847-4602-a070-e9d40cefb422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525275507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2525275507
Directory /workspace/28.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_test_access.2119303965
Short name T5
Test name
Test status
Simulation time 1319386576 ps
CPU time 24.56 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 248760 kb
Host smart-05e5d80e-258b-4fea-9da5-6b04bd7eb709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119303965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2119303965
Directory /workspace/1.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/26.otp_ctrl_check_fail.2574718518
Short name T83
Test name
Test status
Simulation time 2618493665 ps
CPU time 7.57 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 242500 kb
Host smart-9257ebef-32ac-4c95-9d78-a9d1f063f2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574718518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.2574718518
Directory /workspace/26.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_check_fail.4050987517
Short name T63
Test name
Test status
Simulation time 6170500283 ps
CPU time 23.89 seconds
Started Jul 03 07:15:30 PM PDT 24
Finished Jul 03 07:15:56 PM PDT 24
Peak memory 244092 kb
Host smart-0d9d5aff-7092-4358-80a1-f064694ca164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050987517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.4050987517
Directory /workspace/12.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_regwen.3478310847
Short name T1163
Test name
Test status
Simulation time 960624131 ps
CPU time 9.98 seconds
Started Jul 03 07:16:18 PM PDT 24
Finished Jul 03 07:16:31 PM PDT 24
Peak memory 242100 kb
Host smart-a5276e67-8804-415c-b132-378ca239e86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478310847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3478310847
Directory /workspace/29.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/181.otp_ctrl_parallel_lc_esc.3372161283
Short name T356
Test name
Test status
Simulation time 446261100 ps
CPU time 6.68 seconds
Started Jul 03 07:18:28 PM PDT 24
Finished Jul 03 07:18:40 PM PDT 24
Peak memory 242292 kb
Host smart-fa25a1c4-bbd0-4595-a930-4ff9d17485c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372161283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3372161283
Directory /workspace/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.3970835197
Short name T271
Test name
Test status
Simulation time 2675197568 ps
CPU time 19.23 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:42 PM PDT 24
Peak memory 239380 kb
Host smart-09d4259a-17b1-4a7a-86ec-8307b1c1bc6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970835197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_i
ntg_err.3970835197
Directory /workspace/16.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.otp_ctrl_check_fail.1786800232
Short name T58
Test name
Test status
Simulation time 1897425922 ps
CPU time 16.83 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:50 PM PDT 24
Peak memory 242616 kb
Host smart-ddddbc78-bfc9-4157-8b84-ac548aeb6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786800232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1786800232
Directory /workspace/27.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_req.2938579743
Short name T94
Test name
Test status
Simulation time 839884321 ps
CPU time 17.82 seconds
Started Jul 03 07:16:04 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 242228 kb
Host smart-2a952776-39c5-48e6-9374-9bcce6dc28fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2938579743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2938579743
Directory /workspace/24.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_init_fail.3204082849
Short name T187
Test name
Test status
Simulation time 135946207 ps
CPU time 3.71 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:00 PM PDT 24
Peak memory 241936 kb
Host smart-1922bedb-a7d7-4b1a-b1ee-d25110347c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204082849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3204082849
Directory /workspace/0.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/118.otp_ctrl_init_fail.451679536
Short name T229
Test name
Test status
Simulation time 99568527 ps
CPU time 3.3 seconds
Started Jul 03 07:18:01 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 241968 kb
Host smart-50b54c50-5d72-447c-98c6-ccb69252d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451679536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.451679536
Directory /workspace/118.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/126.otp_ctrl_init_fail.3479112363
Short name T1090
Test name
Test status
Simulation time 1965853103 ps
CPU time 3.53 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 242004 kb
Host smart-de6607f1-723e-4d9a-86b4-8b1d76ff388f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479112363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3479112363
Directory /workspace/126.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/131.otp_ctrl_init_fail.164083486
Short name T599
Test name
Test status
Simulation time 241035816 ps
CPU time 3.26 seconds
Started Jul 03 07:18:03 PM PDT 24
Finished Jul 03 07:18:12 PM PDT 24
Peak memory 242292 kb
Host smart-40407370-4458-4f5f-9537-c8b72e20cdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164083486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.164083486
Directory /workspace/131.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_macro_errs.3787725819
Short name T567
Test name
Test status
Simulation time 3247992485 ps
CPU time 17.36 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 243864 kb
Host smart-a1eb8cf8-59b2-42d5-8366-679df65dcad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787725819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3787725819
Directory /workspace/23.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_regwen.2219584038
Short name T814
Test name
Test status
Simulation time 4510748531 ps
CPU time 11.2 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 242124 kb
Host smart-a0282edc-342a-48f2-b025-57d705c632eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2219584038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.2219584038
Directory /workspace/17.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/194.otp_ctrl_init_fail.1305891545
Short name T84
Test name
Test status
Simulation time 232956932 ps
CPU time 3.45 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 242368 kb
Host smart-072eed09-1f28-42df-95d5-268fb7741ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305891545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.1305891545
Directory /workspace/194.otp_ctrl_init_fail/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.409090082
Short name T371
Test name
Test status
Simulation time 673624645 ps
CPU time 10.24 seconds
Started Jul 03 06:26:15 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 239404 kb
Host smart-8c46a043-c35e-42cc-8c2e-99f3662e5ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409090082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_in
tg_err.409090082
Directory /workspace/13.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_wake_up.4160666945
Short name T156
Test name
Test status
Simulation time 62699635 ps
CPU time 1.74 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:05 PM PDT 24
Peak memory 240136 kb
Host smart-f602e920-8def-4d13-a4a2-968bb6c7bf3e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4160666945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.4160666945
Directory /workspace/0.otp_ctrl_wake_up/latest

Test location /workspace/coverage/default/84.otp_ctrl_init_fail.3671257690
Short name T91
Test name
Test status
Simulation time 224833936 ps
CPU time 3.71 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 242152 kb
Host smart-581e8187-ae55-4e8f-ac3c-20db10964494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671257690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3671257690
Directory /workspace/84.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_init_fail.4166721664
Short name T89
Test name
Test status
Simulation time 444736893 ps
CPU time 4.37 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:13 PM PDT 24
Peak memory 242040 kb
Host smart-32435668-a3fb-4221-916c-8bcff7bdd2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166721664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.4166721664
Directory /workspace/42.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/273.otp_ctrl_init_fail.451766522
Short name T78
Test name
Test status
Simulation time 238495313 ps
CPU time 3.53 seconds
Started Jul 03 07:18:50 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 241868 kb
Host smart-596ef721-f4e5-4fb0-b2bd-615a0617cf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451766522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.451766522
Directory /workspace/273.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_req.3976647728
Short name T202
Test name
Test status
Simulation time 3032347771 ps
CPU time 27.32 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:34 PM PDT 24
Peak memory 242028 kb
Host smart-1e87e46e-14aa-4b93-be47-5b1679b46e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976647728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3976647728
Directory /workspace/3.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/105.otp_ctrl_init_fail.1414607264
Short name T1156
Test name
Test status
Simulation time 482519101 ps
CPU time 3.74 seconds
Started Jul 03 07:17:55 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 242180 kb
Host smart-668f2197-d0a9-4d69-bd2d-802de1448e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414607264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.1414607264
Directory /workspace/105.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/220.otp_ctrl_init_fail.3950497032
Short name T967
Test name
Test status
Simulation time 147371135 ps
CPU time 4.27 seconds
Started Jul 03 07:18:36 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 242064 kb
Host smart-596c3e72-3e68-44c2-8004-754b25ff2690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950497032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.3950497032
Directory /workspace/220.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_stress_all.1459475218
Short name T235
Test name
Test status
Simulation time 28289190164 ps
CPU time 247.64 seconds
Started Jul 03 07:15:39 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 250336 kb
Host smart-6d097c4d-e2c9-457e-9a84-e1b068f1cf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459475218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all
.1459475218
Directory /workspace/14.otp_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3351791522
Short name T328
Test name
Test status
Simulation time 151615546 ps
CPU time 4.94 seconds
Started Jul 03 06:25:41 PM PDT 24
Finished Jul 03 06:25:47 PM PDT 24
Peak memory 239196 kb
Host smart-3326aa74-bfd7-495c-b627-4a85a1aa0742
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351791522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_alia
sing.3351791522
Directory /workspace/0.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.413137701
Short name T303
Test name
Test status
Simulation time 577257373 ps
CPU time 9.61 seconds
Started Jul 03 06:25:39 PM PDT 24
Finished Jul 03 06:25:49 PM PDT 24
Peak memory 239284 kb
Host smart-8d212162-e2a3-4aee-9d23-d8696286b186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413137701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_b
ash.413137701
Directory /workspace/0.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.1003026246
Short name T1205
Test name
Test status
Simulation time 180596536 ps
CPU time 2.39 seconds
Started Jul 03 06:25:40 PM PDT 24
Finished Jul 03 06:25:43 PM PDT 24
Peak memory 241244 kb
Host smart-e8d46795-88d2-4438-9314-e66c0911d53e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003026246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_r
eset.1003026246
Directory /workspace/0.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3647107779
Short name T1314
Test name
Test status
Simulation time 95064732 ps
CPU time 2.01 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:50 PM PDT 24
Peak memory 245084 kb
Host smart-d472fc12-1dae-4339-aa11-f614e4785f92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647107779 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.3647107779
Directory /workspace/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2136737302
Short name T307
Test name
Test status
Simulation time 712816609 ps
CPU time 2.2 seconds
Started Jul 03 06:25:41 PM PDT 24
Finished Jul 03 06:25:44 PM PDT 24
Peak memory 239284 kb
Host smart-793eb3ef-fa14-4a16-8285-f5b865f53de6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136737302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2136737302
Directory /workspace/0.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_intr_test.1258105708
Short name T1218
Test name
Test status
Simulation time 99860343 ps
CPU time 1.44 seconds
Started Jul 03 06:25:45 PM PDT 24
Finished Jul 03 06:25:47 PM PDT 24
Peak memory 230384 kb
Host smart-ac478f4d-c973-40d7-b708-2fa10a8ad5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258105708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1258105708
Directory /workspace/0.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.180549522
Short name T1313
Test name
Test status
Simulation time 137938085 ps
CPU time 1.34 seconds
Started Jul 03 06:25:37 PM PDT 24
Finished Jul 03 06:25:39 PM PDT 24
Peak memory 230144 kb
Host smart-93436aa8-c5df-4934-a9e6-60ab3c93970a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180549522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl
_mem_partial_access.180549522
Directory /workspace/0.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1759970120
Short name T1227
Test name
Test status
Simulation time 560671598 ps
CPU time 1.56 seconds
Started Jul 03 06:25:40 PM PDT 24
Finished Jul 03 06:25:43 PM PDT 24
Peak memory 230132 kb
Host smart-0cbdc278-df5a-4514-a8f4-3f1ebae23b36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759970120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk
.1759970120
Directory /workspace/0.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.3391423333
Short name T334
Test name
Test status
Simulation time 78503062 ps
CPU time 2.78 seconds
Started Jul 03 06:25:46 PM PDT 24
Finished Jul 03 06:25:50 PM PDT 24
Peak memory 239116 kb
Host smart-60ce7503-35b0-426d-ac9f-ebc7d60f3f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391423333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_c
trl_same_csr_outstanding.3391423333
Directory /workspace/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4038506368
Short name T1211
Test name
Test status
Simulation time 125957601 ps
CPU time 4.98 seconds
Started Jul 03 06:25:40 PM PDT 24
Finished Jul 03 06:25:46 PM PDT 24
Peak memory 246340 kb
Host smart-374b76fb-46e1-40d4-be7b-13af7d97b718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038506368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4038506368
Directory /workspace/0.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.967857495
Short name T1321
Test name
Test status
Simulation time 150913673 ps
CPU time 5.15 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:53 PM PDT 24
Peak memory 239236 kb
Host smart-9d65d4da-2be3-40cf-ae4f-5c313a685181
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967857495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_alias
ing.967857495
Directory /workspace/1.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.226113241
Short name T306
Test name
Test status
Simulation time 530875356 ps
CPU time 6.56 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:54 PM PDT 24
Peak memory 230976 kb
Host smart-0a1dc30c-2f4d-44e6-a585-c80181ae5c4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226113241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_b
ash.226113241
Directory /workspace/1.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.4011050653
Short name T1214
Test name
Test status
Simulation time 246264419 ps
CPU time 1.93 seconds
Started Jul 03 06:25:43 PM PDT 24
Finished Jul 03 06:25:45 PM PDT 24
Peak memory 241008 kb
Host smart-e30b2273-221e-4b00-a779-7ff7c2806320
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011050653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_r
eset.4011050653
Directory /workspace/1.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2199860706
Short name T1248
Test name
Test status
Simulation time 71426780 ps
CPU time 2.03 seconds
Started Jul 03 06:25:49 PM PDT 24
Finished Jul 03 06:25:52 PM PDT 24
Peak memory 244512 kb
Host smart-b385b27f-c51e-499d-8dd2-5ecb5177f131
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199860706 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2199860706
Directory /workspace/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_csr_rw.2029882510
Short name T305
Test name
Test status
Simulation time 634425159 ps
CPU time 2.38 seconds
Started Jul 03 06:25:45 PM PDT 24
Finished Jul 03 06:25:48 PM PDT 24
Peak memory 241584 kb
Host smart-4db6e951-31dd-40bf-a399-72a5cc6365b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029882510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.2029882510
Directory /workspace/1.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_intr_test.2265292391
Short name T1233
Test name
Test status
Simulation time 150232231 ps
CPU time 1.56 seconds
Started Jul 03 06:25:45 PM PDT 24
Finished Jul 03 06:25:47 PM PDT 24
Peak memory 230372 kb
Host smart-0bf4ea95-9f22-4f90-999c-a84266144444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265292391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.2265292391
Directory /workspace/1.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2917697154
Short name T1236
Test name
Test status
Simulation time 135149811 ps
CPU time 1.48 seconds
Started Jul 03 06:25:45 PM PDT 24
Finished Jul 03 06:25:48 PM PDT 24
Peak memory 229932 kb
Host smart-b2c8d937-eef7-46d9-8124-c083f164adc2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917697154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_mem_partial_access.2917697154
Directory /workspace/1.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_mem_walk.3840782000
Short name T1298
Test name
Test status
Simulation time 510526585 ps
CPU time 1.66 seconds
Started Jul 03 06:25:44 PM PDT 24
Finished Jul 03 06:25:47 PM PDT 24
Peak memory 230084 kb
Host smart-46b942ba-836a-49ac-bec0-c5a2df07b849
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840782000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk
.3840782000
Directory /workspace/1.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.57396484
Short name T335
Test name
Test status
Simulation time 105846445 ps
CPU time 2.54 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:50 PM PDT 24
Peak memory 242364 kb
Host smart-db343425-a3dd-48db-a697-e4a13f029037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57396484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctr
l_same_csr_outstanding.57396484
Directory /workspace/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_errors.3796690617
Short name T1253
Test name
Test status
Simulation time 100344760 ps
CPU time 3.7 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:51 PM PDT 24
Peak memory 246700 kb
Host smart-17ddf845-b293-4b34-bf4f-6577f80fa351
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796690617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.3796690617
Directory /workspace/1.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.2509756747
Short name T369
Test name
Test status
Simulation time 4784653110 ps
CPU time 25.11 seconds
Started Jul 03 06:25:44 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 239404 kb
Host smart-bd81a94e-1171-49a5-ac9c-e4e32a2f24c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509756747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_in
tg_err.2509756747
Directory /workspace/1.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.4136523394
Short name T1213
Test name
Test status
Simulation time 290278527 ps
CPU time 2.77 seconds
Started Jul 03 06:26:09 PM PDT 24
Finished Jul 03 06:26:12 PM PDT 24
Peak memory 247424 kb
Host smart-80bf9060-1723-49b8-92df-3b76da3348b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136523394 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.4136523394
Directory /workspace/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_csr_rw.2353681874
Short name T329
Test name
Test status
Simulation time 567192558 ps
CPU time 1.79 seconds
Started Jul 03 06:26:08 PM PDT 24
Finished Jul 03 06:26:10 PM PDT 24
Peak memory 239152 kb
Host smart-a7d0e19b-d52b-4c74-92bd-70bf4a4aae61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353681874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.2353681874
Directory /workspace/10.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_intr_test.169126318
Short name T1270
Test name
Test status
Simulation time 38779893 ps
CPU time 1.36 seconds
Started Jul 03 06:26:06 PM PDT 24
Finished Jul 03 06:26:08 PM PDT 24
Peak memory 230280 kb
Host smart-9abe1934-fa6e-49e8-8eba-d4d34af80a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169126318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.169126318
Directory /workspace/10.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1008945639
Short name T1304
Test name
Test status
Simulation time 302740023 ps
CPU time 3.75 seconds
Started Jul 03 06:26:10 PM PDT 24
Finished Jul 03 06:26:14 PM PDT 24
Peak memory 239140 kb
Host smart-7faf0549-98bb-48b4-942b-891f9af93b1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008945639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_
ctrl_same_csr_outstanding.1008945639
Directory /workspace/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_errors.3233018576
Short name T1241
Test name
Test status
Simulation time 154430741 ps
CPU time 6.19 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:19 PM PDT 24
Peak memory 246404 kb
Host smart-93fa71db-8c4c-443d-9e59-97398bb2207a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233018576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.3233018576
Directory /workspace/10.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3686567137
Short name T364
Test name
Test status
Simulation time 1231254585 ps
CPU time 19 seconds
Started Jul 03 06:26:06 PM PDT 24
Finished Jul 03 06:26:25 PM PDT 24
Peak memory 239344 kb
Host smart-13219034-52a5-46af-a653-c32c693c172a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686567137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_i
ntg_err.3686567137
Directory /workspace/10.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.2926732891
Short name T1311
Test name
Test status
Simulation time 367445942 ps
CPU time 2.57 seconds
Started Jul 03 06:26:08 PM PDT 24
Finished Jul 03 06:26:11 PM PDT 24
Peak memory 247456 kb
Host smart-f93a9afb-43ba-4611-a8c9-697e0ccc9ed2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926732891 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.2926732891
Directory /workspace/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1133002185
Short name T1278
Test name
Test status
Simulation time 554528284 ps
CPU time 1.87 seconds
Started Jul 03 06:26:10 PM PDT 24
Finished Jul 03 06:26:12 PM PDT 24
Peak memory 240744 kb
Host smart-c0428245-afe7-4c12-b982-13dec51f68d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133002185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1133002185
Directory /workspace/11.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_intr_test.2001710320
Short name T1277
Test name
Test status
Simulation time 132193260 ps
CPU time 1.55 seconds
Started Jul 03 06:26:08 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 230272 kb
Host smart-d4948455-c8ad-42a1-9816-3c6cdc4d1336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001710320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.2001710320
Directory /workspace/11.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.4146732968
Short name T332
Test name
Test status
Simulation time 88576952 ps
CPU time 1.92 seconds
Started Jul 03 06:26:09 PM PDT 24
Finished Jul 03 06:26:11 PM PDT 24
Peak memory 242280 kb
Host smart-d1ee8452-647d-4c32-a76b-2f339008eed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146732968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_
ctrl_same_csr_outstanding.4146732968
Directory /workspace/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3553242879
Short name T1257
Test name
Test status
Simulation time 57065148 ps
CPU time 3.06 seconds
Started Jul 03 06:26:09 PM PDT 24
Finished Jul 03 06:26:12 PM PDT 24
Peak memory 246180 kb
Host smart-1aec53e9-b8fa-4c68-8da7-c8b42244a5ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553242879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3553242879
Directory /workspace/11.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.962827152
Short name T374
Test name
Test status
Simulation time 2479043614 ps
CPU time 19.91 seconds
Started Jul 03 06:26:07 PM PDT 24
Finished Jul 03 06:26:27 PM PDT 24
Peak memory 244836 kb
Host smart-4b33d3a8-3350-4c83-a8cd-49fffee75bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962827152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_in
tg_err.962827152
Directory /workspace/11.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.2862001046
Short name T1204
Test name
Test status
Simulation time 122746917 ps
CPU time 4.46 seconds
Started Jul 03 06:26:14 PM PDT 24
Finished Jul 03 06:26:19 PM PDT 24
Peak memory 247484 kb
Host smart-a4481bfc-516a-4c12-b2d5-c23ef201e3b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862001046 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.2862001046
Directory /workspace/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1244534695
Short name T298
Test name
Test status
Simulation time 158535386 ps
CPU time 1.91 seconds
Started Jul 03 06:26:10 PM PDT 24
Finished Jul 03 06:26:12 PM PDT 24
Peak memory 239156 kb
Host smart-eb37c59e-0064-49de-a1de-0efdd510804e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244534695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1244534695
Directory /workspace/12.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_intr_test.686512975
Short name T1207
Test name
Test status
Simulation time 38858686 ps
CPU time 1.46 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:13 PM PDT 24
Peak memory 231044 kb
Host smart-2fd782fb-890c-44e2-90c4-ab29eb6b28c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686512975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.686512975
Directory /workspace/12.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.965130285
Short name T333
Test name
Test status
Simulation time 1218511585 ps
CPU time 2.6 seconds
Started Jul 03 06:26:13 PM PDT 24
Finished Jul 03 06:26:16 PM PDT 24
Peak memory 239252 kb
Host smart-6ca17497-c1a7-439f-9184-4ebda377eda5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965130285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_c
trl_same_csr_outstanding.965130285
Directory /workspace/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_errors.1706639626
Short name T1200
Test name
Test status
Simulation time 193693225 ps
CPU time 6.83 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:19 PM PDT 24
Peak memory 246648 kb
Host smart-9c173b06-2cc1-4697-b21f-2e620cf5924a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706639626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.1706639626
Directory /workspace/12.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2168621060
Short name T1261
Test name
Test status
Simulation time 1644698323 ps
CPU time 23.97 seconds
Started Jul 03 06:26:11 PM PDT 24
Finished Jul 03 06:26:35 PM PDT 24
Peak memory 244388 kb
Host smart-b475e97b-08ff-46ef-8915-9067173897ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168621060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_i
ntg_err.2168621060
Directory /workspace/12.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1869862369
Short name T1324
Test name
Test status
Simulation time 102589142 ps
CPU time 3.72 seconds
Started Jul 03 06:26:16 PM PDT 24
Finished Jul 03 06:26:20 PM PDT 24
Peak memory 247404 kb
Host smart-b6dcee71-02e6-4996-9572-c82c9703fa4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869862369 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.1869862369
Directory /workspace/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_csr_rw.1459783455
Short name T1235
Test name
Test status
Simulation time 656096596 ps
CPU time 2.45 seconds
Started Jul 03 06:26:16 PM PDT 24
Finished Jul 03 06:26:19 PM PDT 24
Peak memory 239128 kb
Host smart-db338ac5-ec38-456e-8ebc-5c7bb5a2c8ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459783455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.1459783455
Directory /workspace/13.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_intr_test.3866411759
Short name T1267
Test name
Test status
Simulation time 127363295 ps
CPU time 1.4 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:13 PM PDT 24
Peak memory 230316 kb
Host smart-54ad368b-be0f-4c09-8266-fece1ec9b459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866411759 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3866411759
Directory /workspace/13.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.1085298750
Short name T1231
Test name
Test status
Simulation time 70518827 ps
CPU time 2.14 seconds
Started Jul 03 06:26:14 PM PDT 24
Finished Jul 03 06:26:17 PM PDT 24
Peak memory 242220 kb
Host smart-7c2d245e-d50b-4cc4-beab-00cf3ea70f8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085298750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_
ctrl_same_csr_outstanding.1085298750
Directory /workspace/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.otp_ctrl_tl_errors.2222571121
Short name T1283
Test name
Test status
Simulation time 804896285 ps
CPU time 3.78 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:16 PM PDT 24
Peak memory 246040 kb
Host smart-22ff76eb-36e5-4bef-9b85-0f6e1b282799
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222571121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.2222571121
Directory /workspace/13.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1675080391
Short name T270
Test name
Test status
Simulation time 157450376 ps
CPU time 2.96 seconds
Started Jul 03 06:26:19 PM PDT 24
Finished Jul 03 06:26:22 PM PDT 24
Peak memory 247512 kb
Host smart-6a69448e-f861-4466-b2a1-b02bbbf73c9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675080391 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.1675080391
Directory /workspace/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_csr_rw.1999190096
Short name T300
Test name
Test status
Simulation time 37617788 ps
CPU time 1.64 seconds
Started Jul 03 06:26:20 PM PDT 24
Finished Jul 03 06:26:21 PM PDT 24
Peak memory 239228 kb
Host smart-c0c5ba4c-7555-43f5-9c07-81c39b3054ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999190096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.1999190096
Directory /workspace/14.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_intr_test.3721051444
Short name T1217
Test name
Test status
Simulation time 135269493 ps
CPU time 1.48 seconds
Started Jul 03 06:26:16 PM PDT 24
Finished Jul 03 06:26:18 PM PDT 24
Peak memory 230228 kb
Host smart-4131bc51-6e64-4525-ba17-a047ad5a9513
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721051444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3721051444
Directory /workspace/14.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2089840370
Short name T1274
Test name
Test status
Simulation time 114537785 ps
CPU time 2.22 seconds
Started Jul 03 06:26:21 PM PDT 24
Finished Jul 03 06:26:23 PM PDT 24
Peak memory 242020 kb
Host smart-d45b692b-27b0-4605-ae41-14cff38e179f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089840370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_
ctrl_same_csr_outstanding.2089840370
Directory /workspace/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_errors.4183780774
Short name T1202
Test name
Test status
Simulation time 149741683 ps
CPU time 4.57 seconds
Started Jul 03 06:26:16 PM PDT 24
Finished Jul 03 06:26:21 PM PDT 24
Peak memory 246312 kb
Host smart-19105e69-c0c9-4f32-b00d-20c1e368d480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183780774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.4183780774
Directory /workspace/14.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.1191813292
Short name T367
Test name
Test status
Simulation time 640920449 ps
CPU time 9.18 seconds
Started Jul 03 06:26:17 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 244020 kb
Host smart-614da91f-2778-449e-b917-6d848e81c027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191813292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_i
ntg_err.1191813292
Directory /workspace/14.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.4093229810
Short name T1309
Test name
Test status
Simulation time 1149441291 ps
CPU time 3.56 seconds
Started Jul 03 06:26:19 PM PDT 24
Finished Jul 03 06:26:22 PM PDT 24
Peak memory 247384 kb
Host smart-81c3643c-9f4c-410d-bf8f-5b4018473857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093229810 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.4093229810
Directory /workspace/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1989491782
Short name T1224
Test name
Test status
Simulation time 629520035 ps
CPU time 1.75 seconds
Started Jul 03 06:26:21 PM PDT 24
Finished Jul 03 06:26:23 PM PDT 24
Peak memory 239184 kb
Host smart-3dbbb667-87b5-407e-be12-fe10466ecc87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989491782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1989491782
Directory /workspace/15.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_intr_test.2013575183
Short name T1264
Test name
Test status
Simulation time 81056368 ps
CPU time 1.39 seconds
Started Jul 03 06:26:20 PM PDT 24
Finished Jul 03 06:26:22 PM PDT 24
Peak memory 230316 kb
Host smart-f63460e0-13a0-4785-8910-075e607dee3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013575183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.2013575183
Directory /workspace/15.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2719944845
Short name T269
Test name
Test status
Simulation time 55919309 ps
CPU time 2.51 seconds
Started Jul 03 06:26:20 PM PDT 24
Finished Jul 03 06:26:22 PM PDT 24
Peak memory 239216 kb
Host smart-22453ec6-51bd-4209-b971-3f4509380e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719944845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_
ctrl_same_csr_outstanding.2719944845
Directory /workspace/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_errors.662065556
Short name T1317
Test name
Test status
Simulation time 66907785 ps
CPU time 3.64 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 246040 kb
Host smart-3f30c8d7-9fbb-4986-ab9b-248a0388cdfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662065556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.662065556
Directory /workspace/15.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.4250360216
Short name T376
Test name
Test status
Simulation time 5388096005 ps
CPU time 19.38 seconds
Started Jul 03 06:26:20 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 245060 kb
Host smart-55b9de5c-5c50-4935-8261-550f25534c72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250360216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_i
ntg_err.4250360216
Directory /workspace/15.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.938894821
Short name T1328
Test name
Test status
Simulation time 269079113 ps
CPU time 2.07 seconds
Started Jul 03 06:26:23 PM PDT 24
Finished Jul 03 06:26:25 PM PDT 24
Peak memory 244988 kb
Host smart-aaaad8b1-7601-4b40-81b1-a0f8cf9036a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938894821 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.938894821
Directory /workspace/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_csr_rw.1032890232
Short name T310
Test name
Test status
Simulation time 655461979 ps
CPU time 2.06 seconds
Started Jul 03 06:26:24 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 241548 kb
Host smart-586dcc5d-d686-4532-9dbb-d0280eb6b41d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032890232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.1032890232
Directory /workspace/16.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_intr_test.1292716350
Short name T1252
Test name
Test status
Simulation time 571797226 ps
CPU time 1.64 seconds
Started Jul 03 06:26:18 PM PDT 24
Finished Jul 03 06:26:20 PM PDT 24
Peak memory 231096 kb
Host smart-a1ac73ec-ba7e-4d13-8749-aafe473fb47c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292716350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.1292716350
Directory /workspace/16.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2934371982
Short name T1282
Test name
Test status
Simulation time 1453181263 ps
CPU time 5.75 seconds
Started Jul 03 06:26:23 PM PDT 24
Finished Jul 03 06:26:29 PM PDT 24
Peak memory 239268 kb
Host smart-b20a57f1-a451-4900-9bdc-e5fa1afaa974
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934371982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_
ctrl_same_csr_outstanding.2934371982
Directory /workspace/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.otp_ctrl_tl_errors.781287427
Short name T1310
Test name
Test status
Simulation time 180560114 ps
CPU time 5.55 seconds
Started Jul 03 06:26:20 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 246544 kb
Host smart-70889160-f04c-471a-8201-d37d8cd1af83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781287427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.781287427
Directory /workspace/16.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.28513311
Short name T1232
Test name
Test status
Simulation time 69183356 ps
CPU time 2.14 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:24 PM PDT 24
Peak memory 239236 kb
Host smart-290a37a7-7052-4393-bb65-14794275df8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28513311 -assert nopostproc +UVM_TESTNAME=o
tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.28513311
Directory /workspace/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1752587077
Short name T326
Test name
Test status
Simulation time 88992153 ps
CPU time 1.66 seconds
Started Jul 03 06:26:26 PM PDT 24
Finished Jul 03 06:26:28 PM PDT 24
Peak memory 241644 kb
Host smart-30435b92-981d-47a7-a27c-9aa5e3ab97f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752587077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1752587077
Directory /workspace/17.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_intr_test.2504475204
Short name T1289
Test name
Test status
Simulation time 129176149 ps
CPU time 1.44 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:24 PM PDT 24
Peak memory 230576 kb
Host smart-bff3f2d9-88df-4c93-93d0-c8a366b3e734
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504475204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.2504475204
Directory /workspace/17.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.186093510
Short name T1288
Test name
Test status
Simulation time 66886958 ps
CPU time 2.52 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:25 PM PDT 24
Peak memory 239200 kb
Host smart-a2ecffa1-1253-4d53-9fa8-fda4feb5312b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186093510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_same_csr_outstanding.186093510
Directory /workspace/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1396318853
Short name T1266
Test name
Test status
Simulation time 231296539 ps
CPU time 4.75 seconds
Started Jul 03 06:26:25 PM PDT 24
Finished Jul 03 06:26:30 PM PDT 24
Peak memory 247452 kb
Host smart-d81b7c6f-f146-43f2-8d97-b7dde43aa604
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396318853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1396318853
Directory /workspace/17.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.153344081
Short name T1312
Test name
Test status
Simulation time 136826651 ps
CPU time 2.18 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:31 PM PDT 24
Peak memory 244564 kb
Host smart-39661ac6-1a52-4cc4-b79b-04b62a5a2ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153344081 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.153344081
Directory /workspace/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_csr_rw.582242360
Short name T302
Test name
Test status
Simulation time 41261122 ps
CPU time 1.71 seconds
Started Jul 03 06:26:27 PM PDT 24
Finished Jul 03 06:26:29 PM PDT 24
Peak memory 241452 kb
Host smart-abea4bda-db2e-41ee-9c9e-b07429d26dca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582242360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.582242360
Directory /workspace/18.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_intr_test.3794543686
Short name T1295
Test name
Test status
Simulation time 60108878 ps
CPU time 1.46 seconds
Started Jul 03 06:26:22 PM PDT 24
Finished Jul 03 06:26:24 PM PDT 24
Peak memory 230516 kb
Host smart-25c7d56c-596a-48e0-91eb-2bd6f476749b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794543686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.3794543686
Directory /workspace/18.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.4035729791
Short name T1245
Test name
Test status
Simulation time 163336296 ps
CPU time 1.87 seconds
Started Jul 03 06:26:27 PM PDT 24
Finished Jul 03 06:26:30 PM PDT 24
Peak memory 239216 kb
Host smart-3faba56d-41ca-44fc-8883-001ffa2b4d00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035729791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_
ctrl_same_csr_outstanding.4035729791
Directory /workspace/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_errors.2127692242
Short name T1238
Test name
Test status
Simulation time 321352207 ps
CPU time 3.9 seconds
Started Jul 03 06:26:24 PM PDT 24
Finished Jul 03 06:26:28 PM PDT 24
Peak memory 246476 kb
Host smart-6b790d3b-b2f9-4ea9-aff7-0aab8dd39790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127692242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.2127692242
Directory /workspace/18.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.471412574
Short name T365
Test name
Test status
Simulation time 10388083417 ps
CPU time 10.35 seconds
Started Jul 03 06:26:23 PM PDT 24
Finished Jul 03 06:26:34 PM PDT 24
Peak memory 244728 kb
Host smart-689a74b2-9580-4302-a252-920aadc7258d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471412574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_in
tg_err.471412574
Directory /workspace/18.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.2325114670
Short name T1222
Test name
Test status
Simulation time 289687051 ps
CPU time 3.71 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:32 PM PDT 24
Peak memory 247436 kb
Host smart-38fcac37-b5ce-4d39-bd25-d54a8a2198d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325114670 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.2325114670
Directory /workspace/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3853211220
Short name T301
Test name
Test status
Simulation time 53813093 ps
CPU time 1.72 seconds
Started Jul 03 06:26:25 PM PDT 24
Finished Jul 03 06:26:26 PM PDT 24
Peak memory 239276 kb
Host smart-4829dbe7-80f3-4ff0-9573-e6671ae0209c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853211220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3853211220
Directory /workspace/19.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_intr_test.2670558970
Short name T1280
Test name
Test status
Simulation time 77196174 ps
CPU time 1.47 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:30 PM PDT 24
Peak memory 230596 kb
Host smart-c6a4aec9-47cc-411c-b69e-b1bc98fe70db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670558970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2670558970
Directory /workspace/19.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.694001807
Short name T1305
Test name
Test status
Simulation time 435384982 ps
CPU time 3.76 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:32 PM PDT 24
Peak memory 239272 kb
Host smart-d78c87ac-6a3e-47d6-98c8-da110e203536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694001807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_c
trl_same_csr_outstanding.694001807
Directory /workspace/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2292921676
Short name T1272
Test name
Test status
Simulation time 1391268045 ps
CPU time 5.55 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:34 PM PDT 24
Peak memory 246344 kb
Host smart-2f3921bb-9592-43d7-82dc-720109d17f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292921676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2292921676
Directory /workspace/19.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.2204610912
Short name T372
Test name
Test status
Simulation time 2491363334 ps
CPU time 19.36 seconds
Started Jul 03 06:26:28 PM PDT 24
Finished Jul 03 06:26:48 PM PDT 24
Peak memory 244808 kb
Host smart-8806cc11-4cf7-4823-9977-59b8c470f857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204610912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_i
ntg_err.2204610912
Directory /workspace/19.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.2274473998
Short name T1230
Test name
Test status
Simulation time 152520809 ps
CPU time 4.88 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 239180 kb
Host smart-5fcd34d2-69bf-4936-8fe6-07587f860009
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274473998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_alia
sing.2274473998
Directory /workspace/2.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.2702211364
Short name T344
Test name
Test status
Simulation time 1343385350 ps
CPU time 9.44 seconds
Started Jul 03 06:25:50 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 239180 kb
Host smart-d7fc62e5-92d9-4873-8dfe-ff4403b7c83a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702211364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_
bash.2702211364
Directory /workspace/2.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.996846450
Short name T1296
Test name
Test status
Simulation time 107438809 ps
CPU time 2.44 seconds
Started Jul 03 06:25:49 PM PDT 24
Finished Jul 03 06:25:52 PM PDT 24
Peak memory 241176 kb
Host smart-f7698a0d-59ef-4116-99e2-d9cbb65dc428
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996846450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_re
set.996846450
Directory /workspace/2.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1162590857
Short name T1327
Test name
Test status
Simulation time 1636970533 ps
CPU time 4.54 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 247496 kb
Host smart-bd916ad2-2d29-4192-9bf9-05b518b009fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162590857 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1162590857
Directory /workspace/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2293391638
Short name T297
Test name
Test status
Simulation time 40406952 ps
CPU time 1.64 seconds
Started Jul 03 06:25:49 PM PDT 24
Finished Jul 03 06:25:51 PM PDT 24
Peak memory 239224 kb
Host smart-fa0b1ab1-e15a-439f-ad03-e0e3103332a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293391638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2293391638
Directory /workspace/2.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_intr_test.2794844380
Short name T1216
Test name
Test status
Simulation time 619331003 ps
CPU time 1.91 seconds
Started Jul 03 06:25:47 PM PDT 24
Finished Jul 03 06:25:50 PM PDT 24
Peak memory 231116 kb
Host smart-c6656517-91df-4607-9464-f279f1807c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794844380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2794844380
Directory /workspace/2.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1003976642
Short name T1201
Test name
Test status
Simulation time 72405452 ps
CPU time 1.33 seconds
Started Jul 03 06:25:50 PM PDT 24
Finished Jul 03 06:25:52 PM PDT 24
Peak memory 229912 kb
Host smart-5c2c255a-4fb8-4248-ae38-940c05518aec
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003976642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_mem_partial_access.1003976642
Directory /workspace/2.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3589373851
Short name T1316
Test name
Test status
Simulation time 72679720 ps
CPU time 1.39 seconds
Started Jul 03 06:25:50 PM PDT 24
Finished Jul 03 06:25:52 PM PDT 24
Peak memory 230816 kb
Host smart-643f3ede-68ce-43d1-bbc7-bc028e3dd24a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589373851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk
.3589373851
Directory /workspace/2.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.3366486718
Short name T1320
Test name
Test status
Simulation time 107118901 ps
CPU time 1.96 seconds
Started Jul 03 06:25:53 PM PDT 24
Finished Jul 03 06:25:55 PM PDT 24
Peak memory 242280 kb
Host smart-689def39-2a83-4103-8efb-a153dab07b09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366486718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_c
trl_same_csr_outstanding.3366486718
Directory /workspace/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_errors.3235201814
Short name T1325
Test name
Test status
Simulation time 313108997 ps
CPU time 6.28 seconds
Started Jul 03 06:25:49 PM PDT 24
Finished Jul 03 06:25:56 PM PDT 24
Peak memory 246264 kb
Host smart-db45afd6-6da7-457e-be1b-e3e4db146f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235201814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.3235201814
Directory /workspace/2.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.2558571054
Short name T373
Test name
Test status
Simulation time 10229367756 ps
CPU time 14.55 seconds
Started Jul 03 06:25:50 PM PDT 24
Finished Jul 03 06:26:05 PM PDT 24
Peak memory 239472 kb
Host smart-8307f256-7ad4-4dd1-9f7e-b74cfc2c492a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558571054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_in
tg_err.2558571054
Directory /workspace/2.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.otp_ctrl_intr_test.3474254633
Short name T1239
Test name
Test status
Simulation time 41642001 ps
CPU time 1.47 seconds
Started Jul 03 06:26:33 PM PDT 24
Finished Jul 03 06:26:35 PM PDT 24
Peak memory 230332 kb
Host smart-65a2c4aa-2125-47b9-9df4-d5b307f33286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474254633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3474254633
Directory /workspace/20.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.otp_ctrl_intr_test.2759231257
Short name T1219
Test name
Test status
Simulation time 626597725 ps
CPU time 1.74 seconds
Started Jul 03 06:26:31 PM PDT 24
Finished Jul 03 06:26:33 PM PDT 24
Peak memory 231028 kb
Host smart-ebbac0b1-cb8e-4855-ba26-f39d1fcb14ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759231257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2759231257
Directory /workspace/21.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.otp_ctrl_intr_test.1929181757
Short name T1308
Test name
Test status
Simulation time 128088765 ps
CPU time 1.46 seconds
Started Jul 03 06:26:32 PM PDT 24
Finished Jul 03 06:26:33 PM PDT 24
Peak memory 231036 kb
Host smart-e33fdb1d-76f9-4c8b-8e17-06921e4323bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929181757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.1929181757
Directory /workspace/22.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.otp_ctrl_intr_test.1210929156
Short name T1260
Test name
Test status
Simulation time 57616547 ps
CPU time 1.4 seconds
Started Jul 03 06:26:36 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 231040 kb
Host smart-3b8d7666-5c9f-41e6-84f1-14b59b53d6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210929156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.1210929156
Directory /workspace/23.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.otp_ctrl_intr_test.3555649334
Short name T1215
Test name
Test status
Simulation time 156677124 ps
CPU time 1.56 seconds
Started Jul 03 06:26:31 PM PDT 24
Finished Jul 03 06:26:33 PM PDT 24
Peak memory 230268 kb
Host smart-0cd2e322-a205-4802-8f68-04b7fc9611f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555649334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.3555649334
Directory /workspace/24.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.otp_ctrl_intr_test.1271350884
Short name T1284
Test name
Test status
Simulation time 142428688 ps
CPU time 1.65 seconds
Started Jul 03 06:26:31 PM PDT 24
Finished Jul 03 06:26:33 PM PDT 24
Peak memory 230296 kb
Host smart-fbeff86d-f1dd-424c-bbee-ee230cff7955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271350884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.1271350884
Directory /workspace/25.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.otp_ctrl_intr_test.2627503305
Short name T1209
Test name
Test status
Simulation time 143178117 ps
CPU time 1.44 seconds
Started Jul 03 06:26:30 PM PDT 24
Finished Jul 03 06:26:31 PM PDT 24
Peak memory 230956 kb
Host smart-d8ce286e-fc0e-45a6-9f5d-f34de0057212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627503305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.2627503305
Directory /workspace/26.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.otp_ctrl_intr_test.9529004
Short name T1271
Test name
Test status
Simulation time 67472339 ps
CPU time 1.43 seconds
Started Jul 03 06:26:29 PM PDT 24
Finished Jul 03 06:26:31 PM PDT 24
Peak memory 230556 kb
Host smart-dfebd994-edad-4522-810b-0a0f86f52039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9529004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.9529004
Directory /workspace/27.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.otp_ctrl_intr_test.2716542735
Short name T1319
Test name
Test status
Simulation time 49934776 ps
CPU time 1.42 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 230204 kb
Host smart-c8b808ec-7146-48ed-a0fc-37042007c50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716542735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.2716542735
Directory /workspace/28.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.otp_ctrl_intr_test.2397978922
Short name T1269
Test name
Test status
Simulation time 44926104 ps
CPU time 1.52 seconds
Started Jul 03 06:26:29 PM PDT 24
Finished Jul 03 06:26:31 PM PDT 24
Peak memory 231096 kb
Host smart-aa8297de-22d2-43fc-a12d-f5e0ebc3ba9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397978922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.2397978922
Directory /workspace/29.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3010173371
Short name T327
Test name
Test status
Simulation time 1202768984 ps
CPU time 5.88 seconds
Started Jul 03 06:25:54 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 239220 kb
Host smart-0f7af8a9-82f2-43bf-848c-13502e543c0f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010173371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_alia
sing.3010173371
Directory /workspace/3.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.1034581658
Short name T1318
Test name
Test status
Simulation time 243489924 ps
CPU time 6.52 seconds
Started Jul 03 06:25:56 PM PDT 24
Finished Jul 03 06:26:02 PM PDT 24
Peak memory 239216 kb
Host smart-e4b061f4-f4f6-4eef-a7d6-816388b630b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034581658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_
bash.1034581658
Directory /workspace/3.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2683280323
Short name T308
Test name
Test status
Simulation time 187913713 ps
CPU time 2.35 seconds
Started Jul 03 06:25:54 PM PDT 24
Finished Jul 03 06:25:56 PM PDT 24
Peak memory 239172 kb
Host smart-c3a4432a-6e2f-42ce-9a4c-03d52ebda393
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683280323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_r
eset.2683280323
Directory /workspace/3.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.3831427883
Short name T1229
Test name
Test status
Simulation time 67579785 ps
CPU time 2.05 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:25:59 PM PDT 24
Peak memory 245900 kb
Host smart-c9337e50-114e-45e1-ba2a-35cd2d4022f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831427883 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3831427883
Directory /workspace/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3333599185
Short name T1255
Test name
Test status
Simulation time 60205479 ps
CPU time 1.49 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:25:57 PM PDT 24
Peak memory 240876 kb
Host smart-57e05c7b-cb47-49c4-9c97-1eecac7529c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333599185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3333599185
Directory /workspace/3.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_intr_test.2886788987
Short name T1307
Test name
Test status
Simulation time 44181807 ps
CPU time 1.43 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:25:57 PM PDT 24
Peak memory 231044 kb
Host smart-88a79f43-a19c-4c28-b02e-a253f9b90e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886788987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2886788987
Directory /workspace/3.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.218906748
Short name T1292
Test name
Test status
Simulation time 38408518 ps
CPU time 1.36 seconds
Started Jul 03 06:25:52 PM PDT 24
Finished Jul 03 06:25:54 PM PDT 24
Peak memory 229888 kb
Host smart-69039ba4-efd8-4906-a082-0a1e9c5f6125
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218906748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl
_mem_partial_access.218906748
Directory /workspace/3.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_mem_walk.4157630330
Short name T1285
Test name
Test status
Simulation time 520916294 ps
CPU time 1.85 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:25:57 PM PDT 24
Peak memory 230108 kb
Host smart-ad1cfc99-e220-4372-a769-a49d890afa20
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157630330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk
.4157630330
Directory /workspace/3.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2140683159
Short name T1303
Test name
Test status
Simulation time 458041378 ps
CPU time 3.74 seconds
Started Jul 03 06:25:51 PM PDT 24
Finished Jul 03 06:25:55 PM PDT 24
Peak memory 239260 kb
Host smart-9a7f8578-26d5-48ed-a929-e08b760ded69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140683159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_c
trl_same_csr_outstanding.2140683159
Directory /workspace/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1534943212
Short name T1306
Test name
Test status
Simulation time 72695964 ps
CPU time 4.62 seconds
Started Jul 03 06:25:53 PM PDT 24
Finished Jul 03 06:25:58 PM PDT 24
Peak memory 246460 kb
Host smart-77805d67-8d6e-43cc-a6c0-06a5d805d7c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534943212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1534943212
Directory /workspace/3.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2307281637
Short name T375
Test name
Test status
Simulation time 2568520739 ps
CPU time 10.46 seconds
Started Jul 03 06:25:52 PM PDT 24
Finished Jul 03 06:26:03 PM PDT 24
Peak memory 244316 kb
Host smart-be03c887-21c6-4890-9c31-fb52ef40536d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307281637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_in
tg_err.2307281637
Directory /workspace/3.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.otp_ctrl_intr_test.3172809696
Short name T1315
Test name
Test status
Simulation time 155211702 ps
CPU time 1.34 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 230940 kb
Host smart-2e9bc576-4510-4595-b0e0-5965fbee727e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172809696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.3172809696
Directory /workspace/30.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.otp_ctrl_intr_test.89827683
Short name T1279
Test name
Test status
Simulation time 45012026 ps
CPU time 1.35 seconds
Started Jul 03 06:26:29 PM PDT 24
Finished Jul 03 06:26:30 PM PDT 24
Peak memory 230388 kb
Host smart-594d6bff-1fe1-42df-9a2b-5271bfbc556b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89827683 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.89827683
Directory /workspace/31.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.otp_ctrl_intr_test.1663489357
Short name T1240
Test name
Test status
Simulation time 565475458 ps
CPU time 1.71 seconds
Started Jul 03 06:26:30 PM PDT 24
Finished Jul 03 06:26:32 PM PDT 24
Peak memory 230336 kb
Host smart-9f37e097-51e7-4658-9fdb-eb088ac87531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663489357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1663489357
Directory /workspace/32.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.otp_ctrl_intr_test.1250294269
Short name T1246
Test name
Test status
Simulation time 71388030 ps
CPU time 1.43 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 230340 kb
Host smart-2de02616-f005-43c9-8274-f006bdb2a22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250294269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1250294269
Directory /workspace/33.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.otp_ctrl_intr_test.3264719950
Short name T1228
Test name
Test status
Simulation time 121734162 ps
CPU time 1.33 seconds
Started Jul 03 06:26:31 PM PDT 24
Finished Jul 03 06:26:33 PM PDT 24
Peak memory 231016 kb
Host smart-f69cf603-ca45-4b0b-bf92-f5c5acdebe44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264719950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.3264719950
Directory /workspace/34.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.otp_ctrl_intr_test.3212923065
Short name T1300
Test name
Test status
Simulation time 72238653 ps
CPU time 1.46 seconds
Started Jul 03 06:26:36 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 230332 kb
Host smart-a6275997-8630-4008-a4b8-169ede761885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212923065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3212923065
Directory /workspace/35.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.otp_ctrl_intr_test.1878830193
Short name T1273
Test name
Test status
Simulation time 147233468 ps
CPU time 1.35 seconds
Started Jul 03 06:26:31 PM PDT 24
Finished Jul 03 06:26:32 PM PDT 24
Peak memory 231044 kb
Host smart-f97b0d66-5ba4-4b82-aa33-26a0bbfe56a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878830193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1878830193
Directory /workspace/36.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.otp_ctrl_intr_test.2349420648
Short name T1302
Test name
Test status
Simulation time 570942962 ps
CPU time 1.77 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 230640 kb
Host smart-d3614736-174b-479a-b938-ebff75a8dcd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349420648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.2349420648
Directory /workspace/37.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.otp_ctrl_intr_test.4190700145
Short name T1294
Test name
Test status
Simulation time 38250539 ps
CPU time 1.41 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 230332 kb
Host smart-9cd19288-1fcd-4a1e-8717-42ff5a47ee46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190700145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.4190700145
Directory /workspace/38.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.otp_ctrl_intr_test.2471755788
Short name T1212
Test name
Test status
Simulation time 41961302 ps
CPU time 1.4 seconds
Started Jul 03 06:26:37 PM PDT 24
Finished Jul 03 06:26:39 PM PDT 24
Peak memory 230540 kb
Host smart-90fe7e0d-c18b-4275-8f5f-edf2674deb4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471755788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2471755788
Directory /workspace/39.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.3107670252
Short name T296
Test name
Test status
Simulation time 108669551 ps
CPU time 3.1 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 239236 kb
Host smart-17e0ebd3-0ccf-4742-b3ed-4d129f80f4a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107670252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_alia
sing.3107670252
Directory /workspace/4.otp_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2891683246
Short name T1268
Test name
Test status
Simulation time 151901145 ps
CPU time 6.55 seconds
Started Jul 03 06:25:58 PM PDT 24
Finished Jul 03 06:26:05 PM PDT 24
Peak memory 239224 kb
Host smart-a31c871b-b2d0-4b04-8e1d-9c2c7aa543b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891683246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_
bash.2891683246
Directory /workspace/4.otp_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.1130047296
Short name T1243
Test name
Test status
Simulation time 269972784 ps
CPU time 1.9 seconds
Started Jul 03 06:25:58 PM PDT 24
Finished Jul 03 06:26:01 PM PDT 24
Peak memory 241300 kb
Host smart-34464671-2144-401e-8615-ceb491e010d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130047296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_r
eset.1130047296
Directory /workspace/4.otp_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1484625286
Short name T1323
Test name
Test status
Simulation time 451839551 ps
CPU time 3.68 seconds
Started Jul 03 06:25:56 PM PDT 24
Finished Jul 03 06:26:00 PM PDT 24
Peak memory 247500 kb
Host smart-91fc1bdf-4416-43d0-9e82-77c258f4b857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484625286 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1484625286
Directory /workspace/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_intr_test.3875115186
Short name T1281
Test name
Test status
Simulation time 73051307 ps
CPU time 1.49 seconds
Started Jul 03 06:25:55 PM PDT 24
Finished Jul 03 06:25:57 PM PDT 24
Peak memory 230988 kb
Host smart-b7c74dd5-aa95-4a36-a47c-f2334e4661ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875115186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3875115186
Directory /workspace/4.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.37533277
Short name T1276
Test name
Test status
Simulation time 72109446 ps
CPU time 1.37 seconds
Started Jul 03 06:25:56 PM PDT 24
Finished Jul 03 06:25:58 PM PDT 24
Peak memory 229880 kb
Host smart-79535f0a-c758-41cd-b067-f90a8a46abe8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_
mem_partial_access.37533277
Directory /workspace/4.otp_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_mem_walk.572173686
Short name T1322
Test name
Test status
Simulation time 38835142 ps
CPU time 1.32 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:25:59 PM PDT 24
Peak memory 230928 kb
Host smart-6eb73c93-d1c8-479e-a73c-1140226a2403
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572173686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.
572173686
Directory /workspace/4.otp_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.2351587267
Short name T1293
Test name
Test status
Simulation time 55749506 ps
CPU time 2.52 seconds
Started Jul 03 06:25:59 PM PDT 24
Finished Jul 03 06:26:02 PM PDT 24
Peak memory 239196 kb
Host smart-c4e38e27-90a7-4885-9d90-56dd3bf3cebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351587267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_c
trl_same_csr_outstanding.2351587267
Directory /workspace/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3274821175
Short name T1244
Test name
Test status
Simulation time 329330451 ps
CPU time 3.6 seconds
Started Jul 03 06:25:53 PM PDT 24
Finished Jul 03 06:25:57 PM PDT 24
Peak memory 246328 kb
Host smart-dec9e2c5-3b6b-44d9-9d14-a606b6e110d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274821175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3274821175
Directory /workspace/4.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.559888077
Short name T268
Test name
Test status
Simulation time 5002714553 ps
CPU time 21.47 seconds
Started Jul 03 06:25:54 PM PDT 24
Finished Jul 03 06:26:15 PM PDT 24
Peak memory 244948 kb
Host smart-bae3e7dd-f095-48fc-ab19-5333e427e2b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559888077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_int
g_err.559888077
Directory /workspace/4.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.otp_ctrl_intr_test.190522903
Short name T1299
Test name
Test status
Simulation time 551796270 ps
CPU time 1.95 seconds
Started Jul 03 06:26:34 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 230292 kb
Host smart-1c3c8ad1-c879-448a-a630-33ac0d859c4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190522903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.190522903
Directory /workspace/40.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.otp_ctrl_intr_test.3036025321
Short name T1251
Test name
Test status
Simulation time 145059107 ps
CPU time 1.4 seconds
Started Jul 03 06:26:36 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 230536 kb
Host smart-2b97c4bc-836d-4b4e-a3bf-a8886e30178f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036025321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3036025321
Directory /workspace/41.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.otp_ctrl_intr_test.2785571988
Short name T1242
Test name
Test status
Simulation time 559035833 ps
CPU time 1.89 seconds
Started Jul 03 06:26:33 PM PDT 24
Finished Jul 03 06:26:35 PM PDT 24
Peak memory 230328 kb
Host smart-d9058bc4-3721-49ff-982c-27ecb40f4c40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785571988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.2785571988
Directory /workspace/42.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.otp_ctrl_intr_test.1394602409
Short name T1265
Test name
Test status
Simulation time 563229248 ps
CPU time 1.54 seconds
Started Jul 03 06:26:32 PM PDT 24
Finished Jul 03 06:26:34 PM PDT 24
Peak memory 230388 kb
Host smart-e535afa5-875d-426c-8165-02b23ae68f00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394602409 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1394602409
Directory /workspace/43.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.otp_ctrl_intr_test.762604567
Short name T1254
Test name
Test status
Simulation time 80366986 ps
CPU time 1.46 seconds
Started Jul 03 06:26:34 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 231064 kb
Host smart-8b37e0d0-9330-4b4c-b177-f02e8c6003c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762604567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.762604567
Directory /workspace/44.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.otp_ctrl_intr_test.1442749600
Short name T1286
Test name
Test status
Simulation time 43332481 ps
CPU time 1.52 seconds
Started Jul 03 06:26:36 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 230984 kb
Host smart-13abc60b-750c-4aac-834e-041a2a5e2e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442749600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.1442749600
Directory /workspace/45.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.otp_ctrl_intr_test.824617665
Short name T1223
Test name
Test status
Simulation time 56751964 ps
CPU time 1.5 seconds
Started Jul 03 06:26:32 PM PDT 24
Finished Jul 03 06:26:34 PM PDT 24
Peak memory 231116 kb
Host smart-89c98c51-6b11-4128-a27e-987513e4d0e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824617665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.824617665
Directory /workspace/46.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.otp_ctrl_intr_test.4291985753
Short name T1225
Test name
Test status
Simulation time 154807199 ps
CPU time 1.61 seconds
Started Jul 03 06:26:34 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 230272 kb
Host smart-033b9da3-eeea-4f25-b214-ab7f2f28fe91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291985753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.4291985753
Directory /workspace/47.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.otp_ctrl_intr_test.388267971
Short name T1291
Test name
Test status
Simulation time 142366223 ps
CPU time 1.52 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:36 PM PDT 24
Peak memory 230632 kb
Host smart-5eb63497-ef9d-4356-8e08-2c5971986678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388267971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.388267971
Directory /workspace/48.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.otp_ctrl_intr_test.116296109
Short name T1297
Test name
Test status
Simulation time 45769357 ps
CPU time 1.52 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:37 PM PDT 24
Peak memory 231036 kb
Host smart-dc8ae154-c2ac-4277-ad17-8dd1d1cd3c06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116296109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.116296109
Directory /workspace/49.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2265354642
Short name T1210
Test name
Test status
Simulation time 95668206 ps
CPU time 2.23 seconds
Started Jul 03 06:25:56 PM PDT 24
Finished Jul 03 06:25:58 PM PDT 24
Peak memory 244996 kb
Host smart-aa9d56d2-6617-44e6-a2c9-68da0c013e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265354642 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2265354642
Directory /workspace/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_csr_rw.121794096
Short name T330
Test name
Test status
Simulation time 51524183 ps
CPU time 1.67 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:02 PM PDT 24
Peak memory 241428 kb
Host smart-93a210e6-622f-4ebc-a4e4-fffd6d7fc572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121794096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.121794096
Directory /workspace/5.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_intr_test.3065697292
Short name T1258
Test name
Test status
Simulation time 37123665 ps
CPU time 1.47 seconds
Started Jul 03 06:25:59 PM PDT 24
Finished Jul 03 06:26:01 PM PDT 24
Peak memory 230292 kb
Host smart-18124bc9-dc98-41f2-a728-8d05c271906d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065697292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3065697292
Directory /workspace/5.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2068640585
Short name T331
Test name
Test status
Simulation time 1054807883 ps
CPU time 2.53 seconds
Started Jul 03 06:26:01 PM PDT 24
Finished Jul 03 06:26:04 PM PDT 24
Peak memory 239184 kb
Host smart-ee128ec7-eeb6-4a6e-a5b4-2138d84f73fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068640585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_c
trl_same_csr_outstanding.2068640585
Directory /workspace/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1613927613
Short name T1203
Test name
Test status
Simulation time 713971688 ps
CPU time 3.31 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:26:01 PM PDT 24
Peak memory 239292 kb
Host smart-a7cf7ad8-01bf-4168-b5cd-9fcd0ec758d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613927613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1613927613
Directory /workspace/5.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3505789713
Short name T370
Test name
Test status
Simulation time 3846112208 ps
CPU time 20.4 seconds
Started Jul 03 06:26:02 PM PDT 24
Finished Jul 03 06:26:22 PM PDT 24
Peak memory 239320 kb
Host smart-4ca7949d-55b5-4517-9797-1bae874fc7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505789713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_in
tg_err.3505789713
Directory /workspace/5.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2585962444
Short name T1290
Test name
Test status
Simulation time 1101335654 ps
CPU time 2.48 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:03 PM PDT 24
Peak memory 245268 kb
Host smart-9ff0b927-b6e3-4099-bda8-384e47e78f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585962444 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.2585962444
Directory /workspace/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3245400740
Short name T1256
Test name
Test status
Simulation time 157518657 ps
CPU time 1.74 seconds
Started Jul 03 06:25:57 PM PDT 24
Finished Jul 03 06:25:59 PM PDT 24
Peak memory 239196 kb
Host smart-7037004c-0508-4d61-b1b1-dcd46603f850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245400740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3245400740
Directory /workspace/6.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_intr_test.2054294900
Short name T1206
Test name
Test status
Simulation time 594225454 ps
CPU time 1.84 seconds
Started Jul 03 06:25:59 PM PDT 24
Finished Jul 03 06:26:01 PM PDT 24
Peak memory 230620 kb
Host smart-df41ee49-a7dc-456d-adb2-24a1c721c76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054294900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.2054294900
Directory /workspace/6.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.4266096664
Short name T1247
Test name
Test status
Simulation time 349815122 ps
CPU time 3.05 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:03 PM PDT 24
Peak memory 242284 kb
Host smart-c0c40638-2411-4ae0-a306-1a54064f9636
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266096664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_c
trl_same_csr_outstanding.4266096664
Directory /workspace/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3488178377
Short name T1220
Test name
Test status
Simulation time 117313543 ps
CPU time 2.73 seconds
Started Jul 03 06:25:59 PM PDT 24
Finished Jul 03 06:26:02 PM PDT 24
Peak memory 239248 kb
Host smart-30cb6076-0053-417d-92e8-709e1b88e988
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488178377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3488178377
Directory /workspace/6.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2383052052
Short name T1208
Test name
Test status
Simulation time 79463000 ps
CPU time 2.47 seconds
Started Jul 03 06:26:04 PM PDT 24
Finished Jul 03 06:26:07 PM PDT 24
Peak memory 239288 kb
Host smart-7d3a8006-bd48-44ad-898e-250186f0be30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383052052 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.2383052052
Directory /workspace/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_csr_rw.286129017
Short name T304
Test name
Test status
Simulation time 70381181 ps
CPU time 1.5 seconds
Started Jul 03 06:25:59 PM PDT 24
Finished Jul 03 06:26:01 PM PDT 24
Peak memory 241116 kb
Host smart-82a47222-ee3b-481e-a733-26b9ab34bc89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286129017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.286129017
Directory /workspace/7.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_intr_test.429517529
Short name T1262
Test name
Test status
Simulation time 38309399 ps
CPU time 1.39 seconds
Started Jul 03 06:26:01 PM PDT 24
Finished Jul 03 06:26:02 PM PDT 24
Peak memory 231052 kb
Host smart-d397274d-168b-42ad-ad20-daa8fcf577b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429517529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.429517529
Directory /workspace/7.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.242365466
Short name T336
Test name
Test status
Simulation time 296412072 ps
CPU time 2.41 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:03 PM PDT 24
Peak memory 239196 kb
Host smart-e414b943-fc85-4ed3-b8e6-aa6734e952dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242365466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=ot
p_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ct
rl_same_csr_outstanding.242365466
Directory /workspace/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3366141810
Short name T1263
Test name
Test status
Simulation time 421580842 ps
CPU time 4.77 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:05 PM PDT 24
Peak memory 246296 kb
Host smart-d547964b-36a6-48dd-9c93-b2f91c20bdc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366141810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3366141810
Directory /workspace/7.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.598370758
Short name T368
Test name
Test status
Simulation time 20090276396 ps
CPU time 41.39 seconds
Started Jul 03 06:26:00 PM PDT 24
Finished Jul 03 06:26:41 PM PDT 24
Peak memory 246132 kb
Host smart-c2ad0e65-7e8a-46a4-ba28-e07c1d6c1e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598370758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_int
g_err.598370758
Directory /workspace/7.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.159978673
Short name T1221
Test name
Test status
Simulation time 435649798 ps
CPU time 3.81 seconds
Started Jul 03 06:26:05 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 247520 kb
Host smart-db6fbc88-35a3-4bd1-9b4d-29e40504482e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159978673 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.159978673
Directory /workspace/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_csr_rw.753464073
Short name T1259
Test name
Test status
Simulation time 171453152 ps
CPU time 1.81 seconds
Started Jul 03 06:26:05 PM PDT 24
Finished Jul 03 06:26:07 PM PDT 24
Peak memory 241548 kb
Host smart-a1ea6d73-f397-49d3-b915-0fe77d5b4e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753464073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.753464073
Directory /workspace/8.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_intr_test.496900642
Short name T1249
Test name
Test status
Simulation time 579971213 ps
CPU time 1.55 seconds
Started Jul 03 06:26:07 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 230580 kb
Host smart-a278ac41-8c8d-4b9c-93c4-9b2f95ac3381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496900642 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.496900642
Directory /workspace/8.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.3092489366
Short name T1237
Test name
Test status
Simulation time 152847748 ps
CPU time 2.51 seconds
Started Jul 03 06:26:07 PM PDT 24
Finished Jul 03 06:26:10 PM PDT 24
Peak memory 239252 kb
Host smart-9d52b427-87a9-423d-92c7-1340774bd1b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092489366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_c
trl_same_csr_outstanding.3092489366
Directory /workspace/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_errors.2193388420
Short name T1301
Test name
Test status
Simulation time 70090412 ps
CPU time 2.81 seconds
Started Jul 03 06:26:06 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 245932 kb
Host smart-d4977ac9-27bd-423a-9b8e-a0d918df6872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193388420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.2193388420
Directory /workspace/8.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.327238466
Short name T1275
Test name
Test status
Simulation time 1504551573 ps
CPU time 11.16 seconds
Started Jul 03 06:26:05 PM PDT 24
Finished Jul 03 06:26:17 PM PDT 24
Peak memory 244048 kb
Host smart-6cc8d30e-e7ca-4ac5-97ab-3be105c14966
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327238466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_int
g_err.327238466
Directory /workspace/8.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.851432454
Short name T1226
Test name
Test status
Simulation time 1094435449 ps
CPU time 3.82 seconds
Started Jul 03 06:26:12 PM PDT 24
Finished Jul 03 06:26:16 PM PDT 24
Peak memory 244588 kb
Host smart-d3c48153-d93d-417a-8be2-203b3c98c877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851432454 -assert nopostproc +UVM_TESTNAME=
otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.851432454
Directory /workspace/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1698119628
Short name T309
Test name
Test status
Simulation time 40147502 ps
CPU time 1.57 seconds
Started Jul 03 06:26:09 PM PDT 24
Finished Jul 03 06:26:11 PM PDT 24
Peak memory 241164 kb
Host smart-50c09340-a728-4f6f-af02-d46a7ad47b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698119628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1698119628
Directory /workspace/9.otp_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_intr_test.3954779187
Short name T1250
Test name
Test status
Simulation time 48982044 ps
CPU time 1.52 seconds
Started Jul 03 06:26:07 PM PDT 24
Finished Jul 03 06:26:09 PM PDT 24
Peak memory 230620 kb
Host smart-64411f42-7833-49e2-8e55-8f3fe1d4569b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954779187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3954779187
Directory /workspace/9.otp_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2764559855
Short name T1234
Test name
Test status
Simulation time 312560269 ps
CPU time 2.73 seconds
Started Jul 03 06:26:07 PM PDT 24
Finished Jul 03 06:26:10 PM PDT 24
Peak memory 242192 kb
Host smart-d1361df7-93be-4306-a140-d17b042f1e14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764559855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=o
tp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_c
trl_same_csr_outstanding.2764559855
Directory /workspace/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_errors.586727871
Short name T1326
Test name
Test status
Simulation time 3211977658 ps
CPU time 8.73 seconds
Started Jul 03 06:26:08 PM PDT 24
Finished Jul 03 06:26:16 PM PDT 24
Peak memory 247204 kb
Host smart-cfdd1594-8c70-49fe-9db2-037a10eb5aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586727871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.586727871
Directory /workspace/9.otp_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.1657945671
Short name T1287
Test name
Test status
Simulation time 638891116 ps
CPU time 9.44 seconds
Started Jul 03 06:26:04 PM PDT 24
Finished Jul 03 06:26:14 PM PDT 24
Peak memory 243984 kb
Host smart-6cfa982a-6a40-4a09-a65b-520f87aba741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657945671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_in
tg_err.1657945671
Directory /workspace/9.otp_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.otp_ctrl_alert_test.3072559349
Short name T1133
Test name
Test status
Simulation time 160494756 ps
CPU time 1.91 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:14:59 PM PDT 24
Peak memory 240208 kb
Host smart-32412f92-dfde-4334-8c07-f6e009c99f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072559349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3072559349
Directory /workspace/0.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.otp_ctrl_background_chks.952960626
Short name T920
Test name
Test status
Simulation time 5731172868 ps
CPU time 14.15 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 242200 kb
Host smart-b2c0baca-7e1f-4881-8c68-87b610a274e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952960626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.952960626
Directory /workspace/0.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/0.otp_ctrl_check_fail.1065570633
Short name T714
Test name
Test status
Simulation time 10357435318 ps
CPU time 46.77 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:51 PM PDT 24
Peak memory 243368 kb
Host smart-7bf4fca7-3170-44b2-9ce8-dc59b0787f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065570633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1065570633
Directory /workspace/0.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_errs.1905623243
Short name T288
Test name
Test status
Simulation time 1723679196 ps
CPU time 21.78 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:19 PM PDT 24
Peak memory 242132 kb
Host smart-297bf7af-3896-41a2-b012-e0f7f15fd9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905623243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1905623243
Directory /workspace/0.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_dai_lock.2295949228
Short name T844
Test name
Test status
Simulation time 716731536 ps
CPU time 7.19 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 242632 kb
Host smart-b972d31e-4f8d-434d-b765-bb1045c8d9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295949228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.2295949228
Directory /workspace/0.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/0.otp_ctrl_low_freq_read.4146443901
Short name T941
Test name
Test status
Simulation time 6018307277 ps
CPU time 17.31 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 241600 kb
Host smart-c6230f42-3ad0-47b7-ac6e-ce5f2096a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146443901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.4146443901
Directory /workspace/0.otp_ctrl_low_freq_read/latest

Test location /workspace/coverage/default/0.otp_ctrl_macro_errs.68641894
Short name T155
Test name
Test status
Simulation time 442189991 ps
CPU time 4.5 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:00 PM PDT 24
Peak memory 242216 kb
Host smart-16247172-3314-4a33-a4c8-6240cbf22d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68641894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.68641894
Directory /workspace/0.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_key_req.1684319105
Short name T833
Test name
Test status
Simulation time 2929458229 ps
CPU time 41.02 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 248820 kb
Host smart-72caf7e2-18b2-4e07-8ace-38789b8a9fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684319105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1684319105
Directory /workspace/0.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_parallel_lc_req.1581187135
Short name T1085
Test name
Test status
Simulation time 918144462 ps
CPU time 26.78 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 248692 kb
Host smart-670f6ba0-8eb1-4f99-89a7-d73f0dda1425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581187135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.1581187135
Directory /workspace/0.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/0.otp_ctrl_partition_walk.1981296126
Short name T454
Test name
Test status
Simulation time 317617711 ps
CPU time 19.8 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 242008 kb
Host smart-44dcb83e-ddde-45be-b077-4c1aa18e85a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981296126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1981296126
Directory /workspace/0.otp_ctrl_partition_walk/latest

Test location /workspace/coverage/default/0.otp_ctrl_regwen.2546931197
Short name T966
Test name
Test status
Simulation time 3917795135 ps
CPU time 11.21 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:15 PM PDT 24
Peak memory 248804 kb
Host smart-8b754b25-d217-4294-873f-d8a99dc15d9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546931197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.2546931197
Directory /workspace/0.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/0.otp_ctrl_sec_cm.3775128908
Short name T237
Test name
Test status
Simulation time 154705649030 ps
CPU time 362.7 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:20:59 PM PDT 24
Peak memory 272256 kb
Host smart-420e0e5d-5bed-4dd7-a4e5-6031fbee1aca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775128908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3775128908
Directory /workspace/0.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.otp_ctrl_smoke.2871695696
Short name T1075
Test name
Test status
Simulation time 1563811179 ps
CPU time 10.32 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 242256 kb
Host smart-bf7b4f02-6548-4542-b8aa-9a75ceaa4dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871695696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2871695696
Directory /workspace/0.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.3216310518
Short name T907
Test name
Test status
Simulation time 140964361756 ps
CPU time 304.31 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:20:14 PM PDT 24
Peak memory 249668 kb
Host smart-d9d20991-57a4-4a6f-8b4b-9daf9ca82125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216310518 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.3216310518
Directory /workspace/0.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.otp_ctrl_test_access.2903215148
Short name T1055
Test name
Test status
Simulation time 337803359 ps
CPU time 14.36 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 242596 kb
Host smart-e80f5617-9256-48be-942c-3630691fd30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903215148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2903215148
Directory /workspace/0.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/1.otp_ctrl_alert_test.4169151884
Short name T1132
Test name
Test status
Simulation time 861383702 ps
CPU time 1.86 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:04 PM PDT 24
Peak memory 240144 kb
Host smart-dd46c018-43f8-4640-bc6a-45e4f201488b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169151884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4169151884
Directory /workspace/1.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.otp_ctrl_background_chks.3175263635
Short name T174
Test name
Test status
Simulation time 836929908 ps
CPU time 25.31 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:27 PM PDT 24
Peak memory 242556 kb
Host smart-14dd8e35-401c-4cd3-a137-f4896f000edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175263635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.3175263635
Directory /workspace/1.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/1.otp_ctrl_check_fail.1077717466
Short name T865
Test name
Test status
Simulation time 3306230331 ps
CPU time 35.97 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:31 PM PDT 24
Peak memory 245400 kb
Host smart-e4d63c50-92fe-4017-a8b4-f476164e2184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077717466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1077717466
Directory /workspace/1.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_errs.946228997
Short name T1004
Test name
Test status
Simulation time 1416941936 ps
CPU time 24.98 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:30 PM PDT 24
Peak memory 242280 kb
Host smart-9dc5928f-8e30-4631-87f7-8fc614e3ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946228997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.946228997
Directory /workspace/1.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_dai_lock.918391155
Short name T826
Test name
Test status
Simulation time 15462895095 ps
CPU time 24.61 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 243332 kb
Host smart-ae99a959-eca7-48a6-a6de-1a65284a9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918391155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.918391155
Directory /workspace/1.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/1.otp_ctrl_init_fail.3962884990
Short name T1109
Test name
Test status
Simulation time 122378710 ps
CPU time 3.78 seconds
Started Jul 03 07:14:53 PM PDT 24
Finished Jul 03 07:14:58 PM PDT 24
Peak memory 242176 kb
Host smart-3cf56956-09ae-4e3b-b794-1d3eaf0db8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962884990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3962884990
Directory /workspace/1.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/1.otp_ctrl_macro_errs.2569585515
Short name T822
Test name
Test status
Simulation time 680116622 ps
CPU time 19.88 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:31 PM PDT 24
Peak memory 242408 kb
Host smart-17824fdb-0056-4483-ab4a-31baa26662b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569585515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2569585515
Directory /workspace/1.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_key_req.3139664006
Short name T537
Test name
Test status
Simulation time 862647636 ps
CPU time 19.32 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 241944 kb
Host smart-c37e0b36-672d-44d4-a226-e6e6b3782f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139664006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3139664006
Directory /workspace/1.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_esc.2079671627
Short name T152
Test name
Test status
Simulation time 512928694 ps
CPU time 13.61 seconds
Started Jul 03 07:14:53 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 242152 kb
Host smart-e0f0f7bc-6970-42f9-99e2-8325d00d2c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079671627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2079671627
Directory /workspace/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/1.otp_ctrl_parallel_lc_req.2948639387
Short name T398
Test name
Test status
Simulation time 2350363770 ps
CPU time 18.86 seconds
Started Jul 03 07:14:56 PM PDT 24
Finished Jul 03 07:15:17 PM PDT 24
Peak memory 242140 kb
Host smart-f863d192-37b3-486f-aff7-b7ad04e479e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2948639387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2948639387
Directory /workspace/1.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/1.otp_ctrl_regwen.2008781429
Short name T751
Test name
Test status
Simulation time 1912758366 ps
CPU time 5.09 seconds
Started Jul 03 07:14:55 PM PDT 24
Finished Jul 03 07:15:01 PM PDT 24
Peak memory 242284 kb
Host smart-4cf36abf-aedd-46c7-b0f8-7aa3df3e89ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008781429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2008781429
Directory /workspace/1.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/1.otp_ctrl_smoke.1555234308
Short name T518
Test name
Test status
Simulation time 233424988 ps
CPU time 5 seconds
Started Jul 03 07:14:54 PM PDT 24
Finished Jul 03 07:15:00 PM PDT 24
Peak memory 241676 kb
Host smart-87368067-0d8a-4ee2-827e-6a9b14c6d2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555234308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.1555234308
Directory /workspace/1.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/1.otp_ctrl_stress_all.4194328580
Short name T1114
Test name
Test status
Simulation time 28886565697 ps
CPU time 92.03 seconds
Started Jul 03 07:14:53 PM PDT 24
Finished Jul 03 07:16:26 PM PDT 24
Peak memory 248816 kb
Host smart-5438db47-98b5-440a-a9d5-c5a6cc551069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194328580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.
4194328580
Directory /workspace/1.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.otp_ctrl_alert_test.2788889905
Short name T241
Test name
Test status
Simulation time 75431684 ps
CPU time 2.17 seconds
Started Jul 03 07:15:23 PM PDT 24
Finished Jul 03 07:15:27 PM PDT 24
Peak memory 240156 kb
Host smart-4f75e8d5-e4f5-4be5-871b-73181428c45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788889905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.2788889905
Directory /workspace/10.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_errs.1286684450
Short name T724
Test name
Test status
Simulation time 1666408063 ps
CPU time 23.89 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:55 PM PDT 24
Peak memory 242388 kb
Host smart-029f7fd7-a43e-410f-96c0-cd8a360c0714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286684450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1286684450
Directory /workspace/10.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_dai_lock.1446990094
Short name T624
Test name
Test status
Simulation time 5581644304 ps
CPU time 48.81 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:16:17 PM PDT 24
Peak memory 242612 kb
Host smart-5a656a9e-c08f-4128-8d6f-b15f3540d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446990094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1446990094
Directory /workspace/10.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/10.otp_ctrl_init_fail.1062744785
Short name T471
Test name
Test status
Simulation time 2531170543 ps
CPU time 7.78 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:35 PM PDT 24
Peak memory 242096 kb
Host smart-97ab1e2c-8d8a-4084-95b5-5ed90073c02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062744785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1062744785
Directory /workspace/10.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/10.otp_ctrl_macro_errs.2345562026
Short name T1012
Test name
Test status
Simulation time 1751458184 ps
CPU time 36.8 seconds
Started Jul 03 07:15:22 PM PDT 24
Finished Jul 03 07:16:01 PM PDT 24
Peak memory 250008 kb
Host smart-946763bb-3218-4e96-8b94-a6d9c700c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345562026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2345562026
Directory /workspace/10.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_key_req.435352015
Short name T705
Test name
Test status
Simulation time 1003054674 ps
CPU time 11.39 seconds
Started Jul 03 07:15:21 PM PDT 24
Finished Jul 03 07:15:35 PM PDT 24
Peak memory 242396 kb
Host smart-89413187-24b2-4147-9c5f-f54fc342cec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435352015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.435352015
Directory /workspace/10.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_esc.2121122472
Short name T540
Test name
Test status
Simulation time 254097978 ps
CPU time 8.06 seconds
Started Jul 03 07:15:23 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 241840 kb
Host smart-788a062d-2b5c-4ee8-91c4-31d123cd26eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121122472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2121122472
Directory /workspace/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/10.otp_ctrl_parallel_lc_req.300637621
Short name T649
Test name
Test status
Simulation time 1987553907 ps
CPU time 16.98 seconds
Started Jul 03 07:15:22 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 242212 kb
Host smart-9ac38b93-ca7b-4420-883c-380b9fa69d75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=300637621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.300637621
Directory /workspace/10.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/10.otp_ctrl_regwen.3277718395
Short name T379
Test name
Test status
Simulation time 1001025398 ps
CPU time 11.21 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:39 PM PDT 24
Peak memory 242200 kb
Host smart-cce1bcf0-c2dd-49c5-8689-b2ef1594c1a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3277718395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3277718395
Directory /workspace/10.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/10.otp_ctrl_smoke.3382476823
Short name T884
Test name
Test status
Simulation time 682391198 ps
CPU time 6.41 seconds
Started Jul 03 07:15:24 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 242340 kb
Host smart-91d85b1d-7e09-4b1d-9f0c-0b94115d121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382476823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3382476823
Directory /workspace/10.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/10.otp_ctrl_test_access.951290045
Short name T182
Test name
Test status
Simulation time 4265944551 ps
CPU time 26.7 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:55 PM PDT 24
Peak memory 242312 kb
Host smart-d2c1fdb1-c2e5-444a-a681-b486e0635fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951290045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.951290045
Directory /workspace/10.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/100.otp_ctrl_init_fail.116260884
Short name T719
Test name
Test status
Simulation time 149207094 ps
CPU time 4.21 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 241880 kb
Host smart-d05dd806-1f9e-411c-b0e5-8da47deb2d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116260884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.116260884
Directory /workspace/100.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/100.otp_ctrl_parallel_lc_esc.506917808
Short name T1160
Test name
Test status
Simulation time 369274189 ps
CPU time 8.8 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 241900 kb
Host smart-98d693e3-4992-4bac-ae5a-e366535127e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506917808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.506917808
Directory /workspace/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/101.otp_ctrl_init_fail.2751105782
Short name T863
Test name
Test status
Simulation time 301516361 ps
CPU time 4.43 seconds
Started Jul 03 07:17:50 PM PDT 24
Finished Jul 03 07:18:00 PM PDT 24
Peak memory 242140 kb
Host smart-5f723f81-8bae-4af7-b617-41810a494c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751105782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2751105782
Directory /workspace/101.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/101.otp_ctrl_parallel_lc_esc.2282733792
Short name T700
Test name
Test status
Simulation time 297903766 ps
CPU time 3.03 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:00 PM PDT 24
Peak memory 241868 kb
Host smart-909b687b-f943-443e-9162-d803f24265a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282733792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.2282733792
Directory /workspace/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/102.otp_ctrl_init_fail.2177498985
Short name T1102
Test name
Test status
Simulation time 491198672 ps
CPU time 4.47 seconds
Started Jul 03 07:17:49 PM PDT 24
Finished Jul 03 07:18:00 PM PDT 24
Peak memory 242016 kb
Host smart-cb9770da-94f4-40a4-afa2-ab56c545c9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177498985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2177498985
Directory /workspace/102.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/102.otp_ctrl_parallel_lc_esc.139710621
Short name T443
Test name
Test status
Simulation time 2396032962 ps
CPU time 4.89 seconds
Started Jul 03 07:17:50 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 242240 kb
Host smart-dec57d0d-b71d-4264-9bb8-963a360a2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139710621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.139710621
Directory /workspace/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/103.otp_ctrl_init_fail.1023634296
Short name T1063
Test name
Test status
Simulation time 557968349 ps
CPU time 4.51 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 242152 kb
Host smart-dfcf11d3-b751-48e8-a744-4a0d4b756304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023634296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.1023634296
Directory /workspace/103.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_init_fail.4081009595
Short name T530
Test name
Test status
Simulation time 114362255 ps
CPU time 3.4 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 241920 kb
Host smart-b8a4f85e-c7d4-4d8d-9166-962d454b6bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081009595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.4081009595
Directory /workspace/104.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/104.otp_ctrl_parallel_lc_esc.1605312411
Short name T553
Test name
Test status
Simulation time 201035894 ps
CPU time 5 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 242036 kb
Host smart-7f34f069-ee56-42f7-b64e-f407209d4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605312411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1605312411
Directory /workspace/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/105.otp_ctrl_parallel_lc_esc.3541029206
Short name T340
Test name
Test status
Simulation time 1356868051 ps
CPU time 3.23 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 241980 kb
Host smart-3bb2858b-ea20-4772-a0fc-17d62f7d365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541029206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3541029206
Directory /workspace/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/106.otp_ctrl_parallel_lc_esc.198645181
Short name T659
Test name
Test status
Simulation time 178244340 ps
CPU time 7.6 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:07 PM PDT 24
Peak memory 241892 kb
Host smart-01b13949-28e1-46e5-b9e5-fe452a4f3736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198645181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.198645181
Directory /workspace/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/107.otp_ctrl_init_fail.2115830366
Short name T483
Test name
Test status
Simulation time 220435637 ps
CPU time 4.39 seconds
Started Jul 03 07:17:52 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 242176 kb
Host smart-5e38259e-6792-4a7e-9571-5149e981551d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115830366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.2115830366
Directory /workspace/107.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/107.otp_ctrl_parallel_lc_esc.1435087938
Short name T538
Test name
Test status
Simulation time 1145143297 ps
CPU time 15.76 seconds
Started Jul 03 07:17:56 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241916 kb
Host smart-5d8ef465-fa3d-421d-abba-6db86d45097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435087938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.1435087938
Directory /workspace/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/108.otp_ctrl_init_fail.3290341959
Short name T179
Test name
Test status
Simulation time 534374348 ps
CPU time 3.42 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 241876 kb
Host smart-28ade0a9-5ed0-4529-aa99-ce625118a1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290341959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3290341959
Directory /workspace/108.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/108.otp_ctrl_parallel_lc_esc.3019401268
Short name T248
Test name
Test status
Simulation time 9440962287 ps
CPU time 23.28 seconds
Started Jul 03 07:17:52 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 241836 kb
Host smart-21a4a495-5143-4868-8136-788a099794aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019401268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.3019401268
Directory /workspace/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/109.otp_ctrl_init_fail.2298774361
Short name T764
Test name
Test status
Simulation time 130625157 ps
CPU time 3.79 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 242108 kb
Host smart-317def1b-eb56-4ee3-a151-dcdb57de2052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298774361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2298774361
Directory /workspace/109.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/109.otp_ctrl_parallel_lc_esc.4067033710
Short name T357
Test name
Test status
Simulation time 186888716 ps
CPU time 9.09 seconds
Started Jul 03 07:17:53 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 242284 kb
Host smart-56fd9b29-8b6f-4447-877e-567bebc8ffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067033710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.4067033710
Directory /workspace/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_alert_test.992048709
Short name T658
Test name
Test status
Simulation time 44117627 ps
CPU time 1.59 seconds
Started Jul 03 07:15:29 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 240064 kb
Host smart-1dfc7f20-c638-450c-80af-52eaf22db022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992048709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.992048709
Directory /workspace/11.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.otp_ctrl_check_fail.2681422276
Short name T619
Test name
Test status
Simulation time 465648424 ps
CPU time 9.65 seconds
Started Jul 03 07:15:27 PM PDT 24
Finished Jul 03 07:15:40 PM PDT 24
Peak memory 248872 kb
Host smart-1171bc8c-e3af-4869-af59-35b0e825594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681422276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2681422276
Directory /workspace/11.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_errs.911259620
Short name T273
Test name
Test status
Simulation time 2114708016 ps
CPU time 38 seconds
Started Jul 03 07:15:27 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 249352 kb
Host smart-0646c126-142c-48c3-9a26-1177679cbee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911259620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.911259620
Directory /workspace/11.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_dai_lock.2699459934
Short name T397
Test name
Test status
Simulation time 1359591468 ps
CPU time 24.77 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:16:01 PM PDT 24
Peak memory 242264 kb
Host smart-06422836-2fd0-4ad1-a30a-8d2861654e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699459934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2699459934
Directory /workspace/11.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/11.otp_ctrl_init_fail.610434842
Short name T1020
Test name
Test status
Simulation time 514978923 ps
CPU time 4.38 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:32 PM PDT 24
Peak memory 242096 kb
Host smart-54a860f4-3085-4648-90ee-8585072c7e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610434842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.610434842
Directory /workspace/11.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/11.otp_ctrl_macro_errs.2587390660
Short name T199
Test name
Test status
Simulation time 2148639034 ps
CPU time 7.91 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 242048 kb
Host smart-abe793b6-458c-4e87-9589-fd6ab50ccdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587390660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2587390660
Directory /workspace/11.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_key_req.3471617809
Short name T12
Test name
Test status
Simulation time 273059049 ps
CPU time 4.04 seconds
Started Jul 03 07:15:26 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 241968 kb
Host smart-f120957f-e053-4275-8ba0-8e32ee9eb6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471617809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3471617809
Directory /workspace/11.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_esc.1604490195
Short name T1007
Test name
Test status
Simulation time 771448119 ps
CPU time 22.37 seconds
Started Jul 03 07:15:26 PM PDT 24
Finished Jul 03 07:15:52 PM PDT 24
Peak memory 241952 kb
Host smart-a00ac594-d9df-4569-9a1e-4df333176a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604490195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1604490195
Directory /workspace/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/11.otp_ctrl_parallel_lc_req.3275120796
Short name T1177
Test name
Test status
Simulation time 477753279 ps
CPU time 8.18 seconds
Started Jul 03 07:15:29 PM PDT 24
Finished Jul 03 07:15:40 PM PDT 24
Peak memory 242016 kb
Host smart-53ba34be-f0e9-49e6-979b-5313d8864125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275120796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3275120796
Directory /workspace/11.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/11.otp_ctrl_regwen.3414227037
Short name T380
Test name
Test status
Simulation time 4501003747 ps
CPU time 12.42 seconds
Started Jul 03 07:15:30 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 242340 kb
Host smart-fb87772c-1b3e-4f59-90e1-64d0c8338270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414227037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3414227037
Directory /workspace/11.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/11.otp_ctrl_smoke.3952386399
Short name T936
Test name
Test status
Simulation time 1822740394 ps
CPU time 8.58 seconds
Started Jul 03 07:15:21 PM PDT 24
Finished Jul 03 07:15:32 PM PDT 24
Peak memory 248428 kb
Host smart-da44d7d2-b502-4227-af99-bbba66b8cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952386399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.3952386399
Directory /workspace/11.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3333647230
Short name T1071
Test name
Test status
Simulation time 151536474448 ps
CPU time 451.52 seconds
Started Jul 03 07:15:31 PM PDT 24
Finished Jul 03 07:23:05 PM PDT 24
Peak memory 329328 kb
Host smart-37ecb20f-fdf0-45a9-951f-fffd87f556ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333647230 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.3333647230
Directory /workspace/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.otp_ctrl_test_access.3870064915
Short name T974
Test name
Test status
Simulation time 260123825 ps
CPU time 5.51 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 242084 kb
Host smart-808ed4cc-e5bb-41ad-8db5-b3ef3c9145fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870064915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3870064915
Directory /workspace/11.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/110.otp_ctrl_init_fail.4222031284
Short name T718
Test name
Test status
Simulation time 205215984 ps
CPU time 4.36 seconds
Started Jul 03 07:17:56 PM PDT 24
Finished Jul 03 07:18:06 PM PDT 24
Peak memory 242212 kb
Host smart-74f4aca6-12f4-4121-8dae-33e0f5d23c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222031284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.4222031284
Directory /workspace/110.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/110.otp_ctrl_parallel_lc_esc.563941682
Short name T679
Test name
Test status
Simulation time 302637438 ps
CPU time 13.73 seconds
Started Jul 03 07:17:52 PM PDT 24
Finished Jul 03 07:18:12 PM PDT 24
Peak memory 241904 kb
Host smart-888929fb-b225-490f-8e8c-fe543d709007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563941682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.563941682
Directory /workspace/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/111.otp_ctrl_init_fail.1423333204
Short name T748
Test name
Test status
Simulation time 1873665378 ps
CPU time 4.06 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 241916 kb
Host smart-eacfd892-8b52-4f38-ab19-5acce9178797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423333204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.1423333204
Directory /workspace/111.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/111.otp_ctrl_parallel_lc_esc.1402541434
Short name T176
Test name
Test status
Simulation time 116725291 ps
CPU time 5.92 seconds
Started Jul 03 07:17:53 PM PDT 24
Finished Jul 03 07:18:05 PM PDT 24
Peak memory 241968 kb
Host smart-9df96c86-3b7a-405f-8498-b50df0045a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402541434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1402541434
Directory /workspace/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/112.otp_ctrl_init_fail.671058500
Short name T808
Test name
Test status
Simulation time 131681832 ps
CPU time 3.76 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:03 PM PDT 24
Peak memory 241848 kb
Host smart-3f1460a3-afd5-417d-bb0a-a4fe428ac1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671058500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.671058500
Directory /workspace/112.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_init_fail.3938881716
Short name T1031
Test name
Test status
Simulation time 2342752625 ps
CPU time 5.83 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:05 PM PDT 24
Peak memory 242436 kb
Host smart-b602a81b-9b01-4e2b-8f00-8b7f7c86582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938881716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3938881716
Directory /workspace/113.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/113.otp_ctrl_parallel_lc_esc.2477208699
Short name T964
Test name
Test status
Simulation time 6130875460 ps
CPU time 11.68 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:15 PM PDT 24
Peak memory 242200 kb
Host smart-081288c7-c0a9-42cb-bb24-25e442928ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477208699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.2477208699
Directory /workspace/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/114.otp_ctrl_init_fail.2113993065
Short name T317
Test name
Test status
Simulation time 150185417 ps
CPU time 3.82 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 241924 kb
Host smart-f9906451-6a7f-4ff5-861b-8f3a9391441d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113993065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2113993065
Directory /workspace/114.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/114.otp_ctrl_parallel_lc_esc.2270212323
Short name T614
Test name
Test status
Simulation time 301358268 ps
CPU time 8.47 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:13 PM PDT 24
Peak memory 241876 kb
Host smart-2ef303bb-e0fe-4849-90e3-82a50c75841a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270212323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2270212323
Directory /workspace/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/115.otp_ctrl_init_fail.3574445880
Short name T796
Test name
Test status
Simulation time 144996929 ps
CPU time 4.78 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 242000 kb
Host smart-f83ae63c-ee43-4445-98e1-d8ea6469d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574445880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3574445880
Directory /workspace/115.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/115.otp_ctrl_parallel_lc_esc.2800002149
Short name T666
Test name
Test status
Simulation time 1740270423 ps
CPU time 4.14 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 241956 kb
Host smart-c7d168c0-691e-43b4-807b-7348b5705ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800002149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2800002149
Directory /workspace/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/116.otp_ctrl_init_fail.3392490237
Short name T74
Test name
Test status
Simulation time 344891599 ps
CPU time 4.04 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 242028 kb
Host smart-6a142379-7db8-4529-9721-cf80b5761be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392490237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3392490237
Directory /workspace/116.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/116.otp_ctrl_parallel_lc_esc.1977067129
Short name T1030
Test name
Test status
Simulation time 194949695 ps
CPU time 4.83 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 241904 kb
Host smart-62f271e3-f306-454e-b29c-c54aaf74f21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977067129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.1977067129
Directory /workspace/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/117.otp_ctrl_init_fail.2700604170
Short name T560
Test name
Test status
Simulation time 1286958868 ps
CPU time 4.66 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 241988 kb
Host smart-28bb9cce-7a72-4780-a5c2-9529e3ae98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700604170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.2700604170
Directory /workspace/117.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/117.otp_ctrl_parallel_lc_esc.3349819208
Short name T979
Test name
Test status
Simulation time 1223987125 ps
CPU time 11.11 seconds
Started Jul 03 07:18:00 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241804 kb
Host smart-6c7ae8da-78ac-48c8-9e4c-dcfbf0401321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349819208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.3349819208
Directory /workspace/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/118.otp_ctrl_parallel_lc_esc.708162624
Short name T645
Test name
Test status
Simulation time 319892748 ps
CPU time 4.28 seconds
Started Jul 03 07:17:57 PM PDT 24
Finished Jul 03 07:18:07 PM PDT 24
Peak memory 242312 kb
Host smart-1850db71-c194-42b0-9499-cd1bbba2f085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708162624 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.708162624
Directory /workspace/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/119.otp_ctrl_init_fail.173156909
Short name T878
Test name
Test status
Simulation time 226133036 ps
CPU time 3.83 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 242460 kb
Host smart-532f446c-946a-4230-8065-f5c3d8073597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173156909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.173156909
Directory /workspace/119.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/119.otp_ctrl_parallel_lc_esc.1524584221
Short name T736
Test name
Test status
Simulation time 1205736612 ps
CPU time 15.28 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 242188 kb
Host smart-f70a9ab4-798f-47bf-bdea-667c5a90a30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524584221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1524584221
Directory /workspace/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_alert_test.365896328
Short name T804
Test name
Test status
Simulation time 148813273 ps
CPU time 1.55 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:33 PM PDT 24
Peak memory 240464 kb
Host smart-36a0f08d-2e74-4bd2-861e-ab6aca319276
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365896328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.365896328
Directory /workspace/12.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_errs.212685247
Short name T14
Test name
Test status
Simulation time 812921756 ps
CPU time 16.05 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:15:52 PM PDT 24
Peak memory 242160 kb
Host smart-4a014018-8819-4a2e-89f5-6a65551c1e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212685247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.212685247
Directory /workspace/12.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_dai_lock.4080294637
Short name T495
Test name
Test status
Simulation time 818405121 ps
CPU time 26.6 seconds
Started Jul 03 07:15:30 PM PDT 24
Finished Jul 03 07:15:59 PM PDT 24
Peak memory 242616 kb
Host smart-f397cb44-0bd0-4417-9f2b-d0a6a9aade9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080294637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.4080294637
Directory /workspace/12.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/12.otp_ctrl_init_fail.3348246679
Short name T439
Test name
Test status
Simulation time 201692888 ps
CPU time 4.24 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:15:40 PM PDT 24
Peak memory 242032 kb
Host smart-8f61a896-f9c9-47a4-b435-10076b60eb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348246679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3348246679
Directory /workspace/12.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/12.otp_ctrl_macro_errs.410766845
Short name T1175
Test name
Test status
Simulation time 733776978 ps
CPU time 23.5 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:15:59 PM PDT 24
Peak memory 242780 kb
Host smart-ea46f6b0-6bc8-4172-b73a-a5c4ba62e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410766845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.410766845
Directory /workspace/12.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_key_req.1794377860
Short name T520
Test name
Test status
Simulation time 239987855 ps
CPU time 7.02 seconds
Started Jul 03 07:15:27 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 242360 kb
Host smart-4d34f104-fbdc-495c-afb0-0f7a459c8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794377860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.1794377860
Directory /workspace/12.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_esc.3120815972
Short name T175
Test name
Test status
Simulation time 697084436 ps
CPU time 19.5 seconds
Started Jul 03 07:15:33 PM PDT 24
Finished Jul 03 07:15:54 PM PDT 24
Peak memory 241868 kb
Host smart-5d002703-e03e-430a-a98d-21cc34685c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120815972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.3120815972
Directory /workspace/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/12.otp_ctrl_parallel_lc_req.1281087619
Short name T1054
Test name
Test status
Simulation time 1651224891 ps
CPU time 12.9 seconds
Started Jul 03 07:15:34 PM PDT 24
Finished Jul 03 07:15:49 PM PDT 24
Peak memory 241912 kb
Host smart-0e696cb6-2be6-49a9-914e-40a7e4604f90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1281087619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1281087619
Directory /workspace/12.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/12.otp_ctrl_regwen.2284884122
Short name T997
Test name
Test status
Simulation time 208788237 ps
CPU time 4.92 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 242020 kb
Host smart-0f2e62a5-b8c7-419c-937a-7a893f4f4000
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2284884122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2284884122
Directory /workspace/12.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/12.otp_ctrl_smoke.4135668640
Short name T1045
Test name
Test status
Simulation time 3872617951 ps
CPU time 9.03 seconds
Started Jul 03 07:15:31 PM PDT 24
Finished Jul 03 07:15:42 PM PDT 24
Peak memory 242172 kb
Host smart-c025967d-7e2f-4427-9420-5a6134fad104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135668640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.4135668640
Directory /workspace/12.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.2494580949
Short name T908
Test name
Test status
Simulation time 52422742508 ps
CPU time 445.49 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:22:57 PM PDT 24
Peak memory 257184 kb
Host smart-52ff0da2-683a-43f1-a823-69cb5df8c5a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494580949 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.2494580949
Directory /workspace/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.otp_ctrl_test_access.1963641999
Short name T988
Test name
Test status
Simulation time 724068075 ps
CPU time 5.41 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 242040 kb
Host smart-56632782-3327-4da6-aa07-0a91b3f97ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963641999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1963641999
Directory /workspace/12.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/120.otp_ctrl_init_fail.4194670597
Short name T824
Test name
Test status
Simulation time 554927976 ps
CPU time 4.56 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:09 PM PDT 24
Peak memory 241996 kb
Host smart-fe14fc21-55a7-430e-83f7-8bfe69a2bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194670597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4194670597
Directory /workspace/120.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/120.otp_ctrl_parallel_lc_esc.1217570753
Short name T606
Test name
Test status
Simulation time 452378689 ps
CPU time 6.44 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 242384 kb
Host smart-49e90d43-c9db-4ac2-9247-e0f048280d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217570753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.1217570753
Directory /workspace/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/121.otp_ctrl_init_fail.2981054326
Short name T608
Test name
Test status
Simulation time 162527470 ps
CPU time 3.88 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 242512 kb
Host smart-482ce045-3ba7-4964-afdb-56fdbb7504f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981054326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2981054326
Directory /workspace/121.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/121.otp_ctrl_parallel_lc_esc.481201034
Short name T7
Test name
Test status
Simulation time 1286366556 ps
CPU time 19.66 seconds
Started Jul 03 07:18:01 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 242344 kb
Host smart-d633828f-b450-4415-949d-08261eecb844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481201034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.481201034
Directory /workspace/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/122.otp_ctrl_init_fail.781223212
Short name T634
Test name
Test status
Simulation time 150155252 ps
CPU time 4.19 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 242408 kb
Host smart-67bdfa43-3720-4d42-bd2d-844a8c2f7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781223212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.781223212
Directory /workspace/122.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/122.otp_ctrl_parallel_lc_esc.205895340
Short name T123
Test name
Test status
Simulation time 832900669 ps
CPU time 19.42 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:24 PM PDT 24
Peak memory 242272 kb
Host smart-598229d9-f1ef-4ba2-bca6-057ad75ee826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205895340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.205895340
Directory /workspace/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/123.otp_ctrl_init_fail.3043232460
Short name T642
Test name
Test status
Simulation time 488598403 ps
CPU time 3.55 seconds
Started Jul 03 07:17:58 PM PDT 24
Finished Jul 03 07:18:07 PM PDT 24
Peak memory 242396 kb
Host smart-01be77ca-0855-4e6c-84ef-112a6909a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043232460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3043232460
Directory /workspace/123.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/123.otp_ctrl_parallel_lc_esc.1761595041
Short name T562
Test name
Test status
Simulation time 732290793 ps
CPU time 11.82 seconds
Started Jul 03 07:17:59 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241784 kb
Host smart-b0ebe96c-8d4a-4210-bb45-94f2a34a55c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761595041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1761595041
Directory /workspace/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/124.otp_ctrl_init_fail.2651733661
Short name T194
Test name
Test status
Simulation time 139708922 ps
CPU time 3.53 seconds
Started Jul 03 07:18:05 PM PDT 24
Finished Jul 03 07:18:13 PM PDT 24
Peak memory 242080 kb
Host smart-c3e6aefe-a98f-4c77-acba-056fc8bd6447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651733661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.2651733661
Directory /workspace/124.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/124.otp_ctrl_parallel_lc_esc.2882623378
Short name T1069
Test name
Test status
Simulation time 832372373 ps
CPU time 24.51 seconds
Started Jul 03 07:18:05 PM PDT 24
Finished Jul 03 07:18:34 PM PDT 24
Peak memory 241912 kb
Host smart-6a4c7457-8956-41da-b433-87fd5985d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882623378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.2882623378
Directory /workspace/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/125.otp_ctrl_init_fail.3757953289
Short name T779
Test name
Test status
Simulation time 110309369 ps
CPU time 4.25 seconds
Started Jul 03 07:18:01 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 242052 kb
Host smart-b694a8c4-8c13-4881-8b6b-4c51c4d0d2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757953289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.3757953289
Directory /workspace/125.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/125.otp_ctrl_parallel_lc_esc.1921427181
Short name T259
Test name
Test status
Simulation time 913978390 ps
CPU time 22.34 seconds
Started Jul 03 07:18:04 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 241856 kb
Host smart-7af8e651-0b07-408f-ab4b-88599540fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921427181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1921427181
Directory /workspace/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/126.otp_ctrl_parallel_lc_esc.1203928430
Short name T780
Test name
Test status
Simulation time 772838693 ps
CPU time 20.18 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:28 PM PDT 24
Peak memory 242128 kb
Host smart-782b25df-d382-4754-8f95-3a272f0326c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203928430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1203928430
Directory /workspace/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/127.otp_ctrl_parallel_lc_esc.2002236327
Short name T252
Test name
Test status
Simulation time 2261089911 ps
CPU time 18.45 seconds
Started Jul 03 07:18:05 PM PDT 24
Finished Jul 03 07:18:28 PM PDT 24
Peak memory 242308 kb
Host smart-72a30e1d-c003-4b3f-9bf1-f5c0b24c35bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002236327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2002236327
Directory /workspace/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/128.otp_ctrl_init_fail.3214170596
Short name T584
Test name
Test status
Simulation time 109002441 ps
CPU time 4.03 seconds
Started Jul 03 07:18:06 PM PDT 24
Finished Jul 03 07:18:14 PM PDT 24
Peak memory 242124 kb
Host smart-a56a8030-e6ee-4a41-811e-e11e5b0c09be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214170596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3214170596
Directory /workspace/128.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/128.otp_ctrl_parallel_lc_esc.1574439572
Short name T247
Test name
Test status
Simulation time 719544569 ps
CPU time 19.65 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 241916 kb
Host smart-f674bf3a-9b1d-48a1-9863-54d97e56856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574439572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1574439572
Directory /workspace/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/129.otp_ctrl_init_fail.2224934698
Short name T667
Test name
Test status
Simulation time 116739673 ps
CPU time 4.19 seconds
Started Jul 03 07:18:05 PM PDT 24
Finished Jul 03 07:18:14 PM PDT 24
Peak memory 241948 kb
Host smart-5f4373dd-05ed-465b-ad46-efd155482767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224934698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2224934698
Directory /workspace/129.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/129.otp_ctrl_parallel_lc_esc.756139644
Short name T489
Test name
Test status
Simulation time 293617705 ps
CPU time 4.18 seconds
Started Jul 03 07:18:01 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 242276 kb
Host smart-d43030f2-3138-4c97-9943-2e3f46a4e73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756139644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.756139644
Directory /workspace/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_alert_test.3285351956
Short name T1141
Test name
Test status
Simulation time 180092965 ps
CPU time 1.86 seconds
Started Jul 03 07:15:39 PM PDT 24
Finished Jul 03 07:15:43 PM PDT 24
Peak memory 240492 kb
Host smart-5524e8ca-161f-4248-892f-759318297643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285351956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.3285351956
Directory /workspace/13.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.otp_ctrl_check_fail.939518644
Short name T88
Test name
Test status
Simulation time 739644423 ps
CPU time 15.15 seconds
Started Jul 03 07:15:33 PM PDT 24
Finished Jul 03 07:15:50 PM PDT 24
Peak memory 242308 kb
Host smart-28c98d3e-1cc0-4396-860c-5d89c8b78715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939518644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.939518644
Directory /workspace/13.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_errs.1558260967
Short name T363
Test name
Test status
Simulation time 1305698968 ps
CPU time 19.98 seconds
Started Jul 03 07:15:31 PM PDT 24
Finished Jul 03 07:15:53 PM PDT 24
Peak memory 242164 kb
Host smart-97abd5ca-f6ef-4c06-9522-07505ae6711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558260967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.1558260967
Directory /workspace/13.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_dai_lock.3654852922
Short name T1103
Test name
Test status
Simulation time 1023092574 ps
CPU time 9.82 seconds
Started Jul 03 07:15:35 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 242352 kb
Host smart-e5872c81-832a-4d02-9ea4-44e9e8cf4df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654852922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3654852922
Directory /workspace/13.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/13.otp_ctrl_init_fail.3310750
Short name T186
Test name
Test status
Simulation time 264765514 ps
CPU time 3.72 seconds
Started Jul 03 07:15:25 PM PDT 24
Finished Jul 03 07:15:32 PM PDT 24
Peak memory 241916 kb
Host smart-af304259-7901-4320-8901-6ead9f72ee06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3310750
Directory /workspace/13.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/13.otp_ctrl_macro_errs.1461145392
Short name T760
Test name
Test status
Simulation time 1377336456 ps
CPU time 24.48 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:16:03 PM PDT 24
Peak memory 247520 kb
Host smart-0ba4c031-f99a-44bf-9660-68b99fa1be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461145392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1461145392
Directory /workspace/13.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_key_req.3030175073
Short name T1104
Test name
Test status
Simulation time 1005150067 ps
CPU time 14.52 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:15:49 PM PDT 24
Peak memory 248824 kb
Host smart-128deb1c-d66d-4382-9325-c5136f6999f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030175073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.3030175073
Directory /workspace/13.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_esc.3940307314
Short name T575
Test name
Test status
Simulation time 265648057 ps
CPU time 6.49 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 241956 kb
Host smart-22d78791-fce9-4304-bdd8-903ef594b8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940307314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3940307314
Directory /workspace/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/13.otp_ctrl_parallel_lc_req.1866830766
Short name T97
Test name
Test status
Simulation time 1254966585 ps
CPU time 16.29 seconds
Started Jul 03 07:15:27 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 241888 kb
Host smart-eca83406-fd42-44b0-93a1-9abbc317e401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866830766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.1866830766
Directory /workspace/13.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/13.otp_ctrl_smoke.1972559361
Short name T1125
Test name
Test status
Simulation time 336723638 ps
CPU time 6.16 seconds
Started Jul 03 07:15:28 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 242052 kb
Host smart-d1a54285-63ea-4892-8dc0-2e28fd1ddaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972559361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1972559361
Directory /workspace/13.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all.2275862261
Short name T476
Test name
Test status
Simulation time 1714878687 ps
CPU time 35.74 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:16:14 PM PDT 24
Peak memory 243444 kb
Host smart-6d2017a1-4560-4205-9dce-6b6aae74689a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275862261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all
.2275862261
Directory /workspace/13.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.2118188504
Short name T543
Test name
Test status
Simulation time 160820609965 ps
CPU time 927.89 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:31:02 PM PDT 24
Peak memory 280968 kb
Host smart-45dc65a7-361e-422f-a490-9d8c99856fb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118188504 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.2118188504
Directory /workspace/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.otp_ctrl_test_access.807924699
Short name T570
Test name
Test status
Simulation time 249503332 ps
CPU time 5.39 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:15:39 PM PDT 24
Peak memory 242248 kb
Host smart-8b6c8554-1401-4726-98d9-5271f014ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807924699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.807924699
Directory /workspace/13.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/130.otp_ctrl_init_fail.2479290944
Short name T742
Test name
Test status
Simulation time 2183052279 ps
CPU time 4.99 seconds
Started Jul 03 07:18:05 PM PDT 24
Finished Jul 03 07:18:15 PM PDT 24
Peak memory 242160 kb
Host smart-a5878011-c135-4395-b92d-b80a3850ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479290944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2479290944
Directory /workspace/130.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/130.otp_ctrl_parallel_lc_esc.3394122455
Short name T731
Test name
Test status
Simulation time 6224342730 ps
CPU time 15.56 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 242560 kb
Host smart-e030993b-3dd3-4e25-9588-557eeeec0bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394122455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.3394122455
Directory /workspace/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/131.otp_ctrl_parallel_lc_esc.150400869
Short name T515
Test name
Test status
Simulation time 365861041 ps
CPU time 9.17 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:16 PM PDT 24
Peak memory 241820 kb
Host smart-6ecb1c22-e884-498b-91de-c9f2b3438476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150400869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.150400869
Directory /workspace/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/132.otp_ctrl_init_fail.3893810546
Short name T830
Test name
Test status
Simulation time 409514150 ps
CPU time 3.45 seconds
Started Jul 03 07:18:02 PM PDT 24
Finished Jul 03 07:18:11 PM PDT 24
Peak memory 242120 kb
Host smart-d08decbf-9e5e-449d-a267-31461b4e34a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893810546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.3893810546
Directory /workspace/132.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/132.otp_ctrl_parallel_lc_esc.1773640266
Short name T413
Test name
Test status
Simulation time 2436669255 ps
CPU time 9.18 seconds
Started Jul 03 07:18:06 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 242376 kb
Host smart-e9610b20-4999-43ca-bb71-f5892c187411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773640266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1773640266
Directory /workspace/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/133.otp_ctrl_init_fail.210088696
Short name T188
Test name
Test status
Simulation time 108288545 ps
CPU time 4.18 seconds
Started Jul 03 07:18:09 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241888 kb
Host smart-09cbc356-480e-4408-9bc6-8925231e95b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210088696 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.210088696
Directory /workspace/133.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/133.otp_ctrl_parallel_lc_esc.2490065640
Short name T139
Test name
Test status
Simulation time 428544980 ps
CPU time 5.91 seconds
Started Jul 03 07:18:08 PM PDT 24
Finished Jul 03 07:18:18 PM PDT 24
Peak memory 241876 kb
Host smart-aa639aed-5788-467c-aa57-10f93470a9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490065640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.2490065640
Directory /workspace/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/134.otp_ctrl_init_fail.1770457456
Short name T1168
Test name
Test status
Simulation time 1616314491 ps
CPU time 4.92 seconds
Started Jul 03 07:18:11 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 242076 kb
Host smart-180ab8cf-a0a0-47c9-b767-b7e70080cabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770457456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1770457456
Directory /workspace/134.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/134.otp_ctrl_parallel_lc_esc.2071514445
Short name T339
Test name
Test status
Simulation time 100391894 ps
CPU time 3.8 seconds
Started Jul 03 07:18:06 PM PDT 24
Finished Jul 03 07:18:14 PM PDT 24
Peak memory 242012 kb
Host smart-f92080ef-1061-4242-8fb1-e8c26328c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071514445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.2071514445
Directory /workspace/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/135.otp_ctrl_init_fail.2862042061
Short name T69
Test name
Test status
Simulation time 139068408 ps
CPU time 4.2 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 242268 kb
Host smart-b168903b-3a82-457b-a326-8a40d62d2443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862042061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2862042061
Directory /workspace/135.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/135.otp_ctrl_parallel_lc_esc.251478505
Short name T1148
Test name
Test status
Simulation time 517297644 ps
CPU time 15.12 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 242232 kb
Host smart-330a5db0-cb98-48a4-a8c8-0a2784bba39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251478505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.251478505
Directory /workspace/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/136.otp_ctrl_init_fail.1534346919
Short name T618
Test name
Test status
Simulation time 272414339 ps
CPU time 3.21 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:18 PM PDT 24
Peak memory 242180 kb
Host smart-3bcfce63-9fff-4beb-a5e0-46bbae5954f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534346919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.1534346919
Directory /workspace/136.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/136.otp_ctrl_parallel_lc_esc.1949475468
Short name T258
Test name
Test status
Simulation time 476732678 ps
CPU time 6.34 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:24 PM PDT 24
Peak memory 241672 kb
Host smart-7261b1fe-5ab0-4eb8-86f3-0a4f709c3309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949475468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.1949475468
Directory /workspace/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/137.otp_ctrl_init_fail.472805555
Short name T1198
Test name
Test status
Simulation time 1545839193 ps
CPU time 3.87 seconds
Started Jul 03 07:18:09 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241984 kb
Host smart-b51ead8a-80e4-4e06-89da-d6225cfd8f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472805555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.472805555
Directory /workspace/137.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/137.otp_ctrl_parallel_lc_esc.1268258218
Short name T555
Test name
Test status
Simulation time 857987288 ps
CPU time 18.29 seconds
Started Jul 03 07:18:09 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 241896 kb
Host smart-e8f5fe09-ecad-4632-bc04-b664caa2644d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268258218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1268258218
Directory /workspace/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/138.otp_ctrl_parallel_lc_esc.145714350
Short name T146
Test name
Test status
Simulation time 5516900907 ps
CPU time 17.63 seconds
Started Jul 03 07:18:08 PM PDT 24
Finished Jul 03 07:18:30 PM PDT 24
Peak memory 242452 kb
Host smart-4d667a59-5e4a-46a7-8a24-524708988ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145714350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.145714350
Directory /workspace/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/139.otp_ctrl_init_fail.2046697332
Short name T563
Test name
Test status
Simulation time 274046389 ps
CPU time 3.93 seconds
Started Jul 03 07:18:14 PM PDT 24
Finished Jul 03 07:18:22 PM PDT 24
Peak memory 242384 kb
Host smart-7a00128b-f77b-4b59-aae9-cdfda183e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046697332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.2046697332
Directory /workspace/139.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/139.otp_ctrl_parallel_lc_esc.2779750583
Short name T675
Test name
Test status
Simulation time 136694572 ps
CPU time 5.53 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:24 PM PDT 24
Peak memory 241888 kb
Host smart-48c3bf58-6baf-402d-be51-0b23cfe6b980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779750583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2779750583
Directory /workspace/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_alert_test.1412566910
Short name T521
Test name
Test status
Simulation time 84469724 ps
CPU time 1.92 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 240440 kb
Host smart-cbf822f2-6f31-45a2-8172-a4653a2ab9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412566910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1412566910
Directory /workspace/14.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.otp_ctrl_check_fail.1878102551
Short name T112
Test name
Test status
Simulation time 5572959782 ps
CPU time 8.5 seconds
Started Jul 03 07:15:31 PM PDT 24
Finished Jul 03 07:15:42 PM PDT 24
Peak memory 248880 kb
Host smart-1ba48865-f69b-4c87-ac8e-737dce6907c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878102551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.1878102551
Directory /workspace/14.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_errs.872613461
Short name T213
Test name
Test status
Simulation time 1788984356 ps
CPU time 22.17 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:15:57 PM PDT 24
Peak memory 242120 kb
Host smart-5fec7393-a05e-4acb-bf83-5d1ebaf18edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872613461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.872613461
Directory /workspace/14.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_dai_lock.6128653
Short name T572
Test name
Test status
Simulation time 246266661 ps
CPU time 7.83 seconds
Started Jul 03 07:15:35 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 242276 kb
Host smart-55d2cd82-ba15-4499-8348-6b7185f7d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6128653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.6128653
Directory /workspace/14.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/14.otp_ctrl_init_fail.245073303
Short name T610
Test name
Test status
Simulation time 221340420 ps
CPU time 3.1 seconds
Started Jul 03 07:15:33 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 242120 kb
Host smart-945e4ad8-bd6e-4d52-9be5-449fd647d9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245073303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.245073303
Directory /workspace/14.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/14.otp_ctrl_macro_errs.168031612
Short name T972
Test name
Test status
Simulation time 34475833373 ps
CPU time 51.98 seconds
Started Jul 03 07:15:30 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 257060 kb
Host smart-25d9edec-b547-4b25-a15d-4ffdfffd1485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168031612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.168031612
Directory /workspace/14.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_key_req.3004621104
Short name T234
Test name
Test status
Simulation time 973815909 ps
CPU time 6.77 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 242024 kb
Host smart-9fa8bef4-e798-4f78-881e-e36afc82ac22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004621104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3004621104
Directory /workspace/14.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_esc.2714859054
Short name T354
Test name
Test status
Simulation time 152119174 ps
CPU time 7.02 seconds
Started Jul 03 07:15:32 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 241952 kb
Host smart-f75284d2-8449-4787-9671-ff294d5df5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714859054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2714859054
Directory /workspace/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/14.otp_ctrl_parallel_lc_req.1347415647
Short name T399
Test name
Test status
Simulation time 1502758403 ps
CPU time 21.27 seconds
Started Jul 03 07:15:39 PM PDT 24
Finished Jul 03 07:16:03 PM PDT 24
Peak memory 241976 kb
Host smart-c2ad4a66-12b3-42cd-b66f-7f9a69498169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1347415647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.1347415647
Directory /workspace/14.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/14.otp_ctrl_regwen.97429777
Short name T1040
Test name
Test status
Simulation time 325170523 ps
CPU time 9.65 seconds
Started Jul 03 07:15:30 PM PDT 24
Finished Jul 03 07:15:42 PM PDT 24
Peak memory 241948 kb
Host smart-b0177054-c475-4baf-91f3-827039d5026c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=97429777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.97429777
Directory /workspace/14.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/14.otp_ctrl_smoke.1323196480
Short name T768
Test name
Test status
Simulation time 489211649 ps
CPU time 5.73 seconds
Started Jul 03 07:15:33 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 242168 kb
Host smart-b9537c19-b9a1-4aef-a9ef-b81e8da5e82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323196480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.1323196480
Directory /workspace/14.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/14.otp_ctrl_test_access.1849102240
Short name T472
Test name
Test status
Simulation time 2926205717 ps
CPU time 22.78 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:16:06 PM PDT 24
Peak memory 243132 kb
Host smart-f5c900ae-ab28-4ff7-a141-4245218aef8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849102240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.1849102240
Directory /workspace/14.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/140.otp_ctrl_init_fail.2531774575
Short name T86
Test name
Test status
Simulation time 163946209 ps
CPU time 3.95 seconds
Started Jul 03 07:18:07 PM PDT 24
Finished Jul 03 07:18:15 PM PDT 24
Peak memory 242164 kb
Host smart-5f4065e6-09e0-4865-8a59-0455f2cec56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531774575 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2531774575
Directory /workspace/140.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/140.otp_ctrl_parallel_lc_esc.3397338163
Short name T600
Test name
Test status
Simulation time 321474327 ps
CPU time 4.31 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 242224 kb
Host smart-b6fdebd0-49bd-415d-bf38-b97363c8ceef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397338163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3397338163
Directory /workspace/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/141.otp_ctrl_parallel_lc_esc.301915864
Short name T545
Test name
Test status
Simulation time 93448195 ps
CPU time 2.93 seconds
Started Jul 03 07:18:16 PM PDT 24
Finished Jul 03 07:18:22 PM PDT 24
Peak memory 241764 kb
Host smart-3fa04610-3ccd-4b2e-ad68-924a87d448d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301915864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.301915864
Directory /workspace/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/142.otp_ctrl_init_fail.3355910789
Short name T66
Test name
Test status
Simulation time 318596722 ps
CPU time 4.76 seconds
Started Jul 03 07:18:14 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 241984 kb
Host smart-359646b9-31fc-4c4b-845c-2c783a3350ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355910789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3355910789
Directory /workspace/142.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/142.otp_ctrl_parallel_lc_esc.2364303909
Short name T1046
Test name
Test status
Simulation time 489494090 ps
CPU time 4.89 seconds
Started Jul 03 07:18:08 PM PDT 24
Finished Jul 03 07:18:18 PM PDT 24
Peak memory 242136 kb
Host smart-d7a0e771-5c2f-4c1f-88d9-0dea0ece2bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364303909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2364303909
Directory /workspace/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/143.otp_ctrl_init_fail.3692856858
Short name T68
Test name
Test status
Simulation time 140921457 ps
CPU time 3.77 seconds
Started Jul 03 07:18:09 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 241760 kb
Host smart-303f568f-d184-4baf-9c5b-97f51e1a31af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692856858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3692856858
Directory /workspace/143.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/143.otp_ctrl_parallel_lc_esc.3063844744
Short name T1138
Test name
Test status
Simulation time 182028543 ps
CPU time 4.66 seconds
Started Jul 03 07:18:11 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 241892 kb
Host smart-2e75012f-e25b-4835-870c-e466fd0a76e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063844744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3063844744
Directory /workspace/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/144.otp_ctrl_init_fail.3815588015
Short name T807
Test name
Test status
Simulation time 317042914 ps
CPU time 4.06 seconds
Started Jul 03 07:18:07 PM PDT 24
Finished Jul 03 07:18:15 PM PDT 24
Peak memory 242112 kb
Host smart-173198d8-00a4-45a9-9666-a5214eef5123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815588015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.3815588015
Directory /workspace/144.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/144.otp_ctrl_parallel_lc_esc.108293175
Short name T419
Test name
Test status
Simulation time 4475455935 ps
CPU time 15.06 seconds
Started Jul 03 07:18:08 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 241892 kb
Host smart-5d1ee417-e565-458f-b827-99f3b606d5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108293175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.108293175
Directory /workspace/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/145.otp_ctrl_init_fail.2744615882
Short name T60
Test name
Test status
Simulation time 141074545 ps
CPU time 3.66 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:22 PM PDT 24
Peak memory 241932 kb
Host smart-ae338561-ebbe-4c45-b62a-7e0643d719f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744615882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2744615882
Directory /workspace/145.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/145.otp_ctrl_parallel_lc_esc.588575498
Short name T1068
Test name
Test status
Simulation time 466857247 ps
CPU time 13.03 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 241760 kb
Host smart-16248526-2bb6-4b93-9fbd-5aa5c94328f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588575498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.588575498
Directory /workspace/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/146.otp_ctrl_init_fail.3844413892
Short name T772
Test name
Test status
Simulation time 99792813 ps
CPU time 3.87 seconds
Started Jul 03 07:18:16 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 241928 kb
Host smart-dd53c048-9ff2-4613-83fb-d70efd064c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844413892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3844413892
Directory /workspace/146.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/146.otp_ctrl_parallel_lc_esc.137604743
Short name T325
Test name
Test status
Simulation time 475835443 ps
CPU time 5.44 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 242364 kb
Host smart-a20c2855-3608-45b6-827b-1213dc1c26c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137604743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.137604743
Directory /workspace/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/147.otp_ctrl_init_fail.1204596175
Short name T44
Test name
Test status
Simulation time 376946518 ps
CPU time 3.73 seconds
Started Jul 03 07:18:16 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 242080 kb
Host smart-467a2f2a-4edf-479b-a0a3-7f29a8091493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204596175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1204596175
Directory /workspace/147.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/147.otp_ctrl_parallel_lc_esc.1626573396
Short name T589
Test name
Test status
Simulation time 4133524648 ps
CPU time 18.94 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:35 PM PDT 24
Peak memory 241944 kb
Host smart-7d2985d4-e862-471d-99b1-e50296bad3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626573396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.1626573396
Directory /workspace/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/148.otp_ctrl_init_fail.1968031573
Short name T886
Test name
Test status
Simulation time 117203290 ps
CPU time 4.3 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 242096 kb
Host smart-5cff195b-c1c1-4d0c-9c35-e6c7c90c5dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968031573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1968031573
Directory /workspace/148.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/148.otp_ctrl_parallel_lc_esc.1711586936
Short name T423
Test name
Test status
Simulation time 115692895 ps
CPU time 3 seconds
Started Jul 03 07:18:14 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 241940 kb
Host smart-6870a14b-c6f2-4f40-8f06-2b785058f6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711586936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1711586936
Directory /workspace/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/149.otp_ctrl_init_fail.2056466896
Short name T1024
Test name
Test status
Simulation time 113450101 ps
CPU time 3.85 seconds
Started Jul 03 07:18:14 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 241924 kb
Host smart-ead379f0-5b95-4058-aa6c-178c43d9bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056466896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.2056466896
Directory /workspace/149.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/149.otp_ctrl_parallel_lc_esc.194638744
Short name T1099
Test name
Test status
Simulation time 2054716836 ps
CPU time 5.55 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 242420 kb
Host smart-c29d59ba-9287-4652-b32c-f032539dcc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194638744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.194638744
Directory /workspace/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_alert_test.1586804026
Short name T703
Test name
Test status
Simulation time 104668925 ps
CPU time 1.68 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 240528 kb
Host smart-e5dd0bdd-82fc-46b2-aa29-3393055b389e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586804026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.1586804026
Directory /workspace/15.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.otp_ctrl_check_fail.1957869369
Short name T109
Test name
Test status
Simulation time 637698267 ps
CPU time 4.74 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 242280 kb
Host smart-cfc2c674-604b-446a-b411-55e0d4e75621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957869369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1957869369
Directory /workspace/15.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_errs.900351106
Short name T173
Test name
Test status
Simulation time 260259547 ps
CPU time 13.94 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:15:54 PM PDT 24
Peak memory 241836 kb
Host smart-b6b6405c-0e22-42c3-8eef-035dff42b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900351106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.900351106
Directory /workspace/15.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_dai_lock.424661581
Short name T684
Test name
Test status
Simulation time 478847872 ps
CPU time 14.79 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:15:56 PM PDT 24
Peak memory 242000 kb
Host smart-72e5b1ea-0b39-4826-8435-b06b71004c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424661581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.424661581
Directory /workspace/15.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/15.otp_ctrl_init_fail.447954501
Short name T947
Test name
Test status
Simulation time 125355621 ps
CPU time 4.48 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 242040 kb
Host smart-b8554b8b-970e-427d-a217-29ff43f63fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447954501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.447954501
Directory /workspace/15.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/15.otp_ctrl_macro_errs.1274038825
Short name T158
Test name
Test status
Simulation time 12694155117 ps
CPU time 28.01 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:16:12 PM PDT 24
Peak memory 248808 kb
Host smart-9997e1df-51b6-42da-908b-430b5cf40c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274038825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1274038825
Directory /workspace/15.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_key_req.1689521578
Short name T1022
Test name
Test status
Simulation time 10132614121 ps
CPU time 29.18 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 243196 kb
Host smart-12467941-48d5-4dc9-aec4-5ad207208eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689521578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.1689521578
Directory /workspace/15.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_esc.369095892
Short name T923
Test name
Test status
Simulation time 3184050269 ps
CPU time 23.71 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 242212 kb
Host smart-73d1ece1-1116-47d2-985b-f3520306f001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369095892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.369095892
Directory /workspace/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/15.otp_ctrl_parallel_lc_req.3856271490
Short name T547
Test name
Test status
Simulation time 925198776 ps
CPU time 15.89 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:16:00 PM PDT 24
Peak memory 248728 kb
Host smart-420002a6-22ae-4efc-9edd-1b83ce0cfcf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856271490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.3856271490
Directory /workspace/15.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/15.otp_ctrl_regwen.2570323286
Short name T1161
Test name
Test status
Simulation time 99081338 ps
CPU time 3.94 seconds
Started Jul 03 07:15:36 PM PDT 24
Finished Jul 03 07:15:42 PM PDT 24
Peak memory 248616 kb
Host smart-0310f6c1-88f5-4d54-b724-792cef92647a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2570323286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2570323286
Directory /workspace/15.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/15.otp_ctrl_smoke.3994086573
Short name T469
Test name
Test status
Simulation time 176763002 ps
CPU time 3.19 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:15:43 PM PDT 24
Peak memory 242476 kb
Host smart-052e681e-7234-4fda-9984-1bd50180b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994086573 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.3994086573
Directory /workspace/15.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all.2489367603
Short name T902
Test name
Test status
Simulation time 29732795052 ps
CPU time 187.4 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 248832 kb
Host smart-ea8fc816-0d9b-429f-91f1-e2362e194e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489367603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all
.2489367603
Directory /workspace/15.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3108104026
Short name T277
Test name
Test status
Simulation time 816155992820 ps
CPU time 1306.11 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:37:27 PM PDT 24
Peak memory 265320 kb
Host smart-16785172-5f45-432b-9632-adc8520ce30e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108104026 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.3108104026
Directory /workspace/15.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.otp_ctrl_test_access.2080698596
Short name T1120
Test name
Test status
Simulation time 4149449449 ps
CPU time 37.95 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 242084 kb
Host smart-bd9628fb-399e-4e9c-9921-ebd09a801c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080698596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2080698596
Directory /workspace/15.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/150.otp_ctrl_init_fail.618862562
Short name T652
Test name
Test status
Simulation time 584477339 ps
CPU time 4.08 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:20 PM PDT 24
Peak memory 242404 kb
Host smart-c4a9fdf5-b539-41e0-871d-7833f7822c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618862562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.618862562
Directory /workspace/150.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/150.otp_ctrl_parallel_lc_esc.3050965522
Short name T980
Test name
Test status
Simulation time 1995075509 ps
CPU time 15.6 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:32 PM PDT 24
Peak memory 241956 kb
Host smart-d9d1bd4a-ed08-4ac4-a777-da78e1b0aca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050965522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.3050965522
Directory /workspace/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/151.otp_ctrl_init_fail.1448734106
Short name T54
Test name
Test status
Simulation time 140190479 ps
CPU time 4.93 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:20 PM PDT 24
Peak memory 242196 kb
Host smart-78cf37ab-2938-416b-9674-5c6ff99fbd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448734106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.1448734106
Directory /workspace/151.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/151.otp_ctrl_parallel_lc_esc.482901395
Short name T503
Test name
Test status
Simulation time 21900074967 ps
CPU time 41.75 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:57 PM PDT 24
Peak memory 244396 kb
Host smart-4e45b895-d7b4-4ed6-901a-40693224fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482901395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.482901395
Directory /workspace/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/152.otp_ctrl_init_fail.4037364342
Short name T114
Test name
Test status
Simulation time 1732501359 ps
CPU time 5.85 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:21 PM PDT 24
Peak memory 242128 kb
Host smart-78a6ab55-07cf-4003-9076-9601a80b077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037364342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.4037364342
Directory /workspace/152.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/152.otp_ctrl_parallel_lc_esc.789986534
Short name T942
Test name
Test status
Simulation time 386263491 ps
CPU time 8.05 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 242248 kb
Host smart-90399d66-841d-452d-b2df-b693db5a5ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789986534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.789986534
Directory /workspace/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/153.otp_ctrl_init_fail.1624437580
Short name T549
Test name
Test status
Simulation time 165141218 ps
CPU time 4.29 seconds
Started Jul 03 07:18:15 PM PDT 24
Finished Jul 03 07:18:23 PM PDT 24
Peak memory 241884 kb
Host smart-dcb12810-e805-4f01-b36e-d29ab16f0cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624437580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1624437580
Directory /workspace/153.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/153.otp_ctrl_parallel_lc_esc.222204248
Short name T442
Test name
Test status
Simulation time 664131226 ps
CPU time 20.38 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:36 PM PDT 24
Peak memory 241616 kb
Host smart-cf6fb4ff-c578-4366-a51c-dab8118ac328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222204248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.222204248
Directory /workspace/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/154.otp_ctrl_init_fail.3843639374
Short name T740
Test name
Test status
Simulation time 438056377 ps
CPU time 5.7 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:22 PM PDT 24
Peak memory 241920 kb
Host smart-3c03567e-641c-4829-9aec-ab851735dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843639374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3843639374
Directory /workspace/154.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/154.otp_ctrl_parallel_lc_esc.1984057663
Short name T1144
Test name
Test status
Simulation time 278781931 ps
CPU time 6.31 seconds
Started Jul 03 07:18:16 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 241816 kb
Host smart-9cdc6b65-880f-42be-8181-495e905ccf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984057663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1984057663
Directory /workspace/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/155.otp_ctrl_init_fail.3215486994
Short name T474
Test name
Test status
Simulation time 269128174 ps
CPU time 4.1 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:20 PM PDT 24
Peak memory 242072 kb
Host smart-a7e59968-d890-40d7-b465-d47e640242eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215486994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3215486994
Directory /workspace/155.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/155.otp_ctrl_parallel_lc_esc.1672802448
Short name T558
Test name
Test status
Simulation time 490353516 ps
CPU time 5.47 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:20 PM PDT 24
Peak memory 241724 kb
Host smart-f1b985b2-d254-48b0-b0e3-527a24795d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672802448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1672802448
Directory /workspace/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/156.otp_ctrl_init_fail.3970476279
Short name T1003
Test name
Test status
Simulation time 327273714 ps
CPU time 4.76 seconds
Started Jul 03 07:18:11 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 241916 kb
Host smart-cbf32fbd-5b14-4fe1-9d14-f9ccfa2de93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970476279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.3970476279
Directory /workspace/156.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/156.otp_ctrl_parallel_lc_esc.2321726855
Short name T702
Test name
Test status
Simulation time 1464410811 ps
CPU time 3.92 seconds
Started Jul 03 07:18:11 PM PDT 24
Finished Jul 03 07:18:18 PM PDT 24
Peak memory 241824 kb
Host smart-872e8bd5-b564-4eb2-8514-f8c6ef22ffd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321726855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2321726855
Directory /workspace/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/157.otp_ctrl_init_fail.2135764487
Short name T970
Test name
Test status
Simulation time 471733614 ps
CPU time 4.38 seconds
Started Jul 03 07:18:12 PM PDT 24
Finished Jul 03 07:18:19 PM PDT 24
Peak memory 241892 kb
Host smart-e288cc32-d09f-4e56-8f5f-79668bc7132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135764487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.2135764487
Directory /workspace/157.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/157.otp_ctrl_parallel_lc_esc.3524604791
Short name T345
Test name
Test status
Simulation time 305098772 ps
CPU time 9.32 seconds
Started Jul 03 07:18:13 PM PDT 24
Finished Jul 03 07:18:25 PM PDT 24
Peak memory 242252 kb
Host smart-c1c67d7f-88e6-44b9-87ba-23d27290787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524604791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.3524604791
Directory /workspace/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/158.otp_ctrl_init_fail.966870614
Short name T571
Test name
Test status
Simulation time 1668737897 ps
CPU time 5.38 seconds
Started Jul 03 07:18:18 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 242128 kb
Host smart-7faa40e4-a9f1-415f-882c-4b148f299069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966870614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.966870614
Directory /workspace/158.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/158.otp_ctrl_parallel_lc_esc.1396341127
Short name T527
Test name
Test status
Simulation time 368936755 ps
CPU time 5.39 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 241840 kb
Host smart-2f67d7aa-bb48-4c3e-b7ef-65851075b96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396341127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1396341127
Directory /workspace/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/159.otp_ctrl_init_fail.426205444
Short name T870
Test name
Test status
Simulation time 215562433 ps
CPU time 3.63 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:24 PM PDT 24
Peak memory 242252 kb
Host smart-897dc416-c1cf-44b1-834d-77de46a4bd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426205444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.426205444
Directory /workspace/159.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/159.otp_ctrl_parallel_lc_esc.4235664450
Short name T840
Test name
Test status
Simulation time 2487225499 ps
CPU time 8.32 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:29 PM PDT 24
Peak memory 241772 kb
Host smart-06efdbb5-ca51-4ac2-af86-016180a52496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235664450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.4235664450
Directory /workspace/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_alert_test.4254488324
Short name T501
Test name
Test status
Simulation time 199278088 ps
CPU time 1.71 seconds
Started Jul 03 07:15:42 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 240160 kb
Host smart-b673a4cb-8c7f-4c09-b1e9-cbcc5cac289d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254488324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.4254488324
Directory /workspace/16.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.otp_ctrl_check_fail.3627299299
Short name T45
Test name
Test status
Simulation time 21899674139 ps
CPU time 56.06 seconds
Started Jul 03 07:15:39 PM PDT 24
Finished Jul 03 07:16:38 PM PDT 24
Peak memory 248880 kb
Host smart-bb0d948d-d2eb-4897-a5cd-dba10257612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627299299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3627299299
Directory /workspace/16.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_errs.2628774729
Short name T1008
Test name
Test status
Simulation time 927090686 ps
CPU time 29.26 seconds
Started Jul 03 07:15:43 PM PDT 24
Finished Jul 03 07:16:16 PM PDT 24
Peak memory 242036 kb
Host smart-e7d6d9d0-840e-4472-a34e-ac4b1a0b1da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628774729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2628774729
Directory /workspace/16.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_dai_lock.4048036137
Short name T1072
Test name
Test status
Simulation time 435261308 ps
CPU time 3.32 seconds
Started Jul 03 07:15:39 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 241888 kb
Host smart-2f98ab54-e762-4ca0-b56d-efe1d275000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048036137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.4048036137
Directory /workspace/16.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/16.otp_ctrl_init_fail.332001121
Short name T883
Test name
Test status
Simulation time 167800844 ps
CPU time 4.13 seconds
Started Jul 03 07:15:38 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 242040 kb
Host smart-182a8143-1774-4ab8-8966-c28b53c38a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332001121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.332001121
Directory /workspace/16.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/16.otp_ctrl_macro_errs.3443113068
Short name T261
Test name
Test status
Simulation time 5428500527 ps
CPU time 39.93 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 258452 kb
Host smart-e4ca98a7-5ebb-445f-ac32-41449b0b21f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443113068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3443113068
Directory /workspace/16.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_key_req.3110313147
Short name T242
Test name
Test status
Simulation time 5255377922 ps
CPU time 18.53 seconds
Started Jul 03 07:15:41 PM PDT 24
Finished Jul 03 07:16:04 PM PDT 24
Peak memory 248872 kb
Host smart-a08f1e6c-4fbf-4f84-9505-1cd513578d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110313147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3110313147
Directory /workspace/16.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_esc.3743850097
Short name T829
Test name
Test status
Simulation time 2571741776 ps
CPU time 10.12 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:15:54 PM PDT 24
Peak memory 241840 kb
Host smart-d34712ae-9799-4323-9036-d9ea0d7c5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743850097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3743850097
Directory /workspace/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/16.otp_ctrl_parallel_lc_req.65450598
Short name T1196
Test name
Test status
Simulation time 139633033 ps
CPU time 4.6 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:15:48 PM PDT 24
Peak memory 248324 kb
Host smart-a54c035b-eab2-481d-bc00-ff61fdbec23f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=65450598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.65450598
Directory /workspace/16.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/16.otp_ctrl_regwen.687611248
Short name T383
Test name
Test status
Simulation time 287499836 ps
CPU time 7.76 seconds
Started Jul 03 07:15:41 PM PDT 24
Finished Jul 03 07:15:53 PM PDT 24
Peak memory 242032 kb
Host smart-389b2a9a-83f5-4c13-b77c-ba35f5823fe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687611248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.687611248
Directory /workspace/16.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/16.otp_ctrl_smoke.3351387148
Short name T1070
Test name
Test status
Simulation time 3705657074 ps
CPU time 10.36 seconds
Started Jul 03 07:15:37 PM PDT 24
Finished Jul 03 07:15:50 PM PDT 24
Peak memory 242068 kb
Host smart-d488fda3-7fff-4aa3-ad1d-9e7a7228a3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351387148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3351387148
Directory /workspace/16.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/16.otp_ctrl_stress_all.2481811879
Short name T641
Test name
Test status
Simulation time 28935235134 ps
CPU time 207.35 seconds
Started Jul 03 07:15:43 PM PDT 24
Finished Jul 03 07:19:14 PM PDT 24
Peak memory 266576 kb
Host smart-efd80c98-2f14-49a9-9da9-3b73c38dad04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481811879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all
.2481811879
Directory /workspace/16.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.otp_ctrl_test_access.4180906224
Short name T117
Test name
Test status
Simulation time 2835118161 ps
CPU time 38.24 seconds
Started Jul 03 07:15:42 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242768 kb
Host smart-98e08105-46d6-42e7-a395-86887233f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180906224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.4180906224
Directory /workspace/16.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/160.otp_ctrl_init_fail.511262817
Short name T605
Test name
Test status
Simulation time 252175910 ps
CPU time 4.22 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:25 PM PDT 24
Peak memory 242056 kb
Host smart-72cd7148-2459-46f7-9152-29777e6cc6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511262817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.511262817
Directory /workspace/160.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/160.otp_ctrl_parallel_lc_esc.3905918750
Short name T735
Test name
Test status
Simulation time 6739278967 ps
CPU time 17.36 seconds
Started Jul 03 07:18:19 PM PDT 24
Finished Jul 03 07:18:39 PM PDT 24
Peak memory 241904 kb
Host smart-6d9c18cb-87dc-4d46-bd6d-a9b00f3305d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905918750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.3905918750
Directory /workspace/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/161.otp_ctrl_init_fail.2300686232
Short name T825
Test name
Test status
Simulation time 1601800712 ps
CPU time 5.99 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 241796 kb
Host smart-65d322a6-3871-4f08-9ac1-12b2665cb865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300686232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2300686232
Directory /workspace/161.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/161.otp_ctrl_parallel_lc_esc.2491200577
Short name T514
Test name
Test status
Simulation time 322917050 ps
CPU time 4.37 seconds
Started Jul 03 07:18:18 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 241812 kb
Host smart-daf314e5-cb24-42ff-a2fd-d08abaed224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491200577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2491200577
Directory /workspace/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/162.otp_ctrl_init_fail.1134957693
Short name T872
Test name
Test status
Simulation time 245758286 ps
CPU time 3.37 seconds
Started Jul 03 07:18:18 PM PDT 24
Finished Jul 03 07:18:25 PM PDT 24
Peak memory 242060 kb
Host smart-1f837a05-89eb-4327-ae0c-037c1f29bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134957693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1134957693
Directory /workspace/162.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/162.otp_ctrl_parallel_lc_esc.3996831722
Short name T847
Test name
Test status
Simulation time 276548867 ps
CPU time 5.57 seconds
Started Jul 03 07:18:20 PM PDT 24
Finished Jul 03 07:18:29 PM PDT 24
Peak memory 242156 kb
Host smart-bd7140ea-4e00-4ac7-85a9-cf5d5107cbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996831722 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3996831722
Directory /workspace/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/163.otp_ctrl_init_fail.1937766804
Short name T316
Test name
Test status
Simulation time 185423820 ps
CPU time 3.9 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:24 PM PDT 24
Peak memory 242232 kb
Host smart-ea9eba8c-7f96-4e04-a57c-ee158c353a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937766804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1937766804
Directory /workspace/163.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/163.otp_ctrl_parallel_lc_esc.737524593
Short name T147
Test name
Test status
Simulation time 716964845 ps
CPU time 16.45 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 242344 kb
Host smart-c1618fa3-1490-44cd-81e8-9e7c4e2c1bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737524593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.737524593
Directory /workspace/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/164.otp_ctrl_init_fail.3041655910
Short name T992
Test name
Test status
Simulation time 166993493 ps
CPU time 4.77 seconds
Started Jul 03 07:18:20 PM PDT 24
Finished Jul 03 07:18:28 PM PDT 24
Peak memory 241892 kb
Host smart-3e8e08ea-bc89-4445-b5a0-76e28a7a77ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041655910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3041655910
Directory /workspace/164.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/164.otp_ctrl_parallel_lc_esc.2006204330
Short name T143
Test name
Test status
Simulation time 2903921855 ps
CPU time 15.27 seconds
Started Jul 03 07:18:19 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 241900 kb
Host smart-5fc1cbd4-c8ed-4298-879c-c21b212948f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006204330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2006204330
Directory /workspace/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/165.otp_ctrl_init_fail.4074003457
Short name T948
Test name
Test status
Simulation time 332642877 ps
CPU time 4.4 seconds
Started Jul 03 07:18:20 PM PDT 24
Finished Jul 03 07:18:28 PM PDT 24
Peak memory 241880 kb
Host smart-e00a5445-b90d-49a4-85b2-010bd7d9f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074003457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.4074003457
Directory /workspace/165.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/165.otp_ctrl_parallel_lc_esc.2051937618
Short name T391
Test name
Test status
Simulation time 535879341 ps
CPU time 5.98 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 241828 kb
Host smart-00f05d14-8978-4e40-b2fa-310190b77ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051937618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2051937618
Directory /workspace/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/166.otp_ctrl_init_fail.2926342408
Short name T674
Test name
Test status
Simulation time 402177188 ps
CPU time 3.95 seconds
Started Jul 03 07:18:19 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 241980 kb
Host smart-eb4d1e1d-b2f5-4f28-ae1a-25984d629aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926342408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.2926342408
Directory /workspace/166.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/166.otp_ctrl_parallel_lc_esc.2897609079
Short name T438
Test name
Test status
Simulation time 386729791 ps
CPU time 8.76 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:30 PM PDT 24
Peak memory 242408 kb
Host smart-c14e46b8-c0a5-48a8-8b2e-0013a8cae435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897609079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2897609079
Directory /workspace/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/167.otp_ctrl_init_fail.3142538391
Short name T921
Test name
Test status
Simulation time 155511530 ps
CPU time 3.98 seconds
Started Jul 03 07:18:19 PM PDT 24
Finished Jul 03 07:18:27 PM PDT 24
Peak memory 242060 kb
Host smart-77ced2cd-3549-47e6-9857-fa243ffee286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142538391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3142538391
Directory /workspace/167.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/167.otp_ctrl_parallel_lc_esc.1127592515
Short name T877
Test name
Test status
Simulation time 807278817 ps
CPU time 11.48 seconds
Started Jul 03 07:18:17 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 242368 kb
Host smart-7899c781-58f2-4f83-9e02-2dd71d659804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127592515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1127592515
Directory /workspace/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/168.otp_ctrl_init_fail.1383869860
Short name T823
Test name
Test status
Simulation time 2437765277 ps
CPU time 8.44 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:35 PM PDT 24
Peak memory 242104 kb
Host smart-b48aa180-46e6-4995-a9f1-4188dcf136a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383869860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1383869860
Directory /workspace/168.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/168.otp_ctrl_parallel_lc_esc.3719388224
Short name T695
Test name
Test status
Simulation time 1377843290 ps
CPU time 19.08 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 241820 kb
Host smart-f7cbdd03-cd6a-4840-b818-44e3b488d31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719388224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3719388224
Directory /workspace/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/169.otp_ctrl_init_fail.3069001864
Short name T191
Test name
Test status
Simulation time 115120188 ps
CPU time 3.49 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:30 PM PDT 24
Peak memory 242076 kb
Host smart-aec75ee1-1299-4cb2-9a7f-77b85445d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069001864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3069001864
Directory /workspace/169.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/169.otp_ctrl_parallel_lc_esc.1211048905
Short name T587
Test name
Test status
Simulation time 365818317 ps
CPU time 4.71 seconds
Started Jul 03 07:18:26 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 241832 kb
Host smart-4ca2b5c6-b28c-41eb-84cc-532798fba195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211048905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1211048905
Directory /workspace/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_alert_test.2103699616
Short name T524
Test name
Test status
Simulation time 47463029 ps
CPU time 1.6 seconds
Started Jul 03 07:15:42 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 240104 kb
Host smart-3321c266-1268-4c72-8c48-0f0c186d6382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103699616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.2103699616
Directory /workspace/17.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.otp_ctrl_check_fail.185371344
Short name T50
Test name
Test status
Simulation time 1131494774 ps
CPU time 10.53 seconds
Started Jul 03 07:15:43 PM PDT 24
Finished Jul 03 07:15:57 PM PDT 24
Peak memory 242704 kb
Host smart-413a944e-20bd-4697-9834-415406ac58c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185371344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.185371344
Directory /workspace/17.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_errs.3982722596
Short name T8
Test name
Test status
Simulation time 767269009 ps
CPU time 11.64 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 241920 kb
Host smart-3a847d3a-8243-440c-aa42-644698c2ef24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982722596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.3982722596
Directory /workspace/17.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_dai_lock.3673702902
Short name T395
Test name
Test status
Simulation time 852264579 ps
CPU time 13.71 seconds
Started Jul 03 07:15:41 PM PDT 24
Finished Jul 03 07:15:58 PM PDT 24
Peak memory 242216 kb
Host smart-acd2d7aa-4dc2-44a3-b07c-b8356b725ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673702902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.3673702902
Directory /workspace/17.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/17.otp_ctrl_init_fail.1630171594
Short name T1129
Test name
Test status
Simulation time 433421204 ps
CPU time 3.85 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:15:48 PM PDT 24
Peak memory 242056 kb
Host smart-bcc3a56a-d744-472e-ba84-36cf4ae1558c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630171594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1630171594
Directory /workspace/17.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/17.otp_ctrl_macro_errs.2711169225
Short name T1128
Test name
Test status
Simulation time 5817332881 ps
CPU time 32.18 seconds
Started Jul 03 07:15:47 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 248940 kb
Host smart-2b56d7d9-05e8-4b4b-9e3a-0f5bf6995f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711169225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.2711169225
Directory /workspace/17.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_key_req.46771034
Short name T1001
Test name
Test status
Simulation time 429420002 ps
CPU time 3.49 seconds
Started Jul 03 07:15:43 PM PDT 24
Finished Jul 03 07:15:51 PM PDT 24
Peak memory 242284 kb
Host smart-a9aaa22a-3d30-4fdf-bfe7-8a387f5a0137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46771034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.46771034
Directory /workspace/17.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_esc.1998084801
Short name T513
Test name
Test status
Simulation time 327328099 ps
CPU time 17.18 seconds
Started Jul 03 07:15:40 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 242216 kb
Host smart-5d4004ed-8507-4d44-9a46-f0562aced1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998084801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.1998084801
Directory /workspace/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/17.otp_ctrl_parallel_lc_req.3742301784
Short name T534
Test name
Test status
Simulation time 695045907 ps
CPU time 17.43 seconds
Started Jul 03 07:15:41 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 241944 kb
Host smart-046d3497-c3de-4dbd-beb8-659a962b3d1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742301784 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.3742301784
Directory /workspace/17.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/17.otp_ctrl_smoke.2167782963
Short name T107
Test name
Test status
Simulation time 1348338132 ps
CPU time 6.81 seconds
Started Jul 03 07:15:41 PM PDT 24
Finished Jul 03 07:15:52 PM PDT 24
Peak memory 241948 kb
Host smart-f5bee17f-f642-45f6-8ce5-e4e6680c591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167782963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2167782963
Directory /workspace/17.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/17.otp_ctrl_stress_all.1349784002
Short name T257
Test name
Test status
Simulation time 26166683555 ps
CPU time 277.11 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:20:34 PM PDT 24
Peak memory 266920 kb
Host smart-281216b5-6f13-4644-a513-f9712a8766bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349784002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all
.1349784002
Directory /workspace/17.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.otp_ctrl_test_access.1791201092
Short name T845
Test name
Test status
Simulation time 7284504664 ps
CPU time 41.66 seconds
Started Jul 03 07:15:44 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 242148 kb
Host smart-c2b57232-9e6a-46dc-b101-dc59733da361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791201092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.1791201092
Directory /workspace/17.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/170.otp_ctrl_init_fail.921686942
Short name T866
Test name
Test status
Simulation time 322553770 ps
CPU time 3.43 seconds
Started Jul 03 07:18:25 PM PDT 24
Finished Jul 03 07:18:34 PM PDT 24
Peak memory 241996 kb
Host smart-67d1c56b-2ad8-4c67-b2bd-5e890fd42ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921686942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.921686942
Directory /workspace/170.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/170.otp_ctrl_parallel_lc_esc.2594561812
Short name T1170
Test name
Test status
Simulation time 442179266 ps
CPU time 11.41 seconds
Started Jul 03 07:18:26 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 241856 kb
Host smart-dc6c7ca5-f98e-4b42-ad19-110e1728f44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594561812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.2594561812
Directory /workspace/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/171.otp_ctrl_init_fail.1802401709
Short name T126
Test name
Test status
Simulation time 421920388 ps
CPU time 4.12 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:32 PM PDT 24
Peak memory 242140 kb
Host smart-8490d5d7-71ce-4644-8f8d-a129bdc84e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802401709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1802401709
Directory /workspace/171.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/171.otp_ctrl_parallel_lc_esc.2800610242
Short name T1165
Test name
Test status
Simulation time 171464654 ps
CPU time 6.82 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 242136 kb
Host smart-ea639996-50ed-40c1-bcf0-9abc8911302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800610242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2800610242
Directory /workspace/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/172.otp_ctrl_init_fail.4025948396
Short name T548
Test name
Test status
Simulation time 654258797 ps
CPU time 4.93 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:34 PM PDT 24
Peak memory 242320 kb
Host smart-750ea834-f176-4ccc-a7a1-fbeb4de604a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025948396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.4025948396
Directory /workspace/172.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/172.otp_ctrl_parallel_lc_esc.3522420589
Short name T516
Test name
Test status
Simulation time 374499582 ps
CPU time 5.79 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:35 PM PDT 24
Peak memory 242076 kb
Host smart-4ce9bd84-6fec-4234-bb96-2232ef288202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522420589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3522420589
Directory /workspace/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/173.otp_ctrl_init_fail.2735377337
Short name T459
Test name
Test status
Simulation time 142895238 ps
CPU time 5.17 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 242196 kb
Host smart-474fa4df-caf3-4e92-996c-69af173848e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735377337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2735377337
Directory /workspace/173.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/173.otp_ctrl_parallel_lc_esc.2798384491
Short name T578
Test name
Test status
Simulation time 205025059 ps
CPU time 8.91 seconds
Started Jul 03 07:18:24 PM PDT 24
Finished Jul 03 07:18:38 PM PDT 24
Peak memory 242408 kb
Host smart-6a37cb3f-7c3f-41ec-b85c-2b83bea5b414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798384491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.2798384491
Directory /workspace/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/174.otp_ctrl_init_fail.1622187969
Short name T1182
Test name
Test status
Simulation time 249539893 ps
CPU time 4.62 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 242408 kb
Host smart-a9708a39-b6f6-49fd-b575-90d3a7c9fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622187969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1622187969
Directory /workspace/174.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/174.otp_ctrl_parallel_lc_esc.1342067488
Short name T450
Test name
Test status
Simulation time 269708110 ps
CPU time 3.84 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:30 PM PDT 24
Peak memory 241856 kb
Host smart-9b3f7ba0-bf4b-47c6-a316-f6e1ab4b31e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342067488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1342067488
Directory /workspace/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/175.otp_ctrl_parallel_lc_esc.4017576646
Short name T552
Test name
Test status
Simulation time 158484692 ps
CPU time 4.05 seconds
Started Jul 03 07:18:23 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 241908 kb
Host smart-9cae2002-c045-42f0-a84e-911a6630aed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017576646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.4017576646
Directory /workspace/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/176.otp_ctrl_init_fail.3594948584
Short name T1155
Test name
Test status
Simulation time 126449845 ps
CPU time 3.09 seconds
Started Jul 03 07:18:24 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 242028 kb
Host smart-d45d9f1a-1eaa-4bcf-a43a-68ec9f9e9907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594948584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.3594948584
Directory /workspace/176.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/176.otp_ctrl_parallel_lc_esc.2169836085
Short name T859
Test name
Test status
Simulation time 1297205226 ps
CPU time 16.74 seconds
Started Jul 03 07:18:25 PM PDT 24
Finished Jul 03 07:18:47 PM PDT 24
Peak memory 241792 kb
Host smart-f2948e58-92cb-4f89-99b5-68127811b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169836085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2169836085
Directory /workspace/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/177.otp_ctrl_init_fail.2642520059
Short name T1013
Test name
Test status
Simulation time 285997074 ps
CPU time 4.19 seconds
Started Jul 03 07:18:22 PM PDT 24
Finished Jul 03 07:18:31 PM PDT 24
Peak memory 242140 kb
Host smart-57bc80b3-ebe3-4771-81ab-ab187ecf98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642520059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.2642520059
Directory /workspace/177.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/177.otp_ctrl_parallel_lc_esc.4012032081
Short name T473
Test name
Test status
Simulation time 312157162 ps
CPU time 4.55 seconds
Started Jul 03 07:18:28 PM PDT 24
Finished Jul 03 07:18:38 PM PDT 24
Peak memory 241768 kb
Host smart-1a51bdc3-a086-4455-8ba7-6a802718f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012032081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.4012032081
Directory /workspace/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/178.otp_ctrl_init_fail.3569323093
Short name T197
Test name
Test status
Simulation time 2169713820 ps
CPU time 5.51 seconds
Started Jul 03 07:18:26 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 241984 kb
Host smart-7bbf29fa-49ab-4892-8b10-251b297ba9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569323093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3569323093
Directory /workspace/178.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/178.otp_ctrl_parallel_lc_esc.1585485769
Short name T557
Test name
Test status
Simulation time 207162820 ps
CPU time 3.2 seconds
Started Jul 03 07:18:24 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 242240 kb
Host smart-539958b0-0252-479a-a250-660abea51256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585485769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1585485769
Directory /workspace/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/179.otp_ctrl_init_fail.574920589
Short name T597
Test name
Test status
Simulation time 265113779 ps
CPU time 3.95 seconds
Started Jul 03 07:18:28 PM PDT 24
Finished Jul 03 07:18:38 PM PDT 24
Peak memory 242064 kb
Host smart-3ee22112-9b67-4a1c-a593-332204cd6413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574920589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.574920589
Directory /workspace/179.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/179.otp_ctrl_parallel_lc_esc.1547039788
Short name T935
Test name
Test status
Simulation time 2626597804 ps
CPU time 19.32 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 242000 kb
Host smart-17af1126-446f-4fa7-9412-424ecaeb9480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547039788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1547039788
Directory /workspace/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_alert_test.521659443
Short name T828
Test name
Test status
Simulation time 840768680 ps
CPU time 1.82 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:15:59 PM PDT 24
Peak memory 240188 kb
Host smart-b8a84b53-1b87-45e3-9607-df9807862bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521659443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.521659443
Directory /workspace/18.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.otp_ctrl_check_fail.2825405884
Short name T87
Test name
Test status
Simulation time 507526976 ps
CPU time 6.27 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:00 PM PDT 24
Peak memory 242636 kb
Host smart-77ae578f-164e-4faf-8920-5306e967b95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825405884 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.2825405884
Directory /workspace/18.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_errs.2862121674
Short name T541
Test name
Test status
Simulation time 3372507845 ps
CPU time 14.7 seconds
Started Jul 03 07:15:48 PM PDT 24
Finished Jul 03 07:16:05 PM PDT 24
Peak memory 241996 kb
Host smart-1a5e2f61-1396-4954-83b7-f9747a9b116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862121674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2862121674
Directory /workspace/18.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_dai_lock.2135815330
Short name T232
Test name
Test status
Simulation time 12886611232 ps
CPU time 32.55 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 242688 kb
Host smart-d22a196b-b7fe-4fe3-9bfb-21d5847f923f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135815330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2135815330
Directory /workspace/18.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/18.otp_ctrl_init_fail.385785336
Short name T890
Test name
Test status
Simulation time 351306311 ps
CPU time 4.06 seconds
Started Jul 03 07:15:45 PM PDT 24
Finished Jul 03 07:15:53 PM PDT 24
Peak memory 242068 kb
Host smart-08957db9-fe12-4cbd-8ede-e15bade4aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385785336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.385785336
Directory /workspace/18.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/18.otp_ctrl_macro_errs.1247334764
Short name T1150
Test name
Test status
Simulation time 3515865457 ps
CPU time 41.75 seconds
Started Jul 03 07:15:48 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 261072 kb
Host smart-c3c3d92e-3e54-4e5b-8a25-38ee630f6c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247334764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1247334764
Directory /workspace/18.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_key_req.2672925534
Short name T1026
Test name
Test status
Simulation time 507184644 ps
CPU time 12.18 seconds
Started Jul 03 07:15:46 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 242132 kb
Host smart-31ebe382-5f30-4909-8b68-533fcfb59bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672925534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2672925534
Directory /workspace/18.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_esc.2836752604
Short name T626
Test name
Test status
Simulation time 381648072 ps
CPU time 10.92 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:05 PM PDT 24
Peak memory 242324 kb
Host smart-d56d6751-c75b-4719-9fe2-4b486779efe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836752604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2836752604
Directory /workspace/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/18.otp_ctrl_parallel_lc_req.2685214909
Short name T577
Test name
Test status
Simulation time 567222821 ps
CPU time 6.27 seconds
Started Jul 03 07:15:46 PM PDT 24
Finished Jul 03 07:15:56 PM PDT 24
Peak memory 241872 kb
Host smart-986eab77-0441-4fa7-a069-c692215432a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685214909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2685214909
Directory /workspace/18.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/18.otp_ctrl_regwen.343923697
Short name T672
Test name
Test status
Simulation time 275071798 ps
CPU time 8.94 seconds
Started Jul 03 07:15:49 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 242184 kb
Host smart-aa838b51-edde-4564-9717-916b2b6606ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343923697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.343923697
Directory /workspace/18.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/18.otp_ctrl_smoke.2755200535
Short name T944
Test name
Test status
Simulation time 3965981143 ps
CPU time 9.69 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:03 PM PDT 24
Peak memory 242768 kb
Host smart-67f7b57f-1f15-4ed5-999e-bf98ea08f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755200535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2755200535
Directory /workspace/18.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/18.otp_ctrl_stress_all.2286398790
Short name T1056
Test name
Test status
Simulation time 28907415784 ps
CPU time 225.77 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:19:40 PM PDT 24
Peak memory 265288 kb
Host smart-c68a4d63-1ca8-4988-97af-7e6fe78cdeaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286398790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all
.2286398790
Directory /workspace/18.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.otp_ctrl_test_access.589583523
Short name T536
Test name
Test status
Simulation time 1568363427 ps
CPU time 17.88 seconds
Started Jul 03 07:15:45 PM PDT 24
Finished Jul 03 07:16:07 PM PDT 24
Peak memory 242236 kb
Host smart-cec29852-c1e2-4bca-8b9c-98eb14b42307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589583523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.589583523
Directory /workspace/18.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/180.otp_ctrl_init_fail.983831626
Short name T1034
Test name
Test status
Simulation time 163824333 ps
CPU time 4 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 242140 kb
Host smart-e3664a61-3c90-4b55-9419-3932b5360110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983831626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.983831626
Directory /workspace/180.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/181.otp_ctrl_init_fail.1447982008
Short name T593
Test name
Test status
Simulation time 533370968 ps
CPU time 3.6 seconds
Started Jul 03 07:18:31 PM PDT 24
Finished Jul 03 07:18:39 PM PDT 24
Peak memory 241828 kb
Host smart-ce0b0bad-6d73-4e62-aa76-68393fd1cbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447982008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1447982008
Directory /workspace/181.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_init_fail.4218120278
Short name T1094
Test name
Test status
Simulation time 613370865 ps
CPU time 4.13 seconds
Started Jul 03 07:18:31 PM PDT 24
Finished Jul 03 07:18:40 PM PDT 24
Peak memory 242008 kb
Host smart-a13499dd-1edd-45ed-83dd-245e1e43e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218120278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.4218120278
Directory /workspace/182.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/182.otp_ctrl_parallel_lc_esc.4104066320
Short name T224
Test name
Test status
Simulation time 2674037513 ps
CPU time 25.01 seconds
Started Jul 03 07:18:30 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 241940 kb
Host smart-5aca1446-965d-46d7-9d9d-22b9e647a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104066320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.4104066320
Directory /workspace/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/183.otp_ctrl_init_fail.2947523988
Short name T989
Test name
Test status
Simulation time 2072476625 ps
CPU time 5.79 seconds
Started Jul 03 07:18:28 PM PDT 24
Finished Jul 03 07:18:39 PM PDT 24
Peak memory 242032 kb
Host smart-f6996ad3-2412-4319-84fe-db9f4f5ab7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947523988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.2947523988
Directory /workspace/183.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/183.otp_ctrl_parallel_lc_esc.1639462909
Short name T358
Test name
Test status
Simulation time 678160605 ps
CPU time 11.08 seconds
Started Jul 03 07:18:30 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 241336 kb
Host smart-27057318-cc5b-4574-9d83-92f4406a2003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639462909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1639462909
Directory /workspace/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/184.otp_ctrl_init_fail.1552092038
Short name T220
Test name
Test status
Simulation time 109671614 ps
CPU time 4.11 seconds
Started Jul 03 07:18:29 PM PDT 24
Finished Jul 03 07:18:38 PM PDT 24
Peak memory 242432 kb
Host smart-f9362383-247c-4d07-88f0-891a7f8cb64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552092038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1552092038
Directory /workspace/184.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/184.otp_ctrl_parallel_lc_esc.3448650962
Short name T76
Test name
Test status
Simulation time 1051936071 ps
CPU time 13.09 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 242188 kb
Host smart-f4ab2a2f-cae8-4802-8b0e-e654075d54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448650962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3448650962
Directory /workspace/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/185.otp_ctrl_init_fail.3640918478
Short name T673
Test name
Test status
Simulation time 202511019 ps
CPU time 3.85 seconds
Started Jul 03 07:18:30 PM PDT 24
Finished Jul 03 07:18:39 PM PDT 24
Peak memory 241808 kb
Host smart-b328e36e-8202-41a4-b897-99dd07b11e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640918478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3640918478
Directory /workspace/185.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/185.otp_ctrl_parallel_lc_esc.3402641129
Short name T466
Test name
Test status
Simulation time 185511783 ps
CPU time 2.67 seconds
Started Jul 03 07:18:29 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 241732 kb
Host smart-b1fc5b16-ae92-484b-be23-62c696f82f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402641129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3402641129
Directory /workspace/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/186.otp_ctrl_init_fail.2065882114
Short name T189
Test name
Test status
Simulation time 469168097 ps
CPU time 4.92 seconds
Started Jul 03 07:18:27 PM PDT 24
Finished Jul 03 07:18:38 PM PDT 24
Peak memory 242292 kb
Host smart-e33082a2-a1c7-4d1f-9de0-c8d994e1885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065882114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2065882114
Directory /workspace/186.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/186.otp_ctrl_parallel_lc_esc.205969192
Short name T1080
Test name
Test status
Simulation time 772007892 ps
CPU time 19.81 seconds
Started Jul 03 07:18:29 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 241944 kb
Host smart-2212bcc4-780c-40c1-8dd9-86b7a6653721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205969192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.205969192
Directory /workspace/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/187.otp_ctrl_init_fail.660466719
Short name T1038
Test name
Test status
Simulation time 1849020272 ps
CPU time 3.75 seconds
Started Jul 03 07:18:28 PM PDT 24
Finished Jul 03 07:18:37 PM PDT 24
Peak memory 241816 kb
Host smart-86754eab-9adc-43e3-bf2a-22fe74f74e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660466719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.660466719
Directory /workspace/187.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/187.otp_ctrl_parallel_lc_esc.1254314805
Short name T657
Test name
Test status
Simulation time 795263699 ps
CPU time 22.42 seconds
Started Jul 03 07:18:29 PM PDT 24
Finished Jul 03 07:18:57 PM PDT 24
Peak memory 241832 kb
Host smart-6cde1045-91f4-42ad-9d4e-a9d162a8024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254314805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1254314805
Directory /workspace/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/188.otp_ctrl_init_fail.2574374056
Short name T670
Test name
Test status
Simulation time 121909145 ps
CPU time 4.84 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:42 PM PDT 24
Peak memory 242072 kb
Host smart-c4e97abd-1769-4e7d-82ef-ec4c345f7ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574374056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2574374056
Directory /workspace/188.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/188.otp_ctrl_parallel_lc_esc.2448190469
Short name T178
Test name
Test status
Simulation time 562439478 ps
CPU time 8.79 seconds
Started Jul 03 07:18:31 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 241844 kb
Host smart-a57e212d-9793-4e64-aa59-7d8f707c0bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448190469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2448190469
Directory /workspace/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/189.otp_ctrl_init_fail.3690556707
Short name T502
Test name
Test status
Simulation time 127815200 ps
CPU time 3.46 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 242508 kb
Host smart-6372ddae-321b-451b-91d8-e3eb55d7a8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690556707 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3690556707
Directory /workspace/189.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/189.otp_ctrl_parallel_lc_esc.1711480355
Short name T937
Test name
Test status
Simulation time 227617262 ps
CPU time 11.33 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:49 PM PDT 24
Peak memory 241780 kb
Host smart-41e345c1-8049-4730-a779-921a42ad7ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711480355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.1711480355
Directory /workspace/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_alert_test.3463808618
Short name T815
Test name
Test status
Simulation time 68916787 ps
CPU time 1.57 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:15:59 PM PDT 24
Peak memory 240176 kb
Host smart-4f40032b-e452-4a21-a001-78e152b31847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463808618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.3463808618
Directory /workspace/19.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.otp_ctrl_check_fail.424297219
Short name T29
Test name
Test status
Simulation time 11080268982 ps
CPU time 35.52 seconds
Started Jul 03 07:15:49 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 242216 kb
Host smart-f874d952-d8e5-4381-9c80-b4f1476677ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424297219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.424297219
Directory /workspace/19.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_errs.2937971104
Short name T579
Test name
Test status
Simulation time 335227064 ps
CPU time 20.97 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:16:17 PM PDT 24
Peak memory 242264 kb
Host smart-7632ce75-6e97-49b5-abdd-d4a84b48ec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937971104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2937971104
Directory /workspace/19.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_dai_lock.1007161173
Short name T821
Test name
Test status
Simulation time 1040074090 ps
CPU time 37.2 seconds
Started Jul 03 07:15:53 PM PDT 24
Finished Jul 03 07:16:36 PM PDT 24
Peak memory 242068 kb
Host smart-e5ba2e10-87db-4ebd-991e-06532a205582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007161173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1007161173
Directory /workspace/19.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/19.otp_ctrl_init_fail.1034487008
Short name T1087
Test name
Test status
Simulation time 2073269660 ps
CPU time 4.24 seconds
Started Jul 03 07:15:45 PM PDT 24
Finished Jul 03 07:15:53 PM PDT 24
Peak memory 242380 kb
Host smart-43379dd2-ab49-4444-baf5-bc29058b2797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034487008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1034487008
Directory /workspace/19.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/19.otp_ctrl_macro_errs.3871257407
Short name T1018
Test name
Test status
Simulation time 261448010 ps
CPU time 4.32 seconds
Started Jul 03 07:15:53 PM PDT 24
Finished Jul 03 07:16:03 PM PDT 24
Peak memory 242248 kb
Host smart-cd0ecd17-394b-418c-9863-0c985c5ecf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871257407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3871257407
Directory /workspace/19.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_key_req.651712177
Short name T171
Test name
Test status
Simulation time 1820999990 ps
CPU time 39.73 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 242148 kb
Host smart-48a93a9f-c077-4f65-85ac-60542341ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651712177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.651712177
Directory /workspace/19.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_esc.3576252505
Short name T263
Test name
Test status
Simulation time 410407171 ps
CPU time 10.03 seconds
Started Jul 03 07:15:54 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 242324 kb
Host smart-28e99cd7-628c-4f60-817e-24d4a88a1809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576252505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3576252505
Directory /workspace/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/19.otp_ctrl_parallel_lc_req.867421939
Short name T447
Test name
Test status
Simulation time 192637826 ps
CPU time 5 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:15:58 PM PDT 24
Peak memory 241996 kb
Host smart-8631c06d-63a9-46ab-96fc-bdfcfa6c2889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=867421939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.867421939
Directory /workspace/19.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/19.otp_ctrl_regwen.3357272794
Short name T630
Test name
Test status
Simulation time 130876528 ps
CPU time 5.17 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:16:01 PM PDT 24
Peak memory 241964 kb
Host smart-2ce21e22-29db-4af9-a568-583c887226b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357272794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3357272794
Directory /workspace/19.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/19.otp_ctrl_smoke.1026852853
Short name T969
Test name
Test status
Simulation time 264038671 ps
CPU time 6.89 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:04 PM PDT 24
Peak memory 242084 kb
Host smart-4c1b9a18-01c6-400f-acaf-08d26ccd1361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026852853 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1026852853
Directory /workspace/19.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/19.otp_ctrl_stress_all.383366423
Short name T1137
Test name
Test status
Simulation time 5280206979 ps
CPU time 65.13 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 246832 kb
Host smart-d750959a-b95b-4ff3-a54a-16579200586e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383366423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.
383366423
Directory /workspace/19.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.otp_ctrl_test_access.2352772423
Short name T244
Test name
Test status
Simulation time 387694265 ps
CPU time 5 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:05 PM PDT 24
Peak memory 241884 kb
Host smart-0d055faa-390f-401e-aa7b-e785b49b0d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352772423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2352772423
Directory /workspace/19.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/190.otp_ctrl_init_fail.1471258144
Short name T119
Test name
Test status
Simulation time 112703290 ps
CPU time 3.93 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 241960 kb
Host smart-cff266c0-d4b8-4740-8162-58fe0b9e0620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471258144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.1471258144
Directory /workspace/190.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/190.otp_ctrl_parallel_lc_esc.3065390857
Short name T265
Test name
Test status
Simulation time 937790308 ps
CPU time 13.75 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 241800 kb
Host smart-e0425ade-7df9-45af-9998-3d8e71d63bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065390857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3065390857
Directory /workspace/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/191.otp_ctrl_parallel_lc_esc.2181385559
Short name T490
Test name
Test status
Simulation time 146086827 ps
CPU time 5.52 seconds
Started Jul 03 07:18:32 PM PDT 24
Finished Jul 03 07:18:42 PM PDT 24
Peak memory 241892 kb
Host smart-37924779-b667-45a6-b947-6647825f3c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181385559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2181385559
Directory /workspace/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/192.otp_ctrl_init_fail.3346140048
Short name T55
Test name
Test status
Simulation time 155655942 ps
CPU time 3.96 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:42 PM PDT 24
Peak memory 242228 kb
Host smart-8af124b5-f298-49b3-88ed-02e20114fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346140048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.3346140048
Directory /workspace/192.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/192.otp_ctrl_parallel_lc_esc.4209125371
Short name T142
Test name
Test status
Simulation time 127126890 ps
CPU time 6.55 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 241724 kb
Host smart-8018d967-a4bb-4d76-9660-f53798ecf702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209125371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.4209125371
Directory /workspace/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/193.otp_ctrl_init_fail.3409401178
Short name T522
Test name
Test status
Simulation time 117911527 ps
CPU time 5.07 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 241932 kb
Host smart-5211b8cc-0c94-4a65-a93d-4929fb2adba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409401178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3409401178
Directory /workspace/193.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/193.otp_ctrl_parallel_lc_esc.2631111776
Short name T717
Test name
Test status
Simulation time 211875560 ps
CPU time 5.59 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:44 PM PDT 24
Peak memory 241936 kb
Host smart-73531fbd-2bed-401d-8880-1fd310e5f8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631111776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2631111776
Directory /workspace/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/194.otp_ctrl_parallel_lc_esc.2502785410
Short name T767
Test name
Test status
Simulation time 516183644 ps
CPU time 15.21 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 241936 kb
Host smart-56bfbd08-5e4f-4792-998c-41416e9fcca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502785410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2502785410
Directory /workspace/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/195.otp_ctrl_init_fail.653929615
Short name T1005
Test name
Test status
Simulation time 402626023 ps
CPU time 3.89 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:42 PM PDT 24
Peak memory 242384 kb
Host smart-60fdbd05-f33b-4999-988a-50e210f50387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653929615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.653929615
Directory /workspace/195.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/195.otp_ctrl_parallel_lc_esc.4124742690
Short name T144
Test name
Test status
Simulation time 138239651 ps
CPU time 4.39 seconds
Started Jul 03 07:18:32 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 241948 kb
Host smart-9ee72fe2-1958-4218-957f-db431d98809c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124742690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.4124742690
Directory /workspace/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/196.otp_ctrl_init_fail.1636682274
Short name T499
Test name
Test status
Simulation time 1939563654 ps
CPU time 3.79 seconds
Started Jul 03 07:18:32 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 242120 kb
Host smart-0e6a3114-3165-4a65-8e48-f68d20d4f0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636682274 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1636682274
Directory /workspace/196.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/196.otp_ctrl_parallel_lc_esc.2278104639
Short name T585
Test name
Test status
Simulation time 156903602 ps
CPU time 8.66 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:47 PM PDT 24
Peak memory 241892 kb
Host smart-7be00fc5-1d49-4cee-b1fd-881d8b36d182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278104639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.2278104639
Directory /workspace/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/197.otp_ctrl_parallel_lc_esc.3557160138
Short name T791
Test name
Test status
Simulation time 2893791609 ps
CPU time 9.97 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 242012 kb
Host smart-f909f901-0ce8-41f9-a45d-a229723c6e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557160138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3557160138
Directory /workspace/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/198.otp_ctrl_init_fail.670474185
Short name T899
Test name
Test status
Simulation time 204095716 ps
CPU time 4 seconds
Started Jul 03 07:18:34 PM PDT 24
Finished Jul 03 07:18:42 PM PDT 24
Peak memory 241960 kb
Host smart-4abe447e-a002-465b-ac93-cbb6e27559e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670474185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.670474185
Directory /workspace/198.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/198.otp_ctrl_parallel_lc_esc.3970960544
Short name T72
Test name
Test status
Simulation time 121567712 ps
CPU time 4.83 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 241792 kb
Host smart-fbb02f11-a958-4b22-b8a1-de5199c94164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970960544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.3970960544
Directory /workspace/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/199.otp_ctrl_init_fail.6675920
Short name T445
Test name
Test status
Simulation time 112717095 ps
CPU time 4.75 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 241892 kb
Host smart-7da3f0f4-7631-4659-983d-65570b1c402f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6675920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.6675920
Directory /workspace/199.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/199.otp_ctrl_parallel_lc_esc.2032712310
Short name T264
Test name
Test status
Simulation time 243104459 ps
CPU time 6.08 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 242364 kb
Host smart-0651087f-e959-4392-aa09-03e3f6f2d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032712310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.2032712310
Directory /workspace/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_alert_test.1803557935
Short name T682
Test name
Test status
Simulation time 148239944 ps
CPU time 1.61 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:09 PM PDT 24
Peak memory 240464 kb
Host smart-11029d27-6ca7-4a20-90f6-3ff84f6b94d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803557935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1803557935
Directory /workspace/2.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.otp_ctrl_background_chks.325195349
Short name T661
Test name
Test status
Simulation time 1771114875 ps
CPU time 23.28 seconds
Started Jul 03 07:15:03 PM PDT 24
Finished Jul 03 07:15:32 PM PDT 24
Peak memory 248772 kb
Host smart-98ab00ff-5250-46f9-97d0-d59fa7391559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325195349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.325195349
Directory /workspace/2.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/2.otp_ctrl_check_fail.3459110265
Short name T906
Test name
Test status
Simulation time 1576895849 ps
CPU time 9.32 seconds
Started Jul 03 07:15:03 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 248792 kb
Host smart-255ec3d9-ba84-438c-9204-0afbc0416848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459110265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3459110265
Directory /workspace/2.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_errs.1982050590
Short name T943
Test name
Test status
Simulation time 2511267102 ps
CPU time 18.89 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 242584 kb
Host smart-01dc5c4c-e412-4331-98a1-586de2180b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982050590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1982050590
Directory /workspace/2.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_dai_lock.3029421855
Short name T498
Test name
Test status
Simulation time 3647876026 ps
CPU time 33.78 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 242572 kb
Host smart-44c39063-be4c-41dc-a5e1-7db56904f7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029421855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.3029421855
Directory /workspace/2.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/2.otp_ctrl_init_fail.3973181947
Short name T56
Test name
Test status
Simulation time 207945924 ps
CPU time 3.62 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 242036 kb
Host smart-ec163fda-0237-4fb3-94ae-4be6878edc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973181947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.3973181947
Directory /workspace/2.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/2.otp_ctrl_macro_errs.353757417
Short name T999
Test name
Test status
Simulation time 335395184 ps
CPU time 6.63 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 243404 kb
Host smart-414da972-bbbf-4adb-a33a-c63eca5072cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353757417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.353757417
Directory /workspace/2.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_key_req.2011063778
Short name T949
Test name
Test status
Simulation time 4838158586 ps
CPU time 40.44 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 242312 kb
Host smart-a762b4eb-d7df-46a7-82c0-8d7ab03ef92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011063778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2011063778
Directory /workspace/2.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_esc.3385119335
Short name T351
Test name
Test status
Simulation time 790629472 ps
CPU time 11.1 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 241960 kb
Host smart-81b00c88-9bbf-48af-98b2-72c901356e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385119335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3385119335
Directory /workspace/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/2.otp_ctrl_parallel_lc_req.3748075569
Short name T625
Test name
Test status
Simulation time 2366014139 ps
CPU time 5.59 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 248412 kb
Host smart-eb4e501e-bd07-4826-a35a-0ed71a1aa73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748075569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.3748075569
Directory /workspace/2.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/2.otp_ctrl_regwen.1293708940
Short name T963
Test name
Test status
Simulation time 423316730 ps
CPU time 3.1 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:08 PM PDT 24
Peak memory 242140 kb
Host smart-90b664b4-06ec-4b28-b43a-ab0545e8883f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293708940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1293708940
Directory /workspace/2.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/2.otp_ctrl_sec_cm.3919980628
Short name T236
Test name
Test status
Simulation time 13617099618 ps
CPU time 188.7 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:18:22 PM PDT 24
Peak memory 271960 kb
Host smart-33158870-f9f0-4bec-94f1-8d188ead828e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919980628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3919980628
Directory /workspace/2.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.otp_ctrl_smoke.2880384943
Short name T801
Test name
Test status
Simulation time 1022577054 ps
CPU time 11.69 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 242264 kb
Host smart-2c4303de-4367-4623-b053-a0652bdc86ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880384943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2880384943
Directory /workspace/2.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all.2286731115
Short name T253
Test name
Test status
Simulation time 47277921215 ps
CPU time 346.03 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:20:53 PM PDT 24
Peak memory 306016 kb
Host smart-2a3bbda1-bd3c-4bb3-8c7b-a3006c8bcfa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286731115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.
2286731115
Directory /workspace/2.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.3698840906
Short name T1189
Test name
Test status
Simulation time 119476301608 ps
CPU time 1819.64 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:45:27 PM PDT 24
Peak memory 351400 kb
Host smart-43205307-d8fc-40d3-810c-e0919560fc9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698840906 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.3698840906
Directory /workspace/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.otp_ctrl_test_access.4048872736
Short name T950
Test name
Test status
Simulation time 16327338860 ps
CPU time 38.51 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:52 PM PDT 24
Peak memory 248848 kb
Host smart-c4f9e277-c355-4a9e-8f68-b769d009436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048872736 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.4048872736
Directory /workspace/2.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/20.otp_ctrl_alert_test.668368787
Short name T917
Test name
Test status
Simulation time 134713660 ps
CPU time 2.21 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 240068 kb
Host smart-0e9164f4-e35c-4ead-aba7-413c4ba13b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668368787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.668368787
Directory /workspace/20.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.otp_ctrl_check_fail.1229670065
Short name T650
Test name
Test status
Simulation time 474069352 ps
CPU time 4.44 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:16:00 PM PDT 24
Peak memory 242420 kb
Host smart-4a7944d6-7cdb-4516-9beb-a766a788ca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229670065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.1229670065
Directory /workspace/20.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_errs.2187689479
Short name T701
Test name
Test status
Simulation time 3241166640 ps
CPU time 28.36 seconds
Started Jul 03 07:15:53 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 242632 kb
Host smart-c5046fe5-dd02-4f24-9575-1bdeca49aeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187689479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2187689479
Directory /workspace/20.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_dai_lock.3352919434
Short name T617
Test name
Test status
Simulation time 1764037417 ps
CPU time 28.41 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 242308 kb
Host smart-7c72b484-802f-4076-a22d-e57d6d0eb429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352919434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3352919434
Directory /workspace/20.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/20.otp_ctrl_init_fail.1169558706
Short name T479
Test name
Test status
Simulation time 308126211 ps
CPU time 4.74 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:03 PM PDT 24
Peak memory 241876 kb
Host smart-48f4e960-1623-4370-9894-3e5e8e9b9d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169558706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1169558706
Directory /workspace/20.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/20.otp_ctrl_macro_errs.2674622082
Short name T210
Test name
Test status
Simulation time 1918889987 ps
CPU time 19.17 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:21 PM PDT 24
Peak memory 244272 kb
Host smart-ba9a7a88-8517-42e4-8ee2-510d8a3482db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674622082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.2674622082
Directory /workspace/20.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_key_req.910877418
Short name T233
Test name
Test status
Simulation time 1826811258 ps
CPU time 27.95 seconds
Started Jul 03 07:15:54 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 248760 kb
Host smart-b567d2c6-3941-4c95-a06a-8af7506beaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910877418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.910877418
Directory /workspace/20.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_esc.547540946
Short name T464
Test name
Test status
Simulation time 868366352 ps
CPU time 11.57 seconds
Started Jul 03 07:15:54 PM PDT 24
Finished Jul 03 07:16:11 PM PDT 24
Peak memory 241884 kb
Host smart-dcc9d923-5fba-4d1a-87cc-d3a20d12439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547540946 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.547540946
Directory /workspace/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/20.otp_ctrl_parallel_lc_req.792494430
Short name T622
Test name
Test status
Simulation time 473297346 ps
CPU time 13.48 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 241936 kb
Host smart-6101a4c2-24d1-446f-9167-9ba018869791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792494430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.792494430
Directory /workspace/20.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/20.otp_ctrl_regwen.2004354158
Short name T755
Test name
Test status
Simulation time 333166820 ps
CPU time 9.76 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:07 PM PDT 24
Peak memory 242108 kb
Host smart-9f62d4ef-7f3a-4548-b981-966ea2ab619c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004354158 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.2004354158
Directory /workspace/20.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/20.otp_ctrl_smoke.3374010436
Short name T1035
Test name
Test status
Simulation time 675292152 ps
CPU time 11.79 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:12 PM PDT 24
Peak memory 242096 kb
Host smart-ac5f3e05-ce9c-40b2-8c04-480345e30c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374010436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.3374010436
Directory /workspace/20.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/20.otp_ctrl_stress_all.3932123415
Short name T985
Test name
Test status
Simulation time 1573612137 ps
CPU time 66.04 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 250136 kb
Host smart-873fba46-49c6-4fc0-98c3-aa0a91e6843a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932123415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all
.3932123415
Directory /workspace/20.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.otp_ctrl_test_access.1138678731
Short name T715
Test name
Test status
Simulation time 5162136911 ps
CPU time 25.07 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:16:21 PM PDT 24
Peak memory 242084 kb
Host smart-cd04445b-f548-46b5-87bc-33c6f1a4a4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138678731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1138678731
Directory /workspace/20.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/201.otp_ctrl_init_fail.3399266376
Short name T477
Test name
Test status
Simulation time 191075844 ps
CPU time 3.52 seconds
Started Jul 03 07:18:33 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 242116 kb
Host smart-b6f63d4b-d1a8-4ba1-b536-0aa7049f2caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399266376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3399266376
Directory /workspace/201.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/203.otp_ctrl_init_fail.3143593869
Short name T952
Test name
Test status
Simulation time 106514996 ps
CPU time 4.41 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242052 kb
Host smart-66e1f663-f97b-4c66-8a90-117dde3f60bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143593869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.3143593869
Directory /workspace/203.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/204.otp_ctrl_init_fail.2831973002
Short name T25
Test name
Test status
Simulation time 287359697 ps
CPU time 4 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242044 kb
Host smart-f5090fce-b96f-410f-902c-ae4327898ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831973002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2831973002
Directory /workspace/204.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/205.otp_ctrl_init_fail.684909541
Short name T761
Test name
Test status
Simulation time 156339319 ps
CPU time 4.66 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 241884 kb
Host smart-ce56dc5a-a32d-4c1f-bc12-d11bb2eb5473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684909541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.684909541
Directory /workspace/205.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/206.otp_ctrl_init_fail.459965248
Short name T24
Test name
Test status
Simulation time 152337782 ps
CPU time 3.76 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 242076 kb
Host smart-21cf2fac-532c-43ff-8898-7c53038531c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459965248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.459965248
Directory /workspace/206.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/207.otp_ctrl_init_fail.2691749025
Short name T1197
Test name
Test status
Simulation time 122623657 ps
CPU time 3.16 seconds
Started Jul 03 07:18:36 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 241824 kb
Host smart-7d233288-90a8-4d40-9b15-2ae6300ca052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691749025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2691749025
Directory /workspace/207.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/208.otp_ctrl_init_fail.1323990192
Short name T196
Test name
Test status
Simulation time 239027032 ps
CPU time 3.62 seconds
Started Jul 03 07:18:41 PM PDT 24
Finished Jul 03 07:18:49 PM PDT 24
Peak memory 242580 kb
Host smart-a0d04e14-220e-4103-a1d0-1d4a3bbd03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323990192 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1323990192
Directory /workspace/208.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/209.otp_ctrl_init_fail.3147525080
Short name T778
Test name
Test status
Simulation time 1880506659 ps
CPU time 3.99 seconds
Started Jul 03 07:18:40 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 242132 kb
Host smart-fe85f3b9-daa4-49bb-8f49-6b2cb49100c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147525080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.3147525080
Directory /workspace/209.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_alert_test.2952939872
Short name T1135
Test name
Test status
Simulation time 529639017 ps
CPU time 5 seconds
Started Jul 03 07:15:58 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 240560 kb
Host smart-34216521-cba0-4c17-9c11-f765c4a1656d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952939872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2952939872
Directory /workspace/21.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.otp_ctrl_check_fail.1874331979
Short name T955
Test name
Test status
Simulation time 863509734 ps
CPU time 24.32 seconds
Started Jul 03 07:15:56 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 242236 kb
Host smart-37fb156e-f1e7-4673-b663-2e5c909c5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874331979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.1874331979
Directory /workspace/21.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_errs.2635466536
Short name T628
Test name
Test status
Simulation time 6026050486 ps
CPU time 29.54 seconds
Started Jul 03 07:15:54 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 241964 kb
Host smart-613774ee-2bfc-4c50-a16f-a54d4195d39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635466536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2635466536
Directory /workspace/21.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_dai_lock.1145284371
Short name T321
Test name
Test status
Simulation time 9622356212 ps
CPU time 23.47 seconds
Started Jul 03 07:16:00 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 243408 kb
Host smart-becf0796-124e-4f2c-acd0-41444c37a4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145284371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1145284371
Directory /workspace/21.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/21.otp_ctrl_init_fail.1755976598
Short name T1115
Test name
Test status
Simulation time 148806252 ps
CPU time 3.47 seconds
Started Jul 03 07:15:51 PM PDT 24
Finished Jul 03 07:15:59 PM PDT 24
Peak memory 242032 kb
Host smart-c89e8bce-f58e-478a-b580-9f4ed78b90d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755976598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1755976598
Directory /workspace/21.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/21.otp_ctrl_macro_errs.2590926955
Short name T696
Test name
Test status
Simulation time 828094057 ps
CPU time 18.75 seconds
Started Jul 03 07:15:56 PM PDT 24
Finished Jul 03 07:16:20 PM PDT 24
Peak memory 243276 kb
Host smart-58b5d66c-8758-4172-8d2b-cad26611594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590926955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.2590926955
Directory /workspace/21.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_key_req.841881171
Short name T1100
Test name
Test status
Simulation time 481036322 ps
CPU time 17.82 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:12 PM PDT 24
Peak memory 242176 kb
Host smart-0cb164e8-614f-4370-908c-f60c48b900f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841881171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.841881171
Directory /workspace/21.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_esc.227722807
Short name T206
Test name
Test status
Simulation time 276392344 ps
CPU time 14.29 seconds
Started Jul 03 07:15:50 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 242008 kb
Host smart-9a9f483e-f766-4a18-92c3-5cb09c0811c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227722807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.227722807
Directory /workspace/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/21.otp_ctrl_parallel_lc_req.357860453
Short name T880
Test name
Test status
Simulation time 1536403961 ps
CPU time 11.07 seconds
Started Jul 03 07:15:52 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 248736 kb
Host smart-e5d1becf-00b2-40e7-927c-fdc064cb71dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357860453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.357860453
Directory /workspace/21.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/21.otp_ctrl_regwen.841422334
Short name T632
Test name
Test status
Simulation time 654812726 ps
CPU time 10.94 seconds
Started Jul 03 07:15:56 PM PDT 24
Finished Jul 03 07:16:12 PM PDT 24
Peak memory 242484 kb
Host smart-e4cff4ce-f278-4c08-be3e-225eedfb6e89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841422334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.841422334
Directory /workspace/21.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/21.otp_ctrl_smoke.264871293
Short name T588
Test name
Test status
Simulation time 518256982 ps
CPU time 10.03 seconds
Started Jul 03 07:15:53 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 242116 kb
Host smart-6cdd8225-f573-45c0-8153-cc8e7be2243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264871293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.264871293
Directory /workspace/21.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/21.otp_ctrl_stress_all.4157330780
Short name T394
Test name
Test status
Simulation time 4313127419 ps
CPU time 64.41 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:17:12 PM PDT 24
Peak memory 243864 kb
Host smart-3a59e72a-a30f-4bcf-8167-d5f27a9af3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157330780 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all
.4157330780
Directory /workspace/21.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.otp_ctrl_test_access.2962386141
Short name T337
Test name
Test status
Simulation time 650315938 ps
CPU time 3.74 seconds
Started Jul 03 07:15:53 PM PDT 24
Finished Jul 03 07:16:02 PM PDT 24
Peak memory 242024 kb
Host smart-02e33858-ed94-40ab-a9ed-92250ca18bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962386141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2962386141
Directory /workspace/21.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/210.otp_ctrl_init_fail.1084806829
Short name T973
Test name
Test status
Simulation time 1988187243 ps
CPU time 5.13 seconds
Started Jul 03 07:18:39 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 241924 kb
Host smart-17aec1a3-bcd4-48c7-92cf-353380488dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084806829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1084806829
Directory /workspace/210.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/211.otp_ctrl_init_fail.3208956755
Short name T77
Test name
Test status
Simulation time 1900321208 ps
CPU time 5.93 seconds
Started Jul 03 07:18:40 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 242092 kb
Host smart-43d04d07-baa8-459f-b5ce-f766c012078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208956755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.3208956755
Directory /workspace/211.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/212.otp_ctrl_init_fail.103453551
Short name T881
Test name
Test status
Simulation time 174780086 ps
CPU time 4.5 seconds
Started Jul 03 07:18:38 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 242052 kb
Host smart-259a3ae8-61e1-4eba-b45c-1463e723a190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103453551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.103453551
Directory /workspace/212.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/213.otp_ctrl_init_fail.2102912102
Short name T287
Test name
Test status
Simulation time 94519348 ps
CPU time 3.73 seconds
Started Jul 03 07:18:39 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 241888 kb
Host smart-1b0763fc-f063-4558-9f9d-d62a105d9d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102912102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2102912102
Directory /workspace/213.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/214.otp_ctrl_init_fail.3900411371
Short name T82
Test name
Test status
Simulation time 2085270153 ps
CPU time 5.71 seconds
Started Jul 03 07:18:38 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 242004 kb
Host smart-d44509ab-6eda-4f19-9421-628f7b99fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900411371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.3900411371
Directory /workspace/214.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/215.otp_ctrl_init_fail.584840290
Short name T496
Test name
Test status
Simulation time 193571654 ps
CPU time 4.25 seconds
Started Jul 03 07:18:37 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 242160 kb
Host smart-296f12bb-f1a2-4e5b-b0b1-2f8ce2299cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584840290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.584840290
Directory /workspace/215.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/216.otp_ctrl_init_fail.3612620531
Short name T324
Test name
Test status
Simulation time 413275703 ps
CPU time 3.93 seconds
Started Jul 03 07:18:38 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 242396 kb
Host smart-e842eb5f-4de3-4ca9-9f1e-1dc166e8637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612620531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3612620531
Directory /workspace/216.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/217.otp_ctrl_init_fail.2196349644
Short name T1086
Test name
Test status
Simulation time 346063073 ps
CPU time 3.97 seconds
Started Jul 03 07:18:38 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 242068 kb
Host smart-5095b2dd-5889-4b63-9a8e-4d1128bed13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196349644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2196349644
Directory /workspace/217.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/218.otp_ctrl_init_fail.4179599337
Short name T35
Test name
Test status
Simulation time 116423721 ps
CPU time 3.95 seconds
Started Jul 03 07:18:38 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 242044 kb
Host smart-c09cd835-36e8-4000-a7ae-73906f2935d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179599337 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.4179599337
Directory /workspace/218.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/219.otp_ctrl_init_fail.2628227521
Short name T862
Test name
Test status
Simulation time 114925072 ps
CPU time 3.43 seconds
Started Jul 03 07:18:37 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 241876 kb
Host smart-fa000e32-7260-4c54-84a5-20e5f420b9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628227521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2628227521
Directory /workspace/219.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_check_fail.744614071
Short name T111
Test name
Test status
Simulation time 1033231852 ps
CPU time 22.06 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 248680 kb
Host smart-50563fa9-acf9-4dd9-aa43-5e7abd0c4df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744614071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.744614071
Directory /workspace/22.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_errs.3991838838
Short name T713
Test name
Test status
Simulation time 767864887 ps
CPU time 21.88 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 242040 kb
Host smart-5640ff7a-b8a2-499f-8e9e-66ff1b20fa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991838838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.3991838838
Directory /workspace/22.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_dai_lock.1684206351
Short name T687
Test name
Test status
Simulation time 616774155 ps
CPU time 10.32 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:12 PM PDT 24
Peak memory 242364 kb
Host smart-596e4e68-41e0-4cac-bd46-e9342d577e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684206351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1684206351
Directory /workspace/22.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/22.otp_ctrl_init_fail.2098101043
Short name T905
Test name
Test status
Simulation time 1590194708 ps
CPU time 5.18 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:05 PM PDT 24
Peak memory 242192 kb
Host smart-99a5c2c9-63d6-45e9-809a-935c35e099b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098101043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.2098101043
Directory /workspace/22.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/22.otp_ctrl_macro_errs.3432107773
Short name T157
Test name
Test status
Simulation time 1897935283 ps
CPU time 5.87 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 247808 kb
Host smart-ef77973a-d38b-419d-8f86-48ff9fb095d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432107773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.3432107773
Directory /workspace/22.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_key_req.2212316772
Short name T925
Test name
Test status
Simulation time 260536912 ps
CPU time 4.88 seconds
Started Jul 03 07:15:59 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 242328 kb
Host smart-dc9fa69b-f8c4-4e27-8fe3-7ee73a1f6ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212316772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.2212316772
Directory /workspace/22.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_esc.2860335035
Short name T412
Test name
Test status
Simulation time 1679074800 ps
CPU time 6.51 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 242188 kb
Host smart-dac333a3-40ae-4e02-b671-6ec809f0d5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860335035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.2860335035
Directory /workspace/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/22.otp_ctrl_parallel_lc_req.2963695229
Short name T747
Test name
Test status
Simulation time 1165811019 ps
CPU time 19.25 seconds
Started Jul 03 07:15:59 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242208 kb
Host smart-748aa6f6-178e-4873-984a-f8ea0a7c445b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2963695229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.2963695229
Directory /workspace/22.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/22.otp_ctrl_regwen.4074463993
Short name T688
Test name
Test status
Simulation time 88094222 ps
CPU time 3.28 seconds
Started Jul 03 07:15:58 PM PDT 24
Finished Jul 03 07:16:06 PM PDT 24
Peak memory 242160 kb
Host smart-6901bb08-016b-4ff7-a72d-aefc0f70e2a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4074463993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.4074463993
Directory /workspace/22.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/22.otp_ctrl_smoke.3450658585
Short name T212
Test name
Test status
Simulation time 2943669219 ps
CPU time 5.35 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:07 PM PDT 24
Peak memory 242116 kb
Host smart-d1cf67e5-6c89-4b7e-bba7-ea6a446f3046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450658585 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.3450658585
Directory /workspace/22.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/22.otp_ctrl_stress_all.1817059649
Short name T1199
Test name
Test status
Simulation time 812518188 ps
CPU time 17.04 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 241864 kb
Host smart-3a9c55d8-518a-4ef5-9523-98a398e3baf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817059649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all
.1817059649
Directory /workspace/22.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.otp_ctrl_test_access.2910364320
Short name T238
Test name
Test status
Simulation time 632574947 ps
CPU time 18.26 seconds
Started Jul 03 07:15:58 PM PDT 24
Finished Jul 03 07:16:21 PM PDT 24
Peak memory 242552 kb
Host smart-025c1ec5-2af2-46ff-8585-54497b65c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910364320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.2910364320
Directory /workspace/22.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/221.otp_ctrl_init_fail.840016131
Short name T894
Test name
Test status
Simulation time 213551782 ps
CPU time 5.04 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 241912 kb
Host smart-018da051-5eb3-46a6-8c6c-d29a0a6a13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840016131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.840016131
Directory /workspace/221.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/222.otp_ctrl_init_fail.4109344712
Short name T180
Test name
Test status
Simulation time 534984638 ps
CPU time 4.63 seconds
Started Jul 03 07:18:36 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 242052 kb
Host smart-c1f67423-ff2e-422f-a3ec-d4dbdabf406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109344712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.4109344712
Directory /workspace/222.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/223.otp_ctrl_init_fail.1463138372
Short name T891
Test name
Test status
Simulation time 389749043 ps
CPU time 3.49 seconds
Started Jul 03 07:18:40 PM PDT 24
Finished Jul 03 07:18:47 PM PDT 24
Peak memory 241900 kb
Host smart-bf701bbd-b554-4541-8e7d-dc4140408370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463138372 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.1463138372
Directory /workspace/223.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/224.otp_ctrl_init_fail.3185443086
Short name T854
Test name
Test status
Simulation time 1467617312 ps
CPU time 4.14 seconds
Started Jul 03 07:18:36 PM PDT 24
Finished Jul 03 07:18:45 PM PDT 24
Peak memory 242332 kb
Host smart-0e026b98-8bd4-47ab-9f08-e855173a049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185443086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.3185443086
Directory /workspace/224.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/225.otp_ctrl_init_fail.2128701887
Short name T1015
Test name
Test status
Simulation time 93666837 ps
CPU time 3.47 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 242176 kb
Host smart-9cf6913b-2a3f-45a7-bb2f-12d31ed4d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128701887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2128701887
Directory /workspace/225.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/226.otp_ctrl_init_fail.2768234695
Short name T857
Test name
Test status
Simulation time 1592621827 ps
CPU time 4.32 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242072 kb
Host smart-e69e20b1-9e2a-4794-99e1-c87e1674464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768234695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2768234695
Directory /workspace/226.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/227.otp_ctrl_init_fail.4047659163
Short name T554
Test name
Test status
Simulation time 208125328 ps
CPU time 3.6 seconds
Started Jul 03 07:18:35 PM PDT 24
Finished Jul 03 07:18:43 PM PDT 24
Peak memory 242172 kb
Host smart-e59bef0f-0653-4f42-90e1-a967f8fde458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047659163 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.4047659163
Directory /workspace/227.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/228.otp_ctrl_init_fail.1860337574
Short name T338
Test name
Test status
Simulation time 2374139351 ps
CPU time 6.42 seconds
Started Jul 03 07:18:40 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242076 kb
Host smart-a68c4cd6-25e7-44e8-8f0f-df76c78c023b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860337574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.1860337574
Directory /workspace/228.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/229.otp_ctrl_init_fail.3402241466
Short name T615
Test name
Test status
Simulation time 112336125 ps
CPU time 3.62 seconds
Started Jul 03 07:18:39 PM PDT 24
Finished Jul 03 07:18:47 PM PDT 24
Peak memory 242096 kb
Host smart-a2b67721-5c71-417d-b408-a52badcf7a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402241466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3402241466
Directory /workspace/229.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_alert_test.1438640193
Short name T1025
Test name
Test status
Simulation time 230207353 ps
CPU time 1.73 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:09 PM PDT 24
Peak memory 240136 kb
Host smart-36b9dc29-81b1-4cca-9857-650ecab83cde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438640193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1438640193
Directory /workspace/23.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.otp_ctrl_check_fail.969215742
Short name T424
Test name
Test status
Simulation time 1685200679 ps
CPU time 20.36 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:31 PM PDT 24
Peak memory 242096 kb
Host smart-6a188361-ba81-4a64-98c0-aaa9a9a466d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969215742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.969215742
Directory /workspace/23.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_errs.3897913405
Short name T160
Test name
Test status
Simulation time 353573173 ps
CPU time 8.14 seconds
Started Jul 03 07:15:54 PM PDT 24
Finished Jul 03 07:16:08 PM PDT 24
Peak memory 241964 kb
Host smart-ca63c478-eed5-4e6e-9647-f8079d40e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897913405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3897913405
Directory /workspace/23.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/23.otp_ctrl_dai_lock.1829617894
Short name T103
Test name
Test status
Simulation time 2829339631 ps
CPU time 18.48 seconds
Started Jul 03 07:16:01 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242384 kb
Host smart-be6e6eb3-65d8-41b3-9bdc-115ef2494915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829617894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.1829617894
Directory /workspace/23.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/23.otp_ctrl_init_fail.3528321712
Short name T506
Test name
Test status
Simulation time 111416507 ps
CPU time 3.63 seconds
Started Jul 03 07:15:57 PM PDT 24
Finished Jul 03 07:16:06 PM PDT 24
Peak memory 242056 kb
Host smart-ca5ca7f9-2218-47bd-bcd7-129d2ad86cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528321712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.3528321712
Directory /workspace/23.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_key_req.1878293342
Short name T200
Test name
Test status
Simulation time 4240655963 ps
CPU time 77.65 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 243272 kb
Host smart-42e8688f-2c43-4e7e-b734-92de9a31606b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878293342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.1878293342
Directory /workspace/23.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_esc.232840063
Short name T677
Test name
Test status
Simulation time 399011092 ps
CPU time 5.18 seconds
Started Jul 03 07:15:59 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 241836 kb
Host smart-d2569127-13eb-414b-a243-4e6e4c4438d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232840063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.232840063
Directory /workspace/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/23.otp_ctrl_parallel_lc_req.2192938134
Short name T1036
Test name
Test status
Simulation time 2117182837 ps
CPU time 16.56 seconds
Started Jul 03 07:15:56 PM PDT 24
Finished Jul 03 07:16:18 PM PDT 24
Peak memory 241756 kb
Host smart-8630e052-402c-47af-a20d-581b7d20f543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192938134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.2192938134
Directory /workspace/23.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/23.otp_ctrl_regwen.3159433204
Short name T386
Test name
Test status
Simulation time 493788078 ps
CPU time 4.56 seconds
Started Jul 03 07:16:01 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 241924 kb
Host smart-b8586590-953b-4f9f-9ede-dc55fb0b8795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159433204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.3159433204
Directory /workspace/23.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/23.otp_ctrl_smoke.816591313
Short name T1021
Test name
Test status
Simulation time 1460885811 ps
CPU time 5.22 seconds
Started Jul 03 07:15:55 PM PDT 24
Finished Jul 03 07:16:06 PM PDT 24
Peak memory 242192 kb
Host smart-a3ae071a-1807-4c98-bb73-103fa182de96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816591313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.816591313
Directory /workspace/23.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.444806718
Short name T858
Test name
Test status
Simulation time 76969746340 ps
CPU time 862.43 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:30:33 PM PDT 24
Peak memory 295496 kb
Host smart-124aa1ac-814e-4ff3-b013-61d72e5fa4d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444806718 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.444806718
Directory /workspace/23.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.otp_ctrl_test_access.3191559577
Short name T311
Test name
Test status
Simulation time 5840805370 ps
CPU time 33.36 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:40 PM PDT 24
Peak memory 242340 kb
Host smart-40819292-9ea2-4486-81fc-89b7ea99320d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191559577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3191559577
Directory /workspace/23.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/230.otp_ctrl_init_fail.3780400307
Short name T48
Test name
Test status
Simulation time 470843435 ps
CPU time 5.13 seconds
Started Jul 03 07:18:39 PM PDT 24
Finished Jul 03 07:18:48 PM PDT 24
Peak memory 242356 kb
Host smart-955f5b62-430c-49aa-9dfa-371409f154c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780400307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.3780400307
Directory /workspace/230.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/231.otp_ctrl_init_fail.3118920741
Short name T792
Test name
Test status
Simulation time 104984634 ps
CPU time 4.07 seconds
Started Jul 03 07:18:37 PM PDT 24
Finished Jul 03 07:18:46 PM PDT 24
Peak memory 241908 kb
Host smart-fc6c31bf-dcda-4e8c-a3cb-b255011065c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118920741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3118920741
Directory /workspace/231.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/232.otp_ctrl_init_fail.893781019
Short name T958
Test name
Test status
Simulation time 439518476 ps
CPU time 4.3 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242428 kb
Host smart-dd75bbb1-9d66-4a12-bd14-7af65fc3fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893781019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.893781019
Directory /workspace/232.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/233.otp_ctrl_init_fail.1841653581
Short name T43
Test name
Test status
Simulation time 214957804 ps
CPU time 3.18 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242464 kb
Host smart-1aa5cb94-b777-4f63-b5b2-e9d7852cba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841653581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1841653581
Directory /workspace/233.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/234.otp_ctrl_init_fail.1501983715
Short name T228
Test name
Test status
Simulation time 266369261 ps
CPU time 4.21 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 242352 kb
Host smart-307eb6d2-711b-46de-9f87-94c8cbbc93f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501983715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1501983715
Directory /workspace/234.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/235.otp_ctrl_init_fail.4179248814
Short name T70
Test name
Test status
Simulation time 200255803 ps
CPU time 4.18 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242392 kb
Host smart-2774d03d-19e7-431f-a503-338823119d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179248814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.4179248814
Directory /workspace/235.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/236.otp_ctrl_init_fail.2833651592
Short name T1181
Test name
Test status
Simulation time 134205717 ps
CPU time 4.13 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 242256 kb
Host smart-9a5384e0-1617-493c-8f29-f478957fbad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833651592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2833651592
Directory /workspace/236.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/237.otp_ctrl_init_fail.4021722254
Short name T130
Test name
Test status
Simulation time 183801032 ps
CPU time 5.07 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242468 kb
Host smart-019b96cb-ce3b-4af7-8764-aaa5c621b97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021722254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4021722254
Directory /workspace/237.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/238.otp_ctrl_init_fail.3723331043
Short name T653
Test name
Test status
Simulation time 291114560 ps
CPU time 4.1 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 242176 kb
Host smart-e919696c-bbec-4bf2-b7fd-f03618e2d5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723331043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3723331043
Directory /workspace/238.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/239.otp_ctrl_init_fail.2395320380
Short name T786
Test name
Test status
Simulation time 556879809 ps
CPU time 4.01 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 242096 kb
Host smart-2b1a9d7f-108b-4b42-9848-b9bbc0552c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395320380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.2395320380
Directory /workspace/239.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_alert_test.280420365
Short name T481
Test name
Test status
Simulation time 82488538 ps
CPU time 2 seconds
Started Jul 03 07:16:00 PM PDT 24
Finished Jul 03 07:16:07 PM PDT 24
Peak memory 240492 kb
Host smart-5fb89451-0165-4ac2-a290-98c75899f73b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280420365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.280420365
Directory /workspace/24.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.otp_ctrl_check_fail.2485721291
Short name T1019
Test name
Test status
Simulation time 1551959216 ps
CPU time 5.24 seconds
Started Jul 03 07:16:04 PM PDT 24
Finished Jul 03 07:16:15 PM PDT 24
Peak memory 248636 kb
Host smart-10d190c5-45e4-447b-9e19-cedd3deb60bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485721291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.2485721291
Directory /workspace/24.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_errs.1031406346
Short name T131
Test name
Test status
Simulation time 2009192522 ps
CPU time 21.58 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:32 PM PDT 24
Peak memory 242248 kb
Host smart-8ef5aac4-f774-4f3d-a25e-493ba874f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031406346 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.1031406346
Directory /workspace/24.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_dai_lock.2206418911
Short name T1016
Test name
Test status
Simulation time 25973825498 ps
CPU time 51.41 seconds
Started Jul 03 07:16:03 PM PDT 24
Finished Jul 03 07:17:00 PM PDT 24
Peak memory 242696 kb
Host smart-4a303816-46e3-4db9-a5dc-4b2088bf073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206418911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2206418911
Directory /workspace/24.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/24.otp_ctrl_init_fail.980417391
Short name T1145
Test name
Test status
Simulation time 277909920 ps
CPU time 3.25 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 242040 kb
Host smart-f3c34f74-13dd-409e-93ff-c92c6a49208f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980417391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.980417391
Directory /workspace/24.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/24.otp_ctrl_macro_errs.359183300
Short name T226
Test name
Test status
Simulation time 3552008143 ps
CPU time 20.12 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 244112 kb
Host smart-a8133729-6122-4128-a70c-3cd01cf86548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359183300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.359183300
Directory /workspace/24.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_key_req.2963109205
Short name T1169
Test name
Test status
Simulation time 744735902 ps
CPU time 20.14 seconds
Started Jul 03 07:16:08 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 242836 kb
Host smart-090cdd3e-4dbb-4b24-9c7c-fac1bb164a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963109205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2963109205
Directory /workspace/24.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/24.otp_ctrl_parallel_lc_esc.754678187
Short name T939
Test name
Test status
Simulation time 331265115 ps
CPU time 3.84 seconds
Started Jul 03 07:16:01 PM PDT 24
Finished Jul 03 07:16:10 PM PDT 24
Peak memory 241884 kb
Host smart-0892daf0-a451-4a2d-8922-b87a1818be2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754678187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.754678187
Directory /workspace/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/24.otp_ctrl_regwen.2582543101
Short name T390
Test name
Test status
Simulation time 191487560 ps
CPU time 4.37 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:17 PM PDT 24
Peak memory 241984 kb
Host smart-e87d96fb-3b53-41c6-9e05-5267db29d237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582543101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.2582543101
Directory /workspace/24.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/24.otp_ctrl_smoke.233174262
Short name T759
Test name
Test status
Simulation time 2109324625 ps
CPU time 6.63 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:20 PM PDT 24
Peak memory 241816 kb
Host smart-1f5b6467-cdf5-4c43-8266-708215b1c531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233174262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.233174262
Directory /workspace/24.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all.1301929618
Short name T1185
Test name
Test status
Simulation time 3626671950 ps
CPU time 20.31 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 241536 kb
Host smart-1bf57ae3-6d32-4481-8f3a-02575703efe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301929618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all
.1301929618
Directory /workspace/24.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.4161205886
Short name T342
Test name
Test status
Simulation time 128815061561 ps
CPU time 1499.92 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:41:07 PM PDT 24
Peak memory 285920 kb
Host smart-3154771e-0330-4a66-a3dc-7bf13aeab11d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161205886 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.4161205886
Directory /workspace/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.otp_ctrl_test_access.1962922930
Short name T846
Test name
Test status
Simulation time 8477581082 ps
CPU time 20 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 243372 kb
Host smart-c8643c0b-8260-40de-a029-ffcb878f27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962922930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.1962922930
Directory /workspace/24.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/240.otp_ctrl_init_fail.3218930819
Short name T726
Test name
Test status
Simulation time 141549793 ps
CPU time 3.96 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:54 PM PDT 24
Peak memory 242016 kb
Host smart-49b6572f-1e53-4e3c-b8b9-42c4afe1dcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218930819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3218930819
Directory /workspace/240.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/241.otp_ctrl_init_fail.3617645512
Short name T198
Test name
Test status
Simulation time 501012682 ps
CPU time 4.35 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 241876 kb
Host smart-2f68f559-ef8f-4a3d-9fb9-39b31a9fae45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617645512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3617645512
Directory /workspace/241.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/242.otp_ctrl_init_fail.3380649290
Short name T531
Test name
Test status
Simulation time 611515913 ps
CPU time 4.4 seconds
Started Jul 03 07:18:41 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 242144 kb
Host smart-48902f53-92ff-480a-a8bf-5b0f1ae8a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380649290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.3380649290
Directory /workspace/242.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/243.otp_ctrl_init_fail.1123327558
Short name T41
Test name
Test status
Simulation time 2438268429 ps
CPU time 7.04 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 241884 kb
Host smart-529f5d78-3f24-4210-98bd-793eb4f2eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123327558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1123327558
Directory /workspace/243.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/244.otp_ctrl_init_fail.3944035760
Short name T231
Test name
Test status
Simulation time 103839651 ps
CPU time 3.93 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242324 kb
Host smart-63fd7606-6fc8-47a1-bcf9-ed8ec91a5100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944035760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.3944035760
Directory /workspace/244.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/245.otp_ctrl_init_fail.1662971167
Short name T110
Test name
Test status
Simulation time 410884092 ps
CPU time 4.01 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 242380 kb
Host smart-e8a03e79-8c93-46ae-ae42-3289b2d3916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662971167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1662971167
Directory /workspace/245.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/246.otp_ctrl_init_fail.2469235448
Short name T507
Test name
Test status
Simulation time 283877692 ps
CPU time 3.87 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 241928 kb
Host smart-c276bc47-e3ff-4b28-8325-4c3db70f2358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469235448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.2469235448
Directory /workspace/246.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/247.otp_ctrl_init_fail.3017602535
Short name T903
Test name
Test status
Simulation time 263920840 ps
CPU time 4.31 seconds
Started Jul 03 07:18:45 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 242480 kb
Host smart-4fdaeb40-c635-4cee-a5d5-b101c9432a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017602535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3017602535
Directory /workspace/247.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/248.otp_ctrl_init_fail.2608086889
Short name T1098
Test name
Test status
Simulation time 528652807 ps
CPU time 4.43 seconds
Started Jul 03 07:18:42 PM PDT 24
Finished Jul 03 07:18:51 PM PDT 24
Peak memory 242144 kb
Host smart-f9f74d2e-b70d-4685-a21d-434fe97133c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608086889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2608086889
Directory /workspace/248.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/249.otp_ctrl_init_fail.1366542432
Short name T480
Test name
Test status
Simulation time 173941182 ps
CPU time 3.52 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242024 kb
Host smart-197eee43-bb35-42af-b143-b10ed2430f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366542432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1366542432
Directory /workspace/249.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_alert_test.1638038955
Short name T2
Test name
Test status
Simulation time 57008524 ps
CPU time 1.85 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:15 PM PDT 24
Peak memory 240552 kb
Host smart-96d34dfd-95bd-4198-a335-f00de6d5707f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638038955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1638038955
Directory /workspace/25.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_errs.3690898045
Short name T911
Test name
Test status
Simulation time 13558250014 ps
CPU time 34.56 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:48 PM PDT 24
Peak memory 244516 kb
Host smart-00cea2c9-95f3-4908-8a03-7d6faa4c0e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690898045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3690898045
Directory /workspace/25.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_dai_lock.3811475612
Short name T569
Test name
Test status
Simulation time 10227322119 ps
CPU time 20.06 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 242688 kb
Host smart-a9ebe404-2191-4348-9559-a9be7669de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811475612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3811475612
Directory /workspace/25.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/25.otp_ctrl_init_fail.2161889868
Short name T1106
Test name
Test status
Simulation time 391756471 ps
CPU time 4.04 seconds
Started Jul 03 07:16:04 PM PDT 24
Finished Jul 03 07:16:14 PM PDT 24
Peak memory 242324 kb
Host smart-6d3cf1d4-a9cb-4242-9450-412e78bae18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161889868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.2161889868
Directory /workspace/25.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/25.otp_ctrl_macro_errs.3094021618
Short name T841
Test name
Test status
Simulation time 21516163410 ps
CPU time 52.68 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:17:07 PM PDT 24
Peak memory 250432 kb
Host smart-46f41a0b-abb2-4566-b43e-56766ccd09b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094021618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3094021618
Directory /workspace/25.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_esc.2064903099
Short name T993
Test name
Test status
Simulation time 651477110 ps
CPU time 11.04 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 241900 kb
Host smart-7bf2ccad-7245-4fb8-8130-1dfa0a8d644f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064903099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.2064903099
Directory /workspace/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/25.otp_ctrl_parallel_lc_req.1729578567
Short name T788
Test name
Test status
Simulation time 1013434582 ps
CPU time 8.6 seconds
Started Jul 03 07:16:02 PM PDT 24
Finished Jul 03 07:16:16 PM PDT 24
Peak memory 241964 kb
Host smart-038fc922-7e65-4024-82ce-482e78a4c262
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729578567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.1729578567
Directory /workspace/25.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/25.otp_ctrl_regwen.1603553758
Short name T533
Test name
Test status
Simulation time 557094151 ps
CPU time 7.62 seconds
Started Jul 03 07:16:08 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 242032 kb
Host smart-4c83068c-4596-456c-baa8-48f76542eaaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603553758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.1603553758
Directory /workspace/25.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/25.otp_ctrl_smoke.3027787734
Short name T928
Test name
Test status
Simulation time 465024104 ps
CPU time 4.19 seconds
Started Jul 03 07:16:03 PM PDT 24
Finished Jul 03 07:16:13 PM PDT 24
Peak memory 242384 kb
Host smart-709e23d4-e19b-483d-83d6-219dde47d896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027787734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.3027787734
Directory /workspace/25.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all.3294239551
Short name T1059
Test name
Test status
Simulation time 13549353879 ps
CPU time 62.02 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 262832 kb
Host smart-fb407adb-f56e-42fc-a84e-6c367dcc3398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294239551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all
.3294239551
Directory /workspace/25.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1437942499
Short name T837
Test name
Test status
Simulation time 187987271227 ps
CPU time 3844.25 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 08:20:18 PM PDT 24
Peak memory 278008 kb
Host smart-ec83335c-4e1d-406a-b1b3-7876abbbf574
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437942499 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1437942499
Directory /workspace/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.otp_ctrl_test_access.623407636
Short name T1171
Test name
Test status
Simulation time 3103509067 ps
CPU time 31.84 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:43 PM PDT 24
Peak memory 242260 kb
Host smart-86fc0d26-eebd-44ac-b57b-c163921ecf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623407636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.623407636
Directory /workspace/25.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/250.otp_ctrl_init_fail.220645094
Short name T1076
Test name
Test status
Simulation time 2053352241 ps
CPU time 5.73 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242060 kb
Host smart-79434adc-9b55-4f7d-8b6e-132d3c751022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220645094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.220645094
Directory /workspace/250.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/251.otp_ctrl_init_fail.1121596414
Short name T797
Test name
Test status
Simulation time 1698166725 ps
CPU time 5.61 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 241920 kb
Host smart-7212ee24-8884-4404-b67f-87205b966364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121596414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1121596414
Directory /workspace/251.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/252.otp_ctrl_init_fail.3366014849
Short name T46
Test name
Test status
Simulation time 246738895 ps
CPU time 4.54 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 242212 kb
Host smart-f5d8617a-b70c-4c5c-9434-b936e4218a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366014849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.3366014849
Directory /workspace/252.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/253.otp_ctrl_init_fail.2746262558
Short name T218
Test name
Test status
Simulation time 165137007 ps
CPU time 4.13 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 242052 kb
Host smart-dd73ff88-5c76-44df-bf6d-f0bc4889a585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746262558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.2746262558
Directory /workspace/253.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/254.otp_ctrl_init_fail.607293647
Short name T1130
Test name
Test status
Simulation time 307900011 ps
CPU time 3.97 seconds
Started Jul 03 07:18:44 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242156 kb
Host smart-c77e45fd-0a4f-4c53-80c7-660f3a10b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607293647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.607293647
Directory /workspace/254.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/255.otp_ctrl_init_fail.569347092
Short name T505
Test name
Test status
Simulation time 126356705 ps
CPU time 3.51 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241920 kb
Host smart-d8c9d9d7-2408-447f-a4fb-c9cf6abee124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569347092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.569347092
Directory /workspace/255.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/256.otp_ctrl_init_fail.969205261
Short name T1061
Test name
Test status
Simulation time 195298764 ps
CPU time 3.41 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 242388 kb
Host smart-0718b029-61ae-470b-9b86-3461f80f49e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969205261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.969205261
Directory /workspace/256.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/257.otp_ctrl_init_fail.2453957644
Short name T576
Test name
Test status
Simulation time 1577338148 ps
CPU time 4.57 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:53 PM PDT 24
Peak memory 242304 kb
Host smart-3a3caafa-f268-4779-a8fe-be783dd112d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453957644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.2453957644
Directory /workspace/257.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/258.otp_ctrl_init_fail.1622622338
Short name T1124
Test name
Test status
Simulation time 2232876002 ps
CPU time 4.68 seconds
Started Jul 03 07:18:45 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 242060 kb
Host smart-d4204640-5e3a-491f-9f85-69edd57cd5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622622338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1622622338
Directory /workspace/258.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/259.otp_ctrl_init_fail.2645144385
Short name T313
Test name
Test status
Simulation time 571520031 ps
CPU time 4.21 seconds
Started Jul 03 07:18:43 PM PDT 24
Finished Jul 03 07:18:52 PM PDT 24
Peak memory 242140 kb
Host smart-edb35adf-891d-4074-bb22-2d5830746ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645144385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2645144385
Directory /workspace/259.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_alert_test.1821367382
Short name T590
Test name
Test status
Simulation time 175999905 ps
CPU time 1.87 seconds
Started Jul 03 07:16:09 PM PDT 24
Finished Jul 03 07:16:17 PM PDT 24
Peak memory 240112 kb
Host smart-8cf01c08-396f-44aa-903a-afdd6e6d31fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821367382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.1821367382
Directory /workspace/26.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_errs.2252388776
Short name T860
Test name
Test status
Simulation time 2448632893 ps
CPU time 16.25 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 242540 kb
Host smart-2c3324b8-8b16-4bbf-be92-5c5db355e21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252388776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2252388776
Directory /workspace/26.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_dai_lock.4031696663
Short name T766
Test name
Test status
Simulation time 2892551372 ps
CPU time 17 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 248864 kb
Host smart-896c45b0-e58b-420d-ae1c-b0450c6d847a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031696663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.4031696663
Directory /workspace/26.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/26.otp_ctrl_init_fail.2711415540
Short name T219
Test name
Test status
Simulation time 567335803 ps
CPU time 4.53 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 242480 kb
Host smart-26df3cb4-9370-4564-8eca-21561c9b788a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711415540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2711415540
Directory /workspace/26.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/26.otp_ctrl_macro_errs.1369704406
Short name T362
Test name
Test status
Simulation time 1272453903 ps
CPU time 21.25 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 243936 kb
Host smart-08158641-7a20-4b96-a55a-5e7f079d78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369704406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.1369704406
Directory /workspace/26.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_key_req.3562140535
Short name T1127
Test name
Test status
Simulation time 774369428 ps
CPU time 9.39 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 242316 kb
Host smart-1c2545c8-b2fd-4527-ba0d-a6a48ac8bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562140535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3562140535
Directory /workspace/26.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_esc.1638579568
Short name T711
Test name
Test status
Simulation time 666153202 ps
CPU time 18.26 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 241984 kb
Host smart-95c218e7-e836-4ec8-b7f1-0bde9cef367f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638579568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.1638579568
Directory /workspace/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/26.otp_ctrl_parallel_lc_req.2853211591
Short name T494
Test name
Test status
Simulation time 11666942187 ps
CPU time 20.76 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 242080 kb
Host smart-af4cc447-ce0a-47c2-9d2d-795853e950df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2853211591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2853211591
Directory /workspace/26.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/26.otp_ctrl_regwen.1193306327
Short name T385
Test name
Test status
Simulation time 2786451065 ps
CPU time 6.53 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 242432 kb
Host smart-3d24814a-caff-4d53-8472-aba7577ac902
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193306327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.1193306327
Directory /workspace/26.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/26.otp_ctrl_smoke.3861426471
Short name T523
Test name
Test status
Simulation time 4090951718 ps
CPU time 11.72 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242096 kb
Host smart-1bb8f00e-1832-40e0-be9a-fb8d5362d20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861426471 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3861426471
Directory /workspace/26.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all.993208489
Short name T691
Test name
Test status
Simulation time 40714540158 ps
CPU time 292.67 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:21:06 PM PDT 24
Peak memory 273496 kb
Host smart-08e3a420-e762-4253-9223-445c2cf2aa8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993208489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.
993208489
Directory /workspace/26.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.1298348947
Short name T13
Test name
Test status
Simulation time 344672493675 ps
CPU time 2613.37 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:59:46 PM PDT 24
Peak memory 577832 kb
Host smart-ea4fba4e-bf79-4400-9b88-a96b324f52df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298348947 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.1298348947
Directory /workspace/26.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.otp_ctrl_test_access.113711770
Short name T512
Test name
Test status
Simulation time 1198135812 ps
CPU time 12.15 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 242544 kb
Host smart-c2781f83-15c6-4772-87ab-05ef17bdc54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113711770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.113711770
Directory /workspace/26.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/261.otp_ctrl_init_fail.4191433512
Short name T1050
Test name
Test status
Simulation time 106137014 ps
CPU time 3.93 seconds
Started Jul 03 07:18:45 PM PDT 24
Finished Jul 03 07:18:55 PM PDT 24
Peak memory 242044 kb
Host smart-6d469d70-cb5c-4eae-a470-23ca7a3d4ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191433512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.4191433512
Directory /workspace/261.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/262.otp_ctrl_init_fail.1639865638
Short name T1178
Test name
Test status
Simulation time 598094401 ps
CPU time 4.55 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 241996 kb
Host smart-eae2770e-881c-4fda-a40f-9db6edfaeb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639865638 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.1639865638
Directory /workspace/262.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/263.otp_ctrl_init_fail.2950685141
Short name T1151
Test name
Test status
Simulation time 523919661 ps
CPU time 4.43 seconds
Started Jul 03 07:18:45 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 242260 kb
Host smart-ff36f689-4ec6-4a6f-b169-f77732cb9990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950685141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.2950685141
Directory /workspace/263.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/264.otp_ctrl_init_fail.2812810558
Short name T164
Test name
Test status
Simulation time 119290487 ps
CPU time 3.31 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:18:57 PM PDT 24
Peak memory 242408 kb
Host smart-2a32f9ef-289f-4d88-a7bb-e06afb53d525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812810558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.2812810558
Directory /workspace/264.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/265.otp_ctrl_init_fail.328232326
Short name T592
Test name
Test status
Simulation time 203425407 ps
CPU time 4.19 seconds
Started Jul 03 07:18:46 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 241876 kb
Host smart-4fc51179-4016-425f-8612-584a4295cdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328232326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.328232326
Directory /workspace/265.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/266.otp_ctrl_init_fail.3920875102
Short name T743
Test name
Test status
Simulation time 154356251 ps
CPU time 3 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 242204 kb
Host smart-a2d77679-8521-446b-91bf-fa77051cb211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920875102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3920875102
Directory /workspace/266.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/267.otp_ctrl_init_fail.1136380024
Short name T781
Test name
Test status
Simulation time 187462523 ps
CPU time 5.24 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 241912 kb
Host smart-4f845897-57fd-4b91-baab-d9166cea4229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136380024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1136380024
Directory /workspace/267.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/268.otp_ctrl_init_fail.1266496319
Short name T561
Test name
Test status
Simulation time 480812372 ps
CPU time 3.71 seconds
Started Jul 03 07:18:46 PM PDT 24
Finished Jul 03 07:18:56 PM PDT 24
Peak memory 242152 kb
Host smart-6809d88d-db6e-48ba-baf9-e83726015c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266496319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.1266496319
Directory /workspace/268.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/269.otp_ctrl_init_fail.4116015865
Short name T681
Test name
Test status
Simulation time 575171649 ps
CPU time 4.59 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 242144 kb
Host smart-6fedf104-8921-40e7-a7c6-e87548c42ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116015865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.4116015865
Directory /workspace/269.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_alert_test.1445249607
Short name T722
Test name
Test status
Simulation time 97211871 ps
CPU time 1.65 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 240204 kb
Host smart-95d92d64-09be-4940-8206-bb7d9eb7b728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445249607 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1445249607
Directory /workspace/27.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_errs.631962371
Short name T417
Test name
Test status
Simulation time 4859457924 ps
CPU time 21.85 seconds
Started Jul 03 07:16:12 PM PDT 24
Finished Jul 03 07:16:39 PM PDT 24
Peak memory 241868 kb
Host smart-d5a6989f-3f53-459a-bb15-6ca3f7ccf122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631962371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.631962371
Directory /workspace/27.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_dai_lock.1795149238
Short name T426
Test name
Test status
Simulation time 1087959624 ps
CPU time 13.21 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:26 PM PDT 24
Peak memory 242036 kb
Host smart-2a759409-e717-46fc-a9ca-815b9622bd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795149238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1795149238
Directory /workspace/27.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/27.otp_ctrl_init_fail.3394121747
Short name T190
Test name
Test status
Simulation time 1632986300 ps
CPU time 4.86 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:19 PM PDT 24
Peak memory 242188 kb
Host smart-f3578993-d82e-46c1-b8a2-195f84599102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394121747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3394121747
Directory /workspace/27.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/27.otp_ctrl_macro_errs.2658068258
Short name T318
Test name
Test status
Simulation time 5191343490 ps
CPU time 29.43 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 242728 kb
Host smart-4e262c17-97e9-4277-8a23-dcf6fe5d76a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658068258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2658068258
Directory /workspace/27.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_key_req.1388482010
Short name T639
Test name
Test status
Simulation time 1362634622 ps
CPU time 14.78 seconds
Started Jul 03 07:16:14 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 248776 kb
Host smart-d14920c9-20fe-4f92-86e2-49a12d55927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388482010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.1388482010
Directory /workspace/27.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_esc.3596354827
Short name T122
Test name
Test status
Simulation time 312360937 ps
CPU time 17.57 seconds
Started Jul 03 07:16:07 PM PDT 24
Finished Jul 03 07:16:31 PM PDT 24
Peak memory 241968 kb
Host smart-0d88f412-1075-446c-a74f-84ed14a9d0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596354827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3596354827
Directory /workspace/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/27.otp_ctrl_parallel_lc_req.2421992458
Short name T289
Test name
Test status
Simulation time 849395707 ps
CPU time 16.51 seconds
Started Jul 03 07:16:06 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 248696 kb
Host smart-ceb2e345-40b9-4501-a49e-44fe0a9cf089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2421992458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2421992458
Directory /workspace/27.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/27.otp_ctrl_regwen.995360508
Short name T1006
Test name
Test status
Simulation time 1027607022 ps
CPU time 10.92 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 241952 kb
Host smart-3b0b5c51-893e-4c1d-9f39-02bae8302c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995360508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.995360508
Directory /workspace/27.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/27.otp_ctrl_smoke.1790324056
Short name T693
Test name
Test status
Simulation time 292513113 ps
CPU time 4.37 seconds
Started Jul 03 07:16:05 PM PDT 24
Finished Jul 03 07:16:16 PM PDT 24
Peak memory 242532 kb
Host smart-7db3275b-0e01-41a7-b2d7-3acdbfc61e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790324056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.1790324056
Directory /workspace/27.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/27.otp_ctrl_stress_all.2913015650
Short name T888
Test name
Test status
Simulation time 2543449472 ps
CPU time 58.45 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:17:15 PM PDT 24
Peak memory 256976 kb
Host smart-14b949bf-4598-42d5-90d4-1e911b087e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913015650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all
.2913015650
Directory /workspace/27.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.otp_ctrl_test_access.2437593652
Short name T607
Test name
Test status
Simulation time 483634979 ps
CPU time 5.14 seconds
Started Jul 03 07:16:12 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 242112 kb
Host smart-dc512cf5-f40d-43dd-81a8-ff908050e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437593652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2437593652
Directory /workspace/27.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/270.otp_ctrl_init_fail.2312134845
Short name T162
Test name
Test status
Simulation time 2809457037 ps
CPU time 8.62 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242140 kb
Host smart-48bc7ffc-e65e-4a24-8e95-f5f78b177aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312134845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2312134845
Directory /workspace/270.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/271.otp_ctrl_init_fail.3799741883
Short name T230
Test name
Test status
Simulation time 507650066 ps
CPU time 3.3 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241932 kb
Host smart-27cdc230-7a50-4083-ba50-f46796951ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799741883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3799741883
Directory /workspace/271.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/272.otp_ctrl_init_fail.2661452833
Short name T602
Test name
Test status
Simulation time 106462918 ps
CPU time 3.85 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241996 kb
Host smart-e99f5b32-e4a9-462a-b1f7-a21158a302d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661452833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.2661452833
Directory /workspace/272.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/274.otp_ctrl_init_fail.402744533
Short name T737
Test name
Test status
Simulation time 451827258 ps
CPU time 4.79 seconds
Started Jul 03 07:18:46 PM PDT 24
Finished Jul 03 07:18:57 PM PDT 24
Peak memory 242180 kb
Host smart-847cbdd9-ccbb-4870-92ef-fed62a00b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402744533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.402744533
Directory /workspace/274.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/275.otp_ctrl_init_fail.859939576
Short name T904
Test name
Test status
Simulation time 296953931 ps
CPU time 3.96 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241840 kb
Host smart-87e39c51-fdc7-4fae-83b6-d7d34d02e172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859939576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.859939576
Directory /workspace/275.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/276.otp_ctrl_init_fail.1053362151
Short name T699
Test name
Test status
Simulation time 336132431 ps
CPU time 4.89 seconds
Started Jul 03 07:18:47 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241892 kb
Host smart-7f9a7a9e-5656-45bf-872c-9f97419c3870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053362151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1053362151
Directory /workspace/276.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/277.otp_ctrl_init_fail.1644858352
Short name T32
Test name
Test status
Simulation time 140227344 ps
CPU time 5.13 seconds
Started Jul 03 07:18:46 PM PDT 24
Finished Jul 03 07:18:58 PM PDT 24
Peak memory 242124 kb
Host smart-2884821b-6c3b-4ef4-98f8-f620a5b8b911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644858352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1644858352
Directory /workspace/277.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/278.otp_ctrl_init_fail.3342334403
Short name T227
Test name
Test status
Simulation time 102163960 ps
CPU time 3.23 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 242168 kb
Host smart-d11f2597-d665-4bec-9c28-8f35875be09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342334403 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3342334403
Directory /workspace/278.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/279.otp_ctrl_init_fail.832177681
Short name T646
Test name
Test status
Simulation time 2256987599 ps
CPU time 5.9 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 241876 kb
Host smart-cd478136-258e-4de9-8205-64f40001b41b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832177681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.832177681
Directory /workspace/279.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_alert_test.3994782985
Short name T1190
Test name
Test status
Simulation time 38011898 ps
CPU time 1.5 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 240524 kb
Host smart-84e7dafd-0fe3-46a5-9a03-2e8f68201b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994782985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.3994782985
Directory /workspace/28.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.otp_ctrl_check_fail.3679470204
Short name T745
Test name
Test status
Simulation time 1074422106 ps
CPU time 14.68 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 248760 kb
Host smart-b94ec15b-4aab-4ac9-8409-e61727408fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679470204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.3679470204
Directory /workspace/28.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_errs.3105854928
Short name T1126
Test name
Test status
Simulation time 3022967220 ps
CPU time 12.56 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 242384 kb
Host smart-eb6c5fd8-2df3-401e-ab6e-0e54b34dc671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105854928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3105854928
Directory /workspace/28.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/28.otp_ctrl_dai_lock.631417849
Short name T118
Test name
Test status
Simulation time 18536949429 ps
CPU time 44.01 seconds
Started Jul 03 07:16:13 PM PDT 24
Finished Jul 03 07:17:01 PM PDT 24
Peak memory 242116 kb
Host smart-d64435f5-d664-4555-a583-59204ecbbfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631417849 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.631417849
Directory /workspace/28.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/28.otp_ctrl_init_fail.3121714191
Short name T528
Test name
Test status
Simulation time 124718871 ps
CPU time 4.83 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:21 PM PDT 24
Peak memory 242408 kb
Host smart-c7098fd7-4e91-4689-a595-7917b78f2942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121714191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.3121714191
Directory /workspace/28.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_key_req.1678626778
Short name T168
Test name
Test status
Simulation time 9951705385 ps
CPU time 20.83 seconds
Started Jul 03 07:16:14 PM PDT 24
Finished Jul 03 07:16:39 PM PDT 24
Peak memory 242436 kb
Host smart-7bb17cb0-a2e2-410e-b524-e509ed106ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678626778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.1678626778
Directory /workspace/28.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_esc.3366923944
Short name T1110
Test name
Test status
Simulation time 371812984 ps
CPU time 12.47 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 242004 kb
Host smart-505d76dc-41fb-44bf-abe0-02ed640a8cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366923944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.3366923944
Directory /workspace/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/28.otp_ctrl_parallel_lc_req.2257019196
Short name T996
Test name
Test status
Simulation time 1237233033 ps
CPU time 19.76 seconds
Started Jul 03 07:16:10 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 248672 kb
Host smart-6757e9d2-6e55-4cb7-81ad-931db4db6a11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257019196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.2257019196
Directory /workspace/28.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/28.otp_ctrl_smoke.2478401986
Short name T834
Test name
Test status
Simulation time 981205388 ps
CPU time 7.25 seconds
Started Jul 03 07:16:11 PM PDT 24
Finished Jul 03 07:16:23 PM PDT 24
Peak memory 248696 kb
Host smart-a6d36a7b-75b3-4ebf-9dfc-db56dfe1c8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478401986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.2478401986
Directory /workspace/28.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.2427894916
Short name T410
Test name
Test status
Simulation time 86415391865 ps
CPU time 1489.53 seconds
Started Jul 03 07:16:10 PM PDT 24
Finished Jul 03 07:41:05 PM PDT 24
Peak memory 326312 kb
Host smart-12c27162-8cf1-4ae9-84d1-ff0c7ab31798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427894916 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.2427894916
Directory /workspace/28.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.otp_ctrl_test_access.4279951559
Short name T282
Test name
Test status
Simulation time 2230157715 ps
CPU time 20.15 seconds
Started Jul 03 07:16:12 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 242172 kb
Host smart-f616e432-b355-422b-ae69-5ede1796553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279951559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.4279951559
Directory /workspace/28.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/280.otp_ctrl_init_fail.1111554710
Short name T706
Test name
Test status
Simulation time 2317552098 ps
CPU time 8.43 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:05 PM PDT 24
Peak memory 242072 kb
Host smart-cd983a40-5cab-40fc-91cf-d7e9f92f492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111554710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1111554710
Directory /workspace/280.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/281.otp_ctrl_init_fail.3840888812
Short name T897
Test name
Test status
Simulation time 213975669 ps
CPU time 2.75 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:18:59 PM PDT 24
Peak memory 241804 kb
Host smart-1ee52c92-a666-47ba-88ca-78370a3adba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840888812 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3840888812
Directory /workspace/281.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/282.otp_ctrl_init_fail.2218662057
Short name T192
Test name
Test status
Simulation time 1352285611 ps
CPU time 4.56 seconds
Started Jul 03 07:18:48 PM PDT 24
Finished Jul 03 07:19:00 PM PDT 24
Peak memory 242060 kb
Host smart-f183cf33-ce24-4e4d-8290-cac7f242a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218662057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2218662057
Directory /workspace/282.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/283.otp_ctrl_init_fail.3405579065
Short name T485
Test name
Test status
Simulation time 428705401 ps
CPU time 3.28 seconds
Started Jul 03 07:18:46 PM PDT 24
Finished Jul 03 07:18:55 PM PDT 24
Peak memory 241892 kb
Host smart-621838bb-4bf6-4f49-be82-b62fc22fb67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405579065 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.3405579065
Directory /workspace/283.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/284.otp_ctrl_init_fail.3719361386
Short name T1077
Test name
Test status
Simulation time 158414575 ps
CPU time 4.33 seconds
Started Jul 03 07:18:50 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 242224 kb
Host smart-3e9b1e1a-0cd8-49d7-bb1f-36430ef896eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719361386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3719361386
Directory /workspace/284.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/285.otp_ctrl_init_fail.1879237483
Short name T551
Test name
Test status
Simulation time 2026324356 ps
CPU time 4.88 seconds
Started Jul 03 07:18:52 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 242136 kb
Host smart-b3f4b85e-4f26-4c55-bec0-ae596ec00659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879237483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.1879237483
Directory /workspace/285.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/286.otp_ctrl_init_fail.3013654744
Short name T455
Test name
Test status
Simulation time 477131876 ps
CPU time 5.06 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 242368 kb
Host smart-e0db8309-d7b9-4eb2-ba73-f50fdf565369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013654744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.3013654744
Directory /workspace/286.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/287.otp_ctrl_init_fail.2948129500
Short name T583
Test name
Test status
Simulation time 529931650 ps
CPU time 4.28 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242156 kb
Host smart-66b8f882-ebe2-4558-9803-a3b077d927b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948129500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.2948129500
Directory /workspace/287.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/288.otp_ctrl_init_fail.3175938549
Short name T1047
Test name
Test status
Simulation time 629375758 ps
CPU time 4.37 seconds
Started Jul 03 07:18:49 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 242092 kb
Host smart-435206ef-5934-4675-a505-8290795e0417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175938549 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3175938549
Directory /workspace/288.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/289.otp_ctrl_init_fail.2241314672
Short name T1051
Test name
Test status
Simulation time 150044473 ps
CPU time 4.47 seconds
Started Jul 03 07:18:54 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 242252 kb
Host smart-1e47a693-8488-4c77-b8ca-52c475169594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241314672 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2241314672
Directory /workspace/289.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_alert_test.166782992
Short name T1
Test name
Test status
Simulation time 217722693 ps
CPU time 2.12 seconds
Started Jul 03 07:16:16 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 240152 kb
Host smart-68fbdbfc-f04f-49ee-947f-5eb2c69e5adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166782992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.166782992
Directory /workspace/29.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.otp_ctrl_check_fail.547460098
Short name T435
Test name
Test status
Simulation time 474642218 ps
CPU time 6.01 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 242324 kb
Host smart-94a4ef22-de7b-46d9-8b1a-d42f848c47f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547460098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.547460098
Directory /workspace/29.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_errs.3949069897
Short name T926
Test name
Test status
Simulation time 1435489122 ps
CPU time 23.68 seconds
Started Jul 03 07:16:20 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 241968 kb
Host smart-9b6689d6-6c8b-497d-abb3-692e924abb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949069897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3949069897
Directory /workspace/29.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_dai_lock.1097029376
Short name T655
Test name
Test status
Simulation time 2150581161 ps
CPU time 24.94 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:45 PM PDT 24
Peak memory 242040 kb
Host smart-fda0b3af-cb36-43ad-8811-c48eeb928348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097029376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1097029376
Directory /workspace/29.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/29.otp_ctrl_init_fail.2238804397
Short name T698
Test name
Test status
Simulation time 297925101 ps
CPU time 3.93 seconds
Started Jul 03 07:16:19 PM PDT 24
Finished Jul 03 07:16:26 PM PDT 24
Peak memory 242460 kb
Host smart-043aca6c-4da8-48ff-8a68-58f37b8ef1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238804397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.2238804397
Directory /workspace/29.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/29.otp_ctrl_macro_errs.1855707533
Short name T775
Test name
Test status
Simulation time 308095398 ps
CPU time 3 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242296 kb
Host smart-774b2cb8-bd85-4494-b89b-0931dedbf90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855707533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1855707533
Directory /workspace/29.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_key_req.755554938
Short name T1010
Test name
Test status
Simulation time 156755805 ps
CPU time 3.88 seconds
Started Jul 03 07:16:18 PM PDT 24
Finished Jul 03 07:16:25 PM PDT 24
Peak memory 241988 kb
Host smart-b4b402af-c641-4d02-8473-c972331f78e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755554938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.755554938
Directory /workspace/29.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_esc.5594930
Short name T428
Test name
Test status
Simulation time 323514140 ps
CPU time 5.06 seconds
Started Jul 03 07:16:19 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 241828 kb
Host smart-9210e697-e3c8-4e2b-90ec-66f004eba6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5594930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.5594930
Directory /workspace/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/29.otp_ctrl_parallel_lc_req.1735422546
Short name T274
Test name
Test status
Simulation time 157060204 ps
CPU time 4.75 seconds
Started Jul 03 07:16:19 PM PDT 24
Finished Jul 03 07:16:27 PM PDT 24
Peak memory 242112 kb
Host smart-0a71911c-b1ff-4ee8-ada8-11a18b666263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1735422546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.1735422546
Directory /workspace/29.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/29.otp_ctrl_smoke.4066633958
Short name T1079
Test name
Test status
Simulation time 592902901 ps
CPU time 7.6 seconds
Started Jul 03 07:16:10 PM PDT 24
Finished Jul 03 07:16:23 PM PDT 24
Peak memory 242108 kb
Host smart-400b488d-98cb-4743-a401-6d2ccf39e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066633958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.4066633958
Directory /workspace/29.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all.3124927491
Short name T806
Test name
Test status
Simulation time 5335277285 ps
CPU time 41.35 seconds
Started Jul 03 07:16:16 PM PDT 24
Finished Jul 03 07:17:01 PM PDT 24
Peak memory 254996 kb
Host smart-52899894-6996-48dd-b2ae-2d91a01ff640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124927491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all
.3124927491
Directory /workspace/29.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.1256760433
Short name T19
Test name
Test status
Simulation time 102153921579 ps
CPU time 1270.99 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:37:32 PM PDT 24
Peak memory 287724 kb
Host smart-9740e0c4-8d44-45e0-95ab-a9197aefe467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256760433 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.1256760433
Directory /workspace/29.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.otp_ctrl_test_access.975707445
Short name T1174
Test name
Test status
Simulation time 20069736618 ps
CPU time 37.59 seconds
Started Jul 03 07:16:18 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 243416 kb
Host smart-728ec61c-daf7-4105-bfc7-643e8759bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975707445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.975707445
Directory /workspace/29.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/290.otp_ctrl_init_fail.163920142
Short name T1066
Test name
Test status
Simulation time 1560857928 ps
CPU time 4.51 seconds
Started Jul 03 07:18:54 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 241876 kb
Host smart-757dc76a-7eee-43bc-b9a9-d8ed6e077051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163920142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.163920142
Directory /workspace/290.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/291.otp_ctrl_init_fail.2611572925
Short name T1074
Test name
Test status
Simulation time 218205445 ps
CPU time 3.61 seconds
Started Jul 03 07:18:52 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242236 kb
Host smart-16ef0d32-ad2f-401e-a2bc-e4af7c243691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611572925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2611572925
Directory /workspace/291.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/292.otp_ctrl_init_fail.3867921412
Short name T914
Test name
Test status
Simulation time 222262729 ps
CPU time 4.68 seconds
Started Jul 03 07:18:52 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 241916 kb
Host smart-0daa46df-ee7e-4dac-9186-ca868aa8e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867921412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3867921412
Directory /workspace/292.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/293.otp_ctrl_init_fail.266882416
Short name T686
Test name
Test status
Simulation time 295784022 ps
CPU time 4.48 seconds
Started Jul 03 07:18:53 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 242116 kb
Host smart-49adc315-2ad2-416c-a642-636f6062869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266882416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.266882416
Directory /workspace/293.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/294.otp_ctrl_init_fail.1906287193
Short name T203
Test name
Test status
Simulation time 449981735 ps
CPU time 3.28 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 242168 kb
Host smart-4a0d2463-55f1-421f-85a3-e958a8ae30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906287193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.1906287193
Directory /workspace/294.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/296.otp_ctrl_init_fail.181841750
Short name T1154
Test name
Test status
Simulation time 293706269 ps
CPU time 4.11 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242068 kb
Host smart-5dfa0c50-9812-4bfc-8b79-71f555f12751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181841750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.181841750
Directory /workspace/296.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/297.otp_ctrl_init_fail.2078077367
Short name T49
Test name
Test status
Simulation time 136832856 ps
CPU time 4.01 seconds
Started Jul 03 07:18:55 PM PDT 24
Finished Jul 03 07:19:04 PM PDT 24
Peak memory 242344 kb
Host smart-6fe1f987-970d-42f0-997b-ebb2cbaa6ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078077367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2078077367
Directory /workspace/297.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/298.otp_ctrl_init_fail.4253282985
Short name T211
Test name
Test status
Simulation time 120202040 ps
CPU time 3.32 seconds
Started Jul 03 07:18:51 PM PDT 24
Finished Jul 03 07:19:01 PM PDT 24
Peak memory 242096 kb
Host smart-e30acbb8-7132-40fb-9587-a5732a826cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253282985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.4253282985
Directory /workspace/298.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/299.otp_ctrl_init_fail.4075448994
Short name T185
Test name
Test status
Simulation time 167969041 ps
CPU time 4.49 seconds
Started Jul 03 07:18:52 PM PDT 24
Finished Jul 03 07:19:02 PM PDT 24
Peak memory 242032 kb
Host smart-2ed87769-a1a9-4285-a184-703381b9bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075448994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.4075448994
Directory /workspace/299.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_alert_test.2210521850
Short name T1166
Test name
Test status
Simulation time 222799161 ps
CPU time 1.93 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:15 PM PDT 24
Peak memory 240488 kb
Host smart-36853098-3f3d-4516-9b5f-11776b473898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210521850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2210521850
Directory /workspace/3.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.otp_ctrl_background_chks.3628131477
Short name T125
Test name
Test status
Simulation time 1819599147 ps
CPU time 16.74 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:15:24 PM PDT 24
Peak memory 242384 kb
Host smart-66687558-b235-4a0b-9b51-6c5587f99efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628131477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.3628131477
Directory /workspace/3.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/3.otp_ctrl_check_fail.1332808265
Short name T1191
Test name
Test status
Simulation time 1897214918 ps
CPU time 37.23 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 248704 kb
Host smart-98bfe7df-044d-4147-bf8b-1501d7b888ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332808265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.1332808265
Directory /workspace/3.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_errs.2283161907
Short name T978
Test name
Test status
Simulation time 1621715785 ps
CPU time 24.14 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:27 PM PDT 24
Peak memory 242284 kb
Host smart-f0748110-4f69-4be1-8503-5557ced999a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283161907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2283161907
Directory /workspace/3.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_dai_lock.2227374772
Short name T556
Test name
Test status
Simulation time 254095013 ps
CPU time 4.99 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:10 PM PDT 24
Peak memory 241908 kb
Host smart-a69ae70c-bf89-48e1-96e4-591f9b38df0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227374772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.2227374772
Directory /workspace/3.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/3.otp_ctrl_macro_errs.3123357152
Short name T153
Test name
Test status
Simulation time 2601768982 ps
CPU time 16.15 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 245084 kb
Host smart-7ef02873-ed69-4216-9b1d-29b515244d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123357152 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3123357152
Directory /workspace/3.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_key_req.1784335653
Short name T640
Test name
Test status
Simulation time 1156557065 ps
CPU time 23.12 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 242644 kb
Host smart-e1d208a4-e036-4350-8fa8-79dc18ff60e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784335653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1784335653
Directory /workspace/3.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/3.otp_ctrl_parallel_lc_esc.2205035142
Short name T430
Test name
Test status
Simulation time 903115544 ps
CPU time 24.57 seconds
Started Jul 03 07:15:06 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 241852 kb
Host smart-e1eb4b89-b174-44e3-b4af-2886b619a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205035142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2205035142
Directory /workspace/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/3.otp_ctrl_regwen.3161241816
Short name T816
Test name
Test status
Simulation time 214940088 ps
CPU time 6.04 seconds
Started Jul 03 07:15:07 PM PDT 24
Finished Jul 03 07:15:19 PM PDT 24
Peak memory 242208 kb
Host smart-5751b9d1-ee86-47f7-88ae-4a6920de7d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3161241816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3161241816
Directory /workspace/3.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/3.otp_ctrl_sec_cm.3900611061
Short name T22
Test name
Test status
Simulation time 154730742490 ps
CPU time 347.6 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:20:55 PM PDT 24
Peak memory 277296 kb
Host smart-fb2ff9ff-e0dd-4487-be60-4ddb457adc89
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900611061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3900611061
Directory /workspace/3.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.otp_ctrl_smoke.2237950753
Short name T432
Test name
Test status
Simulation time 241281961 ps
CPU time 5.14 seconds
Started Jul 03 07:15:02 PM PDT 24
Finished Jul 03 07:15:12 PM PDT 24
Peak memory 242068 kb
Host smart-f97ec1c7-de73-4c13-8972-5e6410fdbf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237950753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2237950753
Directory /workspace/3.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all.417564291
Short name T873
Test name
Test status
Simulation time 128624820952 ps
CPU time 210.35 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:18:33 PM PDT 24
Peak memory 265588 kb
Host smart-55ed8b83-8e11-4339-98e3-19c9e46d4e20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417564291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.417564291
Directory /workspace/3.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3141744617
Short name T981
Test name
Test status
Simulation time 174331848282 ps
CPU time 387.62 seconds
Started Jul 03 07:15:01 PM PDT 24
Finished Jul 03 07:21:33 PM PDT 24
Peak memory 342400 kb
Host smart-8fc0ad5e-2071-45cb-89bd-af75ec7c5987
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141744617 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3141744617
Directory /workspace/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.otp_ctrl_test_access.3768892057
Short name T723
Test name
Test status
Simulation time 2050109423 ps
CPU time 11.28 seconds
Started Jul 03 07:15:03 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 242368 kb
Host smart-fea515d5-835c-4d34-b747-1c46c1d2f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768892057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3768892057
Directory /workspace/3.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/30.otp_ctrl_alert_test.3211833188
Short name T462
Test name
Test status
Simulation time 93096078 ps
CPU time 2.14 seconds
Started Jul 03 07:16:18 PM PDT 24
Finished Jul 03 07:16:23 PM PDT 24
Peak memory 240132 kb
Host smart-183836df-6739-4a36-932a-6a4cf5871c6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211833188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3211833188
Directory /workspace/30.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.otp_ctrl_check_fail.2704610600
Short name T52
Test name
Test status
Simulation time 179680709 ps
CPU time 5.33 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:26 PM PDT 24
Peak memory 242100 kb
Host smart-fe69efee-881b-4464-9f83-c99dac5f0c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704610600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2704610600
Directory /workspace/30.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_errs.3789613128
Short name T431
Test name
Test status
Simulation time 4146220646 ps
CPU time 34.81 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:55 PM PDT 24
Peak memory 244180 kb
Host smart-ac22f3da-87a3-459f-b4dd-412da3121ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789613128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3789613128
Directory /workspace/30.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_dai_lock.3315315148
Short name T402
Test name
Test status
Simulation time 4894216991 ps
CPU time 29.06 seconds
Started Jul 03 07:16:16 PM PDT 24
Finished Jul 03 07:16:49 PM PDT 24
Peak memory 242076 kb
Host smart-15c3c5d9-cb43-45cd-8a67-3f3ea3ab6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315315148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.3315315148
Directory /workspace/30.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/30.otp_ctrl_macro_errs.3020660915
Short name T1131
Test name
Test status
Simulation time 184879708 ps
CPU time 7.54 seconds
Started Jul 03 07:16:19 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 248636 kb
Host smart-ffa40468-fab6-4acd-a3c2-4411b9bbd391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020660915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3020660915
Directory /workspace/30.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_key_req.3559361285
Short name T566
Test name
Test status
Simulation time 640900785 ps
CPU time 16.11 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 242376 kb
Host smart-61075089-436b-4861-badf-d7227a0ff1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559361285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.3559361285
Directory /workspace/30.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_esc.1540929639
Short name T799
Test name
Test status
Simulation time 4830782016 ps
CPU time 9.56 seconds
Started Jul 03 07:16:14 PM PDT 24
Finished Jul 03 07:16:28 PM PDT 24
Peak memory 242080 kb
Host smart-ecd6d257-8399-483a-88db-1eeb27b28595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540929639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.1540929639
Directory /workspace/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/30.otp_ctrl_parallel_lc_req.4090869301
Short name T407
Test name
Test status
Simulation time 3009047003 ps
CPU time 17.91 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:38 PM PDT 24
Peak memory 248800 kb
Host smart-33c2a627-174e-4d8c-b7e7-c8aa0a24767f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090869301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.4090869301
Directory /workspace/30.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/30.otp_ctrl_regwen.4173129619
Short name T874
Test name
Test status
Simulation time 191451573 ps
CPU time 5.61 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:16:26 PM PDT 24
Peak memory 241960 kb
Host smart-5f0a1201-9cd7-4527-b8db-4711d3972592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173129619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.4173129619
Directory /workspace/30.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/30.otp_ctrl_smoke.2269559405
Short name T291
Test name
Test status
Simulation time 651813899 ps
CPU time 8.99 seconds
Started Jul 03 07:16:16 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 242472 kb
Host smart-fb32b544-0061-4c40-bbae-a7c4853b6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269559405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.2269559405
Directory /workspace/30.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all.4239871268
Short name T1048
Test name
Test status
Simulation time 28333177891 ps
CPU time 169.65 seconds
Started Jul 03 07:16:17 PM PDT 24
Finished Jul 03 07:19:10 PM PDT 24
Peak memory 257116 kb
Host smart-286e5349-080f-45f9-a8f7-7166090dac99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239871268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all
.4239871268
Directory /workspace/30.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.3824193223
Short name T945
Test name
Test status
Simulation time 784726448835 ps
CPU time 1371.96 seconds
Started Jul 03 07:16:15 PM PDT 24
Finished Jul 03 07:39:11 PM PDT 24
Peak memory 489316 kb
Host smart-3dc9b47d-367a-45e9-a49f-f4bf7d148abc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824193223 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.3824193223
Directory /workspace/30.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.otp_ctrl_test_access.2994911411
Short name T1123
Test name
Test status
Simulation time 4318037240 ps
CPU time 30.97 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:16:56 PM PDT 24
Peak memory 242508 kb
Host smart-6d430578-d753-4086-bd12-ccf94660c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994911411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2994911411
Directory /workspace/30.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/31.otp_ctrl_alert_test.3835764450
Short name T635
Test name
Test status
Simulation time 157086561 ps
CPU time 2.01 seconds
Started Jul 03 07:16:22 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 240084 kb
Host smart-bdfe739a-bf2d-4f58-b102-7dd8a828a49d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835764450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3835764450
Directory /workspace/31.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.otp_ctrl_check_fail.3275409956
Short name T1049
Test name
Test status
Simulation time 3498554493 ps
CPU time 29.4 seconds
Started Jul 03 07:16:20 PM PDT 24
Finished Jul 03 07:16:53 PM PDT 24
Peak memory 248820 kb
Host smart-3ebe12b6-0a77-4a08-a65f-102b6e8d0fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275409956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.3275409956
Directory /workspace/31.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_errs.1707756262
Short name T746
Test name
Test status
Simulation time 7333135877 ps
CPU time 16.11 seconds
Started Jul 03 07:16:20 PM PDT 24
Finished Jul 03 07:16:40 PM PDT 24
Peak memory 242388 kb
Host smart-d6b8ecd0-5078-49c8-af27-069ca8c4e6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707756262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1707756262
Directory /workspace/31.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_dai_lock.382229031
Short name T798
Test name
Test status
Simulation time 5238140468 ps
CPU time 17.23 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:16:41 PM PDT 24
Peak memory 242528 kb
Host smart-5d67883b-c0d1-4c1b-a69a-ce246f692de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382229031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.382229031
Directory /workspace/31.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/31.otp_ctrl_init_fail.809137299
Short name T436
Test name
Test status
Simulation time 1408132575 ps
CPU time 3.56 seconds
Started Jul 03 07:16:23 PM PDT 24
Finished Jul 03 07:16:31 PM PDT 24
Peak memory 242144 kb
Host smart-ead47f85-61e2-4a24-bee5-3a5b72c771df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809137299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.809137299
Directory /workspace/31.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/31.otp_ctrl_macro_errs.1001161921
Short name T170
Test name
Test status
Simulation time 743711701 ps
CPU time 5.77 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:16:31 PM PDT 24
Peak memory 248708 kb
Host smart-f2ff617d-d94c-415a-9c16-7242f77a58f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001161921 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.1001161921
Directory /workspace/31.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_key_req.683552837
Short name T864
Test name
Test status
Simulation time 702480290 ps
CPU time 11.46 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 248812 kb
Host smart-54606881-04df-4654-b7bd-15aeefb643d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683552837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.683552837
Directory /workspace/31.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_esc.1675890005
Short name T1017
Test name
Test status
Simulation time 393677624 ps
CPU time 6.15 seconds
Started Jul 03 07:16:22 PM PDT 24
Finished Jul 03 07:16:33 PM PDT 24
Peak memory 242324 kb
Host smart-04d37455-c820-45ad-a4fd-4a82cdcb4862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675890005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1675890005
Directory /workspace/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/31.otp_ctrl_parallel_lc_req.3003871579
Short name T631
Test name
Test status
Simulation time 517534064 ps
CPU time 17.98 seconds
Started Jul 03 07:16:23 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 242024 kb
Host smart-0c954320-d6ee-43f8-ba34-0ecffcc03073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3003871579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3003871579
Directory /workspace/31.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/31.otp_ctrl_regwen.114576072
Short name T381
Test name
Test status
Simulation time 211719861 ps
CPU time 7.51 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:16:32 PM PDT 24
Peak memory 241964 kb
Host smart-0532af2c-cd06-447c-9e7b-5a48f9374566
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=114576072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.114576072
Directory /workspace/31.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/31.otp_ctrl_smoke.1903139386
Short name T427
Test name
Test status
Simulation time 260299319 ps
CPU time 6.53 seconds
Started Jul 03 07:16:22 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 241736 kb
Host smart-70e60ce8-6157-42cf-9222-5c2d39bc33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903139386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1903139386
Directory /workspace/31.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all.1679187594
Short name T820
Test name
Test status
Simulation time 14419079026 ps
CPU time 175.11 seconds
Started Jul 03 07:16:20 PM PDT 24
Finished Jul 03 07:19:19 PM PDT 24
Peak memory 250800 kb
Host smart-c9de7288-bea1-48a4-918d-b221027d2e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679187594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all
.1679187594
Directory /workspace/31.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3260547719
Short name T20
Test name
Test status
Simulation time 359949244637 ps
CPU time 2071.62 seconds
Started Jul 03 07:16:21 PM PDT 24
Finished Jul 03 07:50:58 PM PDT 24
Peak memory 380024 kb
Host smart-af94e5ce-61e1-4b5c-a58a-2947a9e22f75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260547719 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3260547719
Directory /workspace/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.otp_ctrl_test_access.855037266
Short name T871
Test name
Test status
Simulation time 845597919 ps
CPU time 5.32 seconds
Started Jul 03 07:16:24 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 248760 kb
Host smart-916f372e-4e55-448b-9d9e-c498b3deb73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855037266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.855037266
Directory /workspace/31.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/32.otp_ctrl_alert_test.2899218877
Short name T322
Test name
Test status
Simulation time 116992463 ps
CPU time 1.96 seconds
Started Jul 03 07:16:25 PM PDT 24
Finished Jul 03 07:16:32 PM PDT 24
Peak memory 240156 kb
Host smart-24ebdbbf-c14f-433b-9d32-35b11648431e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899218877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2899218877
Directory /workspace/32.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.otp_ctrl_check_fail.1578723948
Short name T1180
Test name
Test status
Simulation time 843620825 ps
CPU time 8.42 seconds
Started Jul 03 07:16:23 PM PDT 24
Finished Jul 03 07:16:36 PM PDT 24
Peak memory 248804 kb
Host smart-a7501158-a570-4ffb-b1cb-5bc728ff8067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578723948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1578723948
Directory /workspace/32.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_errs.2414309383
Short name T1029
Test name
Test status
Simulation time 976931428 ps
CPU time 29.78 seconds
Started Jul 03 07:16:27 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 245344 kb
Host smart-ce06cf22-6906-4d5e-82e8-d248f829c881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414309383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2414309383
Directory /workspace/32.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_dai_lock.2548455020
Short name T946
Test name
Test status
Simulation time 1821580785 ps
CPU time 18 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:51 PM PDT 24
Peak memory 242488 kb
Host smart-5a4b34e9-82b3-49dc-be66-325c49b66cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548455020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2548455020
Directory /workspace/32.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/32.otp_ctrl_init_fail.3198392123
Short name T1081
Test name
Test status
Simulation time 218756633 ps
CPU time 3.89 seconds
Started Jul 03 07:16:24 PM PDT 24
Finished Jul 03 07:16:32 PM PDT 24
Peak memory 242060 kb
Host smart-19155580-160f-4b47-adea-fdfda4983909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198392123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3198392123
Directory /workspace/32.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/32.otp_ctrl_macro_errs.3673817615
Short name T559
Test name
Test status
Simulation time 328093330 ps
CPU time 6.88 seconds
Started Jul 03 07:16:24 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 242432 kb
Host smart-1f9ff33d-d7cc-4a99-afcf-b916aee3d64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673817615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.3673817615
Directory /workspace/32.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_key_req.2459377375
Short name T685
Test name
Test status
Simulation time 644763249 ps
CPU time 11.98 seconds
Started Jul 03 07:16:23 PM PDT 24
Finished Jul 03 07:16:40 PM PDT 24
Peak memory 242588 kb
Host smart-5455c19f-2cb5-4cef-a478-1e0054a5e05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459377375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.2459377375
Directory /workspace/32.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_esc.1027280140
Short name T292
Test name
Test status
Simulation time 447130368 ps
CPU time 5.61 seconds
Started Jul 03 07:16:19 PM PDT 24
Finished Jul 03 07:16:29 PM PDT 24
Peak memory 242028 kb
Host smart-414a304d-0752-4b8e-bfa2-5079073f8afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027280140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1027280140
Directory /workspace/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/32.otp_ctrl_parallel_lc_req.1560285682
Short name T638
Test name
Test status
Simulation time 683937116 ps
CPU time 21.81 seconds
Started Jul 03 07:16:23 PM PDT 24
Finished Jul 03 07:16:49 PM PDT 24
Peak memory 242020 kb
Host smart-67b8c39c-1c52-4105-8ff0-8c2160dc037b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1560285682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1560285682
Directory /workspace/32.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/32.otp_ctrl_regwen.194931131
Short name T968
Test name
Test status
Simulation time 2726752877 ps
CPU time 9.32 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:16:43 PM PDT 24
Peak memory 242492 kb
Host smart-b5269917-fea2-4434-99fc-0b103f9d84a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=194931131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.194931131
Directory /workspace/32.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/32.otp_ctrl_smoke.3871330765
Short name T851
Test name
Test status
Simulation time 463399916 ps
CPU time 5.71 seconds
Started Jul 03 07:16:20 PM PDT 24
Finished Jul 03 07:16:30 PM PDT 24
Peak memory 241972 kb
Host smart-30ed3aac-7f81-4f7f-80b1-bf82751e0279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871330765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3871330765
Directory /workspace/32.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all.1254749473
Short name T405
Test name
Test status
Simulation time 25299408514 ps
CPU time 169.4 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:19:23 PM PDT 24
Peak memory 256968 kb
Host smart-a4342356-670e-45ff-af4d-34f1a09f8aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254749473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all
.1254749473
Directory /workspace/32.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3316588495
Short name T1028
Test name
Test status
Simulation time 177463878056 ps
CPU time 2292.42 seconds
Started Jul 03 07:16:22 PM PDT 24
Finished Jul 03 07:54:39 PM PDT 24
Peak memory 431840 kb
Host smart-d322ceff-eba1-4818-beee-d11f8a0da2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316588495 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3316588495
Directory /workspace/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.otp_ctrl_test_access.1579234654
Short name T986
Test name
Test status
Simulation time 249000168 ps
CPU time 5.22 seconds
Started Jul 03 07:16:24 PM PDT 24
Finished Jul 03 07:16:34 PM PDT 24
Peak memory 248784 kb
Host smart-b05c0e63-5a2a-472a-a86a-4d22936eb3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579234654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1579234654
Directory /workspace/32.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/33.otp_ctrl_alert_test.2482312275
Short name T813
Test name
Test status
Simulation time 227415873 ps
CPU time 1.69 seconds
Started Jul 03 07:16:30 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 240124 kb
Host smart-d2419fc4-3659-41ed-ad32-fea4133f4091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482312275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2482312275
Directory /workspace/33.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.otp_ctrl_check_fail.2455904410
Short name T163
Test name
Test status
Simulation time 344708795 ps
CPU time 6.21 seconds
Started Jul 03 07:16:33 PM PDT 24
Finished Jul 03 07:16:44 PM PDT 24
Peak memory 242272 kb
Host smart-03f11803-64a1-467b-8289-e72df91a250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455904410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2455904410
Directory /workspace/33.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_errs.1238385893
Short name T900
Test name
Test status
Simulation time 8037762190 ps
CPU time 19.5 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:16:54 PM PDT 24
Peak memory 242100 kb
Host smart-d1b8a64d-7496-4131-b9f9-36fe4064469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238385893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.1238385893
Directory /workspace/33.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_dai_lock.2935649827
Short name T1149
Test name
Test status
Simulation time 486537772 ps
CPU time 9.44 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:43 PM PDT 24
Peak memory 242376 kb
Host smart-f94efed6-9a23-495e-9ca0-31e3b44dfa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935649827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.2935649827
Directory /workspace/33.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/33.otp_ctrl_init_fail.3572934587
Short name T1058
Test name
Test status
Simulation time 460134012 ps
CPU time 4.06 seconds
Started Jul 03 07:16:30 PM PDT 24
Finished Jul 03 07:16:39 PM PDT 24
Peak memory 241860 kb
Host smart-d65f7411-ac41-48c8-ba4c-cd4d6348b7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572934587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3572934587
Directory /workspace/33.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/33.otp_ctrl_macro_errs.2107901336
Short name T895
Test name
Test status
Simulation time 269071350 ps
CPU time 5.01 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:16:39 PM PDT 24
Peak memory 242416 kb
Host smart-a591873e-c3dc-4bc3-96f1-47cb9578b3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107901336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2107901336
Directory /workspace/33.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_key_req.3120284990
Short name T769
Test name
Test status
Simulation time 764071967 ps
CPU time 16.62 seconds
Started Jul 03 07:16:26 PM PDT 24
Finished Jul 03 07:16:48 PM PDT 24
Peak memory 242360 kb
Host smart-dfd3f630-be13-4364-9a0f-a67bcccf5bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120284990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3120284990
Directory /workspace/33.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_esc.1353674398
Short name T662
Test name
Test status
Simulation time 1130420493 ps
CPU time 9.15 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:42 PM PDT 24
Peak memory 242324 kb
Host smart-60a4d383-b569-4820-8ebc-7badb044dd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353674398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.1353674398
Directory /workspace/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/33.otp_ctrl_parallel_lc_req.1473803362
Short name T1188
Test name
Test status
Simulation time 664998889 ps
CPU time 14.51 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:16:49 PM PDT 24
Peak memory 242224 kb
Host smart-270c3969-66af-494c-bfb1-33c7544e46f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1473803362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1473803362
Directory /workspace/33.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/33.otp_ctrl_regwen.3816074924
Short name T1083
Test name
Test status
Simulation time 233840473 ps
CPU time 6.83 seconds
Started Jul 03 07:16:26 PM PDT 24
Finished Jul 03 07:16:38 PM PDT 24
Peak memory 241952 kb
Host smart-97290868-ae97-4159-8e01-97ac4e5b0a44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816074924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3816074924
Directory /workspace/33.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/33.otp_ctrl_smoke.2437095521
Short name T106
Test name
Test status
Simulation time 981698900 ps
CPU time 5.95 seconds
Started Jul 03 07:16:24 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 242176 kb
Host smart-bbaa2c50-620b-4f02-874d-817fed51de32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437095521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2437095521
Directory /workspace/33.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/33.otp_ctrl_stress_all.2204007232
Short name T1118
Test name
Test status
Simulation time 1095313774 ps
CPU time 2.6 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:35 PM PDT 24
Peak memory 241356 kb
Host smart-9ba2ec52-247d-4828-b98c-90405d8e8f3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204007232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all
.2204007232
Directory /workspace/33.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.otp_ctrl_test_access.4059340356
Short name T393
Test name
Test status
Simulation time 1595458863 ps
CPU time 27.93 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 241952 kb
Host smart-4691d130-e858-4ba1-9cef-571a2f9487f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059340356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.4059340356
Directory /workspace/33.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/34.otp_ctrl_alert_test.2248775749
Short name T694
Test name
Test status
Simulation time 115297224 ps
CPU time 1.97 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:16:39 PM PDT 24
Peak memory 240268 kb
Host smart-8b47c116-1c5f-4544-ba0a-c8cbf8762086
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248775749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.2248775749
Directory /workspace/34.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.otp_ctrl_check_fail.1658818498
Short name T598
Test name
Test status
Simulation time 1236390550 ps
CPU time 8.3 seconds
Started Jul 03 07:16:31 PM PDT 24
Finished Jul 03 07:16:44 PM PDT 24
Peak memory 242336 kb
Host smart-361822ee-6245-4c9d-8555-56651e9356a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658818498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1658818498
Directory /workspace/34.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_errs.3178603381
Short name T1159
Test name
Test status
Simulation time 3138241493 ps
CPU time 26.73 seconds
Started Jul 03 07:16:33 PM PDT 24
Finished Jul 03 07:17:04 PM PDT 24
Peak memory 244036 kb
Host smart-b7c632a5-44ec-4a07-91f0-52880fd87dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178603381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3178603381
Directory /workspace/34.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_dai_lock.3771891951
Short name T601
Test name
Test status
Simulation time 2801748644 ps
CPU time 24.75 seconds
Started Jul 03 07:16:26 PM PDT 24
Finished Jul 03 07:16:56 PM PDT 24
Peak memory 242296 kb
Host smart-7d440daf-6f2b-49c3-bd57-f2482c3641c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771891951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3771891951
Directory /workspace/34.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/34.otp_ctrl_init_fail.1124297351
Short name T741
Test name
Test status
Simulation time 198771615 ps
CPU time 4.37 seconds
Started Jul 03 07:16:29 PM PDT 24
Finished Jul 03 07:16:38 PM PDT 24
Peak memory 242128 kb
Host smart-1d986de6-3e3b-400d-9da9-49b5616adea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124297351 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1124297351
Directory /workspace/34.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/34.otp_ctrl_macro_errs.2785366054
Short name T1096
Test name
Test status
Simulation time 2170268476 ps
CPU time 32.55 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:17:10 PM PDT 24
Peak memory 257056 kb
Host smart-e82e3098-a939-465d-8ea9-c3845a6ada54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785366054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.2785366054
Directory /workspace/34.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_key_req.3819257821
Short name T962
Test name
Test status
Simulation time 1004191069 ps
CPU time 22.86 seconds
Started Jul 03 07:16:34 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 242268 kb
Host smart-49e2d16f-9942-43f5-89ab-9c26d7d46ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819257821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3819257821
Directory /workspace/34.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_esc.4036166079
Short name T1057
Test name
Test status
Simulation time 305364215 ps
CPU time 8.11 seconds
Started Jul 03 07:16:27 PM PDT 24
Finished Jul 03 07:16:40 PM PDT 24
Peak memory 241964 kb
Host smart-10b472c6-3008-4b84-bd02-57adfea14e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036166079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.4036166079
Directory /workspace/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/34.otp_ctrl_parallel_lc_req.505165654
Short name T463
Test name
Test status
Simulation time 1803668699 ps
CPU time 13.54 seconds
Started Jul 03 07:16:27 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 248760 kb
Host smart-0a7e62b2-e7e4-426e-9ab9-c973c09df5f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505165654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.505165654
Directory /workspace/34.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/34.otp_ctrl_regwen.2322750457
Short name T882
Test name
Test status
Simulation time 4551166376 ps
CPU time 17.05 seconds
Started Jul 03 07:16:31 PM PDT 24
Finished Jul 03 07:16:53 PM PDT 24
Peak memory 242132 kb
Host smart-13b1f7b7-9aff-4812-b4ea-90ba53a4f3fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2322750457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2322750457
Directory /workspace/34.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/34.otp_ctrl_smoke.1699690761
Short name T500
Test name
Test status
Simulation time 402099746 ps
CPU time 4.47 seconds
Started Jul 03 07:16:28 PM PDT 24
Finished Jul 03 07:16:37 PM PDT 24
Peak memory 242384 kb
Host smart-dc36c306-00ab-411a-bf83-307b891808a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699690761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.1699690761
Directory /workspace/34.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all.3829126687
Short name T1157
Test name
Test status
Simulation time 1062171775 ps
CPU time 25.3 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:17:03 PM PDT 24
Peak memory 241608 kb
Host smart-143cd099-6f46-416f-8e89-b6a6caecd72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829126687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all
.3829126687
Directory /workspace/34.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.988255027
Short name T922
Test name
Test status
Simulation time 297027684711 ps
CPU time 921.61 seconds
Started Jul 03 07:16:34 PM PDT 24
Finished Jul 03 07:32:01 PM PDT 24
Peak memory 331812 kb
Host smart-317d981e-9b93-4ccd-b485-e70e3098af19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988255027 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.988255027
Directory /workspace/34.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.otp_ctrl_test_access.1318532851
Short name T401
Test name
Test status
Simulation time 2072560136 ps
CPU time 26.35 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:17:04 PM PDT 24
Peak memory 242248 kb
Host smart-4104c04d-6453-4d06-bc09-96d99c2500c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318532851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.1318532851
Directory /workspace/34.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/35.otp_ctrl_alert_test.2449161500
Short name T504
Test name
Test status
Simulation time 132296757 ps
CPU time 1.89 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 240196 kb
Host smart-4a33fe3a-fd65-49b6-b673-08046acae74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449161500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2449161500
Directory /workspace/35.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_errs.1256707892
Short name T312
Test name
Test status
Simulation time 1354220551 ps
CPU time 38.47 seconds
Started Jul 03 07:16:34 PM PDT 24
Finished Jul 03 07:17:17 PM PDT 24
Peak memory 247256 kb
Host smart-3a4657a1-82f9-4f6b-b2cb-f8d4dc1e9687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256707892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.1256707892
Directory /workspace/35.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_dai_lock.148065592
Short name T406
Test name
Test status
Simulation time 1284098369 ps
CPU time 31.12 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:17:08 PM PDT 24
Peak memory 242328 kb
Host smart-60eb862d-24da-458a-86e7-20f6e678e23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148065592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.148065592
Directory /workspace/35.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/35.otp_ctrl_init_fail.1816242050
Short name T683
Test name
Test status
Simulation time 242092742 ps
CPU time 3.44 seconds
Started Jul 03 07:16:35 PM PDT 24
Finished Jul 03 07:16:43 PM PDT 24
Peak memory 242400 kb
Host smart-211f4586-f0d8-45b6-9278-74c1dd0268dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816242050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.1816242050
Directory /workspace/35.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/35.otp_ctrl_macro_errs.4258581762
Short name T811
Test name
Test status
Simulation time 9224884353 ps
CPU time 28.38 seconds
Started Jul 03 07:16:33 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 243480 kb
Host smart-5425eb27-f607-4421-9a4d-92e82d988269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258581762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.4258581762
Directory /workspace/35.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_key_req.3582210392
Short name T875
Test name
Test status
Simulation time 6954757230 ps
CPU time 55.24 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:17:45 PM PDT 24
Peak memory 243332 kb
Host smart-e6bec665-cce3-442a-946e-c443d2319600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582210392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3582210392
Directory /workspace/35.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_esc.1765573961
Short name T250
Test name
Test status
Simulation time 490221480 ps
CPU time 10.76 seconds
Started Jul 03 07:16:32 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 241932 kb
Host smart-06c9ffca-d1f7-450e-a64f-ed423e18b34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765573961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.1765573961
Directory /workspace/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/35.otp_ctrl_parallel_lc_req.2998489004
Short name T1152
Test name
Test status
Simulation time 1106475358 ps
CPU time 8.34 seconds
Started Jul 03 07:16:33 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 242572 kb
Host smart-ce23cecd-c2b4-4358-a97a-fce535696ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998489004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.2998489004
Directory /workspace/35.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/35.otp_ctrl_regwen.2129043253
Short name T378
Test name
Test status
Simulation time 4146062541 ps
CPU time 14.26 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:58 PM PDT 24
Peak memory 248784 kb
Host smart-edb58785-022c-4db0-8dfa-f4672099bb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2129043253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2129043253
Directory /workspace/35.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/35.otp_ctrl_smoke.327126387
Short name T456
Test name
Test status
Simulation time 430381666 ps
CPU time 11.35 seconds
Started Jul 03 07:16:34 PM PDT 24
Finished Jul 03 07:16:50 PM PDT 24
Peak memory 242080 kb
Host smart-771f59e5-3973-4f85-9ba9-b515fb662a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327126387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.327126387
Directory /workspace/35.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/35.otp_ctrl_stress_all.727307690
Short name T279
Test name
Test status
Simulation time 26114060579 ps
CPU time 277.24 seconds
Started Jul 03 07:16:36 PM PDT 24
Finished Jul 03 07:21:18 PM PDT 24
Peak memory 258600 kb
Host smart-8ba7ba83-2287-4d3f-84c5-3695b72ae43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727307690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.
727307690
Directory /workspace/35.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.otp_ctrl_test_access.3938635966
Short name T39
Test name
Test status
Simulation time 13896565501 ps
CPU time 29.26 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:17:18 PM PDT 24
Peak memory 243360 kb
Host smart-77d6de50-819f-488a-bde2-2c6101b7617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938635966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3938635966
Directory /workspace/35.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/36.otp_ctrl_alert_test.4090711805
Short name T805
Test name
Test status
Simulation time 202621805 ps
CPU time 2.25 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 240232 kb
Host smart-6dbfa941-1e48-4f3f-b73d-2b4586688c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090711805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.4090711805
Directory /workspace/36.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.otp_ctrl_check_fail.3914297819
Short name T121
Test name
Test status
Simulation time 506955903 ps
CPU time 8.12 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:16:50 PM PDT 24
Peak memory 242348 kb
Host smart-6702f0d3-a55b-4820-90c6-77ab80ea468c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914297819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.3914297819
Directory /workspace/36.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_errs.2730226184
Short name T1084
Test name
Test status
Simulation time 1568414393 ps
CPU time 44.34 seconds
Started Jul 03 07:16:37 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 249104 kb
Host smart-d614f8a3-7070-492a-be79-67448acdd841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730226184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.2730226184
Directory /workspace/36.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_dai_lock.580089551
Short name T1136
Test name
Test status
Simulation time 1369017454 ps
CPU time 17.4 seconds
Started Jul 03 07:16:36 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 242048 kb
Host smart-bcbba3d1-6c5a-40b9-883f-f2246a9052a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580089551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.580089551
Directory /workspace/36.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/36.otp_ctrl_init_fail.2441607492
Short name T956
Test name
Test status
Simulation time 488344500 ps
CPU time 3.03 seconds
Started Jul 03 07:16:36 PM PDT 24
Finished Jul 03 07:16:44 PM PDT 24
Peak memory 242564 kb
Host smart-87cc2514-002e-468f-9261-4acff6170e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441607492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2441607492
Directory /workspace/36.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/36.otp_ctrl_macro_errs.2217043945
Short name T517
Test name
Test status
Simulation time 2448829295 ps
CPU time 31.38 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:17:15 PM PDT 24
Peak memory 245964 kb
Host smart-56a892cd-0295-4335-a95a-98e68557c485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217043945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2217043945
Directory /workspace/36.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_key_req.4091233246
Short name T913
Test name
Test status
Simulation time 645405949 ps
CPU time 19.37 seconds
Started Jul 03 07:16:35 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 242684 kb
Host smart-6c9c94e7-8eda-4eda-b7ef-bce862c3d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091233246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.4091233246
Directory /workspace/36.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_esc.286974167
Short name T623
Test name
Test status
Simulation time 88776262 ps
CPU time 3.21 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:16:46 PM PDT 24
Peak memory 241960 kb
Host smart-3381f746-5c17-4f72-9e36-82de8bb9fb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286974167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.286974167
Directory /workspace/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/36.otp_ctrl_parallel_lc_req.1132927713
Short name T392
Test name
Test status
Simulation time 801501529 ps
CPU time 10.75 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:55 PM PDT 24
Peak memory 248692 kb
Host smart-95c47b55-d8f6-41a3-b5f6-4f647c8f14f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1132927713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.1132927713
Directory /workspace/36.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/36.otp_ctrl_regwen.1118496998
Short name T108
Test name
Test status
Simulation time 1672586384 ps
CPU time 5.47 seconds
Started Jul 03 07:16:37 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 241956 kb
Host smart-459b6381-7b08-4cfa-972d-a9c68b392004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118496998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.1118496998
Directory /workspace/36.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/36.otp_ctrl_smoke.1749372491
Short name T222
Test name
Test status
Simulation time 287240363 ps
CPU time 4.08 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 242156 kb
Host smart-3718e190-d7ff-4317-83db-8b7efc1494e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749372491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1749372491
Directory /workspace/36.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all.2875339868
Short name T876
Test name
Test status
Simulation time 11747895665 ps
CPU time 111.89 seconds
Started Jul 03 07:16:36 PM PDT 24
Finished Jul 03 07:18:32 PM PDT 24
Peak memory 259580 kb
Host smart-b5426618-2dcc-48a8-9f3e-8ca631e2e047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875339868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all
.2875339868
Directory /workspace/36.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2353757921
Short name T710
Test name
Test status
Simulation time 56393585978 ps
CPU time 376.14 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:23:06 PM PDT 24
Peak memory 298072 kb
Host smart-9d89f564-dbaa-46cb-8fa4-571694fe0b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353757921 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2353757921
Directory /workspace/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.otp_ctrl_test_access.527622861
Short name T564
Test name
Test status
Simulation time 94729908057 ps
CPU time 677.11 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:28:00 PM PDT 24
Peak memory 242148 kb
Host smart-ec8193bd-1993-4283-8dc9-3cd975adc80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527622861 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.527622861
Directory /workspace/36.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/37.otp_ctrl_alert_test.911147369
Short name T415
Test name
Test status
Simulation time 67248203 ps
CPU time 1.85 seconds
Started Jul 03 07:16:42 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 240088 kb
Host smart-1777ef36-ec87-4dc9-bc45-baf4a91d9bcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911147369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.911147369
Directory /workspace/37.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.otp_ctrl_check_fail.1209449284
Short name T930
Test name
Test status
Simulation time 394486107 ps
CPU time 8.81 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:53 PM PDT 24
Peak memory 242088 kb
Host smart-5cd01cce-4ab0-45d3-b17a-aad780095de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209449284 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1209449284
Directory /workspace/37.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_errs.3280057708
Short name T239
Test name
Test status
Simulation time 1167058833 ps
CPU time 29.67 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:17:12 PM PDT 24
Peak memory 241912 kb
Host smart-d5b8f0d7-390a-4940-9ccd-de0702ede366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280057708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.3280057708
Directory /workspace/37.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_dai_lock.1972260698
Short name T1043
Test name
Test status
Simulation time 829175413 ps
CPU time 9.7 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:54 PM PDT 24
Peak memory 242180 kb
Host smart-dfb1bc26-b766-4162-930f-2b9d21d5dc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972260698 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.1972260698
Directory /workspace/37.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/37.otp_ctrl_init_fail.3905012765
Short name T856
Test name
Test status
Simulation time 1813116521 ps
CPU time 4.64 seconds
Started Jul 03 07:16:38 PM PDT 24
Finished Jul 03 07:16:47 PM PDT 24
Peak memory 242364 kb
Host smart-dd6d38a6-2fb9-4eb3-94b6-68f64fcb1430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905012765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3905012765
Directory /workspace/37.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/37.otp_ctrl_macro_errs.568436983
Short name T207
Test name
Test status
Simulation time 8744966301 ps
CPU time 15.93 seconds
Started Jul 03 07:16:41 PM PDT 24
Finished Jul 03 07:17:01 PM PDT 24
Peak memory 243652 kb
Host smart-6095fecf-7b00-4c76-aebe-a6f9dfed2046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568436983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.568436983
Directory /workspace/37.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_key_req.419386768
Short name T689
Test name
Test status
Simulation time 202882657 ps
CPU time 3.8 seconds
Started Jul 03 07:16:42 PM PDT 24
Finished Jul 03 07:16:49 PM PDT 24
Peak memory 242700 kb
Host smart-3439c3c3-7d5d-4ea9-b594-e6376829baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419386768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.419386768
Directory /workspace/37.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_esc.1062388927
Short name T609
Test name
Test status
Simulation time 6568820080 ps
CPU time 15.81 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 242408 kb
Host smart-621e281c-9e23-4504-8964-6a0f92c4a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062388927 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.1062388927
Directory /workspace/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/37.otp_ctrl_parallel_lc_req.9763930
Short name T954
Test name
Test status
Simulation time 330370637 ps
CPU time 11.64 seconds
Started Jul 03 07:16:35 PM PDT 24
Finished Jul 03 07:16:52 PM PDT 24
Peak memory 242068 kb
Host smart-1c206ad6-41cf-46ad-9479-78190731a413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=9763930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.9763930
Directory /workspace/37.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/37.otp_ctrl_regwen.3857585726
Short name T712
Test name
Test status
Simulation time 587323377 ps
CPU time 10.92 seconds
Started Jul 03 07:16:39 PM PDT 24
Finished Jul 03 07:16:54 PM PDT 24
Peak memory 242100 kb
Host smart-7a457caf-2f79-4c03-bd96-b0f126507599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3857585726 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3857585726
Directory /workspace/37.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/37.otp_ctrl_smoke.858515632
Short name T855
Test name
Test status
Simulation time 3440702855 ps
CPU time 19.99 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:17:04 PM PDT 24
Peak memory 242072 kb
Host smart-f1a8a983-2c3e-4172-b703-5659c556838f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858515632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.858515632
Directory /workspace/37.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2641371334
Short name T961
Test name
Test status
Simulation time 134417387271 ps
CPU time 1875.74 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:48:04 PM PDT 24
Peak memory 293544 kb
Host smart-ffdb1f56-63b6-4ad8-b13b-bcde7e09f4ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641371334 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.2641371334
Directory /workspace/37.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.otp_ctrl_test_access.3461156898
Short name T225
Test name
Test status
Simulation time 1916350480 ps
CPU time 17.05 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 242196 kb
Host smart-7244791d-e37d-41b7-98ca-8ed67d5d8d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461156898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3461156898
Directory /workspace/37.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/38.otp_ctrl_alert_test.489624210
Short name T416
Test name
Test status
Simulation time 60531356 ps
CPU time 1.85 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:16:55 PM PDT 24
Peak memory 240344 kb
Host smart-9da6747e-d449-4843-8601-0b5f7681d029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489624210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.489624210
Directory /workspace/38.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.otp_ctrl_check_fail.3444210250
Short name T127
Test name
Test status
Simulation time 10258702268 ps
CPU time 20.62 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:17:08 PM PDT 24
Peak memory 242416 kb
Host smart-97360bb1-6967-409f-ac2c-2723f3129403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444210250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3444210250
Directory /workspace/38.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_errs.2454144168
Short name T361
Test name
Test status
Simulation time 3614839075 ps
CPU time 15.73 seconds
Started Jul 03 07:16:43 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 242080 kb
Host smart-86d65ca7-1f86-4d43-8234-ad80fa85f424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454144168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2454144168
Directory /workspace/38.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_dai_lock.790941198
Short name T893
Test name
Test status
Simulation time 1166472242 ps
CPU time 12.36 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:17:00 PM PDT 24
Peak memory 248748 kb
Host smart-b9266cfd-b334-4c6f-a45d-5a30a386f78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790941198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.790941198
Directory /workspace/38.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/38.otp_ctrl_init_fail.3513967635
Short name T664
Test name
Test status
Simulation time 453881604 ps
CPU time 3.7 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:48 PM PDT 24
Peak memory 242116 kb
Host smart-8a27f441-3648-42e1-b794-9747b671e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513967635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.3513967635
Directory /workspace/38.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/38.otp_ctrl_macro_errs.1913645433
Short name T1107
Test name
Test status
Simulation time 2307592055 ps
CPU time 19.02 seconds
Started Jul 03 07:16:49 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 248784 kb
Host smart-68acec98-e06e-41fb-aef5-8a34cf8e9031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913645433 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1913645433
Directory /workspace/38.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_key_req.594847875
Short name T613
Test name
Test status
Simulation time 380067749 ps
CPU time 12.41 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 248796 kb
Host smart-a4583864-c4de-4cd8-b1e6-01884c26de85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594847875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.594847875
Directory /workspace/38.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_esc.834623017
Short name T465
Test name
Test status
Simulation time 140953433 ps
CPU time 6.28 seconds
Started Jul 03 07:16:40 PM PDT 24
Finished Jul 03 07:16:50 PM PDT 24
Peak memory 241944 kb
Host smart-7dd93957-6273-45cb-a199-0e16b9b8adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834623017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.834623017
Directory /workspace/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/38.otp_ctrl_parallel_lc_req.810606890
Short name T793
Test name
Test status
Simulation time 2608213320 ps
CPU time 23.59 seconds
Started Jul 03 07:16:42 PM PDT 24
Finished Jul 03 07:17:10 PM PDT 24
Peak memory 248744 kb
Host smart-f6ed070a-d7b0-455c-a524-5bb7a098c06f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810606890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.810606890
Directory /workspace/38.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/38.otp_ctrl_regwen.3343508964
Short name T223
Test name
Test status
Simulation time 824116848 ps
CPU time 7.91 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:16:57 PM PDT 24
Peak memory 242408 kb
Host smart-806287ed-7df2-488f-8c53-793adbda2b3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343508964 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3343508964
Directory /workspace/38.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/38.otp_ctrl_smoke.2589966199
Short name T910
Test name
Test status
Simulation time 607179078 ps
CPU time 9.04 seconds
Started Jul 03 07:16:43 PM PDT 24
Finished Jul 03 07:16:56 PM PDT 24
Peak memory 242128 kb
Host smart-dcda313d-95ce-4bdc-88cf-bdfe6dc2456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589966199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.2589966199
Directory /workspace/38.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all.3959180837
Short name T1011
Test name
Test status
Simulation time 52027089475 ps
CPU time 202.82 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:20:10 PM PDT 24
Peak memory 257484 kb
Host smart-7f63961a-181e-4711-ac33-cada3077dfa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959180837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all
.3959180837
Directory /workspace/38.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.31493307
Short name T1162
Test name
Test status
Simulation time 866909773294 ps
CPU time 3412.18 seconds
Started Jul 03 07:16:48 PM PDT 24
Finished Jul 03 08:13:47 PM PDT 24
Peak memory 476224 kb
Host smart-1b98938a-46cc-461d-b97c-ea719719f712
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31493307 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.31493307
Directory /workspace/38.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.otp_ctrl_test_access.3344665924
Short name T396
Test name
Test status
Simulation time 6274102401 ps
CPU time 36.22 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 242120 kb
Host smart-2b6a376b-1146-4a60-bd7c-1a53bff6f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344665924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.3344665924
Directory /workspace/38.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/39.otp_ctrl_alert_test.2906261591
Short name T539
Test name
Test status
Simulation time 762777180 ps
CPU time 1.68 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:16:54 PM PDT 24
Peak memory 240188 kb
Host smart-e0d4e014-89b2-4f31-977f-b17efcd80de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906261591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.2906261591
Directory /workspace/39.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.otp_ctrl_check_fail.974040796
Short name T457
Test name
Test status
Simulation time 1158134096 ps
CPU time 12.03 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:17:03 PM PDT 24
Peak memory 242560 kb
Host smart-34467d03-11ba-4db9-83dc-8ae6e3136323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974040796 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.974040796
Directory /workspace/39.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_errs.2458084627
Short name T425
Test name
Test status
Simulation time 13614716332 ps
CPU time 40.57 seconds
Started Jul 03 07:16:49 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 244196 kb
Host smart-78504df7-c959-4a22-9819-9df60b9576d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458084627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.2458084627
Directory /workspace/39.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_dai_lock.2944390118
Short name T433
Test name
Test status
Simulation time 419955631 ps
CPU time 4.63 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:16:56 PM PDT 24
Peak memory 241912 kb
Host smart-4686f6b6-d636-40ad-84da-a8734a8ca291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944390118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.2944390118
Directory /workspace/39.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/39.otp_ctrl_init_fail.3999047995
Short name T470
Test name
Test status
Simulation time 479094638 ps
CPU time 3.54 seconds
Started Jul 03 07:16:49 PM PDT 24
Finished Jul 03 07:16:58 PM PDT 24
Peak memory 242292 kb
Host smart-6cfbec2a-0d5b-4651-a945-1f512b9c3eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999047995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.3999047995
Directory /workspace/39.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/39.otp_ctrl_macro_errs.201248724
Short name T546
Test name
Test status
Simulation time 585745519 ps
CPU time 5.29 seconds
Started Jul 03 07:16:44 PM PDT 24
Finished Jul 03 07:16:53 PM PDT 24
Peak memory 242408 kb
Host smart-da558829-019b-4c0b-af17-e242ff9cf536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201248724 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.201248724
Directory /workspace/39.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_key_req.2994898905
Short name T183
Test name
Test status
Simulation time 557207847 ps
CPU time 21.1 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 242092 kb
Host smart-d83d36f2-2f73-4832-bc71-897ab09ca237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994898905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.2994898905
Directory /workspace/39.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_esc.3101302840
Short name T789
Test name
Test status
Simulation time 837806960 ps
CPU time 13.81 seconds
Started Jul 03 07:16:48 PM PDT 24
Finished Jul 03 07:17:08 PM PDT 24
Peak memory 242220 kb
Host smart-d678d46f-152c-4d67-b946-93748266d624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101302840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.3101302840
Directory /workspace/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/39.otp_ctrl_parallel_lc_req.3539165766
Short name T100
Test name
Test status
Simulation time 329006112 ps
CPU time 11.95 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:17:03 PM PDT 24
Peak memory 242272 kb
Host smart-bad0f3e0-a6ac-4c47-bf55-d2832f473dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3539165766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.3539165766
Directory /workspace/39.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/39.otp_ctrl_regwen.3779281503
Short name T831
Test name
Test status
Simulation time 180718908 ps
CPU time 4.76 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:16:56 PM PDT 24
Peak memory 242128 kb
Host smart-57fed138-685b-403f-ac80-e950f04edf35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779281503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.3779281503
Directory /workspace/39.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/39.otp_ctrl_smoke.1623518960
Short name T177
Test name
Test status
Simulation time 365346610 ps
CPU time 5.47 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:16:58 PM PDT 24
Peak memory 242088 kb
Host smart-be5df3e4-4220-4084-a07a-dd00f7b9d637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623518960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1623518960
Directory /workspace/39.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all.2606372493
Short name T1060
Test name
Test status
Simulation time 25721535693 ps
CPU time 91.16 seconds
Started Jul 03 07:16:49 PM PDT 24
Finished Jul 03 07:18:26 PM PDT 24
Peak memory 245580 kb
Host smart-5b7b6789-e966-4be3-8026-319e66b6e0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606372493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all
.2606372493
Directory /workspace/39.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3742685154
Short name T843
Test name
Test status
Simulation time 457225599649 ps
CPU time 1356.72 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:39:26 PM PDT 24
Peak memory 354620 kb
Host smart-92477e59-a607-4f83-83c1-6292b643c7de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742685154 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3742685154
Directory /workspace/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.otp_ctrl_test_access.1942779344
Short name T708
Test name
Test status
Simulation time 1187680254 ps
CPU time 21.37 seconds
Started Jul 03 07:16:46 PM PDT 24
Finished Jul 03 07:17:12 PM PDT 24
Peak memory 242512 kb
Host smart-14e2e17d-8df0-4142-8acd-51f984bdc588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942779344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1942779344
Directory /workspace/39.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/4.otp_ctrl_alert_test.3117391067
Short name T721
Test name
Test status
Simulation time 162352842 ps
CPU time 1.72 seconds
Started Jul 03 07:15:09 PM PDT 24
Finished Jul 03 07:15:15 PM PDT 24
Peak memory 240568 kb
Host smart-204a47ef-1684-42ca-81b3-630d7b0bbf3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117391067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3117391067
Directory /workspace/4.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.otp_ctrl_background_chks.372073544
Short name T491
Test name
Test status
Simulation time 5928801942 ps
CPU time 17.91 seconds
Started Jul 03 07:15:00 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 242724 kb
Host smart-5874b658-37bf-473e-a6ec-53caa7bc3b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372073544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.372073544
Directory /workspace/4.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/4.otp_ctrl_check_fail.3137813874
Short name T116
Test name
Test status
Simulation time 624062174 ps
CPU time 15.03 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 242288 kb
Host smart-e89c78a0-321d-4249-8bb0-4aa0a630626e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137813874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.3137813874
Directory /workspace/4.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_errs.2076959521
Short name T492
Test name
Test status
Simulation time 3377832353 ps
CPU time 15.46 seconds
Started Jul 03 07:14:59 PM PDT 24
Finished Jul 03 07:15:19 PM PDT 24
Peak memory 241888 kb
Host smart-716ccb53-9188-4b34-89af-022b4a0acd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076959521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2076959521
Directory /workspace/4.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_dai_lock.673674441
Short name T918
Test name
Test status
Simulation time 708944502 ps
CPU time 12.32 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:22 PM PDT 24
Peak memory 242608 kb
Host smart-ef2bf696-8c96-4827-b066-cd0d5689fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673674441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.673674441
Directory /workspace/4.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/4.otp_ctrl_init_fail.535814353
Short name T1033
Test name
Test status
Simulation time 2422698421 ps
CPU time 4.37 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:06 PM PDT 24
Peak memory 242508 kb
Host smart-fcfc40bb-d693-4251-9f04-8c9aa4bfd416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535814353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.535814353
Directory /workspace/4.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/4.otp_ctrl_macro_errs.4276423388
Short name T1065
Test name
Test status
Simulation time 777556503 ps
CPU time 26.11 seconds
Started Jul 03 07:15:02 PM PDT 24
Finished Jul 03 07:15:34 PM PDT 24
Peak memory 245384 kb
Host smart-04ccbac7-a0f3-44ef-8518-0ca43526d864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276423388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.4276423388
Directory /workspace/4.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_key_req.3207336815
Short name T290
Test name
Test status
Simulation time 724369081 ps
CPU time 12.33 seconds
Started Jul 03 07:15:02 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 242408 kb
Host smart-053f08bc-2b1a-4256-83f1-5a149d397e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207336815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3207336815
Directory /workspace/4.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_esc.465691062
Short name T293
Test name
Test status
Simulation time 241744489 ps
CPU time 12.03 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 241952 kb
Host smart-1971fff7-78c3-4e07-ae52-9a73e14777fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465691062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.465691062
Directory /workspace/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/4.otp_ctrl_parallel_lc_req.1396640655
Short name T795
Test name
Test status
Simulation time 803911310 ps
CPU time 18.81 seconds
Started Jul 03 07:14:58 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 241788 kb
Host smart-e41197ba-9c40-44bc-a4b6-9038568520b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1396640655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1396640655
Directory /workspace/4.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/4.otp_ctrl_regwen.1076599008
Short name T388
Test name
Test status
Simulation time 338331392 ps
CPU time 4.91 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 242328 kb
Host smart-2def21d1-1369-43bf-9f08-b34dfdade0e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076599008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1076599008
Directory /workspace/4.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/4.otp_ctrl_sec_cm.1130014148
Short name T21
Test name
Test status
Simulation time 23374521452 ps
CPU time 207.49 seconds
Started Jul 03 07:15:09 PM PDT 24
Finished Jul 03 07:18:41 PM PDT 24
Peak memory 264416 kb
Host smart-8674136a-a0ab-49ab-a745-ff50e4371b68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130014148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.1130014148
Directory /workspace/4.otp_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.otp_ctrl_smoke.915395772
Short name T1053
Test name
Test status
Simulation time 1362192836 ps
CPU time 12.76 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 242216 kb
Host smart-85957732-8811-4111-b8d7-12ee1e252338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915395772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.915395772
Directory /workspace/4.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all.1904426486
Short name T1078
Test name
Test status
Simulation time 3696127970 ps
CPU time 149.37 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:17:39 PM PDT 24
Peak memory 256864 kb
Host smart-9b432c1a-e331-4904-b6c6-d2924210c780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904426486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.
1904426486
Directory /workspace/4.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.4228252160
Short name T348
Test name
Test status
Simulation time 159774405626 ps
CPU time 1073.49 seconds
Started Jul 03 07:15:03 PM PDT 24
Finished Jul 03 07:33:02 PM PDT 24
Peak memory 312228 kb
Host smart-6504b4f4-4e3d-4ebc-bf6c-e3b155cc487e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228252160 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.4228252160
Directory /workspace/4.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.otp_ctrl_test_access.1274487315
Short name T484
Test name
Test status
Simulation time 419518722 ps
CPU time 11.46 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:22 PM PDT 24
Peak memory 242136 kb
Host smart-e50b5997-89d0-4e60-9c00-039a24c130f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274487315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1274487315
Directory /workspace/4.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/40.otp_ctrl_alert_test.2201970336
Short name T749
Test name
Test status
Simulation time 170188962 ps
CPU time 1.97 seconds
Started Jul 03 07:16:50 PM PDT 24
Finished Jul 03 07:16:59 PM PDT 24
Peak memory 240576 kb
Host smart-d3bab8af-9ba9-43c7-a86f-074fe55927f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201970336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2201970336
Directory /workspace/40.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_errs.3061689037
Short name T763
Test name
Test status
Simulation time 11843536502 ps
CPU time 19.89 seconds
Started Jul 03 07:16:52 PM PDT 24
Finished Jul 03 07:17:18 PM PDT 24
Peak memory 242220 kb
Host smart-dfb37fd9-0db6-4539-b65f-ce5a1e9580e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061689037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3061689037
Directory /workspace/40.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_dai_lock.2181124682
Short name T616
Test name
Test status
Simulation time 1126382279 ps
CPU time 19.84 seconds
Started Jul 03 07:16:48 PM PDT 24
Finished Jul 03 07:17:13 PM PDT 24
Peak memory 242580 kb
Host smart-c07610ef-0e77-4daf-8038-75c9325c8f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181124682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.2181124682
Directory /workspace/40.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/40.otp_ctrl_init_fail.1712123862
Short name T636
Test name
Test status
Simulation time 124211459 ps
CPU time 4.03 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:16:55 PM PDT 24
Peak memory 242084 kb
Host smart-c4465080-fd3b-4bb9-9a8a-98e5878f7549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712123862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1712123862
Directory /workspace/40.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/40.otp_ctrl_macro_errs.1596507075
Short name T165
Test name
Test status
Simulation time 2162209408 ps
CPU time 36.08 seconds
Started Jul 03 07:16:51 PM PDT 24
Finished Jul 03 07:17:34 PM PDT 24
Peak memory 247408 kb
Host smart-945f7da7-03e2-452b-85d3-b9b8b448b6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596507075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1596507075
Directory /workspace/40.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_key_req.3849039242
Short name T971
Test name
Test status
Simulation time 2815888704 ps
CPU time 20.05 seconds
Started Jul 03 07:16:52 PM PDT 24
Finished Jul 03 07:17:19 PM PDT 24
Peak memory 248824 kb
Host smart-fc64dc28-86a7-4743-b87f-39273c6f6f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849039242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3849039242
Directory /workspace/40.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_esc.3885702582
Short name T1173
Test name
Test status
Simulation time 3693695310 ps
CPU time 12.5 seconds
Started Jul 03 07:16:49 PM PDT 24
Finished Jul 03 07:17:07 PM PDT 24
Peak memory 242240 kb
Host smart-9e93814b-20e6-4585-8151-c78981084da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885702582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3885702582
Directory /workspace/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/40.otp_ctrl_parallel_lc_req.3860250781
Short name T848
Test name
Test status
Simulation time 4319396270 ps
CPU time 11.61 seconds
Started Jul 03 07:16:47 PM PDT 24
Finished Jul 03 07:17:04 PM PDT 24
Peak memory 242176 kb
Host smart-4c5a34c8-56d3-4ebe-ae5d-c7ea7a33b1dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860250781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.3860250781
Directory /workspace/40.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/40.otp_ctrl_regwen.3228828329
Short name T794
Test name
Test status
Simulation time 2388118709 ps
CPU time 6.43 seconds
Started Jul 03 07:16:50 PM PDT 24
Finished Jul 03 07:17:03 PM PDT 24
Peak memory 242184 kb
Host smart-de21e6fa-219f-4a23-b2d0-3f42a5ecc30a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228828329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3228828329
Directory /workspace/40.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/40.otp_ctrl_smoke.3572681515
Short name T1101
Test name
Test status
Simulation time 173780878 ps
CPU time 2.61 seconds
Started Jul 03 07:16:45 PM PDT 24
Finished Jul 03 07:16:52 PM PDT 24
Peak memory 242248 kb
Host smart-f26d1ef5-4465-4d56-8de3-986580fb05bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572681515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3572681515
Directory /workspace/40.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all.2967513932
Short name T1172
Test name
Test status
Simulation time 8429548037 ps
CPU time 157.86 seconds
Started Jul 03 07:16:51 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 248864 kb
Host smart-66c754f9-039a-41e8-9994-93d57b69ad94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967513932 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all
.2967513932
Directory /workspace/40.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.3937371078
Short name T762
Test name
Test status
Simulation time 709307833167 ps
CPU time 1988.23 seconds
Started Jul 03 07:16:52 PM PDT 24
Finished Jul 03 07:50:08 PM PDT 24
Peak memory 398132 kb
Host smart-704e3811-8828-4dc2-aaad-9ccd62a79bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937371078 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.3937371078
Directory /workspace/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.otp_ctrl_test_access.2962476875
Short name T787
Test name
Test status
Simulation time 1217354010 ps
CPU time 13.48 seconds
Started Jul 03 07:16:51 PM PDT 24
Finished Jul 03 07:17:12 PM PDT 24
Peak memory 248720 kb
Host smart-d118acab-b19c-4c41-8484-955e4cb763ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962476875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2962476875
Directory /workspace/40.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/41.otp_ctrl_alert_test.547867100
Short name T596
Test name
Test status
Simulation time 836267320 ps
CPU time 2.46 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:11 PM PDT 24
Peak memory 240136 kb
Host smart-e65f0315-4cb8-45cf-a48f-4cff05148fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547867100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.547867100
Directory /workspace/41.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.otp_ctrl_check_fail.3218503803
Short name T739
Test name
Test status
Simulation time 864863936 ps
CPU time 6.7 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 242632 kb
Host smart-cec8fd82-2453-4fb4-9dde-6bccf26dd38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218503803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3218503803
Directory /workspace/41.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_errs.3365529693
Short name T429
Test name
Test status
Simulation time 11807394782 ps
CPU time 26.8 seconds
Started Jul 03 07:16:57 PM PDT 24
Finished Jul 03 07:17:30 PM PDT 24
Peak memory 242280 kb
Host smart-d93bf312-6d2d-41bf-aa7d-08717ed75a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365529693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.3365529693
Directory /workspace/41.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_dai_lock.2721269121
Short name T350
Test name
Test status
Simulation time 370949797 ps
CPU time 5.03 seconds
Started Jul 03 07:16:53 PM PDT 24
Finished Jul 03 07:17:05 PM PDT 24
Peak memory 242292 kb
Host smart-95a64e50-bd90-41fc-9c6e-d7ba3bad7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721269121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2721269121
Directory /workspace/41.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/41.otp_ctrl_init_fail.3889216009
Short name T437
Test name
Test status
Simulation time 1909964540 ps
CPU time 5.38 seconds
Started Jul 03 07:16:51 PM PDT 24
Finished Jul 03 07:17:02 PM PDT 24
Peak memory 241884 kb
Host smart-9c16c9c4-7e15-426c-b1e4-7c40f0e07e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889216009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3889216009
Directory /workspace/41.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/41.otp_ctrl_macro_errs.2933506790
Short name T1176
Test name
Test status
Simulation time 419044482 ps
CPU time 5.13 seconds
Started Jul 03 07:16:56 PM PDT 24
Finished Jul 03 07:17:08 PM PDT 24
Peak memory 242200 kb
Host smart-db0e7d6e-cced-485d-b8f9-c054971090c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933506790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2933506790
Directory /workspace/41.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_key_req.3717273332
Short name T1117
Test name
Test status
Simulation time 1330371715 ps
CPU time 16.84 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 242172 kb
Host smart-1c6f7be8-89ac-47c0-980b-ebbb4c964039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717273332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3717273332
Directory /workspace/41.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_esc.3596212019
Short name T991
Test name
Test status
Simulation time 307099328 ps
CPU time 8.08 seconds
Started Jul 03 07:16:54 PM PDT 24
Finished Jul 03 07:17:08 PM PDT 24
Peak memory 241780 kb
Host smart-b9d18631-1a08-4e7f-ba2a-e7941e5ef304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596212019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.3596212019
Directory /workspace/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/41.otp_ctrl_parallel_lc_req.2883996083
Short name T104
Test name
Test status
Simulation time 511572301 ps
CPU time 9.96 seconds
Started Jul 03 07:16:51 PM PDT 24
Finished Jul 03 07:17:07 PM PDT 24
Peak memory 242192 kb
Host smart-3866336a-8d70-4337-9461-8139e4bb5bab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883996083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2883996083
Directory /workspace/41.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/41.otp_ctrl_regwen.1994463440
Short name T637
Test name
Test status
Simulation time 455273521 ps
CPU time 4.53 seconds
Started Jul 03 07:16:55 PM PDT 24
Finished Jul 03 07:17:07 PM PDT 24
Peak memory 241964 kb
Host smart-6398f99f-8d10-4a76-9808-ce6e684e5430
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994463440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1994463440
Directory /workspace/41.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/41.otp_ctrl_smoke.1178210777
Short name T441
Test name
Test status
Simulation time 857631724 ps
CPU time 9.18 seconds
Started Jul 03 07:16:50 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 242488 kb
Host smart-8295d953-6527-4977-8254-10e7a948af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178210777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.1178210777
Directory /workspace/41.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/41.otp_ctrl_stress_all.3931570647
Short name T756
Test name
Test status
Simulation time 6147310967 ps
CPU time 47.64 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:54 PM PDT 24
Peak memory 245304 kb
Host smart-b2fef276-3ab3-4683-8a30-15e375a0f209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931570647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all
.3931570647
Directory /workspace/41.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.otp_ctrl_test_access.1708022456
Short name T580
Test name
Test status
Simulation time 353195222 ps
CPU time 4.8 seconds
Started Jul 03 07:16:55 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 248680 kb
Host smart-871379a1-8660-4cf5-847d-a2c5e4cb8444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708022456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.1708022456
Directory /workspace/41.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/42.otp_ctrl_alert_test.2053604395
Short name T420
Test name
Test status
Simulation time 920348199 ps
CPU time 2.12 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:17:13 PM PDT 24
Peak memory 240124 kb
Host smart-fd6910e7-d383-4655-aee5-de3f4c0f911b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053604395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.2053604395
Directory /workspace/42.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.otp_ctrl_check_fail.331783864
Short name T919
Test name
Test status
Simulation time 2060485856 ps
CPU time 18.83 seconds
Started Jul 03 07:16:56 PM PDT 24
Finished Jul 03 07:17:21 PM PDT 24
Peak memory 242404 kb
Host smart-3ffd66a9-8d9b-4cd3-b357-83fba22c3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331783864 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.331783864
Directory /workspace/42.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_errs.3567800021
Short name T752
Test name
Test status
Simulation time 9723423387 ps
CPU time 31.96 seconds
Started Jul 03 07:16:55 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 242452 kb
Host smart-c2219119-3c08-4b28-bdc4-67e3adc24436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567800021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.3567800021
Directory /workspace/42.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/42.otp_ctrl_dai_lock.3384940720
Short name T790
Test name
Test status
Simulation time 98682321 ps
CPU time 3.43 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:09 PM PDT 24
Peak memory 241936 kb
Host smart-44cbbfca-055c-4f0f-b099-29d089e7df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384940720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3384940720
Directory /workspace/42.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_key_req.2218091014
Short name T730
Test name
Test status
Simulation time 1712591348 ps
CPU time 33.73 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 243504 kb
Host smart-9b67bc8a-9c4d-4de3-a63c-b7fa795d316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218091014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.2218091014
Directory /workspace/42.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_esc.646884114
Short name T734
Test name
Test status
Simulation time 428138762 ps
CPU time 7.64 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:16 PM PDT 24
Peak memory 242044 kb
Host smart-f39d141c-f875-4ca9-acad-dbe90f09b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646884114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.646884114
Directory /workspace/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/42.otp_ctrl_parallel_lc_req.1243162519
Short name T493
Test name
Test status
Simulation time 200530993 ps
CPU time 5.94 seconds
Started Jul 03 07:16:56 PM PDT 24
Finished Jul 03 07:17:09 PM PDT 24
Peak memory 242184 kb
Host smart-40fc60ec-2d6e-41b8-8faf-30d1a0da33dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243162519 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1243162519
Directory /workspace/42.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/42.otp_ctrl_regwen.3635890792
Short name T377
Test name
Test status
Simulation time 183287943 ps
CPU time 4.6 seconds
Started Jul 03 07:16:55 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 242100 kb
Host smart-eb28f19d-fd6b-4ec0-a916-008a0d79b839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635890792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.3635890792
Directory /workspace/42.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/42.otp_ctrl_smoke.2511594734
Short name T671
Test name
Test status
Simulation time 134792956 ps
CPU time 5.02 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:13 PM PDT 24
Peak memory 248076 kb
Host smart-bfdacba6-68e6-45fa-b565-c4068b7ba9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511594734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.2511594734
Directory /workspace/42.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all.1561501839
Short name T184
Test name
Test status
Simulation time 19891856375 ps
CPU time 171.61 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:19:56 PM PDT 24
Peak memory 262748 kb
Host smart-1e395e6d-b59d-4343-b0c4-eb2c9d6c5497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561501839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all
.1561501839
Directory /workspace/42.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.3539738620
Short name T861
Test name
Test status
Simulation time 25574726686 ps
CPU time 621.89 seconds
Started Jul 03 07:17:01 PM PDT 24
Finished Jul 03 07:27:28 PM PDT 24
Peak memory 292300 kb
Host smart-3d25d1d5-77a9-471b-a250-ed12c79ee0dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539738620 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.3539738620
Directory /workspace/42.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.otp_ctrl_test_access.3609754196
Short name T889
Test name
Test status
Simulation time 14444468134 ps
CPU time 49.68 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:54 PM PDT 24
Peak memory 242416 kb
Host smart-b74f3bd4-8fb3-40c2-a5bf-f7b55906ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609754196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3609754196
Directory /workspace/42.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/43.otp_ctrl_alert_test.143317164
Short name T449
Test name
Test status
Simulation time 252045526 ps
CPU time 2.27 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:06 PM PDT 24
Peak memory 240128 kb
Host smart-aab9267d-4f4e-45e9-9486-5afafc866a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143317164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.143317164
Directory /workspace/43.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_errs.3998471918
Short name T1183
Test name
Test status
Simulation time 256507140 ps
CPU time 14.86 seconds
Started Jul 03 07:17:01 PM PDT 24
Finished Jul 03 07:17:21 PM PDT 24
Peak memory 242284 kb
Host smart-bea1a0ab-cb78-48d7-a481-3f748c504ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998471918 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.3998471918
Directory /workspace/43.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_dai_lock.1575770086
Short name T644
Test name
Test status
Simulation time 1704695898 ps
CPU time 18.42 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 242076 kb
Host smart-ca852072-24cf-4644-aad9-0c547359caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575770086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.1575770086
Directory /workspace/43.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/43.otp_ctrl_init_fail.4070897005
Short name T648
Test name
Test status
Simulation time 279127346 ps
CPU time 4.31 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:09 PM PDT 24
Peak memory 242120 kb
Host smart-e7cef873-6dba-4ff1-b9f4-82aa91312ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070897005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.4070897005
Directory /workspace/43.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/43.otp_ctrl_macro_errs.1655071013
Short name T166
Test name
Test status
Simulation time 7768795862 ps
CPU time 33.77 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:38 PM PDT 24
Peak memory 248828 kb
Host smart-7db68930-49b9-4c0d-9c40-af2fc1f301d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655071013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.1655071013
Directory /workspace/43.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_key_req.995482794
Short name T819
Test name
Test status
Simulation time 3449314058 ps
CPU time 24.82 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 242360 kb
Host smart-ead52539-8900-4a1f-8998-7b155c8e03ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995482794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.995482794
Directory /workspace/43.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_esc.3545806176
Short name T586
Test name
Test status
Simulation time 354685562 ps
CPU time 7.85 seconds
Started Jul 03 07:17:01 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 241768 kb
Host smart-41ac8456-7862-44b4-aa6d-a71c9d2c0656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545806176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3545806176
Directory /workspace/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/43.otp_ctrl_parallel_lc_req.1129403481
Short name T1158
Test name
Test status
Simulation time 1121681717 ps
CPU time 15.06 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:20 PM PDT 24
Peak memory 242020 kb
Host smart-3fd19936-f006-4aba-93b6-86ffbad73853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129403481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.1129403481
Directory /workspace/43.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/43.otp_ctrl_regwen.1243078581
Short name T1037
Test name
Test status
Simulation time 1298416336 ps
CPU time 12.56 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:20 PM PDT 24
Peak memory 242228 kb
Host smart-fc062185-9f31-4a2b-88cd-7a7cf3cabb65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1243078581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.1243078581
Directory /workspace/43.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/43.otp_ctrl_smoke.1407787703
Short name T754
Test name
Test status
Simulation time 200070872 ps
CPU time 4.79 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:09 PM PDT 24
Peak memory 241948 kb
Host smart-d7f2affc-84ae-4816-a253-69cdeefb6380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407787703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.1407787703
Directory /workspace/43.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/43.otp_ctrl_stress_all.535014381
Short name T240
Test name
Test status
Simulation time 6430027060 ps
CPU time 88.31 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:18:40 PM PDT 24
Peak memory 250848 kb
Host smart-6261ef94-7929-4d30-b00c-617532840e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535014381 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.
535014381
Directory /workspace/43.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.otp_ctrl_test_access.284639803
Short name T849
Test name
Test status
Simulation time 910199089 ps
CPU time 15.19 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:17:25 PM PDT 24
Peak memory 242420 kb
Host smart-33cbd456-eea6-41b9-ac61-ef0a6435999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284639803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.284639803
Directory /workspace/43.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/44.otp_ctrl_alert_test.614609966
Short name T803
Test name
Test status
Simulation time 213784824 ps
CPU time 2.37 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 240404 kb
Host smart-51ac00af-ab32-480f-8779-d247fc1469f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614609966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.614609966
Directory /workspace/44.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.otp_ctrl_check_fail.864594546
Short name T40
Test name
Test status
Simulation time 3994860067 ps
CPU time 22.19 seconds
Started Jul 03 07:17:02 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 244624 kb
Host smart-3116be22-dcd3-4153-85e2-fd1906215b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864594546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.864594546
Directory /workspace/44.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_errs.625564021
Short name T957
Test name
Test status
Simulation time 1642175020 ps
CPU time 23.27 seconds
Started Jul 03 07:17:02 PM PDT 24
Finished Jul 03 07:17:31 PM PDT 24
Peak memory 242036 kb
Host smart-be65bea8-52b4-4f89-aebe-9d4edfee1e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625564021 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.625564021
Directory /workspace/44.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_dai_lock.3401733383
Short name T595
Test name
Test status
Simulation time 385609164 ps
CPU time 8.67 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:18 PM PDT 24
Peak memory 241956 kb
Host smart-42fa4d38-5a97-4f05-af27-06d2c98b5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401733383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3401733383
Directory /workspace/44.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/44.otp_ctrl_init_fail.1985267484
Short name T565
Test name
Test status
Simulation time 250879492 ps
CPU time 4.09 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 242148 kb
Host smart-95d78b80-4cd5-48be-8663-35b727daa251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985267484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.1985267484
Directory /workspace/44.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/44.otp_ctrl_macro_errs.3123385810
Short name T208
Test name
Test status
Simulation time 2397842044 ps
CPU time 32.59 seconds
Started Jul 03 07:17:02 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 245700 kb
Host smart-934d080a-e47a-4f32-9f58-8417f1e07418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123385810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3123385810
Directory /workspace/44.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_key_req.2146310891
Short name T28
Test name
Test status
Simulation time 1212753214 ps
CPU time 32.85 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:45 PM PDT 24
Peak memory 242496 kb
Host smart-3b090058-4551-4c98-96fd-d39d59ec2225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146310891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2146310891
Directory /workspace/44.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_esc.1624418005
Short name T1027
Test name
Test status
Simulation time 194660299 ps
CPU time 3.86 seconds
Started Jul 03 07:17:00 PM PDT 24
Finished Jul 03 07:17:09 PM PDT 24
Peak memory 241960 kb
Host smart-ffeced46-2df5-4549-98f7-21f4e674a57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624418005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1624418005
Directory /workspace/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/44.otp_ctrl_parallel_lc_req.3939200686
Short name T836
Test name
Test status
Simulation time 1699608853 ps
CPU time 22.38 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:17:37 PM PDT 24
Peak memory 242112 kb
Host smart-265632ae-6b76-4ed0-a23a-6e7fc6ac7c2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3939200686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.3939200686
Directory /workspace/44.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/44.otp_ctrl_regwen.2120100076
Short name T1002
Test name
Test status
Simulation time 592241097 ps
CPU time 9.5 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:17:23 PM PDT 24
Peak memory 242052 kb
Host smart-821986ca-e799-43a9-b03e-3f6740bfc9d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120100076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.2120100076
Directory /workspace/44.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/44.otp_ctrl_smoke.1534756526
Short name T1194
Test name
Test status
Simulation time 6174883178 ps
CPU time 47.71 seconds
Started Jul 03 07:16:59 PM PDT 24
Finished Jul 03 07:17:52 PM PDT 24
Peak memory 242240 kb
Host smart-daec5f0a-852d-40d7-9c43-dac13a142e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534756526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1534756526
Directory /workspace/44.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.3601815523
Short name T283
Test name
Test status
Simulation time 483049404740 ps
CPU time 1013.2 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:34:03 PM PDT 24
Peak memory 265368 kb
Host smart-98efa9a1-f134-484d-a580-2e822e9898fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601815523 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.3601815523
Directory /workspace/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.otp_ctrl_test_access.4237827511
Short name T1142
Test name
Test status
Simulation time 399366915 ps
CPU time 3.26 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:15 PM PDT 24
Peak memory 246984 kb
Host smart-62d129e3-d489-46a1-9288-75eb3222b8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237827511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.4237827511
Directory /workspace/44.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/45.otp_ctrl_alert_test.3416913886
Short name T738
Test name
Test status
Simulation time 144872680 ps
CPU time 2.29 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:17:13 PM PDT 24
Peak memory 240164 kb
Host smart-0f3b86b9-e434-4062-aeb0-f46407253f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416913886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3416913886
Directory /workspace/45.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.otp_ctrl_check_fail.1793910727
Short name T784
Test name
Test status
Simulation time 1757810508 ps
CPU time 20.08 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:17:34 PM PDT 24
Peak memory 242296 kb
Host smart-92637fa0-6b83-4116-8f2c-a08ddce660df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793910727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1793910727
Directory /workspace/45.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_errs.3982950326
Short name T526
Test name
Test status
Simulation time 620967184 ps
CPU time 14.71 seconds
Started Jul 03 07:17:08 PM PDT 24
Finished Jul 03 07:17:31 PM PDT 24
Peak memory 242144 kb
Host smart-15a5fc05-9632-4437-a725-1ef3dfdb0ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982950326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.3982950326
Directory /workspace/45.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_dai_lock.3416895220
Short name T929
Test name
Test status
Simulation time 1459600033 ps
CPU time 32.05 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 242420 kb
Host smart-f654fe08-c6c1-4ce7-a6ac-8a66b65628fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416895220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3416895220
Directory /workspace/45.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/45.otp_ctrl_init_fail.1807668584
Short name T1009
Test name
Test status
Simulation time 123939649 ps
CPU time 3.35 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:23 PM PDT 24
Peak memory 242388 kb
Host smart-0548bcc6-75c8-48dc-b180-8f68302975a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807668584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1807668584
Directory /workspace/45.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/45.otp_ctrl_macro_errs.2947536319
Short name T660
Test name
Test status
Simulation time 4265814406 ps
CPU time 12 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 243988 kb
Host smart-a640055c-8be4-4e8f-b62c-403612f81008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947536319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.2947536319
Directory /workspace/45.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_key_req.3321204413
Short name T668
Test name
Test status
Simulation time 2025796258 ps
CPU time 12.68 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:17:23 PM PDT 24
Peak memory 242300 kb
Host smart-1cea754b-d724-44cc-8394-bf790b6e062d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321204413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.3321204413
Directory /workspace/45.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_esc.249170107
Short name T141
Test name
Test status
Simulation time 587200439 ps
CPU time 5.55 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:18 PM PDT 24
Peak memory 241880 kb
Host smart-ea7c291f-037b-4cbd-a072-1d51c25f3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249170107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.249170107
Directory /workspace/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/45.otp_ctrl_parallel_lc_req.1356730085
Short name T535
Test name
Test status
Simulation time 204401322 ps
CPU time 5.18 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:17 PM PDT 24
Peak memory 241984 kb
Host smart-1df1c6c6-6c7e-4d22-8676-5f8fff366298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356730085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.1356730085
Directory /workspace/45.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/45.otp_ctrl_regwen.325937714
Short name T975
Test name
Test status
Simulation time 133154810 ps
CPU time 4.31 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:23 PM PDT 24
Peak memory 242084 kb
Host smart-1b61c7ac-d4dc-477d-9ac7-dfdd385af742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325937714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.325937714
Directory /workspace/45.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/45.otp_ctrl_smoke.2607141410
Short name T1167
Test name
Test status
Simulation time 344997188 ps
CPU time 11.71 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:17:23 PM PDT 24
Peak memory 242276 kb
Host smart-7f0c86b0-f6f4-4074-be99-aa38e203fd3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607141410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.2607141410
Directory /workspace/45.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all.4069013609
Short name T770
Test name
Test status
Simulation time 3928447472 ps
CPU time 112.32 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:19:03 PM PDT 24
Peak memory 257212 kb
Host smart-7f4a8e12-9f29-4129-a021-de9d8fe98546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069013609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all
.4069013609
Directory /workspace/45.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2485102992
Short name T1184
Test name
Test status
Simulation time 41563360469 ps
CPU time 604.09 seconds
Started Jul 03 07:17:04 PM PDT 24
Finished Jul 03 07:27:14 PM PDT 24
Peak memory 271840 kb
Host smart-8c678f3c-ac18-46a1-a5e5-1b76459e3813
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485102992 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.2485102992
Directory /workspace/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.otp_ctrl_test_access.3183983757
Short name T654
Test name
Test status
Simulation time 291216313 ps
CPU time 6.53 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:19 PM PDT 24
Peak memory 241996 kb
Host smart-32aab57e-03f5-4615-a2e5-69e06c70d17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183983757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3183983757
Directory /workspace/45.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/46.otp_ctrl_alert_test.4191013821
Short name T478
Test name
Test status
Simulation time 53473253 ps
CPU time 1.78 seconds
Started Jul 03 07:17:08 PM PDT 24
Finished Jul 03 07:17:18 PM PDT 24
Peak memory 240000 kb
Host smart-aaef4711-a10d-4524-b4f2-90bd0147271f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191013821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.4191013821
Directory /workspace/46.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.otp_ctrl_check_fail.2630143248
Short name T508
Test name
Test status
Simulation time 1190089442 ps
CPU time 7.16 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 242188 kb
Host smart-be443d0e-4598-49f7-85d3-51861166dc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630143248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2630143248
Directory /workspace/46.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_errs.2552050024
Short name T774
Test name
Test status
Simulation time 3002658381 ps
CPU time 12.7 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:25 PM PDT 24
Peak memory 242228 kb
Host smart-28b2b001-9df1-4a1e-8287-f70c863e8f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552050024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.2552050024
Directory /workspace/46.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_dai_lock.695160073
Short name T802
Test name
Test status
Simulation time 527773262 ps
CPU time 11.45 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:17:25 PM PDT 24
Peak memory 242652 kb
Host smart-90940706-0058-4d7e-b95d-e8d3863412e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695160073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.695160073
Directory /workspace/46.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/46.otp_ctrl_init_fail.3914279900
Short name T33
Test name
Test status
Simulation time 224588998 ps
CPU time 4.89 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:22 PM PDT 24
Peak memory 242156 kb
Host smart-cb8272f7-e378-4c18-a098-e80bbc2f6be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914279900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.3914279900
Directory /workspace/46.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/46.otp_ctrl_macro_errs.3536719944
Short name T853
Test name
Test status
Simulation time 2886343972 ps
CPU time 31.84 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:44 PM PDT 24
Peak memory 248588 kb
Host smart-63e15144-ae40-4c2e-be33-26716ef616ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536719944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.3536719944
Directory /workspace/46.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_key_req.2705857341
Short name T953
Test name
Test status
Simulation time 1393449239 ps
CPU time 9.74 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 248740 kb
Host smart-5a6d16a1-f9eb-4835-8dc2-d1673980cf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705857341 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.2705857341
Directory /workspace/46.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_esc.1988679714
Short name T934
Test name
Test status
Simulation time 633429920 ps
CPU time 4.84 seconds
Started Jul 03 07:17:08 PM PDT 24
Finished Jul 03 07:17:20 PM PDT 24
Peak memory 241612 kb
Host smart-4a08d9e6-53e6-42d4-a3cd-ae539bde7a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988679714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1988679714
Directory /workspace/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/46.otp_ctrl_parallel_lc_req.4069529042
Short name T418
Test name
Test status
Simulation time 3076430406 ps
CPU time 9.27 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:22 PM PDT 24
Peak memory 242080 kb
Host smart-4b51fefb-4742-485b-a92f-9fe38dfed04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069529042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.4069529042
Directory /workspace/46.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/46.otp_ctrl_regwen.3055278508
Short name T1000
Test name
Test status
Simulation time 235821609 ps
CPU time 6.83 seconds
Started Jul 03 07:17:08 PM PDT 24
Finished Jul 03 07:17:22 PM PDT 24
Peak memory 242108 kb
Host smart-681b8d60-d153-4a14-a46b-2801bb8a8354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055278508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3055278508
Directory /workspace/46.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/46.otp_ctrl_smoke.3478893845
Short name T782
Test name
Test status
Simulation time 147561084 ps
CPU time 4.77 seconds
Started Jul 03 07:17:03 PM PDT 24
Finished Jul 03 07:17:14 PM PDT 24
Peak memory 242216 kb
Host smart-65493cd4-2a67-4122-b425-f67bfeb70c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478893845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.3478893845
Directory /workspace/46.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all.616114406
Short name T912
Test name
Test status
Simulation time 32624348247 ps
CPU time 184.55 seconds
Started Jul 03 07:17:05 PM PDT 24
Finished Jul 03 07:20:15 PM PDT 24
Peak memory 249928 kb
Host smart-0760568c-37f1-4000-acc4-18069e36ded8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616114406 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.
616114406
Directory /workspace/46.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.92822345
Short name T280
Test name
Test status
Simulation time 268369184318 ps
CPU time 921.93 seconds
Started Jul 03 07:17:07 PM PDT 24
Finished Jul 03 07:32:35 PM PDT 24
Peak memory 265368 kb
Host smart-a2f8605c-79af-4dc2-b064-3c6a3df0c3c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92822345 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.92822345
Directory /workspace/46.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.otp_ctrl_test_access.4230662039
Short name T987
Test name
Test status
Simulation time 219640655 ps
CPU time 8.09 seconds
Started Jul 03 07:17:06 PM PDT 24
Finished Jul 03 07:17:20 PM PDT 24
Peak memory 242052 kb
Host smart-535c1d04-23e4-4d78-bd67-59d3d212bb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230662039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.4230662039
Directory /workspace/46.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/47.otp_ctrl_alert_test.2520301254
Short name T511
Test name
Test status
Simulation time 750007370 ps
CPU time 2.05 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:19 PM PDT 24
Peak memory 240080 kb
Host smart-25542775-f17d-4de2-ac26-2de7e3edd21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520301254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2520301254
Directory /workspace/47.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.otp_ctrl_check_fail.1915322645
Short name T709
Test name
Test status
Simulation time 570765092 ps
CPU time 13.64 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:17:34 PM PDT 24
Peak memory 248780 kb
Host smart-ab11e942-dd54-46b2-9c3f-83ee9d084e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915322645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1915322645
Directory /workspace/47.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_errs.724766324
Short name T594
Test name
Test status
Simulation time 716283771 ps
CPU time 10.21 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:17:31 PM PDT 24
Peak memory 241836 kb
Host smart-5b0b80ab-eb09-4512-8de1-56c98156c940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724766324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.724766324
Directory /workspace/47.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_dai_lock.707986069
Short name T940
Test name
Test status
Simulation time 1564894942 ps
CPU time 5.92 seconds
Started Jul 03 07:17:10 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 248612 kb
Host smart-3a8f0178-610c-4b3f-8e02-3f061de711e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707986069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.707986069
Directory /workspace/47.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/47.otp_ctrl_init_fail.4100512762
Short name T933
Test name
Test status
Simulation time 292836830 ps
CPU time 4.3 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:27 PM PDT 24
Peak memory 242052 kb
Host smart-8117ff82-3909-4bef-95b0-433ca3e6e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100512762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4100512762
Directory /workspace/47.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/47.otp_ctrl_macro_errs.2221158943
Short name T1113
Test name
Test status
Simulation time 3613388141 ps
CPU time 35.37 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:55 PM PDT 24
Peak memory 248280 kb
Host smart-39b70d51-14b2-4252-9efe-6a3852ac5dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221158943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.2221158943
Directory /workspace/47.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_key_req.3649219776
Short name T832
Test name
Test status
Simulation time 2981892956 ps
CPU time 42.24 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:18:05 PM PDT 24
Peak memory 242356 kb
Host smart-36c480f4-1d36-4c04-ab0d-239a161b444a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649219776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3649219776
Directory /workspace/47.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_esc.1384588714
Short name T932
Test name
Test status
Simulation time 476782386 ps
CPU time 8.33 seconds
Started Jul 03 07:17:13 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 242296 kb
Host smart-6dcc671c-83a0-45e4-b763-6e2978e6af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384588714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1384588714
Directory /workspace/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/47.otp_ctrl_parallel_lc_req.2679408723
Short name T323
Test name
Test status
Simulation time 3510354490 ps
CPU time 28.79 seconds
Started Jul 03 07:17:10 PM PDT 24
Finished Jul 03 07:17:47 PM PDT 24
Peak memory 242048 kb
Host smart-65a5c927-5e18-4ec7-964c-603a99ade915
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679408723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2679408723
Directory /workspace/47.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/47.otp_ctrl_regwen.201485395
Short name T314
Test name
Test status
Simulation time 457351563 ps
CPU time 9.49 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 242140 kb
Host smart-33b40b4c-ab4d-42fd-9d8b-92cb89f9a92e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201485395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.201485395
Directory /workspace/47.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/47.otp_ctrl_smoke.583117031
Short name T680
Test name
Test status
Simulation time 674476770 ps
CPU time 4.36 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:27 PM PDT 24
Peak memory 248488 kb
Host smart-5df69f19-7b88-4bd6-9672-91273f2315b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583117031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.583117031
Directory /workspace/47.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all.2275116187
Short name T262
Test name
Test status
Simulation time 27270188010 ps
CPU time 238.01 seconds
Started Jul 03 07:17:13 PM PDT 24
Finished Jul 03 07:21:20 PM PDT 24
Peak memory 257748 kb
Host smart-547d1d1f-b33d-4f72-802b-99831dee9a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275116187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all
.2275116187
Directory /workspace/47.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.3322811901
Short name T678
Test name
Test status
Simulation time 95450532349 ps
CPU time 722.77 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:29:23 PM PDT 24
Peak memory 255244 kb
Host smart-4c01b9c7-28ce-4a1e-b7a2-c074a783f7d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322811901 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.3322811901
Directory /workspace/47.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.otp_ctrl_test_access.590392370
Short name T707
Test name
Test status
Simulation time 1056155161 ps
CPU time 17.44 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 242440 kb
Host smart-8811c28a-eece-43a1-a53a-7df2b90c4943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590392370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.590392370
Directory /workspace/47.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/48.otp_ctrl_alert_test.1011580893
Short name T753
Test name
Test status
Simulation time 125198965 ps
CPU time 2.14 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:25 PM PDT 24
Peak memory 240080 kb
Host smart-487f6da5-f421-4b69-a9cd-560b47d734b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011580893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1011580893
Directory /workspace/48.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.otp_ctrl_check_fail.3410156757
Short name T62
Test name
Test status
Simulation time 1551181046 ps
CPU time 32.75 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 244412 kb
Host smart-6a56468b-1f3e-4a1c-ba98-046da2b1d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410156757 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.3410156757
Directory /workspace/48.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_errs.1908456086
Short name T422
Test name
Test status
Simulation time 3356403415 ps
CPU time 43.41 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:18:06 PM PDT 24
Peak memory 254068 kb
Host smart-f84d6d71-cf06-46b5-bc8b-209761bd841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908456086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.1908456086
Directory /workspace/48.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_dai_lock.4233863875
Short name T92
Test name
Test status
Simulation time 8335183754 ps
CPU time 23.33 seconds
Started Jul 03 07:17:10 PM PDT 24
Finished Jul 03 07:17:41 PM PDT 24
Peak memory 242436 kb
Host smart-3e9b0b2f-21e7-4416-999a-a64a2fa6de2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233863875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.4233863875
Directory /workspace/48.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/48.otp_ctrl_init_fail.1740575584
Short name T663
Test name
Test status
Simulation time 1976290812 ps
CPU time 4.75 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:22 PM PDT 24
Peak memory 241912 kb
Host smart-0c0ce148-e2a7-42ef-ba70-9e43dd93b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740575584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1740575584
Directory /workspace/48.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/48.otp_ctrl_macro_errs.1435138349
Short name T773
Test name
Test status
Simulation time 870000476 ps
CPU time 6.51 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 242512 kb
Host smart-e77c88d4-583f-4f29-91c8-77b0795279c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435138349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.1435138349
Directory /workspace/48.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_key_req.4183348925
Short name T434
Test name
Test status
Simulation time 430299666 ps
CPU time 13.91 seconds
Started Jul 03 07:17:10 PM PDT 24
Finished Jul 03 07:17:32 PM PDT 24
Peak memory 248784 kb
Host smart-3acf98e3-ac1d-4682-a31a-ddaf580b2551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183348925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.4183348925
Directory /workspace/48.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_esc.2123442264
Short name T994
Test name
Test status
Simulation time 2662435276 ps
CPU time 5.25 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:24 PM PDT 24
Peak memory 242100 kb
Host smart-6a501150-07c5-4c76-b4d5-a1ef85c98096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123442264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2123442264
Directory /workspace/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/48.otp_ctrl_parallel_lc_req.2334356391
Short name T812
Test name
Test status
Simulation time 779803958 ps
CPU time 13.11 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 241924 kb
Host smart-3eab74a1-67dc-4642-b847-4b229736b423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2334356391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2334356391
Directory /workspace/48.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/48.otp_ctrl_regwen.952779936
Short name T389
Test name
Test status
Simulation time 4619892683 ps
CPU time 18.1 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:38 PM PDT 24
Peak memory 242252 kb
Host smart-5c8e834a-a575-4594-a773-f5cc0a22caf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=952779936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.952779936
Directory /workspace/48.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/48.otp_ctrl_smoke.1877844689
Short name T1121
Test name
Test status
Simulation time 231489909 ps
CPU time 8.11 seconds
Started Jul 03 07:17:11 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 242436 kb
Host smart-7276f81b-020c-49bb-9260-6b20b1d6f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877844689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1877844689
Directory /workspace/48.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all.2670337764
Short name T360
Test name
Test status
Simulation time 81441649778 ps
CPU time 157.67 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:19:58 PM PDT 24
Peak memory 295640 kb
Host smart-12a13870-b558-4010-b9c1-4d9d1cf3b3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670337764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all
.2670337764
Directory /workspace/48.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3901118821
Short name T294
Test name
Test status
Simulation time 121049800738 ps
CPU time 1498.67 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:42:19 PM PDT 24
Peak memory 373188 kb
Host smart-c81918a6-3b31-4e5f-8354-8ec5df49a15f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901118821 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.3901118821
Directory /workspace/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.otp_ctrl_test_access.788320327
Short name T1039
Test name
Test status
Simulation time 18448929302 ps
CPU time 46.21 seconds
Started Jul 03 07:17:12 PM PDT 24
Finished Jul 03 07:18:07 PM PDT 24
Peak memory 242116 kb
Host smart-6dd36fba-1743-4c21-919f-cb587d671aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788320327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.788320327
Directory /workspace/48.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/49.otp_ctrl_alert_test.1883871992
Short name T633
Test name
Test status
Simulation time 708820396 ps
CPU time 2.16 seconds
Started Jul 03 07:17:19 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 240488 kb
Host smart-eb16d7bb-6b01-4877-b3bf-49360b106ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883871992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.1883871992
Directory /workspace/49.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.otp_ctrl_check_fail.1756279032
Short name T80
Test name
Test status
Simulation time 3340673737 ps
CPU time 44.66 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 245304 kb
Host smart-a0697301-73b7-4e3e-80ce-61586975a72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756279032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1756279032
Directory /workspace/49.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_errs.207305662
Short name T885
Test name
Test status
Simulation time 14327848089 ps
CPU time 38.52 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 246740 kb
Host smart-e043978c-7ad9-4658-9a2e-93c23d071e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207305662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.207305662
Directory /workspace/49.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_dai_lock.898644239
Short name T98
Test name
Test status
Simulation time 1687275879 ps
CPU time 17.75 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:41 PM PDT 24
Peak memory 242384 kb
Host smart-180f7588-0615-4a4b-9cbd-d19e9af6ca7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898644239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.898644239
Directory /workspace/49.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/49.otp_ctrl_macro_errs.879869308
Short name T960
Test name
Test status
Simulation time 4120625276 ps
CPU time 29.4 seconds
Started Jul 03 07:17:14 PM PDT 24
Finished Jul 03 07:17:52 PM PDT 24
Peak memory 248756 kb
Host smart-657ec2d5-73ca-4546-8d77-8ca410dc1eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879869308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.879869308
Directory /workspace/49.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_key_req.2914700976
Short name T93
Test name
Test status
Simulation time 790647581 ps
CPU time 18.47 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:17:44 PM PDT 24
Peak memory 241972 kb
Host smart-e8968a4d-b80e-49c1-9063-dcf3d016da80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914700976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2914700976
Directory /workspace/49.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_esc.2671266898
Short name T938
Test name
Test status
Simulation time 175827476 ps
CPU time 7.2 seconds
Started Jul 03 07:17:15 PM PDT 24
Finished Jul 03 07:17:31 PM PDT 24
Peak memory 241880 kb
Host smart-d137928b-b889-4291-9d13-9def0859a876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671266898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2671266898
Directory /workspace/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/49.otp_ctrl_parallel_lc_req.1443007536
Short name T486
Test name
Test status
Simulation time 1146502470 ps
CPU time 18.67 seconds
Started Jul 03 07:17:09 PM PDT 24
Finished Jul 03 07:17:36 PM PDT 24
Peak memory 241836 kb
Host smart-9fcec368-e28c-42e2-b497-cab6963e71b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443007536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.1443007536
Directory /workspace/49.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/49.otp_ctrl_regwen.131943469
Short name T387
Test name
Test status
Simulation time 303370059 ps
CPU time 9.36 seconds
Started Jul 03 07:17:15 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 242440 kb
Host smart-50317db4-ac59-4c54-a5b6-f548a474de12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131943469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.131943469
Directory /workspace/49.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/49.otp_ctrl_smoke.2225839606
Short name T6
Test name
Test status
Simulation time 523593555 ps
CPU time 3.64 seconds
Started Jul 03 07:17:10 PM PDT 24
Finished Jul 03 07:17:22 PM PDT 24
Peak memory 241956 kb
Host smart-28971213-ab06-4b68-9afb-9ffa6197d668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225839606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2225839606
Directory /workspace/49.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all.456690739
Short name T201
Test name
Test status
Simulation time 59542593719 ps
CPU time 128.57 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:19:34 PM PDT 24
Peak memory 248632 kb
Host smart-68bbccd7-ef25-429e-bac7-0f5f9ac76917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456690739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.
456690739
Directory /workspace/49.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.4070930937
Short name T17
Test name
Test status
Simulation time 363565733672 ps
CPU time 802.52 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:30:48 PM PDT 24
Peak memory 267756 kb
Host smart-79e5e3f0-0df1-4647-90a2-0d31c441fabf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070930937 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.4070930937
Directory /workspace/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.otp_ctrl_test_access.3992435085
Short name T927
Test name
Test status
Simulation time 1685852277 ps
CPU time 29.55 seconds
Started Jul 03 07:17:15 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 242428 kb
Host smart-281efb2f-0eeb-4d70-9560-e9b34b2caa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992435085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.3992435085
Directory /workspace/49.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/5.otp_ctrl_alert_test.1218618168
Short name T243
Test name
Test status
Simulation time 63102302 ps
CPU time 1.73 seconds
Started Jul 03 07:15:10 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 240124 kb
Host smart-0bd1446a-a72b-4e16-b3b2-255271575306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218618168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1218618168
Directory /workspace/5.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.otp_ctrl_background_chks.950836147
Short name T1062
Test name
Test status
Simulation time 1674942285 ps
CPU time 23.93 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:34 PM PDT 24
Peak memory 242264 kb
Host smart-468130f9-5041-4874-9b42-e7f117fac226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950836147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.950836147
Directory /workspace/5.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/5.otp_ctrl_check_fail.2283440083
Short name T64
Test name
Test status
Simulation time 23692453972 ps
CPU time 67.94 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:16:17 PM PDT 24
Peak memory 244704 kb
Host smart-c98172c0-9ada-4148-8690-7a6fd8c792b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283440083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2283440083
Directory /workspace/5.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_errs.2256698701
Short name T809
Test name
Test status
Simulation time 966953560 ps
CPU time 27.86 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 242264 kb
Host smart-c6b43edc-b9ff-45b7-a168-20114a82c9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256698701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2256698701
Directory /workspace/5.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_dai_lock.432777253
Short name T867
Test name
Test status
Simulation time 2681661395 ps
CPU time 15.85 seconds
Started Jul 03 07:15:07 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 242136 kb
Host smart-48823e65-2956-4ce4-b4cc-04552a291ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432777253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.432777253
Directory /workspace/5.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/5.otp_ctrl_init_fail.3034243051
Short name T916
Test name
Test status
Simulation time 351559202 ps
CPU time 4.45 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:14 PM PDT 24
Peak memory 242160 kb
Host smart-5069c6a6-ddbd-419c-901a-514e46d03aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034243051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.3034243051
Directory /workspace/5.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/5.otp_ctrl_macro_errs.2090394960
Short name T159
Test name
Test status
Simulation time 1400649289 ps
CPU time 18.63 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 248776 kb
Host smart-3cf88f90-891b-4db1-862b-848203132f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090394960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2090394960
Directory /workspace/5.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_key_req.163586572
Short name T977
Test name
Test status
Simulation time 901540661 ps
CPU time 21.34 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:32 PM PDT 24
Peak memory 242544 kb
Host smart-4e60cad8-2e57-4424-9286-7c56df2b6ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163586572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.163586572
Directory /workspace/5.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_esc.383416558
Short name T1140
Test name
Test status
Simulation time 561520467 ps
CPU time 13.62 seconds
Started Jul 03 07:15:05 PM PDT 24
Finished Jul 03 07:15:24 PM PDT 24
Peak memory 241772 kb
Host smart-a4a3d309-3705-487d-becd-a320882a1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383416558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.383416558
Directory /workspace/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/5.otp_ctrl_parallel_lc_req.3727417377
Short name T733
Test name
Test status
Simulation time 2641404993 ps
CPU time 24.44 seconds
Started Jul 03 07:15:04 PM PDT 24
Finished Jul 03 07:15:34 PM PDT 24
Peak memory 248768 kb
Host smart-c8d8f5e5-f199-4b7e-819a-0e3c070c0ef5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3727417377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.3727417377
Directory /workspace/5.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/5.otp_ctrl_regwen.3286351262
Short name T384
Test name
Test status
Simulation time 130465527 ps
CPU time 4.35 seconds
Started Jul 03 07:15:07 PM PDT 24
Finished Jul 03 07:15:16 PM PDT 24
Peak memory 242080 kb
Host smart-139d58a5-c553-4f45-a584-775ad5cfbb34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286351262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3286351262
Directory /workspace/5.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/5.otp_ctrl_smoke.1618190344
Short name T776
Test name
Test status
Simulation time 506430925 ps
CPU time 5.85 seconds
Started Jul 03 07:15:07 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 242368 kb
Host smart-6d419c63-5946-466d-8313-6f7609b16efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618190344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.1618190344
Directory /workspace/5.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all.129253755
Short name T690
Test name
Test status
Simulation time 7943059625 ps
CPU time 66.53 seconds
Started Jul 03 07:15:11 PM PDT 24
Finished Jul 03 07:16:22 PM PDT 24
Peak memory 244568 kb
Host smart-c86262ae-a602-416e-a308-302207288ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129253755 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.129253755
Directory /workspace/5.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1013656321
Short name T343
Test name
Test status
Simulation time 55531536849 ps
CPU time 1232.77 seconds
Started Jul 03 07:15:10 PM PDT 24
Finished Jul 03 07:35:48 PM PDT 24
Peak memory 312516 kb
Host smart-826337a8-72fe-4461-b3f1-517eec25a837
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013656321 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1013656321
Directory /workspace/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.otp_ctrl_test_access.1563678265
Short name T1193
Test name
Test status
Simulation time 11892066383 ps
CPU time 23.82 seconds
Started Jul 03 07:15:06 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 248932 kb
Host smart-a919ed7b-f994-471a-96d8-24bfaafca14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563678265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.1563678265
Directory /workspace/5.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/50.otp_ctrl_init_fail.109415445
Short name T217
Test name
Test status
Simulation time 146360734 ps
CPU time 4.18 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 242080 kb
Host smart-04e89833-1dea-40ac-9dae-270d102ee868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109415445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.109415445
Directory /workspace/50.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/50.otp_ctrl_parallel_lc_esc.1827612451
Short name T879
Test name
Test status
Simulation time 2358290874 ps
CPU time 7.07 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:17:32 PM PDT 24
Peak memory 241884 kb
Host smart-4d8cec4a-8755-48be-b68e-2605ae18eb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827612451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1827612451
Directory /workspace/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_init_fail.353830148
Short name T1164
Test name
Test status
Simulation time 242983223 ps
CPU time 3.75 seconds
Started Jul 03 07:17:18 PM PDT 24
Finished Jul 03 07:17:30 PM PDT 24
Peak memory 242076 kb
Host smart-4dff62d6-2ffd-4ba1-bdc0-e777882b0498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353830148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.353830148
Directory /workspace/51.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/51.otp_ctrl_parallel_lc_esc.574150888
Short name T529
Test name
Test status
Simulation time 542953847 ps
CPU time 14.64 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 242164 kb
Host smart-444a9504-705e-41cd-bc07-9625308314d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574150888 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.574150888
Directory /workspace/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.3185779173
Short name T901
Test name
Test status
Simulation time 392361312072 ps
CPU time 1231.06 seconds
Started Jul 03 07:17:15 PM PDT 24
Finished Jul 03 07:37:55 PM PDT 24
Peak memory 397608 kb
Host smart-b9ac3199-0b2d-4532-95f6-e0bf35d503c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185779173 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.3185779173
Directory /workspace/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.otp_ctrl_init_fail.826701928
Short name T488
Test name
Test status
Simulation time 118661079 ps
CPU time 2.88 seconds
Started Jul 03 07:17:15 PM PDT 24
Finished Jul 03 07:17:26 PM PDT 24
Peak memory 242120 kb
Host smart-31cd03dc-0241-4f01-a66e-71e7e5b97713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826701928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.826701928
Directory /workspace/52.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/52.otp_ctrl_parallel_lc_esc.2332659516
Short name T620
Test name
Test status
Simulation time 447665026 ps
CPU time 4.04 seconds
Started Jul 03 07:17:16 PM PDT 24
Finished Jul 03 07:17:29 PM PDT 24
Peak memory 242172 kb
Host smart-17a8523c-5801-42f2-ac31-c159ec3d884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332659516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2332659516
Directory /workspace/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_init_fail.759058264
Short name T525
Test name
Test status
Simulation time 548740013 ps
CPU time 4.24 seconds
Started Jul 03 07:17:21 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 241912 kb
Host smart-4bb90b6b-f335-470f-b19a-1f3dff8b27a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759058264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.759058264
Directory /workspace/53.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/53.otp_ctrl_parallel_lc_esc.3346169303
Short name T99
Test name
Test status
Simulation time 2918285015 ps
CPU time 23.22 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 242200 kb
Host smart-2d6c132d-021c-488f-8821-f97cc7b638be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346169303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3346169303
Directory /workspace/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.800161972
Short name T285
Test name
Test status
Simulation time 219427264069 ps
CPU time 1068.05 seconds
Started Jul 03 07:17:21 PM PDT 24
Finished Jul 03 07:35:17 PM PDT 24
Peak memory 348308 kb
Host smart-7bf738f7-d780-4353-95db-3eb6d19511bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800161972 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.800161972
Directory /workspace/53.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.otp_ctrl_init_fail.1030194088
Short name T1041
Test name
Test status
Simulation time 111574750 ps
CPU time 3.61 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 241900 kb
Host smart-a82c154a-717a-46c6-b2bc-7ccae9d993d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030194088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1030194088
Directory /workspace/54.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/54.otp_ctrl_parallel_lc_esc.4149434890
Short name T73
Test name
Test status
Simulation time 2870554622 ps
CPU time 10.38 seconds
Started Jul 03 07:17:21 PM PDT 24
Finished Jul 03 07:17:39 PM PDT 24
Peak memory 242316 kb
Host smart-9ab13a10-8796-454b-a4d2-fb4827662e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149434890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.4149434890
Directory /workspace/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.3351308477
Short name T149
Test name
Test status
Simulation time 97016435054 ps
CPU time 1482.44 seconds
Started Jul 03 07:17:21 PM PDT 24
Finished Jul 03 07:42:12 PM PDT 24
Peak memory 458876 kb
Host smart-4a5b6c16-098a-4b94-9eae-6f8fc991a5d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351308477 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3351308477
Directory /workspace/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.otp_ctrl_init_fail.4107605635
Short name T510
Test name
Test status
Simulation time 557686222 ps
CPU time 4.13 seconds
Started Jul 03 07:17:19 PM PDT 24
Finished Jul 03 07:17:32 PM PDT 24
Peak memory 242036 kb
Host smart-868a271a-84ec-4e0b-a337-c61c75dd010f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107605635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.4107605635
Directory /workspace/55.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/55.otp_ctrl_parallel_lc_esc.779598282
Short name T1093
Test name
Test status
Simulation time 355841654 ps
CPU time 5.93 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:36 PM PDT 24
Peak memory 242368 kb
Host smart-5802b1bc-736d-486a-9b28-bb58c2addf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779598282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.779598282
Directory /workspace/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/55.otp_ctrl_stress_all_with_rand_reset.312018986
Short name T800
Test name
Test status
Simulation time 266670118778 ps
CPU time 828.49 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:31:20 PM PDT 24
Peak memory 273500 kb
Host smart-afc72e48-1075-4fb5-95ca-0918e8bd3d8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312018986 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.312018986
Directory /workspace/55.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.otp_ctrl_init_fail.876915436
Short name T120
Test name
Test status
Simulation time 163732655 ps
CPU time 4.19 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:37 PM PDT 24
Peak memory 242032 kb
Host smart-ab19c087-e4ac-47e6-955e-1bfc51712b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876915436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.876915436
Directory /workspace/56.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/56.otp_ctrl_parallel_lc_esc.1472913201
Short name T352
Test name
Test status
Simulation time 835176047 ps
CPU time 22.83 seconds
Started Jul 03 07:17:20 PM PDT 24
Finished Jul 03 07:17:51 PM PDT 24
Peak memory 241968 kb
Host smart-0ba7439a-4d04-4b04-a092-16d42ca84af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472913201 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1472913201
Directory /workspace/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.1543285647
Short name T256
Test name
Test status
Simulation time 168773822101 ps
CPU time 624.55 seconds
Started Jul 03 07:17:22 PM PDT 24
Finished Jul 03 07:27:55 PM PDT 24
Peak memory 258020 kb
Host smart-ced5f245-0470-4f6c-ac7a-f3206fca5194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543285647 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.1543285647
Directory /workspace/56.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.otp_ctrl_init_fail.1771345718
Short name T128
Test name
Test status
Simulation time 2337925704 ps
CPU time 6.37 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:37 PM PDT 24
Peak memory 242192 kb
Host smart-b59d8892-ec59-42a0-8432-76e505b7ffc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771345718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1771345718
Directory /workspace/57.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/57.otp_ctrl_parallel_lc_esc.1048507386
Short name T315
Test name
Test status
Simulation time 405026679 ps
CPU time 5.27 seconds
Started Jul 03 07:17:19 PM PDT 24
Finished Jul 03 07:17:33 PM PDT 24
Peak memory 242268 kb
Host smart-33b0312d-7880-4ae5-bfb0-37c70427cb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048507386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1048507386
Directory /workspace/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3579463743
Short name T341
Test name
Test status
Simulation time 560691477308 ps
CPU time 1948.82 seconds
Started Jul 03 07:17:22 PM PDT 24
Finished Jul 03 07:49:59 PM PDT 24
Peak memory 379908 kb
Host smart-0e5f69fb-6b29-4282-9c33-a478b4927fe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579463743 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3579463743
Directory /workspace/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.otp_ctrl_init_fail.2938635461
Short name T604
Test name
Test status
Simulation time 525452007 ps
CPU time 4.26 seconds
Started Jul 03 07:17:19 PM PDT 24
Finished Jul 03 07:17:32 PM PDT 24
Peak memory 241912 kb
Host smart-ffbbc95e-7be5-4fe0-a0fd-70228729ced9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938635461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.2938635461
Directory /workspace/58.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/58.otp_ctrl_parallel_lc_esc.2797177740
Short name T727
Test name
Test status
Simulation time 387704485 ps
CPU time 5.89 seconds
Started Jul 03 07:17:20 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 241968 kb
Host smart-7501bff8-ab3c-4beb-910c-773903bafca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797177740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2797177740
Directory /workspace/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.194535241
Short name T133
Test name
Test status
Simulation time 205971250055 ps
CPU time 1551.72 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:43:24 PM PDT 24
Peak memory 297936 kb
Host smart-0f281d9f-7f8c-4f25-b681-95216a168f28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194535241 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.194535241
Directory /workspace/58.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.otp_ctrl_init_fail.2377656715
Short name T11
Test name
Test status
Simulation time 2315406057 ps
CPU time 6.73 seconds
Started Jul 03 07:17:27 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 242128 kb
Host smart-c1f4ad89-8b90-4b59-b289-e96ee4d6053f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377656715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2377656715
Directory /workspace/59.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/59.otp_ctrl_parallel_lc_esc.662984747
Short name T651
Test name
Test status
Simulation time 1938601390 ps
CPU time 6.37 seconds
Started Jul 03 07:17:20 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 241832 kb
Host smart-4dd39a8a-0f64-4711-bda0-afb4dbde903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662984747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.662984747
Directory /workspace/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.1261026358
Short name T295
Test name
Test status
Simulation time 337054732173 ps
CPU time 3903.57 seconds
Started Jul 03 07:17:17 PM PDT 24
Finished Jul 03 08:22:30 PM PDT 24
Peak memory 606344 kb
Host smart-9bf36b00-137d-4fc8-bf1e-8dd283927573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261026358 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1261026358
Directory /workspace/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_alert_test.3734833555
Short name T453
Test name
Test status
Simulation time 906021003 ps
CPU time 1.9 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:15:20 PM PDT 24
Peak memory 240192 kb
Host smart-16edbcc1-0cf4-4ee2-a2a1-10f3d9fdd2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734833555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3734833555
Directory /workspace/6.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.otp_ctrl_background_chks.3582181014
Short name T124
Test name
Test status
Simulation time 1702692387 ps
CPU time 32.1 seconds
Started Jul 03 07:15:10 PM PDT 24
Finished Jul 03 07:15:47 PM PDT 24
Peak memory 243008 kb
Host smart-fe5c0e68-d928-4e72-ab1c-cc4e1970dc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582181014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3582181014
Directory /workspace/6.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/6.otp_ctrl_check_fail.1936546340
Short name T758
Test name
Test status
Simulation time 3645137327 ps
CPU time 25.83 seconds
Started Jul 03 07:15:11 PM PDT 24
Finished Jul 03 07:15:41 PM PDT 24
Peak memory 245632 kb
Host smart-cfd9ef80-9a08-4039-986c-ac7950f4ca8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936546340 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1936546340
Directory /workspace/6.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_errs.2254092440
Short name T951
Test name
Test status
Simulation time 359824555 ps
CPU time 10.58 seconds
Started Jul 03 07:15:09 PM PDT 24
Finished Jul 03 07:15:25 PM PDT 24
Peak memory 241888 kb
Host smart-b378e573-96fb-4d05-999e-c46a1eca753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254092440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.2254092440
Directory /workspace/6.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_dai_lock.1483053962
Short name T621
Test name
Test status
Simulation time 16516289837 ps
CPU time 35.86 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:49 PM PDT 24
Peak memory 243200 kb
Host smart-13cbf49d-c7aa-4f2e-b125-a16a409f277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483053962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1483053962
Directory /workspace/6.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/6.otp_ctrl_init_fail.1954370273
Short name T995
Test name
Test status
Simulation time 107492473 ps
CPU time 4.54 seconds
Started Jul 03 07:15:07 PM PDT 24
Finished Jul 03 07:15:17 PM PDT 24
Peak memory 242184 kb
Host smart-1afe40d9-5dea-4bcd-ae58-8d774fa9f1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954370273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.1954370273
Directory /workspace/6.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/6.otp_ctrl_macro_errs.3971875401
Short name T777
Test name
Test status
Simulation time 664250674 ps
CPU time 14.99 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:29 PM PDT 24
Peak memory 243824 kb
Host smart-9a7e044d-46e8-4822-9ca7-0b89d37d906a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971875401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3971875401
Directory /workspace/6.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_key_req.586283329
Short name T1067
Test name
Test status
Simulation time 584511240 ps
CPU time 13.21 seconds
Started Jul 03 07:15:08 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 241960 kb
Host smart-f28bb05a-6fb6-4c1f-9a98-14488ace6a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586283329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.586283329
Directory /workspace/6.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_esc.1222099248
Short name T827
Test name
Test status
Simulation time 169093353 ps
CPU time 4.86 seconds
Started Jul 03 07:15:09 PM PDT 24
Finished Jul 03 07:15:18 PM PDT 24
Peak memory 241980 kb
Host smart-14e328c2-ffb5-4c02-b636-ea0110abbf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222099248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1222099248
Directory /workspace/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/6.otp_ctrl_parallel_lc_req.1377850865
Short name T497
Test name
Test status
Simulation time 681988317 ps
CPU time 21.26 seconds
Started Jul 03 07:15:13 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 241988 kb
Host smart-656bd766-708e-4538-a457-b811bc60fac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377850865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1377850865
Directory /workspace/6.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/6.otp_ctrl_regwen.3768257891
Short name T896
Test name
Test status
Simulation time 431665164 ps
CPU time 5.37 seconds
Started Jul 03 07:15:13 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 242136 kb
Host smart-fd3eab25-70d5-46c2-96d6-60f511656081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768257891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.3768257891
Directory /workspace/6.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/6.otp_ctrl_smoke.501488763
Short name T998
Test name
Test status
Simulation time 3577880222 ps
CPU time 7.08 seconds
Started Jul 03 07:15:09 PM PDT 24
Finished Jul 03 07:15:21 PM PDT 24
Peak memory 242088 kb
Host smart-ca53fe7c-f324-41f6-ab68-46070cbc6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501488763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.501488763
Directory /workspace/6.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all.399765930
Short name T245
Test name
Test status
Simulation time 16607115742 ps
CPU time 211.18 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:18:50 PM PDT 24
Peak memory 257596 kb
Host smart-62ae23cd-db27-4a74-aea7-69e2f9a34667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399765930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.399765930
Directory /workspace/6.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.otp_ctrl_stress_all_with_rand_reset.2678127645
Short name T411
Test name
Test status
Simulation time 89613499541 ps
CPU time 1526.33 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:40:45 PM PDT 24
Peak memory 279328 kb
Host smart-cf321983-55e9-48b9-b0fe-a3656d5ee7ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678127645 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.2678127645
Directory /workspace/6.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.otp_ctrl_test_access.1087487553
Short name T868
Test name
Test status
Simulation time 305768581 ps
CPU time 7.26 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 242500 kb
Host smart-22433a42-d858-49e0-b0b9-c9f784814d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087487553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.1087487553
Directory /workspace/6.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/60.otp_ctrl_init_fail.1733433620
Short name T720
Test name
Test status
Simulation time 367043980 ps
CPU time 3.78 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 242252 kb
Host smart-f96ee63b-1dd0-4a17-9b43-3e8589880b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733433620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1733433620
Directory /workspace/60.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/60.otp_ctrl_parallel_lc_esc.1124320269
Short name T482
Test name
Test status
Simulation time 2442305487 ps
CPU time 17.94 seconds
Started Jul 03 07:17:27 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 242072 kb
Host smart-a7cd5737-eb70-4f37-8eb1-7c358b604999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124320269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1124320269
Directory /workspace/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2334369301
Short name T286
Test name
Test status
Simulation time 291917032311 ps
CPU time 1787.43 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:47:19 PM PDT 24
Peak memory 361716 kb
Host smart-0059bb2a-a41d-4aa7-9004-41f464ee87fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334369301 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.2334369301
Directory /workspace/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.otp_ctrl_init_fail.1825511596
Short name T36
Test name
Test status
Simulation time 162315028 ps
CPU time 4.12 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:37 PM PDT 24
Peak memory 242220 kb
Host smart-bc5032db-a49b-43d6-8ee8-2d055ae7fd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825511596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1825511596
Directory /workspace/61.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/61.otp_ctrl_parallel_lc_esc.1538179648
Short name T204
Test name
Test status
Simulation time 502197041 ps
CPU time 7.48 seconds
Started Jul 03 07:17:25 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 241912 kb
Host smart-a6df861b-44a7-4c8b-8be8-812f3e2f128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538179648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.1538179648
Directory /workspace/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.2204772252
Short name T676
Test name
Test status
Simulation time 61597528062 ps
CPU time 390.86 seconds
Started Jul 03 07:17:22 PM PDT 24
Finished Jul 03 07:24:01 PM PDT 24
Peak memory 265356 kb
Host smart-0b468ad8-f09b-4c1a-93aa-7a1298619863
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204772252 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2204772252
Directory /workspace/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.otp_ctrl_init_fail.1781601479
Short name T716
Test name
Test status
Simulation time 135546124 ps
CPU time 3.54 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 242072 kb
Host smart-a6ce771a-d6f1-4b5b-ac71-46a7564a1b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781601479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.1781601479
Directory /workspace/62.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/62.otp_ctrl_parallel_lc_esc.1520551109
Short name T75
Test name
Test status
Simulation time 312077977 ps
CPU time 5.46 seconds
Started Jul 03 07:17:26 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 242164 kb
Host smart-4a8c01d0-4e3a-4988-bbfd-a60cefd2dd7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520551109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1520551109
Directory /workspace/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_parallel_lc_esc.3618607270
Short name T1023
Test name
Test status
Simulation time 899866085 ps
CPU time 17.05 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 241820 kb
Host smart-dae80824-00f6-4890-99f3-96c712bdc4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618607270 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.3618607270
Directory /workspace/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1069665994
Short name T275
Test name
Test status
Simulation time 224453335650 ps
CPU time 1517.52 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:42:50 PM PDT 24
Peak memory 263396 kb
Host smart-6f7cf386-4815-4aba-94e0-58190cb0281b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069665994 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1069665994
Directory /workspace/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.otp_ctrl_init_fail.624214721
Short name T79
Test name
Test status
Simulation time 108313325 ps
CPU time 3.85 seconds
Started Jul 03 07:17:23 PM PDT 24
Finished Jul 03 07:17:35 PM PDT 24
Peak memory 242368 kb
Host smart-dd24e270-07f2-491e-bb18-dedc306ff011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624214721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.624214721
Directory /workspace/64.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/64.otp_ctrl_parallel_lc_esc.1199013303
Short name T765
Test name
Test status
Simulation time 9845177508 ps
CPU time 30.58 seconds
Started Jul 03 07:17:26 PM PDT 24
Finished Jul 03 07:18:05 PM PDT 24
Peak memory 241988 kb
Host smart-13937c74-a529-4757-bd59-80aa905f155b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199013303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.1199013303
Directory /workspace/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.1056672357
Short name T835
Test name
Test status
Simulation time 81562033539 ps
CPU time 1085.98 seconds
Started Jul 03 07:17:26 PM PDT 24
Finished Jul 03 07:35:40 PM PDT 24
Peak memory 294072 kb
Host smart-857cdc73-edc1-4ada-a908-926f69fe61ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056672357 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1056672357
Directory /workspace/64.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.otp_ctrl_init_fail.260489015
Short name T1179
Test name
Test status
Simulation time 1550632070 ps
CPU time 6.42 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:39 PM PDT 24
Peak memory 242120 kb
Host smart-41147c73-ddb3-4396-98d1-9fcd6d667bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260489015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.260489015
Directory /workspace/65.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/65.otp_ctrl_parallel_lc_esc.4062081387
Short name T440
Test name
Test status
Simulation time 337063145 ps
CPU time 6.9 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:17:43 PM PDT 24
Peak memory 241948 kb
Host smart-683a4862-a3f9-42ec-85fc-939dbb5c625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062081387 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.4062081387
Directory /workspace/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/66.otp_ctrl_init_fail.840105790
Short name T475
Test name
Test status
Simulation time 256501905 ps
CPU time 4.73 seconds
Started Jul 03 07:17:25 PM PDT 24
Finished Jul 03 07:17:38 PM PDT 24
Peak memory 242156 kb
Host smart-a22a9a41-0732-4796-ac3c-165a2cc69716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840105790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.840105790
Directory /workspace/66.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/66.otp_ctrl_parallel_lc_esc.3341245533
Short name T1044
Test name
Test status
Simulation time 920436751 ps
CPU time 12.03 seconds
Started Jul 03 07:17:26 PM PDT 24
Finished Jul 03 07:17:46 PM PDT 24
Peak memory 242212 kb
Host smart-8470b61a-ff65-499c-a3dd-cb345798853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341245533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3341245533
Directory /workspace/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_init_fail.2601832804
Short name T216
Test name
Test status
Simulation time 1912813946 ps
CPU time 6.26 seconds
Started Jul 03 07:17:25 PM PDT 24
Finished Jul 03 07:17:40 PM PDT 24
Peak memory 241976 kb
Host smart-71d6d1ed-cdcf-4ade-abe0-8d1f8dacab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601832804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.2601832804
Directory /workspace/67.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/67.otp_ctrl_parallel_lc_esc.1661531062
Short name T519
Test name
Test status
Simulation time 952869477 ps
CPU time 7.8 seconds
Started Jul 03 07:17:24 PM PDT 24
Finished Jul 03 07:17:41 PM PDT 24
Peak memory 242352 kb
Host smart-df80ba0c-a4f1-4c69-939a-14c41f56e944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661531062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1661531062
Directory /workspace/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/67.otp_ctrl_stress_all_with_rand_reset.513070165
Short name T9
Test name
Test status
Simulation time 149460768158 ps
CPU time 1469.65 seconds
Started Jul 03 07:17:29 PM PDT 24
Finished Jul 03 07:42:08 PM PDT 24
Peak memory 399064 kb
Host smart-e0597928-de89-422a-9a18-6ad0726d29cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513070165 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.513070165
Directory /workspace/67.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.otp_ctrl_init_fail.2469395559
Short name T169
Test name
Test status
Simulation time 407203040 ps
CPU time 3.81 seconds
Started Jul 03 07:17:30 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 241976 kb
Host smart-39764fbf-9140-490d-8dcf-60428c46bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469395559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2469395559
Directory /workspace/68.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/68.otp_ctrl_parallel_lc_esc.97306353
Short name T260
Test name
Test status
Simulation time 1312313496 ps
CPU time 10.4 seconds
Started Jul 03 07:17:30 PM PDT 24
Finished Jul 03 07:17:49 PM PDT 24
Peak memory 241956 kb
Host smart-98de5f6f-ce76-4eba-85e5-376792a2ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97306353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.97306353
Directory /workspace/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1800723379
Short name T272
Test name
Test status
Simulation time 79555217375 ps
CPU time 1046.66 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:35:03 PM PDT 24
Peak memory 273460 kb
Host smart-b28aa1d3-3592-475b-8ecf-8925994a1e39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800723379 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.1800723379
Directory /workspace/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.otp_ctrl_init_fail.1183348868
Short name T446
Test name
Test status
Simulation time 179615138 ps
CPU time 4.23 seconds
Started Jul 03 07:17:31 PM PDT 24
Finished Jul 03 07:17:43 PM PDT 24
Peak memory 242256 kb
Host smart-ab53b111-da49-48a0-81fe-f95a1a3911d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183348868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1183348868
Directory /workspace/69.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/69.otp_ctrl_parallel_lc_esc.686970432
Short name T810
Test name
Test status
Simulation time 122542803 ps
CPU time 4.91 seconds
Started Jul 03 07:17:30 PM PDT 24
Finished Jul 03 07:17:43 PM PDT 24
Peak memory 242144 kb
Host smart-d25ecefe-fb3f-417a-a5d6-b19bc8396955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686970432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.686970432
Directory /workspace/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_alert_test.1702793097
Short name T750
Test name
Test status
Simulation time 115612060 ps
CPU time 2.14 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:15:21 PM PDT 24
Peak memory 240232 kb
Host smart-616e332e-1bc0-460c-95d5-e5d88ffaa3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702793097 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1702793097
Directory /workspace/7.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.otp_ctrl_background_chks.3853699865
Short name T647
Test name
Test status
Simulation time 8359670193 ps
CPU time 63.88 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:16:24 PM PDT 24
Peak memory 242492 kb
Host smart-9807ac03-0db0-4acd-8287-6156698ebaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853699865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3853699865
Directory /workspace/7.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/7.otp_ctrl_check_fail.4026325716
Short name T209
Test name
Test status
Simulation time 1896102261 ps
CPU time 11.22 seconds
Started Jul 03 07:15:12 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 242168 kb
Host smart-35e37d38-f510-44b7-b1b4-55f9329a5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026325716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.4026325716
Directory /workspace/7.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_errs.3567470960
Short name T568
Test name
Test status
Simulation time 3555751777 ps
CPU time 17.19 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:38 PM PDT 24
Peak memory 241444 kb
Host smart-8d26fe01-1aa1-4f01-86c9-23c767ca708a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567470960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.3567470960
Directory /workspace/7.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_dai_lock.101626066
Short name T102
Test name
Test status
Simulation time 3452822791 ps
CPU time 18.59 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:15:39 PM PDT 24
Peak memory 242488 kb
Host smart-46a4c732-d086-4166-8a74-c02d12b40884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101626066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.101626066
Directory /workspace/7.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/7.otp_ctrl_init_fail.1484206348
Short name T195
Test name
Test status
Simulation time 412152257 ps
CPU time 4.6 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 241928 kb
Host smart-cb255966-1fc1-4bb4-b1b4-891a20a61c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484206348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1484206348
Directory /workspace/7.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/7.otp_ctrl_macro_errs.3406016667
Short name T4
Test name
Test status
Simulation time 1591481549 ps
CPU time 12.36 seconds
Started Jul 03 07:15:15 PM PDT 24
Finished Jul 03 07:15:31 PM PDT 24
Peak memory 242240 kb
Host smart-0a3814b1-c408-48a0-9232-087abcb16b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406016667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3406016667
Directory /workspace/7.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_key_req.2719761865
Short name T1139
Test name
Test status
Simulation time 1953880244 ps
CPU time 48.1 seconds
Started Jul 03 07:15:15 PM PDT 24
Finished Jul 03 07:16:07 PM PDT 24
Peak memory 242740 kb
Host smart-7fd1638c-46e1-4ba4-85aa-7aed2d1c85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719761865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2719761865
Directory /workspace/7.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_esc.2747871349
Short name T692
Test name
Test status
Simulation time 2648747219 ps
CPU time 5.62 seconds
Started Jul 03 07:15:12 PM PDT 24
Finished Jul 03 07:15:22 PM PDT 24
Peak memory 241920 kb
Host smart-cf03c331-7718-40f0-a51c-2848f8bcf794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747871349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.2747871349
Directory /workspace/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/7.otp_ctrl_parallel_lc_req.3131947458
Short name T408
Test name
Test status
Simulation time 2164143049 ps
CPU time 16.33 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 248728 kb
Host smart-1075c50c-6b72-41d4-922e-41d48a5d47e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3131947458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.3131947458
Directory /workspace/7.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/7.otp_ctrl_regwen.1123155634
Short name T1091
Test name
Test status
Simulation time 244584800 ps
CPU time 5.64 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:15:24 PM PDT 24
Peak memory 242668 kb
Host smart-e0f014b4-de9b-4e52-9479-344687dfe933
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1123155634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1123155634
Directory /workspace/7.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/7.otp_ctrl_smoke.421912375
Short name T1192
Test name
Test status
Simulation time 3741202453 ps
CPU time 7.55 seconds
Started Jul 03 07:15:15 PM PDT 24
Finished Jul 03 07:15:27 PM PDT 24
Peak memory 242280 kb
Host smart-86266c06-d869-4ca1-bc69-168dde440dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421912375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.421912375
Directory /workspace/7.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all.2727481733
Short name T582
Test name
Test status
Simulation time 49524973239 ps
CPU time 191.11 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:18:29 PM PDT 24
Peak memory 248788 kb
Host smart-a49abc9f-f5c4-4112-9b76-4a5dd725c73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727481733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.
2727481733
Directory /workspace/7.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2785092448
Short name T771
Test name
Test status
Simulation time 99663237814 ps
CPU time 1837.89 seconds
Started Jul 03 07:15:13 PM PDT 24
Finished Jul 03 07:45:55 PM PDT 24
Peak memory 342272 kb
Host smart-197a954e-e763-4c9f-bf82-2234ef2f3d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785092448 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.2785092448
Directory /workspace/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.otp_ctrl_test_access.2211662298
Short name T95
Test name
Test status
Simulation time 5937959602 ps
CPU time 9 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:30 PM PDT 24
Peak memory 242632 kb
Host smart-4950fefb-45b6-4d04-91ea-d1e1f1aeb822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211662298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2211662298
Directory /workspace/7.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/70.otp_ctrl_init_fail.3841529811
Short name T320
Test name
Test status
Simulation time 131311777 ps
CPU time 3.72 seconds
Started Jul 03 07:17:32 PM PDT 24
Finished Jul 03 07:17:43 PM PDT 24
Peak memory 242032 kb
Host smart-2fc3b646-165e-49b6-a53d-495de57a9b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841529811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3841529811
Directory /workspace/70.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_init_fail.2384815283
Short name T818
Test name
Test status
Simulation time 130830545 ps
CPU time 3.73 seconds
Started Jul 03 07:17:30 PM PDT 24
Finished Jul 03 07:17:42 PM PDT 24
Peak memory 242172 kb
Host smart-2dc21767-6738-4865-91f3-dfda83c80ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384815283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2384815283
Directory /workspace/71.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/71.otp_ctrl_parallel_lc_esc.4160422479
Short name T400
Test name
Test status
Simulation time 384167363 ps
CPU time 9.32 seconds
Started Jul 03 07:17:30 PM PDT 24
Finished Jul 03 07:17:48 PM PDT 24
Peak memory 241924 kb
Host smart-43c80eb9-d970-4492-95ac-154653b77aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160422479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.4160422479
Directory /workspace/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.1811006186
Short name T725
Test name
Test status
Simulation time 434223124093 ps
CPU time 1058.77 seconds
Started Jul 03 07:17:28 PM PDT 24
Finished Jul 03 07:35:16 PM PDT 24
Peak memory 322708 kb
Host smart-0403bde4-5a9d-46d3-b477-f75d79952545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811006186 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.1811006186
Directory /workspace/71.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.otp_ctrl_init_fail.4154568661
Short name T1032
Test name
Test status
Simulation time 565980912 ps
CPU time 4.17 seconds
Started Jul 03 07:17:32 PM PDT 24
Finished Jul 03 07:17:44 PM PDT 24
Peak memory 242076 kb
Host smart-9f6e7b5a-136c-48bc-b982-27357a700dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154568661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.4154568661
Directory /workspace/72.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/72.otp_ctrl_parallel_lc_esc.564850515
Short name T1097
Test name
Test status
Simulation time 2008738387 ps
CPU time 5.3 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:49 PM PDT 24
Peak memory 242340 kb
Host smart-e48eab76-ac53-4c57-9cae-4601fb22ee84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564850515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.564850515
Directory /workspace/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.1778192221
Short name T983
Test name
Test status
Simulation time 256781805312 ps
CPU time 2636.87 seconds
Started Jul 03 07:17:35 PM PDT 24
Finished Jul 03 08:01:40 PM PDT 24
Peak memory 348500 kb
Host smart-351e7e8f-c06f-457c-b835-f4a405769e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778192221 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.1778192221
Directory /workspace/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.otp_ctrl_init_fail.1062329536
Short name T468
Test name
Test status
Simulation time 429106573 ps
CPU time 4.42 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:48 PM PDT 24
Peak memory 241856 kb
Host smart-50177797-711d-48e6-92db-f7d7a21ed96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062329536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1062329536
Directory /workspace/73.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/73.otp_ctrl_parallel_lc_esc.2852477924
Short name T1122
Test name
Test status
Simulation time 160792575 ps
CPU time 6.92 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:17:48 PM PDT 24
Peak memory 242004 kb
Host smart-ca7cf7fa-188b-4f33-99aa-046771521078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852477924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.2852477924
Directory /workspace/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.4018778356
Short name T18
Test name
Test status
Simulation time 375542064182 ps
CPU time 1046.52 seconds
Started Jul 03 07:17:38 PM PDT 24
Finished Jul 03 07:35:12 PM PDT 24
Peak memory 274028 kb
Host smart-ddcea9cc-886c-44a8-89c1-650dee32b705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018778356 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.4018778356
Directory /workspace/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.otp_ctrl_init_fail.923353999
Short name T924
Test name
Test status
Simulation time 94418064 ps
CPU time 3.34 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:47 PM PDT 24
Peak memory 241940 kb
Host smart-dede9288-b6ce-42a2-ae4c-f58e50b141b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923353999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.923353999
Directory /workspace/74.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/74.otp_ctrl_parallel_lc_esc.1533018842
Short name T150
Test name
Test status
Simulation time 1176820481 ps
CPU time 10.15 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:17:52 PM PDT 24
Peak memory 241788 kb
Host smart-8c20b1f6-fe74-4b8c-a09b-0c80ee150489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533018842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1533018842
Directory /workspace/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/74.otp_ctrl_stress_all_with_rand_reset.3193668686
Short name T581
Test name
Test status
Simulation time 90709461904 ps
CPU time 1760.76 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:47:03 PM PDT 24
Peak memory 294004 kb
Host smart-24f82a0a-6e59-4881-8f36-2afc97ef21dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193668686 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.3193668686
Directory /workspace/74.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.otp_ctrl_init_fail.4029877520
Short name T1042
Test name
Test status
Simulation time 367945001 ps
CPU time 4.95 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:17:47 PM PDT 24
Peak memory 242172 kb
Host smart-56a2b5fc-83e2-4317-abec-379f42baaf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029877520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.4029877520
Directory /workspace/75.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/75.otp_ctrl_parallel_lc_esc.36787788
Short name T421
Test name
Test status
Simulation time 211119014 ps
CPU time 11.72 seconds
Started Jul 03 07:17:38 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 242336 kb
Host smart-280533a6-30a0-4dbb-b52b-7192644344da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36787788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.36787788
Directory /workspace/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.2914015090
Short name T1147
Test name
Test status
Simulation time 270009046952 ps
CPU time 876.32 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:32:20 PM PDT 24
Peak memory 348268 kb
Host smart-b56cc81e-7f3c-4651-af56-c7193f3f8c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914015090 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.2914015090
Directory /workspace/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.otp_ctrl_init_fail.206947559
Short name T1088
Test name
Test status
Simulation time 99769347 ps
CPU time 3.08 seconds
Started Jul 03 07:17:37 PM PDT 24
Finished Jul 03 07:17:47 PM PDT 24
Peak memory 242436 kb
Host smart-08492010-5930-4c44-8d78-657e6ba171c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206947559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.206947559
Directory /workspace/76.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/76.otp_ctrl_parallel_lc_esc.4055170961
Short name T1092
Test name
Test status
Simulation time 3074427805 ps
CPU time 7.67 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:51 PM PDT 24
Peak memory 242236 kb
Host smart-d309a1d5-3fab-4752-896c-06d767e22bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055170961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.4055170961
Directory /workspace/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.1532853290
Short name T132
Test name
Test status
Simulation time 137799154299 ps
CPU time 1559.02 seconds
Started Jul 03 07:17:37 PM PDT 24
Finished Jul 03 07:43:43 PM PDT 24
Peak memory 356640 kb
Host smart-0688de65-6fd0-4823-9a90-59f995acc25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532853290 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1532853290
Directory /workspace/76.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.otp_ctrl_init_fail.3354605238
Short name T669
Test name
Test status
Simulation time 224605739 ps
CPU time 4.38 seconds
Started Jul 03 07:17:37 PM PDT 24
Finished Jul 03 07:17:49 PM PDT 24
Peak memory 242068 kb
Host smart-89aafc54-dee8-4b16-b9d4-6c2ac59024bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354605238 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3354605238
Directory /workspace/77.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/77.otp_ctrl_parallel_lc_esc.4079608300
Short name T1064
Test name
Test status
Simulation time 224106920 ps
CPU time 8.71 seconds
Started Jul 03 07:17:38 PM PDT 24
Finished Jul 03 07:17:54 PM PDT 24
Peak memory 242172 kb
Host smart-f6678a22-93da-45a2-bc15-6ff5ae765ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079608300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.4079608300
Directory /workspace/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.33131190
Short name T1108
Test name
Test status
Simulation time 121546424496 ps
CPU time 2088.24 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:52:30 PM PDT 24
Peak memory 432128 kb
Host smart-fc73fd1b-a151-42b8-bd11-13719c88bd27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33131190 -assert nopos
tproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.33131190
Directory /workspace/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.otp_ctrl_init_fail.2672330739
Short name T542
Test name
Test status
Simulation time 1829235806 ps
CPU time 5.93 seconds
Started Jul 03 07:17:34 PM PDT 24
Finished Jul 03 07:17:48 PM PDT 24
Peak memory 241940 kb
Host smart-4a1bfd5c-5c22-4ec0-8619-dd77e4117adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672330739 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2672330739
Directory /workspace/78.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/78.otp_ctrl_parallel_lc_esc.1935433367
Short name T544
Test name
Test status
Simulation time 715347631 ps
CPU time 9.62 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:54 PM PDT 24
Peak memory 241920 kb
Host smart-852026fa-282d-4725-9cd8-ee85c6639a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935433367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.1935433367
Directory /workspace/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.2529395077
Short name T1143
Test name
Test status
Simulation time 58758759591 ps
CPU time 1241.96 seconds
Started Jul 03 07:17:37 PM PDT 24
Finished Jul 03 07:38:26 PM PDT 24
Peak memory 273436 kb
Host smart-4f5125fd-f62c-4739-90ab-8eacd4896d91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529395077 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.2529395077
Directory /workspace/78.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.otp_ctrl_init_fail.1065285319
Short name T129
Test name
Test status
Simulation time 180035556 ps
CPU time 4.36 seconds
Started Jul 03 07:17:33 PM PDT 24
Finished Jul 03 07:17:46 PM PDT 24
Peak memory 241936 kb
Host smart-a81b34a5-bda1-4bb6-989f-747f7c5c3c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065285319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.1065285319
Directory /workspace/79.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/79.otp_ctrl_parallel_lc_esc.799016944
Short name T1134
Test name
Test status
Simulation time 1440245792 ps
CPU time 12.5 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 242168 kb
Host smart-4d2b386e-e765-40f3-91a2-b352e4d81e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799016944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.799016944
Directory /workspace/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.122733209
Short name T1111
Test name
Test status
Simulation time 151594972628 ps
CPU time 1911.07 seconds
Started Jul 03 07:17:35 PM PDT 24
Finished Jul 03 07:49:34 PM PDT 24
Peak memory 314100 kb
Host smart-9694297a-21ec-42ad-8f43-049edfdbb4b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122733209 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.122733209
Directory /workspace/79.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_alert_test.3158197032
Short name T181
Test name
Test status
Simulation time 817061566 ps
CPU time 1.99 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 240464 kb
Host smart-a7249dfa-8c67-4183-bda7-b565d517b252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158197032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3158197032
Directory /workspace/8.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.otp_ctrl_background_chks.4292483582
Short name T319
Test name
Test status
Simulation time 7985490459 ps
CPU time 24.72 seconds
Started Jul 03 07:15:13 PM PDT 24
Finished Jul 03 07:15:42 PM PDT 24
Peak memory 248844 kb
Host smart-29c0fc84-2f53-4117-84d6-c2ca43039c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292483582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.4292483582
Directory /workspace/8.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/8.otp_ctrl_check_fail.3621076022
Short name T850
Test name
Test status
Simulation time 342261885 ps
CPU time 6.82 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 242136 kb
Host smart-86d22f4e-3f7d-491b-9ca6-f88af58f1b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621076022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3621076022
Directory /workspace/8.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_errs.2209780234
Short name T448
Test name
Test status
Simulation time 1007821413 ps
CPU time 24.29 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:45 PM PDT 24
Peak memory 241132 kb
Host smart-2535ba1c-29ae-4e39-ba07-28757dc84059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209780234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.2209780234
Directory /workspace/8.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_dai_lock.1458176530
Short name T509
Test name
Test status
Simulation time 2584977898 ps
CPU time 24.42 seconds
Started Jul 03 07:15:15 PM PDT 24
Finished Jul 03 07:15:44 PM PDT 24
Peak memory 242072 kb
Host smart-9b5332ef-c3f5-4fd6-9dd4-d7c2aa19e8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458176530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1458176530
Directory /workspace/8.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/8.otp_ctrl_init_fail.677919241
Short name T838
Test name
Test status
Simulation time 248976726 ps
CPU time 3.45 seconds
Started Jul 03 07:15:15 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 242396 kb
Host smart-2cf21406-529f-4aef-86f9-0a91ebfae466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677919241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.677919241
Directory /workspace/8.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/8.otp_ctrl_macro_errs.1813752956
Short name T869
Test name
Test status
Simulation time 3874403461 ps
CPU time 5.78 seconds
Started Jul 03 07:15:19 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 242712 kb
Host smart-c4c72d5e-c0fc-46c4-acfa-6b52cc747581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813752956 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1813752956
Directory /workspace/8.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_key_req.4078265240
Short name T409
Test name
Test status
Simulation time 1763315650 ps
CPU time 21.76 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:43 PM PDT 24
Peak memory 248744 kb
Host smart-cb9f0fbc-2a38-4778-a45c-bfe8250bbf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078265240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.4078265240
Directory /workspace/8.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_esc.4180488504
Short name T1187
Test name
Test status
Simulation time 107583567 ps
CPU time 4.53 seconds
Started Jul 03 07:15:13 PM PDT 24
Finished Jul 03 07:15:23 PM PDT 24
Peak memory 241732 kb
Host smart-d926f896-5921-4043-8712-62c8533e5c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180488504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.4180488504
Directory /workspace/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/8.otp_ctrl_parallel_lc_req.3112714860
Short name T612
Test name
Test status
Simulation time 1591274207 ps
CPU time 24.74 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:15:44 PM PDT 24
Peak memory 242000 kb
Host smart-189be0cc-8952-4fcc-81a7-c8c8acd53c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112714860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3112714860
Directory /workspace/8.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/8.otp_ctrl_regwen.3097015374
Short name T611
Test name
Test status
Simulation time 166686746 ps
CPU time 6.09 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:27 PM PDT 24
Peak memory 242340 kb
Host smart-bdf1136b-16f2-49a7-a4f2-35b1b5bcbf57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3097015374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.3097015374
Directory /workspace/8.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/8.otp_ctrl_smoke.3852849077
Short name T460
Test name
Test status
Simulation time 1075218587 ps
CPU time 7.92 seconds
Started Jul 03 07:15:14 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 242308 kb
Host smart-fff620b2-91ea-4734-a16f-5d1930a7cd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852849077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3852849077
Directory /workspace/8.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all.3301810110
Short name T915
Test name
Test status
Simulation time 1623515028 ps
CPU time 28.39 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:50 PM PDT 24
Peak memory 243212 kb
Host smart-9bf8ab9c-6046-4519-b812-e74f54469194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301810110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.
3301810110
Directory /workspace/8.otp_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.886687100
Short name T627
Test name
Test status
Simulation time 27537978687 ps
CPU time 739.9 seconds
Started Jul 03 07:15:19 PM PDT 24
Finished Jul 03 07:27:42 PM PDT 24
Peak memory 264216 kb
Host smart-8c2d3f43-455e-403e-901c-0c22e8fb7b80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886687100 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.886687100
Directory /workspace/8.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.otp_ctrl_test_access.3238594841
Short name T467
Test name
Test status
Simulation time 3326028758 ps
CPU time 24.46 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:46 PM PDT 24
Peak memory 243104 kb
Host smart-b2aef261-86d7-424f-82b9-14990c5281ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238594841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3238594841
Directory /workspace/8.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/80.otp_ctrl_init_fail.3359938364
Short name T574
Test name
Test status
Simulation time 122449308 ps
CPU time 3.21 seconds
Started Jul 03 07:17:33 PM PDT 24
Finished Jul 03 07:17:44 PM PDT 24
Peak memory 242084 kb
Host smart-59d0edf5-80f6-4300-aeb4-64407fe7cbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359938364 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3359938364
Directory /workspace/80.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/80.otp_ctrl_parallel_lc_esc.2690046366
Short name T1119
Test name
Test status
Simulation time 946539267 ps
CPU time 14.13 seconds
Started Jul 03 07:17:35 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 242284 kb
Host smart-9373490b-9e3f-428b-8a7a-12ce5078e368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690046366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.2690046366
Directory /workspace/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.3789463183
Short name T744
Test name
Test status
Simulation time 251208790703 ps
CPU time 1214.03 seconds
Started Jul 03 07:17:36 PM PDT 24
Finished Jul 03 07:37:58 PM PDT 24
Peak memory 398712 kb
Host smart-664f3a99-1dde-4bf2-b66d-b0a1c4b724bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789463183 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.3789463183
Directory /workspace/80.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1761774765
Short name T976
Test name
Test status
Simulation time 764543060107 ps
CPU time 2491.56 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:59:20 PM PDT 24
Peak memory 393176 kb
Host smart-43c1d49c-c6e8-440d-8934-aa318f2c1c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761774765 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1761774765
Directory /workspace/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.otp_ctrl_init_fail.1511404667
Short name T61
Test name
Test status
Simulation time 145370078 ps
CPU time 3.5 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:17:51 PM PDT 24
Peak memory 242360 kb
Host smart-ba773cfd-3351-4f23-ac7b-b3e85b6ec7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511404667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.1511404667
Directory /workspace/82.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/82.otp_ctrl_parallel_lc_esc.3412768421
Short name T1082
Test name
Test status
Simulation time 1827244077 ps
CPU time 6.13 seconds
Started Jul 03 07:17:41 PM PDT 24
Finished Jul 03 07:17:54 PM PDT 24
Peak memory 242240 kb
Host smart-ff919765-8059-4b44-aeff-3d882b10dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412768421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3412768421
Directory /workspace/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.2426437409
Short name T346
Test name
Test status
Simulation time 87289359123 ps
CPU time 1037.74 seconds
Started Jul 03 07:17:39 PM PDT 24
Finished Jul 03 07:35:04 PM PDT 24
Peak memory 273220 kb
Host smart-ca1b86ff-77d6-47ad-8d5b-f9e558ae2caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426437409 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.2426437409
Directory /workspace/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.otp_ctrl_init_fail.753040450
Short name T1186
Test name
Test status
Simulation time 361579973 ps
CPU time 3.01 seconds
Started Jul 03 07:17:39 PM PDT 24
Finished Jul 03 07:17:50 PM PDT 24
Peak memory 242040 kb
Host smart-92b1dc8d-7261-4575-8b4f-1551cf5f3231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753040450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.753040450
Directory /workspace/83.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/83.otp_ctrl_parallel_lc_esc.3143740495
Short name T355
Test name
Test status
Simulation time 6311961696 ps
CPU time 14.16 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 248808 kb
Host smart-116d99f7-3d28-4ba1-a8c9-f4064c591a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143740495 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3143740495
Directory /workspace/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/83.otp_ctrl_stress_all_with_rand_reset.3881406756
Short name T629
Test name
Test status
Simulation time 47819897595 ps
CPU time 1275.01 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:39:08 PM PDT 24
Peak memory 496240 kb
Host smart-c6c8bbb7-829e-4b9f-8ee1-4fe361b22381
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881406756 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.3881406756
Directory /workspace/83.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.otp_ctrl_parallel_lc_esc.3044808983
Short name T532
Test name
Test status
Simulation time 1608990017 ps
CPU time 15.15 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 241960 kb
Host smart-0c12c635-fffd-449b-8e43-2cb54a67b8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044808983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3044808983
Directory /workspace/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.2990710158
Short name T603
Test name
Test status
Simulation time 40197730575 ps
CPU time 485.09 seconds
Started Jul 03 07:17:39 PM PDT 24
Finished Jul 03 07:25:52 PM PDT 24
Peak memory 276704 kb
Host smart-23a51f8c-de1c-4b64-a8d4-d5f5b56b6284
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990710158 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.2990710158
Directory /workspace/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.otp_ctrl_init_fail.1895343206
Short name T892
Test name
Test status
Simulation time 153381950 ps
CPU time 4.15 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:17:52 PM PDT 24
Peak memory 242040 kb
Host smart-4336e647-5366-49a1-bda0-b413300c3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895343206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1895343206
Directory /workspace/85.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/85.otp_ctrl_parallel_lc_esc.60400936
Short name T134
Test name
Test status
Simulation time 2354901208 ps
CPU time 8.79 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 241916 kb
Host smart-e6dd8945-c5e9-426a-9501-23558b7dbd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60400936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.60400936
Directory /workspace/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/85.otp_ctrl_stress_all_with_rand_reset.1770375352
Short name T732
Test name
Test status
Simulation time 16629747343 ps
CPU time 421.55 seconds
Started Jul 03 07:17:39 PM PDT 24
Finished Jul 03 07:24:47 PM PDT 24
Peak memory 248936 kb
Host smart-b32ec1e3-5849-4d9f-98b8-b4d4abde8db6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770375352 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.1770375352
Directory /workspace/85.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.otp_ctrl_init_fail.2437547874
Short name T452
Test name
Test status
Simulation time 572098128 ps
CPU time 4.76 seconds
Started Jul 03 07:17:41 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 242208 kb
Host smart-37598420-28f8-40c6-bab9-e8d3d7339002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437547874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.2437547874
Directory /workspace/86.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/86.otp_ctrl_parallel_lc_esc.1381921700
Short name T249
Test name
Test status
Simulation time 845975162 ps
CPU time 11.37 seconds
Started Jul 03 07:17:38 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 241872 kb
Host smart-c5c5de5c-b757-4259-aeb3-4dc695022f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381921700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1381921700
Directory /workspace/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.499339156
Short name T839
Test name
Test status
Simulation time 52443963121 ps
CPU time 719.3 seconds
Started Jul 03 07:17:41 PM PDT 24
Finished Jul 03 07:29:48 PM PDT 24
Peak memory 265424 kb
Host smart-5b85087a-644d-45b4-8884-e326cf238f24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499339156 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.499339156
Directory /workspace/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.otp_ctrl_init_fail.2538406050
Short name T729
Test name
Test status
Simulation time 353724134 ps
CPU time 4.05 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 242096 kb
Host smart-e72606b3-005a-49a6-8fc5-73d22d3da769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538406050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.2538406050
Directory /workspace/87.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/87.otp_ctrl_parallel_lc_esc.1905563680
Short name T353
Test name
Test status
Simulation time 11358027184 ps
CPU time 22.98 seconds
Started Jul 03 07:17:40 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 241924 kb
Host smart-670e716e-30c7-4fa9-811a-580f7e66eaa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905563680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1905563680
Directory /workspace/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.1965711707
Short name T931
Test name
Test status
Simulation time 155356625801 ps
CPU time 629.89 seconds
Started Jul 03 07:17:43 PM PDT 24
Finished Jul 03 07:28:20 PM PDT 24
Peak memory 317876 kb
Host smart-20a79e50-b957-4fc7-b8fa-c5ab8395a03d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965711707 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1965711707
Directory /workspace/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.otp_ctrl_init_fail.793140459
Short name T1112
Test name
Test status
Simulation time 159181408 ps
CPU time 4.03 seconds
Started Jul 03 07:17:44 PM PDT 24
Finished Jul 03 07:17:55 PM PDT 24
Peak memory 241792 kb
Host smart-42c59ec7-a2d4-4e84-bbe2-250d00411fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793140459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.793140459
Directory /workspace/88.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/88.otp_ctrl_parallel_lc_esc.3154748711
Short name T1073
Test name
Test status
Simulation time 318336908 ps
CPU time 4.31 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 242216 kb
Host smart-2a279056-0c3a-487c-bef2-242a4a4ab9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154748711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.3154748711
Directory /workspace/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.3325650129
Short name T1095
Test name
Test status
Simulation time 46346293523 ps
CPU time 573.28 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:27:25 PM PDT 24
Peak memory 320100 kb
Host smart-c72eafc3-1c3f-494c-a9bb-a9f76d69674a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325650129 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.3325650129
Directory /workspace/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.otp_ctrl_init_fail.2109661020
Short name T115
Test name
Test status
Simulation time 459917979 ps
CPU time 3.78 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:17:57 PM PDT 24
Peak memory 242008 kb
Host smart-ae3955dd-14d7-49dd-a601-4a0be7c7efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109661020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2109661020
Directory /workspace/89.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/89.otp_ctrl_parallel_lc_esc.3616496200
Short name T817
Test name
Test status
Simulation time 154840397 ps
CPU time 7.14 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 241988 kb
Host smart-c437413f-6ebf-4775-b2ae-5e05bef772af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616496200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3616496200
Directory /workspace/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.1278052275
Short name T665
Test name
Test status
Simulation time 56523117572 ps
CPU time 1362.92 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:40:37 PM PDT 24
Peak memory 285608 kb
Host smart-0aabd7a1-cf03-4dd1-8a1d-e489e63c7dce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278052275 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.1278052275
Directory /workspace/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.otp_ctrl_alert_test.1977485846
Short name T461
Test name
Test status
Simulation time 74003470 ps
CPU time 1.61 seconds
Started Jul 03 07:15:22 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 240360 kb
Host smart-39397465-e301-4b67-b90e-133761b332fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977485846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.1977485846
Directory /workspace/9.otp_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.otp_ctrl_background_chks.340182004
Short name T403
Test name
Test status
Simulation time 7624734046 ps
CPU time 15.5 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:15:36 PM PDT 24
Peak memory 248848 kb
Host smart-41ab4fc1-1830-4762-a068-46d90781f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340182004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.340182004
Directory /workspace/9.otp_ctrl_background_chks/latest

Test location /workspace/coverage/default/9.otp_ctrl_check_fail.3877801690
Short name T172
Test name
Test status
Simulation time 302210074 ps
CPU time 3.08 seconds
Started Jul 03 07:15:19 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 241988 kb
Host smart-4a881b40-ab87-41e5-99db-1669d9ef52d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877801690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.3877801690
Directory /workspace/9.otp_ctrl_check_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_errs.3697660635
Short name T214
Test name
Test status
Simulation time 5696357587 ps
CPU time 23.7 seconds
Started Jul 03 07:15:22 PM PDT 24
Finished Jul 03 07:15:48 PM PDT 24
Peak memory 242384 kb
Host smart-17e50bfb-55ae-4c07-a7c2-e2b346d19419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697660635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3697660635
Directory /workspace/9.otp_ctrl_dai_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_dai_lock.2671199173
Short name T990
Test name
Test status
Simulation time 9794988877 ps
CPU time 21.09 seconds
Started Jul 03 07:15:19 PM PDT 24
Finished Jul 03 07:15:43 PM PDT 24
Peak memory 242372 kb
Host smart-7f7bd794-eaf3-48d1-8ed3-25f907503ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671199173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2671199173
Directory /workspace/9.otp_ctrl_dai_lock/latest

Test location /workspace/coverage/default/9.otp_ctrl_init_fail.4283663184
Short name T193
Test name
Test status
Simulation time 196406649 ps
CPU time 4.48 seconds
Started Jul 03 07:15:16 PM PDT 24
Finished Jul 03 07:15:25 PM PDT 24
Peak memory 241940 kb
Host smart-bc7e435d-ced9-4dbd-b7c0-b5fdeb9b336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283663184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.4283663184
Directory /workspace/9.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/9.otp_ctrl_macro_errs.1744885027
Short name T898
Test name
Test status
Simulation time 1946626354 ps
CPU time 15.62 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:37 PM PDT 24
Peak memory 244044 kb
Host smart-91e3a47c-00a1-4a37-a4f4-5e84152383ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744885027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.1744885027
Directory /workspace/9.otp_ctrl_macro_errs/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_key_req.931361856
Short name T404
Test name
Test status
Simulation time 2510706749 ps
CPU time 30.19 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:51 PM PDT 24
Peak memory 248820 kb
Host smart-a8e533b1-305a-46be-8496-8f1e0cb52b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931361856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.931361856
Directory /workspace/9.otp_ctrl_parallel_key_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_esc.1596151894
Short name T550
Test name
Test status
Simulation time 234005089 ps
CPU time 7.16 seconds
Started Jul 03 07:15:22 PM PDT 24
Finished Jul 03 07:15:31 PM PDT 24
Peak memory 242224 kb
Host smart-57b7e55b-cc4f-44ef-9148-05b633406800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596151894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1596151894
Directory /workspace/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/9.otp_ctrl_parallel_lc_req.604148132
Short name T704
Test name
Test status
Simulation time 2858369382 ps
CPU time 6.28 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:28 PM PDT 24
Peak memory 248692 kb
Host smart-652a4e12-5cf9-454e-b55d-6f211ad7e581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604148132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.604148132
Directory /workspace/9.otp_ctrl_parallel_lc_req/latest

Test location /workspace/coverage/default/9.otp_ctrl_regwen.2463071826
Short name T697
Test name
Test status
Simulation time 220769162 ps
CPU time 5.56 seconds
Started Jul 03 07:15:17 PM PDT 24
Finished Jul 03 07:15:26 PM PDT 24
Peak memory 242124 kb
Host smart-1155cfa0-5234-4a62-8042-a88409be31e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463071826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.2463071826
Directory /workspace/9.otp_ctrl_regwen/latest

Test location /workspace/coverage/default/9.otp_ctrl_smoke.356725620
Short name T451
Test name
Test status
Simulation time 829860415 ps
CPU time 8.79 seconds
Started Jul 03 07:15:18 PM PDT 24
Finished Jul 03 07:15:30 PM PDT 24
Peak memory 242016 kb
Host smart-6b43414a-dcbd-44df-b01b-7c029e058aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356725620 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.356725620
Directory /workspace/9.otp_ctrl_smoke/latest

Test location /workspace/coverage/default/9.otp_ctrl_test_access.1289179949
Short name T1105
Test name
Test status
Simulation time 1247111386 ps
CPU time 27.3 seconds
Started Jul 03 07:15:23 PM PDT 24
Finished Jul 03 07:15:53 PM PDT 24
Peak memory 242524 kb
Host smart-9bce7c98-38e9-4fc5-884a-f824192d7e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289179949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1289179949
Directory /workspace/9.otp_ctrl_test_access/latest

Test location /workspace/coverage/default/90.otp_ctrl_init_fail.2436209554
Short name T444
Test name
Test status
Simulation time 2025359907 ps
CPU time 6.11 seconds
Started Jul 03 07:17:43 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 242088 kb
Host smart-b2dbe854-142b-4038-addc-8d4b43eb9673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436209554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.2436209554
Directory /workspace/90.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/90.otp_ctrl_parallel_lc_esc.3847352170
Short name T959
Test name
Test status
Simulation time 274786876 ps
CPU time 16.75 seconds
Started Jul 03 07:17:44 PM PDT 24
Finished Jul 03 07:18:08 PM PDT 24
Peak memory 241740 kb
Host smart-1f85588d-d992-4748-ab40-09d679521bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847352170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3847352170
Directory /workspace/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.934072183
Short name T276
Test name
Test status
Simulation time 448225702286 ps
CPU time 2232.29 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:55:04 PM PDT 24
Peak memory 297356 kb
Host smart-5595f71f-2876-4c3c-84d4-cf708371ddb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934072183 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.934072183
Directory /workspace/90.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.otp_ctrl_init_fail.1984008285
Short name T246
Test name
Test status
Simulation time 446039009 ps
CPU time 4.46 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 241984 kb
Host smart-1a6d982c-4b7c-497c-a244-f27373d9805e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984008285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1984008285
Directory /workspace/91.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/91.otp_ctrl_parallel_lc_esc.3134298101
Short name T1146
Test name
Test status
Simulation time 245353301 ps
CPU time 6.09 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:17:58 PM PDT 24
Peak memory 242300 kb
Host smart-22ac4d7d-2fbc-4ad0-94b8-944e7ce8753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134298101 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3134298101
Directory /workspace/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.2321043413
Short name T591
Test name
Test status
Simulation time 60495107001 ps
CPU time 1355.76 seconds
Started Jul 03 07:17:43 PM PDT 24
Finished Jul 03 07:40:26 PM PDT 24
Peak memory 379428 kb
Host smart-5edf294c-163e-47de-a35c-855915477971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321043413 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2321043413
Directory /workspace/91.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.otp_ctrl_init_fail.660363999
Short name T965
Test name
Test status
Simulation time 186001839 ps
CPU time 4.23 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 241904 kb
Host smart-933edf8f-1449-47cf-b35f-2cef3cc178b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660363999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.660363999
Directory /workspace/92.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/92.otp_ctrl_parallel_lc_esc.2154617481
Short name T1116
Test name
Test status
Simulation time 849053491 ps
CPU time 6.78 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:18:00 PM PDT 24
Peak memory 241932 kb
Host smart-ffde1b36-f530-4006-9609-c6924398fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154617481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2154617481
Directory /workspace/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.2068546767
Short name T842
Test name
Test status
Simulation time 223649527752 ps
CPU time 2621.28 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 08:01:33 PM PDT 24
Peak memory 530648 kb
Host smart-2a4d2092-4f3b-44c8-822a-868fae956138
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068546767 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.2068546767
Directory /workspace/92.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.otp_ctrl_init_fail.3014638838
Short name T573
Test name
Test status
Simulation time 292059657 ps
CPU time 4.14 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:17:56 PM PDT 24
Peak memory 241920 kb
Host smart-caf9370c-7ecd-4dfb-a5c0-639c26df1482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014638838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.3014638838
Directory /workspace/93.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/93.otp_ctrl_parallel_lc_esc.2113272202
Short name T887
Test name
Test status
Simulation time 717806905 ps
CPU time 10.25 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 241876 kb
Host smart-2bf21699-b839-42ce-b081-631ea1c84cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113272202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2113272202
Directory /workspace/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.3044639710
Short name T852
Test name
Test status
Simulation time 56782295999 ps
CPU time 666.13 seconds
Started Jul 03 07:17:44 PM PDT 24
Finished Jul 03 07:28:58 PM PDT 24
Peak memory 261364 kb
Host smart-431b1e4a-12d6-4839-9ff4-5fa5c59242c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044639710 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.3044639710
Directory /workspace/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.otp_ctrl_init_fail.2512887641
Short name T1089
Test name
Test status
Simulation time 1600297582 ps
CPU time 4.71 seconds
Started Jul 03 07:17:44 PM PDT 24
Finished Jul 03 07:17:55 PM PDT 24
Peak memory 242128 kb
Host smart-68da6b9a-4935-4e8c-8616-dc80c30f10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512887641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.2512887641
Directory /workspace/94.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/94.otp_ctrl_parallel_lc_esc.95533890
Short name T135
Test name
Test status
Simulation time 226665520 ps
CPU time 6.35 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 241916 kb
Host smart-1e3b257e-1333-4450-9a1b-89594351c62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95533890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.95533890
Directory /workspace/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_init_fail.4073269176
Short name T643
Test name
Test status
Simulation time 2106331081 ps
CPU time 5.98 seconds
Started Jul 03 07:17:46 PM PDT 24
Finished Jul 03 07:17:59 PM PDT 24
Peak memory 242036 kb
Host smart-12622b25-4e08-4921-af6f-44ad32580a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073269176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4073269176
Directory /workspace/95.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/95.otp_ctrl_parallel_lc_esc.1569354535
Short name T138
Test name
Test status
Simulation time 2691033881 ps
CPU time 22.48 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:18:17 PM PDT 24
Peak memory 242348 kb
Host smart-4548f025-b1c7-4102-93be-0b9a7b40b131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569354535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.1569354535
Directory /workspace/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.2433612691
Short name T1014
Test name
Test status
Simulation time 48743280036 ps
CPU time 1218.96 seconds
Started Jul 03 07:17:45 PM PDT 24
Finished Jul 03 07:38:11 PM PDT 24
Peak memory 360880 kb
Host smart-e3672f9d-0dec-42a3-a789-0ffd94745bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433612691 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.2433612691
Directory /workspace/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.otp_ctrl_init_fail.2718742783
Short name T909
Test name
Test status
Simulation time 107854818 ps
CPU time 3.65 seconds
Started Jul 03 07:17:43 PM PDT 24
Finished Jul 03 07:17:53 PM PDT 24
Peak memory 242268 kb
Host smart-bec11dd7-4178-4050-a3e8-b18ecf9ded36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718742783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2718742783
Directory /workspace/96.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/96.otp_ctrl_parallel_lc_esc.2548995268
Short name T205
Test name
Test status
Simulation time 948772021 ps
CPU time 6.67 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 242448 kb
Host smart-35e10e34-63dc-4307-b4e4-fa90377fc3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548995268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2548995268
Directory /workspace/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.306766676
Short name T728
Test name
Test status
Simulation time 66802542925 ps
CPU time 822.23 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:31:42 PM PDT 24
Peak memory 273988 kb
Host smart-16efcadc-5f4a-427a-bbad-93465a5b1933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306766676 -assert nopo
stproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.306766676
Directory /workspace/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.otp_ctrl_init_fail.3877545772
Short name T656
Test name
Test status
Simulation time 2288344870 ps
CPU time 6.41 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:04 PM PDT 24
Peak memory 242072 kb
Host smart-18c17461-00a9-413e-a8cf-bda04db773c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877545772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3877545772
Directory /workspace/97.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/97.otp_ctrl_parallel_lc_esc.4025127193
Short name T414
Test name
Test status
Simulation time 122021007 ps
CPU time 4.48 seconds
Started Jul 03 07:17:51 PM PDT 24
Finished Jul 03 07:18:02 PM PDT 24
Peak memory 242184 kb
Host smart-8923c488-5c35-4d0f-b110-f313ea9d4800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025127193 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.4025127193
Directory /workspace/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/97.otp_ctrl_stress_all_with_rand_reset.2543326809
Short name T984
Test name
Test status
Simulation time 68300484278 ps
CPU time 2087.25 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:52:41 PM PDT 24
Peak memory 511756 kb
Host smart-a40d76bc-4546-42b7-a5cd-f9eb9cc8de91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543326809 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.2543326809
Directory /workspace/97.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.otp_ctrl_init_fail.1879844113
Short name T1153
Test name
Test status
Simulation time 260011195 ps
CPU time 4.11 seconds
Started Jul 03 07:17:48 PM PDT 24
Finished Jul 03 07:17:58 PM PDT 24
Peak memory 242064 kb
Host smart-0d3a215b-0468-4c8b-9ce7-ce2f1daf4628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879844113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.1879844113
Directory /workspace/98.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/98.otp_ctrl_parallel_lc_esc.2762856355
Short name T785
Test name
Test status
Simulation time 526647575 ps
CPU time 13.06 seconds
Started Jul 03 07:17:50 PM PDT 24
Finished Jul 03 07:18:10 PM PDT 24
Peak memory 241836 kb
Host smart-af5251c1-908a-4b97-8ac5-4a6b98cc47f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762856355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2762856355
Directory /workspace/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.4090003496
Short name T757
Test name
Test status
Simulation time 129594523360 ps
CPU time 2852.43 seconds
Started Jul 03 07:17:49 PM PDT 24
Finished Jul 03 08:05:29 PM PDT 24
Peak memory 520312 kb
Host smart-bdf087db-a207-4ddc-9bf4-e48bbea70c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090003496 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.4090003496
Directory /workspace/98.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.otp_ctrl_init_fail.3647305314
Short name T458
Test name
Test status
Simulation time 2129207963 ps
CPU time 5.01 seconds
Started Jul 03 07:17:54 PM PDT 24
Finished Jul 03 07:18:05 PM PDT 24
Peak memory 242048 kb
Host smart-f6c67b79-137d-404b-b04b-65fb00f9cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647305314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3647305314
Directory /workspace/99.otp_ctrl_init_fail/latest

Test location /workspace/coverage/default/99.otp_ctrl_parallel_lc_esc.601106392
Short name T487
Test name
Test status
Simulation time 598842886 ps
CPU time 4.75 seconds
Started Jul 03 07:17:50 PM PDT 24
Finished Jul 03 07:18:01 PM PDT 24
Peak memory 242300 kb
Host smart-7b72bf6d-2a13-4ee1-a231-451083d849da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601106392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.601106392
Directory /workspace/99.otp_ctrl_parallel_lc_esc/latest

Test location /workspace/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.1877698321
Short name T1195
Test name
Test status
Simulation time 61151668667 ps
CPU time 1447.12 seconds
Started Jul 03 07:17:47 PM PDT 24
Finished Jul 03 07:42:02 PM PDT 24
Peak memory 314464 kb
Host smart-d6698627-cb23-4158-8dba-b6345ad62c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877698321 -assert nop
ostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.1877698321
Directory /workspace/99.otp_ctrl_stress_all_with_rand_reset/latest
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