Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
flash_data_req_during_flash_addr_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_lc_esc	2	0	2	100.00	100	1	1	0
flash_data_req_during_otbn_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_otp_idle	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_0_req	2	0	2	100.00	100	1	1	2
flash_data_req_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable flash_data_req_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11912

1

T10

2

T4

4

T5

6

auto[1]

924

1

T6

3

T7

14

T94

7

---

Summary for Variable flash_data_req_during_lc_esc

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for flash_data_req_during_lc_esc

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

lc_esc_off

12805

1

T10

1

T4

4

T5

6

lc_esc_on

31

1

T10

1

T21

1

T98

1

---

Summary for Variable flash_data_req_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12011

1

T10

2

T4

4

T5

4

auto[1]

825

1

T5

2

T6

3

T7

19

---

Summary for Variable flash_data_req_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1546

1

T10

1

T5

1

T6

12

auto[1]

11290

1

T10

1

T4

4

T5

5

---

Summary for Variable flash_data_req_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10713

1

T10

2

T4

2

T5

4

auto[1]

2123

1

T4

2

T5

2

T6

2

---

Summary for Variable flash_data_req_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12346

1

T10

2

T4

4

T5

6

auto[1]

490

1

T6

1

T7

7

T107

1