Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv



Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
flash_data_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_data_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_data_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12614 1 T1 12 T3 20 T4 8
auto[1] 826 1 T5 2 T9 21 T6 2



Summary for Variable flash_data_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_data_req_during_lc_esc

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
lc_esc_off 13399 1 T1 12 T3 20 T4 8
lc_esc_on 41 1 T200 1 T16 1 T159 1



Summary for Variable flash_data_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otbn_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 12479 1 T1 12 T3 20 T4 8
auto[1] 961 1 T5 4 T9 16 T6 5



Summary for Variable flash_data_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otp_idle

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2014 1 T3 5 T5 20 T9 21
auto[1] 11426 1 T1 12 T3 15 T4 8



Summary for Variable flash_data_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 11004 1 T1 6 T3 10 T4 4
auto[1] 2436 1 T1 6 T3 10 T4 4



Summary for Variable flash_data_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13007 1 T1 12 T3 20 T4 8
auto[1] 433 1 T5 3 T9 1 T6 3

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